Display device

Abstract

A display device is provided. The display device includes a pixel circuit disposed on a substrate and a display element located on the pixel circuit. The pixel circuit includes: a first thin film transistor including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer; a second thin film transistor including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode; a first shielding layer overlapping the second semiconductor layer; and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0160007, filed with the Korean Intellectual Property Office on December 4, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present invention relates to a display device, and more particularly, to a display device including a thin - film transistor having a shielding layer. Background art

[0004] Generally, a display device includes display elements and a driving circuit for controlling an electrical signal applied to the display elements. The driving circuit includes thin - film transistors (TFTs), storage capacitors, and a plurality of signal lines.

[0005] In order to precisely control whether a display element emits light and the emission degree of the display element, the number of TFTs electrically connected to one display element has been increased. Therefore, methods for solving problems related to high integration and power consumption of display devices are being actively studied. Summary of the invention

[0006] One or more embodiments include a display device having enhanced display quality. However, this purpose is only an example, and the scope of the present disclosure is not limited thereby.

[0007] Additional aspects will be partially set forth in the following description, and will be partially obvious from the description, or may be learned by practicing the presented embodiments of the present disclosure.

[0008] According to an exemplary embodiment of the present invention, a display device includes a pixel circuit disposed on a substrate and a display element on the pixel circuit. The pixel circuit includes: a first thin - film transistor including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer; a second thin - film transistor including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, a first end of the second semiconductor layer being connected to a first end of the first semiconductor layer and a second end of the second semiconductor layer being connected to the first gate electrode; a first shielding layer overlapping the second semiconductor layer; and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.

[0009] The second gate electrode includes a first sub - gate electrode and a second sub - gate electrode. The second semiconductor layer includes a first channel region and a second channel region. The second gate electrode includes a first sub - gate electrode overlapping the first channel region and a second sub - gate electrode overlapping the second channel region. The second shielding layer overlaps a part between the first channel region and the second channel region.

[0010] The first sub-gate electrode and the second sub-gate electrode are located on the same layer.

[0011] The first shielding layer and the second shielding layer include the same material.

[0012] The first shielding layer and the second shielding layer include materials different from each other.

[0013] The pixel circuit further includes: a capacitor including an upper electrode and a part of the first gate electrode as a lower electrode; and a power supply voltage line connected to the upper electrode. The upper electrode overlaps with this part of the first gate electrode.

[0014] The first shielding layer, the second shielding layer, and the upper electrode include the same material. The second shielding layer is a part of the power supply voltage line. The first shielding layer is connected to the power supply voltage line.

[0015] The first shielding layer and the upper electrode include the same material. The second shielding layer and the power supply voltage line include the same material.

[0016] The pixel circuit further includes: a capacitor including an upper electrode and a part of the first gate electrode as a lower electrode; a power supply voltage line connected to the upper electrode; and a third shielding layer stacked on the second shielding layer. The second shielding layer is between the first shielding layer and the third shielding layer. The upper electrode and the first shielding layer are located on the same layer. The upper electrode overlaps with this part of the first gate electrode. The power supply voltage line and the second shielding layer are located on the same layer. The third shielding layer overlaps with the second semiconductor layer.

[0017] The display device further includes a data line connected to the pixel circuit. The data line and the third shielding layer are located on the same layer.

[0018] The first shielding layer and the upper electrode include the same material. The second shielding layer and the power supply voltage line include the same material. The third shielding layer and the data line include the same material.

[0019] The third shielding layer is connected to the power supply voltage line.

[0020] According to an exemplary embodiment of the present invention, a display device includes: a pixel circuit disposed on a substrate and a display element on the pixel circuit. The pixel circuit includes a thin film transistor, and the thin film transistor includes: a semiconductor layer including a first channel region and a second channel region, a first sub-gate electrode overlapping with the first channel region, and a second sub-gate electrode overlapping with the second channel region. The pixel circuit further includes: a first shielding layer overlapping with a part between the first channel region and the second channel region; and a second shielding layer stacked on the first shielding layer.

[0021] The first shielding layer and the second shielding layer include the same material.

[0022] The first shielding layer and the second shielding layer include different materials from each other.

[0023] The pixel circuit further includes: a capacitor including a lower electrode and an upper electrode, and a power supply voltage line electrically connected to the upper electrode of the capacitor. The lower electrode, the first sub-gate electrode, and the second sub-gate electrode are located on the same layer. The upper electrode overlaps the lower electrode. The first shielding layer and the upper electrode of the capacitor include the same material. The second shielding layer and the power supply voltage line include the same material.

[0024] The second shielding layer is a part of the power supply voltage line. The first shielding layer is connected to the power supply voltage line.

[0025] The pixel circuit further includes a third shielding layer located on the second shielding layer. The third shielding layer overlaps a part between the first channel region and the second channel region.

[0026] The pixel circuit further includes a data line connected to the pixel circuit. The data line and the third shielding layer are located on the same layer. Description of the Drawings

[0027] Through the following description made in conjunction with the drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more clearly understood. In the drawings:

[0028] Figure 1 is a perspective view schematically showing a display device according to an exemplary embodiment;

[0029] Figure 2 is a cross-sectional view schematically showing a display device according to an exemplary embodiment;

[0030] Figure 3 is a plan view schematically showing a display panel according to an exemplary embodiment;

[0031] Figure 4 is a cross-sectional view schematically showing a pixel of a display panel according to an exemplary embodiment;

[0032] Figure 5 is a schematic layout diagram of a plurality of pixels of a display device according to an exemplary embodiment;

[0033] Figure 6 is an equivalent circuit diagram schematically showing a pixel circuit of a display panel according to an exemplary embodiment;

[0034] Figures 7A to 7D is a cross-sectional view schematically showing a thin film transistor according to an exemplary embodiment;

[0035] Figure 8is a layout diagram showing the positions of a plurality of thin film transistors and capacitors arranged in a pixel circuit of a display device according to an exemplary embodiment;

[0036] Figure 9A and Figure 9B is according to an exemplary embodiment Figure 8 an enlarged view of a region including a third thin film transistor;

[0037] Figure 10 is a schematic cross-sectional view of a display device taken along line II-II' of Figure 8 according to an exemplary embodiment; and

[0038] Figure 11 is a schematic cross-sectional view of a display device taken along line III-III' of Figure 8 according to an exemplary embodiment. DETAILED DESCRIPTION

[0039] Now, embodiments of the present disclosure will be described in detail with reference to examples shown in the drawings, in which like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments are described below only by referring to the drawings to explain various aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0040] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the drawings below. Regardless of the figure numbers, the same or corresponding elements are given the same reference numerals, and redundant descriptions thereof are omitted.

[0041] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0042] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0043] It will also be understood that the terms "comprises" and / or "comprising" as used herein specify the presence of the stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0044] It will be understood that when a layer, region or element is referred to as being "formed on" another layer, region or element, it can be formed directly or indirectly on the other layer, region or element. That is, for example, there may be an intermediate layer, region or element.

[0045] For ease of explanation, the dimensions of the elements in the figures may be enlarged or reduced. In other words, since the dimensions and thicknesses of the components in the figures are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0046] When a certain embodiment can be implemented differently, a specific processing order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order.

[0047] In this specification, "A and / or B" represents A, B, or A and B. "At least one of A and B" represents A, B, or A and B.

[0048] It will be understood that when a layer, region or element is referred to as being "connected to" another layer, region or element, it can be directly or indirectly connected to the other layer, region or element. That is, for example, there may be an intermediate layer, region or element. For example, it will be understood that when a layer, region or element is referred to as being "electrically connected to" another layer, region or element, it can be directly or indirectly electrically connected to the other layer, region or element. That is, for example, there may be an intermediate layer, region or element.

[0049] Figure 1 is a perspective view schematically showing a display device according to an exemplary embodiment. Figure 2 is a cross-sectional view schematically showing a display device according to an exemplary embodiment, the cross-sectional view corresponding to the cross-section taken along Figure 1 the line I-I'.

[0050] The display device according to one or more exemplary embodiments can be implemented with an electronic device such as a smart phone, a mobile phone, a smart watch, a navigation device, a game console, a television (TV), a vehicle head unit, a laptop computer, a notebook computer, a tablet computer, a personal media player (PMP), or a personal digital assistant (PDA). In addition, the electronic device can be a flexible device.

[0051] The display device 1 may include a display area DA in which an image is displayed and a peripheral area PA around the display area DA. The display device 1 can use light emitted from a plurality of pixels arranged in the display area DA to provide a specific image.

[0052] In a plan view of the display area DA, the display area DA may have a rectangular shape, such as Figure 1As shown. The present invention is not limited thereto. In an exemplary embodiment, the display area DA may have a polygonal shape, such as a triangular, pentagonal, or hexagonal shape; or may have an irregular shape, such as a circular or oval shape.

[0053] The peripheral area PA around the display area DA may be of a type of non-display area where no pixels are arranged. In an exemplary embodiment, the peripheral area PA may be a pixel-free area. The display area DA may be completely surrounded by the peripheral area PA. Various signal lines for supplying electrical signals to the display area DA and pads to which a printed circuit board (PCB) or a driver integrated circuit (IC) chip is attached may be arranged in the peripheral area PA.

[0054] Hereinafter, an organic light-emitting display device will be described as an example of the display device 1 according to an exemplary embodiment. However, the display device according to the present disclosure is not limited thereto. In an exemplary embodiment, examples of the display device 1 according to the present disclosure may include an inorganic light-emitting display device, an inorganic electroluminescence (EL) display device, or a quantum dot light-emitting display device.

[0055] Referring to Figure 2 , the display device 1 may include a display panel 10, an input sensing layer 40 located on the display panel 10, an optical function layer 50, and a window 60. The window 60 may cover the optical function layer 50.

[0056] The display panel 10 may display an image. The display panel 10 includes pixels arranged in the display area DA. The pixels may include display elements. The display elements may be connected to pixel circuits. The display elements may include organic light-emitting diodes or quantum organic light-emitting diodes.

[0057] The input sensing layer 40 may be configured to obtain coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes or touch electrodes and traces connected to the sensing electrodes. The input sensing layer 40 may be located on the display panel 10. The input sensing layer 40 may be configured to sense an external input by using the mutual capacitance method and / or the self-capacitance method.

[0058] The input sensing layer 40 may be directly formed on the display panel 10, or may be formed separately from the display panel 10 and then may be coupled to the display panel 10 by using an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 may be continuously formed after performing the process of forming the display panel 10. In this case, the input sensing layer 40 may be a part of the display panel 10, and there may be no adhesive layer between the input sensing layer 40 and the display panel 10. In Figure 2 , the input sensing layer 40 is interposed between the display panel 10 and the optical function layer 50. However, the present invention is not limited thereto. In an exemplary embodiment, the input sensing layer 40 may be located on the optical function layer 50.

[0059] The optical functional layer 50 may include an antireflection layer. The antireflection layer may be configured to reduce the reflectance of light (external light) incident on the display panel 10 from the outside through the window 60. The antireflection layer may include a phase retarder and a polarizer. The phase retarder may be of a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be of a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a specific arrangement. The phase retarder and the polarizer may further include a protective film. The phase retarder and the polarizer themselves or the protective film may be defined as a base layer for the antireflection layer.

[0060] In an exemplary embodiment, the antireflection layer may include a black matrix and a color filter. The color filter may be arranged in consideration of the color of light emitted from each pixel of the display panel 10. In another embodiment, the antireflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located on different layers. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may undergo destructive interference. Accordingly, the reflectance of external light may be reduced.

[0061] The optical functional layer 50 may include a lens layer. The lens layer may be configured to increase the emission efficiency of light emitted from the display panel 10 or to reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or multiple layers having different refractive indices. The optical functional layer 50 may include both the above-described antireflection layer and the lens layer or one of them.

[0062] In an exemplary embodiment, the optical functional layer 50 may be continuously formed after performing a process of forming the display panel 10 and / or the input sensing layer 40. In this case, there may be no adhesive layer between the optical functional layer 50 and the display panel 10 and / or the input sensing layer 40.

[0063] Figure 3 is a plan view schematically showing a display panel according to an exemplary embodiment. Figure 4 is a cross-sectional view schematically showing one pixel of a display panel according to an exemplary embodiment. For ease of description and clarity of the drawing, Figure 4 the thin film encapsulation layer as an encapsulation member is omitted.

[0064] Referring to Figure 3 , the display panel 10 may include a display area DA and a peripheral area PA. Figure 3 shows a substrate 100 of the display panel 10. For example, the substrate 100 may have a first region corresponding to the display area DA and a second region corresponding to the peripheral area PA.

[0065] The substrate 100 may include various materials, such as glass, metal, or plastic. In an embodiment, the substrate 100 may include a flexible material. Here, the flexible material refers to a substrate that can be bent, folded, or rolled. The substrate 100 made of a flexible material may include ultra-thin glass, metal, or plastic.

[0066] The display panel 10 includes a plurality of pixels P disposed in a display area DA. Each of the plurality of pixels P may include an organic light-emitting diode OLED as a display element, as Figure 4 shown. The organic light-emitting diode OLED may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and capacitors. Each of the plurality of pixels P may emit red light, green light, blue light, or white light from, for example, the organic light-emitting diode OLED.

[0067] The organic light-emitting diode OLED may include a pixel electrode 221, a counter electrode 223 spaced apart from the pixel electrode 221, and an intermediate layer 222 interposed between the pixel electrode 221 and the counter electrode 223.

[0068] The pixel electrode 221 is located on the planarization layer PNL. The pixel electrode 221 may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrode 221 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In an exemplary embodiment, the pixel electrode 221 may further include a layer including ITO, IZO, ZnO, or In2O3 on / under the above reflective layer.

[0069] The pixel defining layer PDL may be formed on the pixel electrode 221. The pixel defining layer PDL may include an opening OP for exposing the upper surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. For example, the opening OP may extend through the pixel defining layer PDL to expose the upper surface of the pixel electrode 221. The pixel defining layer PDL may include an organic insulating material. In an exemplary embodiment, the pixel defining layer PDL may include an organic insulating material or an inorganic insulating material. The emission region may be defined by the opening OP of the pixel defining layer PDL. The emission region may be the region where the emission layer 222b is located.

[0070] The intermediate layer 222 may include an emission layer 222b. The intermediate layer 222 may further include a first functional layer 222a under the emission layer 222b and / or a second functional layer 222c on the emission layer 222b. The emission layer 222b may include a polymer or a small molecular weight organic material that emits light of a certain color.

[0071] The first functional layer 222a may have a single-layer structure or a multi-layer structure. For example, when the first functional layer 222a includes a polymer material, the first functional layer 222a, which is a hole transport layer (HTL) having a single-layer structure, may include poly-(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a includes a small molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and an HTL.

[0072] The second functional layer 222c may be omitted. For example, when the first functional layer 222a and the emission layer 222b include polymer materials, the second functional layer 222c may be formed. The second functional layer 222c may have a single-layer structure or a multi-layer structure. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0073] The emission layer 222b of the intermediate layer 222 may be located in each pixel. For example, the emission layer 222b may be patterned to correspond to the pixel electrode 221. Different from the emission layer 222b, each of the first functional layer 222a and the second functional layer 222c of the intermediate layer 222 may be formed as a single body to correspond to a plurality of pixels P.

[0074] The counter electrode 223 may include a conductive material having a small work function. For example, the counter electrode 223 may include a (semi)transparent layer, and the (semi)transparent layer includes Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereof. In an exemplary embodiment, the counter electrode 223 may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer including the above materials.

[0075] The cover layer 230 may be located on the counter electrode 223. For example, the cover layer 230 may include lithium fluoride (LiF), and may be formed by using thermal deposition. In some exemplary embodiments, the cover layer 230 may be omitted.

[0076] A scan driver 1100 for providing a scan signal to a pixel circuit connected to each pixel P, a data driver 1200 for providing a data signal to a pixel circuit connected to each pixel P, and a main power line (not shown) for providing a first power voltage and a second power voltage may be arranged in the peripheral area PA. In Figure 3 this case, the data driver 1200 is adjacent to one side of the substrate 100. However, the present invention is not limited thereto. In an exemplary embodiment, the data driver 1200 may be arranged on a flexible printed circuit board (FPCB) electrically connected to pads arranged on one side of the display panel 10.

[0077] Figure 5 It is a schematic layout diagram of a plurality of pixels in a display area of a display device according to an exemplary embodiment. Figure 5 The arrangement of the pixels shown in may correspond to the arrangement of the emission regions of the plurality of pixels. The emission region may be the region where the emission layer 222b is located as shown in Figure 4 the figure.

[0078] For example, the display area DA may include a first pixel P1, a second pixel P2, and a third pixel P3. The first pixel P1, the second pixel P2, and the third pixel P3 may be repeatedly arranged in the x-direction (first direction) and the y-direction (second direction) according to certain patterns in the display area DA. Each of the first pixel P1, the second pixel P2, and the third pixel P3 may include an organic light-emitting diode OLED. The organic light-emitting diode OLED of each pixel may be arranged on the upper layer of the pixel circuit. The organic light-emitting diode OLED may be exactly located above the pixel circuit to overlap with the pixel circuit, or may be offset from the pixel circuit to overlap with a part of the pixel circuit of another pixel arranged in an adjacent row or column.

[0079] The first pixel P1 may include a first emission region EA1, the second pixel P2 may include a second emission region EA2, and the third pixel P3 may include a third emission region EA3. The emission region of the pixel as the region where the emission layer is located may be defined by an opening of a pixel defining layer as shown in Figure 4 the figure.

[0080] The first emission region EA1 of the first pixel P1 and the third emission region EA3 of the third pixel P3 may be alternately arranged in the odd-numbered columns in the y-direction. The second emission region EA2 of the second pixel P2 may be repeatedly arranged in the even-numbered columns in the y-direction. In Figure 5 the figure, for ease of description, it is assumed that the pixels are arranged in four columns 1M to 4M and two rows 1N and 2N. The arrangement of the pixels in the display area DA will be described with reference to the four columns 1M to 4M and the two rows 1N and 2N. For example, the first emission region EA1 of the first pixel P1 and the third emission region EA3 of the third pixel P3 may be alternately arranged in the first column 1M and the third column 3M in the y-direction. The second emission region EA2 of the second pixel P2 may be repeatedly arranged in the second column 2M and the fourth column 4M. The second column 2M is between the first column 1M and the third column 3M. The third column 3M is between the second column 2M and the fourth column 4M. The arrangement of the first emission region EA1 of the first pixel P1 and the third emission region EA3 of the third pixel P3 in the first column 1M may be opposite to the arrangement of the first emission region EA1 of the first pixel P1 and the third emission region EA3 of the third pixel P3 in the third column 3M.

[0081] The first emission region EA1 of the first pixel P1 and the third emission region EA3 of the third pixel P3 may be alternately arranged in the x direction in the first sub-row 1SN of each of row 1N and row 2N, and the second emission region EA2 of the second pixel P2 may be repeatedly arranged in the x direction in the second sub-row 2SN of each of row 1N and row 2N. For example, the first emission region EA1 of the first pixel P1, the second emission region EA2 of the second pixel P2, the third emission region EA3 of the third pixel P3, and the second emission region EA2 of the second pixel P2 may be repeatedly arranged in a zigzag manner in each of row 1N and row 2N.

[0082] The first emission region EA1 of the first pixel P1, the second emission region EA2 of the second pixel P2, and the third emission region EA3 of the third pixel P3 may have different areas. In an exemplary embodiment, the third emission region EA3 of the third pixel P3 may have an area larger than the area of the first emission region EA1 of the first pixel P1. Moreover, the third emission region EA3 of the third pixel P3 may have an area larger than the area of the second emission region EA2 of the second pixel P2. The first emission region EA1 of the first pixel P1 may have an area larger than the area of the second emission region EA2 of the second pixel P2. However, the present invention is not limited thereto. In an exemplary embodiment, the third emission region EA3 of the third pixel P3 may have the same area as the area of the first emission region EA1 of the first pixel P1, and each of the first emission region EA1 and the third emission region EA3 may have an area larger than the area of the second emission region EA2. In an exemplary embodiment, the first emission region EA1 of the first pixel P1 may have an area larger than the areas of the second emission region EA2 of the second pixel P2 and the third emission region EA3 of the third pixel P3.

[0083] The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape (such as a rectangular shape or an octagonal shape), a circular shape, or an elliptical shape. The polygonal shape may also include a shape in which the vertices are rounded.

[0084] In an exemplary embodiment, as Figure 5 shown, the first pixel P1 may be a red pixel R that emits red light, the second pixel P2 may be a green pixel G that emits green light, and the third pixel P3 may be a blue pixel B that emits blue light. In an exemplary embodiment, the first pixel P1 may be a red pixel R, the second pixel P2 may be a blue pixel B, and the third pixel P3 may be a green pixel G.

[0085] The pixel arrangement according to an exemplary embodiment is not limited to the above arrangement. For example, the present disclosure can be applied to pixel arrangements having a stripe arrangement, a mosaic arrangement, or a triangular arrangement. In addition, the present disclosure can also be applied to a pixel arrangement structure that further includes white pixels for emitting white light.

[0086] Figure 6 is a circuit diagram schematically showing a pixel circuit of a pixel of a display panel according to an exemplary embodiment.

[0087] Referring to Figure 6 , the pixel circuit PC of the pixel P may include first to seventh transistors T1 to T7 and a capacitor Cst. The first to seventh transistors T1 to T7 can be implemented with thin film transistors.

[0088] The pixel P may be connected to a first scan line SL1 for transmitting a scan signal Sn, a second scan line SL2 for transmitting a previous scan signal Sn−1, a third scan line SL3 for transmitting a scan signal Sn, an emission control line EL for transmitting an emission control signal En, and a data line DL for transmitting a data signal Dm. The first scan line SL1 and the third scan line SL3 may be electrically connected to each other, and the same scan signal Sn may be applied to the first scan line SL1 and the third scan line SL3.

[0089] A power supply voltage line PL may be configured to transmit a first power supply voltage ELVDD to the first transistor T1. A first initialization voltage line VL1 may be configured to transmit an initialization voltage Vint to the first transistor T1. A second initialization voltage line VL2 may be configured to transmit an initialization voltage Vint to the seventh transistor T7.

[0090] The first scan line SL1, the second scan line SL2, the third scan line SL3, the emission control line EL, and the first initialization voltage line VL1 and the second initialization voltage line VL2 may extend in the x direction and may be spaced apart from each other in the y direction. The data line DL and the power supply voltage line PL may extend in the y direction and may be spaced apart from each other in the x direction.

[0091] The pixel circuit PC may include first to seventh transistors T1 to T7 and a capacitor Cst. The x direction and the y direction refer to the directions in the layout of the pixel circuit PC that will be described with reference to Figure 8 , Figure 9A and Figure 9B for the layout of the pixel circuit PC.

[0092] The first transistor T1 includes a gate electrode G1, a source electrode S1 connected to a power supply voltage line PL via a fifth transistor T5, and a drain electrode D1 electrically connected to a pixel electrode of an organic light-emitting diode OLED via a sixth transistor T6. The gate electrode G1 of the first transistor T1 is connected to a lower electrode CE1 of a capacitor Cst, a drain electrode D3 of a third transistor T3, and a drain electrode D4 of a fourth transistor T4 at a node N. The first transistor T1 serves as a driving transistor, receives a data signal Dm according to a switching operation of a second transistor T2, and supplies a current to the organic light-emitting diode OLED.

[0093] The second transistor T2 (switching transistor) includes a gate electrode G2 connected to a first scan line SL1, a source electrode S2 connected to a data line DL, and a drain electrode D2 connected to a source electrode S1 of the first transistor T1. The second transistor T2 is turned on according to a scan signal Sn transmitted via the first scan line SL1, and performs a switching operation of transmitting the data signal Dm transmitted to the data line DL to the source electrode S1 of the first transistor T1.

[0094] The third transistor T3 (compensation transistor) includes a gate electrode G3 connected to the first scan line SL1, a source electrode S3 connected to a drain electrode D1 of the first transistor T1, and a drain electrode D3 connected to the lower electrode CE1 of the capacitor Cst, a drain electrode D4 of the fourth transistor T4, and a gate electrode G1 of the first transistor T1. The source electrode S3 of the third transistor T3 is connected to the pixel electrode of the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3 is turned on according to the scan signal Sn transmitted via the first scan line SL1, and diode-connects the first transistor T1. The third transistor T3 compensates for the threshold voltage of the first transistor T1.

[0095] The fourth transistor T4 (first initialization transistor) includes a gate electrode G4 connected to a second scan line SL2, a source electrode S4 connected to a first initialization voltage line VL1, and a drain electrode D4 connected to the lower electrode CE1 of the capacitor Cst, a drain electrode D3 of the third transistor T3, and a gate electrode G1 of the first transistor T1. The fourth transistor T4 is turned on according to a previous scan signal Sn-1 transmitted via the second scan line SL2, and transmits an initialization voltage Vint to the gate electrode G1 of the first transistor T1, thereby initializing the gate voltage of the first transistor T1.

[0096] The fifth transistor T5 (first emission control transistor) includes a gate electrode G5 connected to an emission control line EL, a source electrode S5 connected to the power supply voltage line PL, and a drain electrode D5 connected to the source electrode S1 of the first transistor T1 and the drain electrode D2 of the second transistor T2.

[0097] The sixth transistor T6 (second emission control transistor) includes a gate electrode G6 connected to an emission control line EL, a source electrode S6 connected to a drain electrode D1 of the first transistor T1 and a source electrode S3 of the third transistor T3, and a drain electrode D6 connected to a pixel electrode of the organic light-emitting diode OLED.

[0098] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to an emission control signal En transmitted via the emission control line EL, so that current can flow through the organic light-emitting diode OLED.

[0099] The seventh transistor T7 (second initialization transistor) includes a gate electrode G7 connected to a third scan line SL3, a source electrode S7 connected to a drain electrode D6 of the sixth transistor T6 and a pixel electrode of the organic light-emitting diode OLED, and a drain electrode D7 connected to a second initialization voltage line VL2. The seventh transistor T7 is turned on according to a scan signal Sn transmitted via the third scan line SL3, and transmits an initialization voltage Vint to the pixel electrode of the organic light-emitting diode OLED, thereby initializing the pixel electrode of the organic light-emitting diode OLED. The seventh transistor T7 can be omitted.

[0100] The capacitor Cst may include a lower electrode CE1 connected to a gate electrode G1 of the first transistor T1 and an upper electrode CE2 connected to a power supply voltage line PL. The lower electrode CE1 of the capacitor Cst is also connected to a drain electrode D3 of the third transistor T3 and a drain electrode D4 of the fourth transistor T4.

[0101] The organic light-emitting diode OLED may include a pixel electrode, a counter electrode, and an emission layer interposed between the pixel electrode and the counter electrode. A second power supply voltage ELVSS may be applied to the counter electrode. The organic light-emitting diode OLED may receive a driving current I from the first transistor T1 OLED to emit light and display an image.

[0102] In an embodiment, the positions of the source electrode and the drain electrode of each of the first transistor T1 to the seventh transistor T7 may be changed according to the type of the transistor (p-type or n-type) and / or its operating conditions. Figure 6 The transistor is a p-type metal oxide semiconductor (MOS) transistor. The present invention is not limited thereto. In an exemplary embodiment, Figure 6 the transistor may be an n-type MOS transistor.

[0103] In Figure 6In [the figure], the third transistor T3 may include dual gate electrodes such that two transistors can be connected in series. Similarly, the fourth transistor T4 may include dual gate electrodes such that two transistors can be connected in series. In an exemplary embodiment, compared with a single transistor, the third transistor T3 including two sub-transistors connected in series may have a reduced channel capacitance to have a faster high-frequency response and lower power consumption.

[0104] Figures 7A to 7D Cross-sectional views schematically showing thin film transistors according to exemplary embodiments are shown, respectively. Figures 7A to 7D are respectively Figure 6 a cross-sectional view of the third transistor T3 of [the figure]. In an exemplary embodiment, the third transistor T3 may have the same configuration as the fourth transistor T4. Hereinafter, the third transistor T3 will be described as an example, and this may also apply to the fourth transistor T4.

[0105] Referring to Figure 7A , the third thin film transistor T3 may include a semiconductor layer A3, a gate electrode G3 on and insulated from the semiconductor layer A3, a source electrode S3, and a drain electrode D3.

[0106] A buffer layer BL may be located on the substrate 100, and the semiconductor layer A3 of the third transistor T3 may be located on the buffer layer BL.

[0107] The semiconductor layer A3 may include a first channel region C31, a second channel region C32, a source region S3', a drain region D3', and an intermediate region M3. The semiconductor layer A3 may include polysilicon. In an exemplary embodiment, the semiconductor layer A3 may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The third thin film transistor T3 includes two channel regions, the first channel region C31 and the second channel region C32, separated by the intermediate region M3.

[0108] The gate electrode G3 may include a first gate electrode G31 overlapping the first channel region C31 and a second gate electrode G32 overlapping the second channel region C32. The gate electrode G3 may include a low-resistance metal material. The gate electrode G3 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and the gate electrode G3 may have a multi-layer structure or a single-layer structure including the above materials. A first gate insulating layer GI1 may be interposed between the semiconductor layer A3 and the gate electrode G3. The first gate electrode G31 and the second gate electrode G32 are connected to the first scan line SL1, and thus, receive the same signal of the scan signal Sn transmitted via the first scan line SL1.

[0109] The source electrode S3 and the drain electrode D3 may be electrically connected to the source region S3' and the drain region D3' of the semiconductor layer A3, respectively. In an exemplary embodiment, the third transistor T3 includes a first sub-transistor and a second sub-transistor connected in series with each other. The first sub-transistor includes a first gate electrode G31, a first channel region C31, a source region S3', and an intermediate region M3. The second sub-transistor includes a second gate electrode G32, a second channel region C32, a drain region D3', and an intermediate region M3. The first sub-transistor and the second sub-transistor are connected in series with each other via the intermediate region M3 shared by the two sub-transistors. In the first sub-transistor, the intermediate region M3 serves as a drain region, and in the second sub-transistor, the intermediate region M3 serves as a source region. The intermediate region may also be referred to as a common source-drain region.

[0110] The source electrode S3 and the drain electrode D3 may include a material having good electrical conductivity. The source electrode S3 and the drain electrode D3 may include a conductive material, the conductive material including Mo, Al, Cu, or Ti, and the source electrode S3 and the drain electrode D3 may have a multi-layer structure or a single-layer structure including the above materials. In an exemplary embodiment, the source electrode S3 and the drain electrode D3 may have a multi-layer structure including Ti / Al / Ti. The second gate insulating layer GI2 and the interlayer insulating layer IL may be interposed between the gate electrode G3 and the source electrode S3 and between the gate electrode G3 and the drain electrode D3. In an exemplary embodiment, the second gate insulating layer GI2 may cover the gate electrode G3, and the interlayer insulating layer IL may be disposed on the second gate insulating layer GI2.

[0111] Each of the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IL may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IL may have a single-layer structure or a multi-layer structure including the above materials.

[0112] The planarization layer PNL may be located on the source electrode S3 and the drain electrode D3. For example, the planarization layer PNL may be disposed on the interlayer insulating layer IL to cover the source electrode S3 and the drain electrode D3.

[0113] The shielding layer SHL may overlap with an intermediate region of the semiconductor layer A3 (i.e., an intermediate region that is part between the first channel region and the second channel region or a common source-drain region). In an exemplary embodiment, the shielding layer SHL may overlap with the common source-drain region not covered by the upper electrode layer. For example, unlike the source region S3' and the drain region D3' respectively connected to the source electrode S3 and the drain electrode D3, the common source-drain region has no corresponding electrode connected thereto. At least a part of the shielding layer SHL may overlap with the common source-drain region of the semiconductor layer A3 not covered by the source electrode S3, the drain electrode D3, and the gate electrode G3. For example, as Figure 7A shown, the shielding layer SHL may overlap with an intermediate region M3 (i.e., the common source-drain region) between the first channel region C31 and the second channel region C32. The intermediate region M3 serving as both the source region of the second sub-transistor and the drain region of the first sub-transistor may be doped with impurities. For example, the intermediate region M3 may be a region including a drain region adjacent to the first channel region C31 and a source region adjacent to the second channel region C32.

[0114] The shielding layer SHL may include at least two layers located on different layers. Each of the different shielding layers SHL may overlap with at least a part of the intermediate region M3. At least a part of the different shielding layers SHL may overlap with each other. The parts of the different shielding layers SHL may include different materials, and other parts of the different shielding layers SHL may include the same materials.

[0115] In an exemplary embodiment, the shielding layer SHL may overlap with a region between two channel regions of a thin film transistor including a double gate electrode, i.e., the intermediate region M3 of the semiconductor layer A3. Therefore, the region exposed by light that can be applied from above the substrate 100 is minimized, so that damage to the semiconductor layer A3 can be minimized or prevented.

[0116] Moreover, in an exemplary embodiment of the present disclosure, the shielding layer SHL may be arranged in a multi-layer structure such that the exposed regions of the source region and the drain region of the semiconductor layer are minimized, and thus, the thin film transistor can be robustly protected from external light.

[0117] In an exemplary embodiment, as Figure 7A shown, the shielding layer SHL may include a first shielding layer SHL1 and a second shielding layer SHL2. The first shielding layer SHL1 may be between the second gate insulating layer GI2 and the interlayer insulating layer IL. The second shielding layer SHL2 may be located on the interlayer insulating layer IL. The planarization layer PNL may be located on the second shielding layer SHL2, covering the second shielding layer SHL2.

[0118] The first shielding layer SHL1 and the second shielding layer SHL2 may include different materials. For example, the first shielding layer SHL1 may include the same material as that used for forming the upper electrode CE2 of the capacitor Cst, and the second shielding layer SHL2 may include the same material as that used for forming the source electrode S3 and the drain electrode D3.

[0119] In an exemplary embodiment, as Figure 7B shown, in addition to the first shielding layer SHL1 and the second shielding layer SHL2, the shielding layer SHL may further include a third shielding layer SHL3. The first shielding layer SHL1 may be interposed between the second gate insulating layer GI2 and the interlayer insulating layer IL, the second shielding layer SHL2 may be interposed between the interlayer insulating layer IL and the first planarization layer PNL1, and the third shielding layer SHL3 may be interposed between the first planarization layer PNL1 and the second planarization layer PNL2.

[0120] The third shielding layer SHL3 may include the same material as that used for forming the first shielding layer SHL1 or the second shielding layer SHL2. The third shielding layer SHL3 may include a material different from that used for forming the first shielding layer SHL1 or the second shielding layer SHL2.

[0121] Figure 7C An example is shown in which the second gate insulating layer GI2 and two interlayer insulating layers including the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2 are arranged between the gate electrode G3 and the source electrode S3 and the drain electrode D3. The shielding layer SHL may include the first shielding layer SHL1 and the second shielding layer SHL2, and the first shielding layer SHL1 and the second shielding layer SHL2 may include the same material. For example, the first shielding layer SHL1 and the second shielding layer SHL2 may include the same material as that used for forming the upper electrode CE2 of the capacitor Cst. The first shielding layer SHL1 and the second shielding layer SHL2 may also include different materials.

[0122] In Figures 7A to 7C the embodiment of, each of the first shielding layer SHL1 and the second shielding layer SHL2 completely overlaps with the middle region M3 of the semiconductor layer A3. However, the present invention is not limited thereto. In an exemplary embodiment, as Figure 7D shown, each of the first shielding layer SHL1 and the second shielding layer SHL2 may partially overlap with the middle region M3 of the semiconductor layer A3. The first shielding layer SHL1 and the second shielding layer SHL2 are biased. Therefore, a part of the first shielding layer SHL1 overlapping with the middle region M3 of the semiconductor layer A3 may be different from a part of the second shielding layer SHL2 overlapping with the middle region M3 of the semiconductor layer A3. The second shielding layer SHL2 may overlap with the local region R of the first shielding layer SHL1.

[0123] Although not shown, inFigure 7D In an exemplary embodiment, the third shielding layer SHL3 may be further located on the first shielding layer SHL1 and the second shielding layer SHL2, as Figure 7B shown. The third shielding layer SHL3 may be offset with respect to the first shielding layer SHL1 and / or the second shielding layer SHL2, and thus, may partially overlap with the first shielding layer SHL1 and / or the second shielding layer SHL2. The present invention is not limited thereto. In an exemplary embodiment, the third shielding layer SHL3 may completely overlap with the first shielding layer SHL1 and the second shielding layer SHL2.

[0124] In Figures 7A to 7D , the first shielding layer SHL1, the second shielding layer SHL2, and the third shielding layer SHL3 may be electrically connected to a line having a constant voltage, and thus, a constant voltage may be applied to the first shielding layer SHL1, the second shielding layer SHL2, and the third shielding layer SHL3.

[0125] In Figures 7A to 7D , the source electrode S3 and the drain electrode D3 respectively connected to the source region S3' and the drain region D3' of the third thin film transistor T3 have been described. In some exemplary embodiments, the source region S3' and the drain region D3' may be a part of the source electrode S3 and a part of the drain electrode D3, respectively. Hereinafter, the source region and the drain region of the thin film transistor may be used as including the source electrode and the drain electrode, respectively.

[0126] Figure 8 is a layout diagram showing the positions of a plurality of thin film transistors and capacitors arranged in a pixel circuit of a display device according to an exemplary embodiment. Figure 9A and Figure 9B are Figure 8 an enlarged view of a region including the third thin film transistor. Figure 10 is along Figure 8 a schematic cross-sectional view of the display device taken along line II-II'; and Figure 11 is along Figure 8 a schematic cross-sectional view of the display device taken along line III-III'. Figure 8 The pixel circuit PC of Figure 6 may be the pixel circuit shown in

[0127] Referring to Figure 8 , the pixel circuit PC of the display device according to an exemplary embodiment may include a first scan line SL1, a second scan line SL2, a third scan line SL3, an emission control line EL, a first initialization voltage line VL1, and a second initialization voltage line VL2 extending in the x direction, and may include a data line DL and a power supply voltage line PL extending in the y direction intersecting the x direction.

[0128] Moreover, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor Cst. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be implemented by thin film transistors. Hereinafter, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 will be described.

[0129] The first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 may be arranged along the semiconductor layer ACT, and a partial region of the semiconductor layer ACT may include the semiconductor layers of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7.

[0130] Hereinafter, reference will be made to Figure 10 and Figure 11 to describe this.

[0131] The semiconductor layer ACT may be formed on the substrate 100. In an exemplary embodiment, a buffer layer 110 may be formed on the substrate 100, and the semiconductor layer ACT may be formed on the buffer layer 110.

[0132] The substrate 100 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate 100 may have a multilayer structure. For example, as shown in the enlarged view of Figure 10 the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104.

[0133] The first base layer 101 and the second base layer 103 may include the above polymer resin. The first barrier layer 102 and the second barrier layer 104, as layers for preventing the penetration of external foreign substances, may have a structure including, for example, silicon nitride (SiN x ) and silicon oxide (SiO xa single-layer or multi-layer structure of an inorganic material.

[0134] The buffer layer 110 may be disposed on the upper surface of the substrate 100 to provide a planarized surface. The buffer layer 110 may include an oxide layer such as silicon oxide (SiO x ) and / or a nitride layer such as silicon nitride (SiN x ) or silicon oxynitride (SiON).

[0135] The semiconductor layer ACT may include low-temperature polycrystalline silicon (LTPS). The polycrystalline silicon material has a high electron mobility (100 / Vs or higher), low power consumption, and excellent reliability. In an exemplary embodiment, the semiconductor layer ACT may include amorphous silicon (a-Si) and / or an oxide semiconductor. The local semiconductor layers of the plurality of thin-film transistors may be formed of LTPS, and the other semiconductor layers of the semiconductor layer ACT may include a-Si and / or an oxide semiconductor.

[0136] The semiconductor layer ACT of each of the first thin-film transistor T1 to the seventh thin-film transistor T7 may include a source region, a drain region, and a channel region between the source region and the drain region. In an exemplary embodiment, each of the first thin-film transistor T1 to the seventh thin-film transistor T7 may be formed of a corresponding portion of the semiconductor layer ACT. The source region and the drain region may be doped regions near the channel region. The positions of the source region and the drain region may be reversed according to the exemplary embodiment. In an exemplary embodiment, the source region and the drain region may also be used as the source electrode and the drain electrode of the thin-film transistor.

[0137] The first gate insulating layer 111 may be located on the semiconductor layer ACT, and the gate electrode G1 of the first transistor T1, the first scan line SL1, the second scan line SL2, the third scan line SL3, and the emission control line EL may be located on the first gate insulating layer 111.

[0138] The first gate insulating layer 111 may include silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0139] The gate electrode G2 of the second thin film transistor T2 and the gate electrodes G31 and G32 of the third thin film transistor T3 may be a part of the first scan line SL1 that crosses the channel regions of the second thin film transistor T2 and the third thin film transistor T3 or a protruding part of the first scan line SL1. The gate electrodes G41 and G42 of the fourth thin film transistor T4 may be a part of the second scan line SL2 that crosses or partially crosses the semiconductor layer or a protruding part of the second scan line SL2. The gate electrode G7 of the seventh thin film transistor T7 may be a part of the third scan line SL3 that crosses the semiconductor layer. The gate electrode G5 of the fifth thin film transistor T5 and the gate electrode G6 of the sixth thin film transistor T6 may be a part of the emission control line EL that crosses or partially crosses the semiconductor layer or a protruding part of the emission control line EL. The gate electrode G1 of the first thin film transistor T1 may be arranged in an island shape.

[0140] The second gate insulating layer 112 may be disposed on the first scan line SL1, the second scan line SL2, the third scan line SL3, and the emission control line EL. The second gate insulating layer 112 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0141] The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may be arranged on the second gate insulating layer 112.

[0142] The electrode voltage line HL may cover at least a part of the gate electrode G1 of the first thin film transistor T1 and may be configured to form a capacitor Cst with the gate electrode G1 of the first thin film transistor T1. The lower electrode CE1 of the capacitor Cst may be formed as a single body with the gate electrode G1 of the first thin film transistor T1. For example, the gate electrode G1 of the first thin film transistor T1 may be used as the lower electrode CE1 of the capacitor Cst. The region of the electrode voltage line HL that overlaps with the gate electrode G1 of the first thin film transistor T1 may be the upper electrode CE2 of the capacitor Cst. Therefore, the second gate insulating layer 112 may be used as the dielectric layer of the capacitor Cst. An opening SOP may be formed in the upper electrode CE2 of the capacitor Cst. The node electrode 174 may be configured to electrically connect the lower electrode CE1 of the capacitor Cst to the drain region D3 of the third thin film transistor T3 through the opening SOP. For example, the node electrode 174 includes a part that extends through the interlayer insulating layer 113 and the second gate insulating layer 112 to contact the gate electrode G1. This part of the node electrode 174 extends through the upper electrode CE2 via the opening SOP without contacting the upper electrode CE2.

[0143] The first initialization voltage line VL1 may include a portion overlapping with the middle region M4 of the fourth thin film transistor T4. For example, the portion of the first initialization voltage line VL1 overlapping with the middle region M4 of the fourth thin film transistor T4 may be used as a shielding layer.

[0144] In a plan view, the second initialization voltage line VL2 may be interposed between the emission control line EL and the third scan line SL3.

[0145] The first shielding layer SHL1 may be located on the second gate insulating layer 112. A portion of the first shielding layer SHL1 may overlap with the middle region M3 of the third thin film transistor T3. Moreover, the first shielding layer SHL1 may overlap with the drain region D4 and the source region S4 of the fourth thin film transistor T4.

[0146] The first shielding layer SHL1, the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may have a single-layer structure or a multi-layer structure including one or more materials selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu.

[0147] The interlayer insulating layer 113 is located on the first shielding layer SHL1, the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2. The interlayer insulating layer 113 may include silicon oxide (SiO2), silicon nitride (SiN x )), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0148] The power supply voltage line PL, the node electrode 174, the first connection line 175, the second connection line 176, and the first connection electrode 177 and the second connection electrode 178 may be located on the interlayer insulating layer 113. The power supply voltage line PL, the node electrode 174, the first connection line 175, the second connection line 176, and the first connection electrode 177 and the second connection electrode 178 may include a conductive material containing Mo, Al, Cu, or Ti, and may have a multi-layer structure or a single-layer structure including the above materials. For example, the power supply voltage line PL, the node electrode 174, the first connection line 175, the second connection line 176, and the first connection electrode 177 and the second connection electrode 178 may have a multi-layer structure including Ti / Al / Ti.

[0149] The power supply voltage line PL can be between the data line DL and the data line DL' of the pixel circuit adjacent to the right side in the plan view. The power supply voltage line PL can be electrically connected to the upper electrode CE2 of the capacitor Cst through the contact hole 12 formed in the interlayer insulating layer 113. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the power supply voltage line PL. A part of the power supply voltage line PL that protrudes and extends in the x direction can be electrically connected to the drain region D5 of the fifth thin film transistor of the pixel circuit adjacent to the right side through the contact hole 13'. For example, Figure 8 the drain region D5 of the fifth thin film transistor of the pixel circuit PC shown in can be electrically connected to a part that protrudes and extends in the x direction from the power supply voltage line PL of the pixel circuit adjacent to the left side through the contact hole 13. A part of the power supply voltage line PL can overlap at least a part of the intermediate region M3 of the third thin film transistor.

[0150] As Figure 9A and Figure 10 shown in, the power supply voltage line PL can include a second shielding layer SHL2 that overlaps a part of the first shielding layer SHL1 that overlaps the intermediate region M3 of the third thin film transistor. For example, the second shielding layer SHL2 can be a part of the power supply voltage line PL. As Figure 9A shown in, the power supply voltage line PL can be electrically connected to the first shielding layer SHL1 through the contact hole 20. For example, the first shielding layer SHL1 and the second shielding layer SHL2 can receive a constant voltage from the power supply voltage line PL.

[0151] In the plan view, the first part 131 of the first shielding layer SHL1 can be between the data line DL and the node electrode 174, and can shield the coupling between the data line DL and the node electrode 174. The second part 132 of the first shielding layer SHL1 can overlap the intermediate region M3 of the third thin film transistor T3, and can shield the semiconductor layer A3 of the third thin film transistor T3 from external light. The first shielding layer SHL1 can include a third part 133 between the first part 131 and the second part 132. The third part 133 of the first shielding layer SHL1 can overlap the source region S4 and the drain region D4 of the fourth thin film transistor T4.

[0152] In Figure 9A the second part 132 of the first shielding layer SHL1 can partially overlap the intermediate region M3 of the third thin film transistor T3. And the second shielding layer SHL2 can overlap a part of the intermediate region M3 of the third thin film transistor T3 that does not overlap the second part 132 of the first shielding layer SHL1. The second shielding layer SHL2 can partially overlap the second part 132 of the first shielding layer SHL1 and the third part 133 of the first shielding layer SHL1. In an exemplary embodiment, as Figure 9BAs shown, the second shielding layer SHL2 can completely cover the middle region M3 of the third thin film transistor T3 and the second part 132 of the first shielding layer SHL1.

[0153] One end of the node electrode 174 can be electrically connected to the drain region D3 of the third thin film transistor T3 and the drain region D4 of the fourth thin film transistor T4 through the contact hole 14, and the other end of the node electrode 174 can be electrically connected to the gate electrode G1 of the first thin film transistor T1 through the contact hole 15. The contact hole 15 can overlap with the opening SOP formed in the upper electrode CE2 of the capacitor Cst.

[0154] One end of the first connection line 175 can be electrically connected to the source region S4 of the fourth thin film transistor T4 through the contact hole 16, and the other end of the first connection line 175 can be electrically connected to the first initialization voltage line VL1 through the contact hole 17.

[0155] One end of the second connection line 176 can be electrically connected to the drain region D7 of the seventh thin film transistor T7 through the contact hole 18, and the other end of the second connection line 176 can be electrically connected to the second initialization voltage line VL2 through the contact hole 19. The same constant voltage (e.g., -2V) can be applied to the first initialization voltage line VL1 and the second initialization voltage line VL2.

[0156] The first connection electrode 177 can be electrically connected to the source region S2 of the second thin film transistor T2 through the contact hole 11.

[0157] The second connection electrode 178 can be electrically connected to the drain region D6 of the sixth thin film transistor T6 through the contact hole 21.

[0158] The first planarization layer 114 can be located on the power supply voltage line PL, the node electrode 174, the first connection line 175 and the second connection line 176, and the first connection electrode 177 and the second connection electrode 178. The data line DL and the third connection electrode 181 can be located on the first planarization layer 114.

[0159] The data line DL can be electrically connected to the first connection electrode 177 through the contact hole 23, thereby being electrically connected to the source region S2 of the second thin film transistor T2.

[0160] The third connection electrode 181 can be electrically connected to the second connection electrode 178 through the contact hole 24, thereby being electrically connected to the drain region D6 of the sixth thin film transistor T6. The third connection electrode 181 can be electrically connected to the pixel electrode 221 through the contact hole 27.

[0161] Although not shown, as Figure 7BAs shown, the third shielding layer is located on the same layer as the data line DL, and at least a part thereof overlaps with the middle region M3 of the third thin film transistor T3. At least a part of the third shielding layer may overlap with the first shielding layer SHL1 and / or the second shielding layer SHL2.

[0162] The second planarization layer 115 may be located on the data line DL and the third connection electrode 181, and the organic light emitting diode OLED may be located on the second planarization layer 115.

[0163] The first planarization layer 114 and the second planarization layer 115 may have a flat upper surface so that the pixel electrode 221 can be formed flatly. The first planarization layer 114 and the second planarization layer 115 may have a single-layer structure or a multi-layer structure including an organic material. The first planarization layer 114 and the second planarization layer 115 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PXMMA), or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a polyvinyl alcohol polymer, and a mixture thereof.

[0164] In an exemplary embodiment, the first planarization layer 114 and the second planarization layer 115 may include an inorganic material. The first planarization layer 114 and the second planarization layer 115 may include silicon oxide (SiO2), silicon nitride (SiN x )), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). When the first planarization layer 114 and the second planarization layer 115 include an inorganic material, chemical mechanical polishing may be performed to form the first planarization layer 114 and the second planarization layer 115. In an exemplary embodiment, the first planarization layer 114 and the second planarization layer 115 may include both an organic material and an inorganic material.

[0165] The pixel defining layer 116 may be located on the second planarization layer 115. The pixel defining layer 116 may have an opening for exposing a part of the pixel electrode 221, thereby defining the emission region of the pixel. Moreover, the pixel defining layer 116 may increase the distance between the edge of the pixel electrode 221 and the counter electrode 223, thereby preventing arc discharge from occurring at the edge of the pixel electrode 221. The pixel defining layer 116 may include an organic insulating material, such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin.

[0166] The organic light emitting diode OLED may include a pixel electrode 221, an intermediate layer 222, and an opposite electrode 223. Figure 4 Same as the description. Figure 4 The planarization layer PNL can be Figure 10 The second planarization layer 115. Figure 4 As depicted, the intermediate layer 222 includes the emission layer 222 b , the first functional layer 222 a , and / or the second functional layer 222 c . The opposing electrode 223 may be formed as a single body to correspond to the plurality of pixel electrodes 221 .

[0167] The first initialization voltage line VL1 , the second scan line SL2 , the third initialization voltage line VL3 , and the third scan line SL3 may be shared between two pixel circuits adjacent to each other in the y direction.

[0168] For example, the first initialization voltage line VL1 and the second scan line SL2 may be electrically connected to a position located at a Figure 8 . Therefore, the seventh thin film transistor of the adjacent pixel circuit can receive the previous scan signal applied to the second scan line SL2 as a scan signal, and can receive the initialization voltage from the first initialization voltage line VL1. Similarly, the second initialization voltage line VL2 and the third scan line SL3 can be electrically connected to the upper portion of the pixel circuit PC in the y direction shown in FIG. Figure 8 The fourth thin film transistor of the adjacent pixel circuit at the lower part in the y direction of the pixel circuit PC shown in the figure, and therefore the fourth thin film transistor of the adjacent pixel circuit can receive the scan signal applied to the third scan line SL3 as the previous scan signal and can receive the initialization voltage from the second initialization voltage line VL2.

[0169] Although not shown, a thin film encapsulation layer (not shown) or a sealing substrate (not shown) may be located on the relative electrode 223, thereby covering the organic light emitting diode OLED to protect the organic light emitting diode OLED. The thin film encapsulation layer (not shown) may cover the display area DA and may extend to the outside of the display area DA. The thin film encapsulation layer may include at least one inorganic encapsulation layer including an inorganic material and at least one organic encapsulation layer including an organic material. In some exemplary embodiments, the thin film encapsulation layer may have a stacked structure of a first inorganic encapsulation layer / organic encapsulation layer / second inorganic encapsulation layer. The sealing substrate (not shown) may be spaced apart from the substrate 100 and may be bonded to the substrate 100 in the peripheral area PA using a sealing member such as a sealant or glass material.

[0170] Also, a spacer for preventing mask imprint may be further included on the pixel defining layer 116 .

[0171] exist Figure 8Among them, a double shielding layer including a first shielding layer SHL1 and a second shielding layer SHL2 can be positioned to overlap with an intermediate region M3 of a third thin film transistor T3, and a first initialization voltage line VL1 can be positioned as a single shielding layer to overlap with an intermediate region M4 of a fourth thin film transistor T4. In an exemplary embodiment, a shielding layer on the interlayer insulating layer 113 (e.g., Figure 10 the second shielding layer SHL2 therein) and / or a shielding layer on the first planarization layer 114 (e.g., Figure 7B the third shielding layer SHL3 therein) can be further positioned to overlap with the intermediate region M4 of the fourth thin film transistor T4. The shielding layer on the interlayer insulating layer 113 and the power supply voltage line PL can include the same material and can be located on the same layer. The shielding layer on the first planarization layer 114 and the data line DL can include the same material and can be located on the same layer.

[0172] In Figure 8 , Figure 10 and Figure 11 , the data line DL can be located on the first planarization layer 114 and can be electrically connected to a source region S2 of the second thin film transistor T2 through a first connection electrode 177. The power supply voltage line PL can be located on the interlayer insulating layer 113. The present invention is not limited thereto. In an exemplary embodiment, the data line DL and the power supply voltage line PL can be located on the same layer. In this case, the power supply voltage line PL can be positioned such that the data line DL and the power supply voltage line PL can be insulated from each other, and the second shielding layer as an element separated from the power supply voltage line PL can be provided in an island shape. The power supply voltage line PL can be electrically connected to the first shielding layer SHL1, and the island-shaped second shielding layer can be electrically connected to the first shielding layer SHL1. The second shielding layer and the power supply voltage line PL can include the same material and can be provided on the same layer (e.g., the first planarization layer 114), or the second shielding layer and the third connection electrode 181 can include the same material and can be provided on the same layer (e.g., the first planarization layer 114).

[0173] In a display device according to one or more embodiments, the external influence on the thin film transistor in a pixel can be minimized, so that high-quality images can be provided. The scope of the present disclosure is not limited by these effects.

[0174] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope defined by the following claims.

Claims

1. A display device, comprising: A pixel circuit disposed on a substrate; And A display element located on the pixel circuit, Wherein, the pixel circuit includes: A first thin film transistor including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer; A second thin film transistor including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode; A third thin film transistor including a third semiconductor layer and a third gate electrode insulated from the third semiconductor layer, A first shielding layer overlapping with a source region and a drain region of the third semiconductor layer and the second semiconductor layer; and A second shielding layer overlapping with the second semiconductor layer and stacked on the first shielding layer.

2. The display device according to claim 1, Among them, The second semiconductor layer includes a first channel region and a second channel region, Wherein, the second gate electrode includes a first sub-gate electrode overlapping with the first channel region and a second sub-gate electrode overlapping with the second channel region, and Wherein, the second shielding layer overlaps with a part between the first channel region and the second channel region.

3. The display device according to claim 2, Among them, The first sub-gate electrode and the second sub-gate electrode are located on the same layer.

4. The display device according to claim 1, Among them, The first shielding layer and the second shielding layer include the same material.

5. The display device according to claim 1, Among them, The first shielding layer and the second shielding layer include different materials from each other.

6. The display device according to claim 1, Among them, The pixel circuit further includes: A capacitor including an upper electrode and a part of the first gate electrode as a lower electrode; and A power supply voltage line connected to the upper electrode, Wherein, the upper electrode overlaps with the part of the first gate electrode.

7. The display device according to claim 6, Among them, The first shielding layer, the second shielding layer and the upper electrode include the same material.

8. The display device according to claim 6, Among them, The second shielding layer is a part of the power supply voltage line, and Wherein, the first shielding layer is connected to the power supply voltage line.

9. The display device according to claim 6, Among them, The first shielding layer and the upper electrode include the same material, and Wherein, the second shielding layer and the power supply voltage line include the same material.

10. The display device according to claim 1, Among them, The pixel circuit further includes: A capacitor including an upper electrode and a part of the first gate electrode as a lower electrode; A power supply voltage line connected to the upper electrode; and A third shielding layer stacked on the second shielding layer, Wherein, the second shielding layer is between the first shielding layer and the third shielding layer, Wherein, the upper electrode and the first shielding layer are located on the same layer, Wherein, the upper electrode overlaps with the part of the first gate electrode, Wherein, the power supply voltage line and the second shielding layer are located on the same layer, and Among them, the third shielding layer overlaps with the second semiconductor layer.

11. The display device according to claim 10, further comprising: A data line connected to the pixel circuit, wherein the data line and the third shielding layer are on the same layer.

12. The display device according to claim 11, Among them, The first shielding layer and the upper electrode are made of the same material, wherein the second shielding layer and the power supply voltage line are made of the same material, and wherein the third shielding layer and the data line are made of the same material.

13. The display device according to claim 10, Among them, The third shielding layer is connected to the power supply voltage line.

14. A display device, comprising: A pixel circuit disposed on a substrate; And A display element located on the pixel circuit, wherein the pixel circuit includes: A first thin film transistor, including: a first semiconductor layer including a first channel region and a second channel region, a first sub-gate electrode overlapping with the first channel region, and a second sub-gate electrode overlapping with the second channel region; A second thin film transistor, including: a second semiconductor layer including a third channel region, a fourth channel region, a source region, and a drain region, a third sub-gate electrode overlapping with the third channel region, and a fourth sub-gate electrode overlapping with the fourth channel region; A first shielding layer overlapping with a part between the first channel region and the second channel region and the source region and the drain region of the second semiconductor layer; and A second shielding layer stacked on the first shielding layer.

15. The display device according to claim 14, Among them, The first shielding layer and the second shielding layer are made of the same material.

16. The display device according to claim 14, Among them, The first shielding layer and the second shielding layer are made of different materials from each other.

17. The display device according to claim 14, Among them, The pixel circuit further includes: A capacitor, the capacitor including a lower electrode and an upper electrode, wherein the lower electrode, the first sub-gate electrode, and the second sub-gate electrode are on the same layer, and wherein the upper electrode overlaps with the lower electrode; and A power supply voltage line connected to the upper electrode of the capacitor, wherein the first shielding layer and the upper electrode of the capacitor are made of the same material, and wherein the second shielding layer and the power supply voltage line are made of the same material.

18. The display device according to claim 17, Among them, The second shielding layer is a part of the power supply voltage line, and wherein the first shielding layer is connected to the power supply voltage line.

19. The display device according to claim 18, Among them, The pixel circuit further includes: a third shielding layer located on the second shielding layer, wherein the third shielding layer overlaps with the part between the first channel region and the second channel region.

20. The display device according to claim 19, Further included are: A data line connected to the pixel circuit, wherein the data line and the third shielding layer are on the same layer.

Images