Bus voltage equalization regulation method for power converter and power converter

Abstract

The application provides a BUS voltage equalization regulation method of a power converter and the power converter. The method comprises the following steps: taking the difference between the BUS voltage of the positive maximum phase and the BUS voltage of the negative maximum phase in multiple phase voltages of the power converter as an error input of a voltage equalization loop to calculate a voltage equalization regulation duty ratio of each phase; determining a regulation direction of a driving duty ratio of each phase according to the difference between the BUS voltage of a main phase and the average value of the BUS voltages of all phases, wherein the main phase is a phase with the maximum absolute value in the multiple phase voltages; and performing equalization regulation on the BUS voltage of each phase according to the regulation direction of the driving duty ratio of each phase and the voltage equalization regulation duty ratio of each phase.

Description

Technical Field

[0001] This invention relates to the field of switching power supply conversion technology, and more specifically, to a BUS voltage equalization regulation method for a power converter and a power converter. Background Technology

[0002] Driven by both demand and technology, three-phase rectifier products have demonstrated a development trend of high power density, high efficiency, and low cost. With the continuous expansion of energy product types, three-phase DC power supply products have gradually expanded to charging pile modules and data center HVDC modules, with significantly increased power levels. Three-phase PFC topologies can be broadly categorized into three types: passive rectification, hybrid rectification, and active PFC. Early circuits using diode-based uncontrolled rectification are called passive rectification systems. The most typical application of hybrid rectification systems is injecting third harmonic current into the input side of the uncontrolled rectifier bridge to reduce THD. However, both passive and hybrid rectification suffer from high input current harmonic content and output voltage limitations imposed by the input voltage. Currently, active PFC circuits are more widely used.

[0003] Active power rectifiers (PFCs) can be divided into three-phase rectifiers and single-phase modular combined three-phase rectifiers. Three-phase rectifiers mainly include six-switch Boost, Vienna rectifiers, six-switch Buck, and Swiss rectifiers. The first two are step-up type, while the latter two are step-down type. Boost circuits can use higher bus voltages and have higher efficiency, making them the most commonly used three-phase rectifier topology. The Vienna rectifier, with its 3-level structure, reduces device stress and magnetic component size, offering higher efficiency and power density compared to the six-switch Boost, and is currently a widely used topology in the industry. Three-phase converters using modular single-phase circuits can achieve uniform stress across all switching devices. Each phase uses an H-bridge structure connected in a star or delta configuration to form the three-phase converter. The overall efficiency of the converter depends on the efficiency level of each power conversion unit. When the stress level of all switching devices is reduced, its performance will inevitably be superior to existing three-phase rectifiers. Single-phase modular combination conversion technology can improve the conversion efficiency of three-phase rectifiers to 98%. The application of wide bandgap devices and SMD power devices can increase the switching frequency, reduce the size of power devices and magnetic components, increase the overall power density, and thus reduce the overall cost.

[0004] Whether it's a traditional rectifier like the Vienna with two buses or a three-bus single-phase modular combined three-phase rectifier, the problem of uneven bus voltage exists. Due to differences in the hardware parameters of each phase, or when the load is unbalanced or the three-phase input voltage is unbalanced, the bus voltage will be uneven. Uneven bus voltage will lead to excessive output ripple, deterioration of various input indicators, and may even cause the higher voltage of the bus to exceed the withstand voltage range of the DC capacitor and other switching devices, thereby damaging the devices.

[0005] Therefore, additional control strategies are needed to achieve voltage equalization across the various bus paths. Existing voltage equalization strategies are divided into hardware and software strategies. Hardware strategies involve adding an auxiliary voltage equalization circuit to the circuit topology. This circuit typically consists of multiple switching transistors, capacitors, inductors, and other components, increasing component costs. Existing software strategies involve adding a voltage equalization control strategy in software. This involves sampling and subtracting the voltages of the two bus paths, adjusting the difference through a PI loop, and ultimately controlling the on / off time of each switching transistor to achieve voltage equalization between the two bus paths. This solution does not increase component costs, but it is only suitable for traditional three-phase rectifiers with two bus paths and is not applicable to single-phase modular combined three-phase rectifiers with three bus paths. Calculating the voltage equalization error for three or more bus paths by continuing the two-bus voltage equalization strategy—subtracting the voltages pairwise or using the difference between the maximum and minimum bus voltages as the error input for the voltage equalization loop—cannot effectively achieve bus voltage equalization and may even exacerbate the imbalance in bus voltages. Since single-phase modular combined three-phase rectifiers for three-bus systems and rectifier topologies for multiple-bus systems represent the future development trend of high-power charging modules, the voltage equalization problem of these topologies is an inevitable challenge. Therefore, a voltage equalization solution for three-bus and multiple-bus topologies is urgently needed. Summary of the Invention

[0006] This invention provides a BUS voltage equalization regulation method and a power converter, to at least solve the BUS voltage equalization control problem of the rectifier circuit in related technologies.

[0007] According to an embodiment of the present invention, a BUS voltage equalization adjustment method for a power converter is provided, comprising: calculating the equalization adjustment duty cycle of each phase using the difference between the BUS voltage of the phase with the largest positive value and the phase with the largest negative value among a plurality of phase voltages of the power converter as the error input of the equalization loop; determining the adjustment direction of the driving duty cycle of each phase according to the difference between the main phase BUS voltage and the average value of the BUS voltages of all phases, wherein the main phase is the phase with the largest absolute value among the plurality of phase voltages; and equalizing the BUS voltage of each phase according to the adjustment direction of the driving duty cycle of each phase and the equalization adjustment duty cycle of each phase.

[0008] Optionally, before calculating the voltage equalization regulation duty cycle of each phase by using the difference between the BUS voltage of the positive maximum phase and the BUS voltage of the negative maximum phase among the multiple phase voltages of the converter as the error input of the voltage equalization loop, the method further includes: sampling the multiple phase voltages of the converter.

[0009] Optionally, determining the adjustment direction of the drive duty cycle of each phase based on the difference between the main phase BUS voltage and the average value of the BUS voltages of other phases includes at least one of the following: when the difference between the main phase BUS voltage and the average value of the BUS voltages of all phases is greater than a first preset voltage, the adjustment direction of the drive duty cycle of the main phase is to decrease the main phase BUS voltage, and the adjustment direction of the drive duty cycle of other phases is to increase the BUS voltages of other phases; when the difference between the main phase BUS voltage and the average value of the BUS voltages of all phases is less than a second preset voltage, the adjustment direction of the drive duty cycle of the main phase is to increase the main phase BUS voltage, and the adjustment direction of the drive duty cycle of other phases is to decrease the BUS voltages of other phases; when the difference between the main phase BUS voltage and the average value of the BUS voltages of all phases is greater than the second preset voltage and less than the first preset voltage, the BUS voltage of each phase is not adjusted.

[0010] Optionally, equalizing the BUS voltage of each phase according to the adjustment direction of the driving duty cycle of each phase and the equalizing duty cycle of each phase includes: superimposing the equalizing duty cycle of each phase with the feedforward duty cycle of each phase and the fine-tuning portion of the PWM duty cycle output by the current loop according to the adjustment direction of the driving duty cycle of each phase; and adjusting the corresponding BUS voltage according to the superimposed duty cycle of each phase.

[0011] Optionally, the equalization adjustment of the BUS voltage of each phase according to the adjustment direction of the driving duty cycle of each phase and the equalization adjustment duty cycle of each phase includes: superimposing the output value of the equalization loop of each phase onto the instantaneous input voltage sampling value of each phase to calculate the feedforward duty cycle of each phase; superimposing the feedforward duty cycle of each phase with the fine-tuning part of the PWM duty cycle output by the current loop; and adjusting the corresponding BUS voltage according to the superimposed duty cycle of each phase.

[0012] Optionally, adjusting the corresponding BUS voltage according to the duty cycle of each phase superimposed includes: obtaining the modulation wave of each phase according to the duty cycle of each phase superimposed; converting the modulation wave of each phase into a PWM drive signal; controlling the switching on and off of the control power switch of the converter and adjusting the corresponding BUS voltage according to the PWM drive signal.

[0013] According to another embodiment of the present invention, a power converter is provided, comprising: a control unit and a power conversion unit. The control unit includes a voltage equalization ring, which is configured to calculate the voltage equalization adjustment duty cycle of each phase using the difference between the BUS voltage of the positive maximum phase and the BUS voltage of the negative maximum phase among a plurality of phase voltages of the power converter as an error input, and determine the adjustment direction of the driving duty cycle of each phase according to the difference between the main phase BUS voltage and the average value of the BUS voltages of all phases, wherein the main phase is the phase with the largest absolute value among the plurality of phase voltages; the power conversion unit is configured to perform equalization adjustment of the BUS voltage of each phase of the power converter according to the adjustment direction of the driving duty cycle of each phase and the voltage equalization adjustment duty cycle of each phase.

[0014] Optionally, the control unit further includes a sampling subunit for sampling the plurality of phase voltages of the converter.

[0015] Optionally, the equalizing ring determines the adjustment direction of the driving duty cycle of each phase by at least one of the following methods: when the difference between the BUS voltage of the main phase and the average value of the BUS voltages of all phases is greater than a first preset voltage, the adjustment direction of the driving duty cycle of the main phase is to decrease the BUS voltage of the main phase, and the adjustment direction of the driving duty cycle of other phases is to increase the BUS voltage of other phases; when the difference between the BUS voltage value of the main phase and the average value of the BUS voltages of all phases is less than a second preset voltage, the adjustment direction of the driving duty cycle of the main phase is to increase the BUS voltage of the main phase, and the adjustment direction of the driving duty cycle of other phases is to decrease the BUS voltage of other phases; when the difference between the BUS voltage value of the main phase and the average value of the BUS voltages of all phases is greater than the second preset voltage and less than the first preset voltage, the BUS voltage of each phase is not adjusted.

[0016] Optionally, the control unit further includes: an analog-to-digital conversion subunit for converting the sampled multiple phase voltages from analog signals to digital signals; a feedforward subunit for calculating the feedforward duty cycle of each phase based on the target voltage and the input phase voltage of each phase; a voltage loop for calculating the output current loop setpoint using the difference between the average value of the BUS voltage of each phase and the target set BUS voltage as the error input; a current loop for outputting the fine-tuning part of the PWM duty cycle using the setpoint of the current loop and the difference between the currents of each phase as the input of the current loop; and a PWM drive subunit for superimposing the voltage equalization adjustment duty cycle of each phase, the feedforward duty cycle of each phase, and the fine-tuning part of the PWM duty cycle according to the adjustment direction of the drive duty cycle of each phase, obtaining the modulation wave of each phase based on the superimposed duty cycle of each phase, converting the modulation wave of each phase into a PWM drive signal, and outputting it to the power conversion unit.

[0017] Optionally, the control unit further includes: an analog-to-digital conversion subunit, used to convert the sampled multiple phase voltages from analog signals into digital signals; a voltage loop, used to calculate the output current loop setpoint using the difference between the average value of the BUS voltage of each phase and the target set BUS voltage as an error input; a current loop, used to output the fine-tuning part of the PWM duty cycle using the setpoint of the current loop and the difference between the currents of each phase as the input of the current loop; a feedforward subunit, used to superimpose the output value of the voltage equalization loop of each phase onto the instantaneous input voltage sample value of each phase to calculate the feedforward duty cycle of each phase; and a PWM drive subunit, used to superimpose the feedforward duty cycle of each phase and the fine-tuning part of the PWM duty cycle according to the adjustment direction of the drive duty cycle of each phase, obtain the modulation wave of each phase according to the superimposed duty cycle of each phase, convert the modulation wave of each phase into a PWM drive signal, and output it to the power conversion unit.

[0018] Optionally, the power conversion unit is further configured to: control the switching on and off of the control power switch of the converter according to the PWM drive signal and to adjust the corresponding BUS voltage.

[0019] According to yet another embodiment of the present invention, a storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0020] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0021] In the above embodiments of the present invention, no additional hardware cost is required. A voltage equalization control loop can be added in the software. The control error of this loop is obtained by sampling the difference between the BUS voltage corresponding to the maximum positive input voltage and the BUS voltage corresponding to the maximum negative input voltage in real time. After the error is adjusted by the loop, the adjustment direction when the output of the voltage equalization loop is injected into the control system of each phase is determined by the difference between the main corresponding BUS voltage and the average value of other phase BUS. This accurately changes the charging and discharging time of each phase BUS capacitor, thereby achieving voltage equalization of each phase BUS. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0023] Figure 1This is a flowchart of a BUS voltage equalization adjustment method for a power converter according to an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of a power conversion device according to an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of a power conversion unit according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the control of a power conversion device according to Embodiment 1 of the present invention;

[0027] Figure 5 These are the PWM modulation wave and drive waveform during the switching cycle according to Embodiment 1 of the present invention;

[0028] Figure 6 This is a waveform diagram of the three-phase AC input voltage according to Embodiment 1 of the present invention;

[0029] Figure 7 These are the PWM modulation wave and drive waveform during the switching cycle according to Embodiment 1 of the present invention;

[0030] Figure 8 This is a flowchart of the pressure equalization control algorithm according to Embodiment 1 of the present invention;

[0031] Figure 9 This is a schematic diagram of the power conversion device control according to Embodiment 2 of the present invention;

[0032] Figure 10 This is a waveform diagram of the three-phase AC input voltage according to Embodiment 2 of the present invention;

[0033] Figure 11 This is a flowchart of the pressure equalization control algorithm according to Embodiment 2 of the present invention. Detailed Implementation

[0034] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the present application can be combined with each other.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0036] To address the issue of inconsistent voltages among the various BUS capacitors in a power converter, this embodiment provides a method for equalizing and regulating the BUS voltage in a power converter. Figure 1 This is a flowchart of a method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0037] Step S102: The difference between the BUS voltage of the positive maximum phase and the BUS voltage of the negative maximum phase among the multiple phase voltages of the power converter is used as the error input of the voltage equalization loop to calculate the voltage equalization regulation duty cycle of each phase.

[0038] Step S104: Determine the adjustment direction of the driving duty cycle of each phase based on the difference between the main phase BUS voltage and the average value of all phase BUS voltages, wherein the main phase is the phase with the largest absolute value among the multiple phase voltages;

[0039] Step S106: The BUS voltage of each phase is balanced and adjusted according to the adjustment direction of the driving duty cycle of each phase and the equalization adjustment duty cycle of each phase.

[0040] Before step S102 in this embodiment, the method may further include sampling the plurality of phase voltages of the converter.

[0041] In step S104 of this embodiment, when the difference between the BUS voltage of the main phase and the average value of the BUS voltages of all phases is greater than a first preset voltage, the adjustment direction of the drive duty cycle of the main phase is to decrease the BUS voltage of the main phase, and the adjustment direction of the drive duty cycle of other phases is to increase the BUS voltage of other phases; when the difference between the BUS voltage value of the main phase and the average value of the BUS voltages of all phases is less than a second preset voltage, the adjustment direction of the drive duty cycle of the main phase is to increase the BUS voltage of the main phase, and the adjustment direction of the drive duty cycle of other phases is to decrease the BUS voltage of other phases; when the difference between the BUS voltage value of the main phase and the average value of the BUS voltages of all phases is greater than the second preset voltage and less than the first preset voltage, the BUS voltage of each phase is not adjusted.

[0042] In step S106 of this embodiment, the BUS voltage of each phase can be balanced and adjusted in the following two ways:

[0043] Method 1: According to the adjustment direction of the driving duty cycle of each phase, the voltage equalization adjustment duty cycle of each phase is superimposed with the feedforward duty cycle of each phase and the fine-tuning part of the PWM duty cycle output by the current loop; the corresponding BUS voltage is adjusted according to the superimposed duty cycle of each phase.

[0044] Method 2: The output values ​​of the voltage equalization loop of each phase are superimposed on the instantaneous input voltage sampling values ​​of each phase to calculate the feedforward duty cycle of each phase; the feedforward duty cycle of each phase is superimposed on the fine-tuning part of the PWM duty cycle output by the current loop; the corresponding BUS voltage is adjusted according to the superimposed duty cycle of each phase.

[0045] In step S106 of this embodiment, adjusting the corresponding BUS voltage according to the duty cycle of each phase superimposed includes: obtaining the modulation wave of each phase according to the duty cycle of each phase superimposed; converting the modulation wave of each phase into a PWM drive signal; controlling the switching on and off of the control power switch of the converter and adjusting the corresponding BUS voltage according to the PWM drive signal.

[0046] In the above embodiments, no additional hardware cost is required. A voltage equalization control loop can be added in the software. The control error of this loop is obtained by sampling and subtracting the BUS voltage corresponding to the maximum positive input voltage and the BUS voltage corresponding to the maximum negative input voltage in real time. After the error is adjusted by a PI loop, the adjustment direction of the voltage equalization loop output injected into the control system of each phase is determined by the difference between the main corresponding BUS voltage and the average value of the three-phase BUS. The calculation of the loop error is determined according to the different sectors of the input three-phase voltage, and it changes continuously in a cycle. The voltage equalization compensation direction of each phase is also determined according to the main corresponding BUS voltage of the input voltage. At the same time, the main phase also changes continuously over time. The BUS voltage equalization control process of three-BUS and multi-BUS rectifier circuits is more complex and the controlled object is more precise, thereby accurately changing the charging and discharging time of each phase BUS capacitor, and ultimately achieving the balance of charging energy.

[0047] To facilitate understanding of the technical solutions provided by this invention, a detailed description will be given below in conjunction with specific embodiments.

[0048] This embodiment provides a voltage equalization control method for DC bus capacitors in three-bus and multi-bus converters, solving the problem of inconsistent voltages among the various bus capacitors in a multi-bus three-phase converter.

[0049] like Figure 2 As shown, in this embodiment, the power conversion device includes a power supply unit, an inductor unit, a power conversion unit group, and a control unit. The power supply unit includes a three-phase AC source, and the three inductor units, each composed of inductors, enable the charging and discharging of the power circuit. The power conversion unit group includes three power conversion units. The three-phase outputs of the power supply unit are connected in series with the three inductor units. One input of each power conversion unit is connected to its corresponding inductor unit, and the other ends are connected together in a star configuration. The output of each power conversion unit is connected to a BUS capacitor. The output BUS voltage of each power conversion unit serves as the power conversion result of the power conversion device.

[0050] The control unit is connected to each power conversion unit, inputting corresponding control signals to each power conversion unit to control the switching time of each power conversion unit, so that the BUS voltage output by each power conversion unit reaches the target value. The control unit also includes a voltage equalization ring to ensure voltage balance across all BUS lines.

[0051] The equalization strategy in this embodiment can adopt the following technical solution:

[0052] The difference between the BUS voltage corresponding to the maximum positive input voltage and the BUS voltage corresponding to the maximum negative input voltage is calculated and used as the error input for the voltage equalization loop. The difference between the corresponding BUS voltage and the average BUS voltage is calculated to determine the adjustment direction of the voltage equalization loop. The output of the voltage equalization loop is injected into the control system of each phase of the three-phase rectifier according to the determined adjustment direction. PWM control signals are generated by the PWM generation module, and then the driving module controls the switching devices in each power conversion unit of the three-phase converter to turn on and off, thereby controlling the charging and discharging time of each BUS capacitor, ultimately achieving the effect of voltage equalization.

[0053] In this embodiment, the "main phase" refers to the phase with the largest absolute value of the input voltage. The voltage equalization adjustment direction is as follows: when the difference between the main phase's corresponding BUS voltage and the average BUS voltage is greater than a certain specific voltage, the adjustment direction for the main phase is "+", and the adjustment direction for the other two phases is "-". That is, the duty cycle of the main phase increases, and the corresponding BUS voltage decreases; the duty cycle of the other two phases decreases, and the corresponding BUS voltage increases, thereby achieving voltage equalization across the three BUS lines. When the difference between the main phase's corresponding BUS voltage and the average BUS voltage is less than a certain specific voltage, the adjustment direction for the main phase is "-", and the adjustment direction for the other two phases is "+". That is, the duty cycle of the main phase decreases, and the corresponding BUS voltage increases; the duty cycle of the other two phases increases, and the corresponding BUS voltage decreases, thereby achieving voltage equalization across the three BUS lines. When the difference between the main phase's corresponding BUS voltage and the average BUS voltage is less than... and greater than At that time, no pressure equalization adjustment is performed.

[0054] Furthermore, the output of this voltage equalization control loop is injected into the control systems of each phase of the three-phase rectifier according to the determined adjustment direction. The output of the voltage equalization loop can be directly superimposed on the output duty cycle of the control system, directly controlling the on / off time of the power switches. Alternatively, the output of the voltage equalization loop can be injected into the calculation of the feedforward duty cycle of each phase. By adjusting the magnitude of the input phase voltage in the feedforward calculation, the magnitude of the feedforward duty cycle is adjusted, ultimately regulating the on / off time of the power switches in each phase. The injection point of the voltage equalization loop output can be selected from any control node in the control system. The choice of different injection points has little impact on the voltage equalization effect.

[0055] This embodiment includes the calculation of loop error, the design of the control loop, and the calculation of the compensation and control direction. The digital controller used in this embodiment includes, but is not limited to, a DSP; other controllers such as microcontrollers or ARM processors can also be implemented. The voltage equalization loop control algorithm used in this invention includes, but is not limited to, proportional regulators, integral regulators, proportional-integral regulators, and proportional-integral-derivative regulators. The topology applicable to this invention is not limited to single-phase modular combined three-phase rectifiers; other single-phase and three-phase multi-bus topologies, such as single-phase multi-channel PFC series circuits, three-phase star and delta PFC topologies, are also applicable.

[0056] This embodiment provides a simple, easy-to-use, and low-cost digital voltage equalization control method for three-phase power converters with three or more buses. It solves the voltage equalization problem of DC capacitors in multi-bus three-phase rectifier converters, which cannot be addressed by existing software voltage equalization control methods. Using this voltage equalization control method, the voltage difference between multiple buses can be controlled within a specified range, and the output ripple of the rectifier module can be significantly reduced, improving input and output performance. Example

[0057] In this embodiment, the single-phase modular combined three-phase PFC rectifier topology can largely meet the industry requirements of high efficiency, high power density, and low cost. For example... Figure 2 This power conversion device mainly includes a power supply unit, an inductor unit, a power conversion unit group, and a control unit. The power supply unit includes a three-phase AC source, and the three inductor units, composed of inductors, enable the charging and discharging of the power circuit. The power conversion unit group includes three power conversion units. The three-phase output of the power supply unit is connected in series with the three inductor units. One end of the input of each power conversion unit is connected to its corresponding inductor unit, and the other ends are connected together in a star configuration. The output of each power conversion unit is connected to a BUS capacitor. The output BUS voltage of each power conversion unit serves as the power conversion result of the power conversion device.

[0058] The power conversion unit in this embodiment is as follows: Figure 3 As shown, Q1 and Q2 are two power MOSFETs, which are high-frequency switching transistors. The PWM1 and PWM2 drivers are calculated by the control unit. By controlling the duty cycle of the PWM drivers, the turn-on and turn-off times of the MOSFETs are controlled, thereby controlling the voltage across the BUS capacitor C1. VT1 and VT2 are power frequency return transistors, which may include, but are not limited to, power diodes, or other power switching transistors such as MOSFETs. The midpoint COM of the high-frequency MOSFET is connected to a boost inductor, and the midpoint N of the power frequency diode is connected to the N point of other power units, forming a star connection.

[0059] The control unit in this embodiment is as follows: Figure 4As shown, the control unit samples the input voltage, inductor current, and BUS voltage, and calculates the control signals for each power conversion module through loop control, thereby obtaining a stable BUS voltage. Specifically, the control unit includes a sampling subunit, an analog-to-digital conversion subunit, a feedforward mechanism, a voltage loop, a current loop, a voltage equalization subunit, and a PWM drive subunit.

[0060] Specifically, in this embodiment, the sampling subunit samples the line voltage of the three-phase power supply, the inductor current of the three-phase inductor, and the BUS voltage of the three-phase BUS through signal conditioning circuits such as operational amplifiers, and sends the sampled analog quantities to the ADC port of the main control chip DSP.

[0061] Furthermore, the analog-to-digital conversion subunit inside the DSP converts the sampled analog signal into a digital signal, restores the actual voltage and current values, and participates in the calculation of the voltage loop, current loop, and voltage equalization subunit.

[0062] Specifically, the target voltage and the input phase voltage of each phase are first determined using the formula... The real-time feedforward duty cycle D0 of each phase is calculated, which constitutes the main part of the final duty cycle. The average value of the BUS voltage is calculated from the sampled three-phase BUS voltage, and the difference is taken with the target set BUS voltage to obtain the error input of the voltage loop. The setpoint of the output current loop is calculated through the voltage loop (including but not limited to P regulators, PI regulators, and PID regulators). The difference between the current loop setpoint and the real-time sampled phase current is used as the input of the current loop, and the output D1 of the current loop (including but not limited to P regulators, PI regulators, and PID regulators) is the fine-tuning part of the PWM duty cycle.

[0063] Without the equalization control strategy, the feedforward duty cycle D0 and the fine-tuning duty cycle D1 are superimposed to calculate the comparison values ​​of each phase, i.e., the modulation waves Ua, Ub, and Uc, as follows: Figure 5 As shown, the switching drive waveforms Sa, Sb, and Sc for each phase are obtained by comparing them with the triangular carrier waves of the positive and negative half-cycles, respectively. These waveforms are then sent to the power conversion units of each phase to control the on / off state of the switching transistors. At this time, the main phase is phase A, which is in the positive half-cycle, while the phase voltages of phases B and C are in the negative half-cycle. The waveforms at other times are similar. At this time, it can only ensure that the BUS voltage of each phase is close to the target value, but it cannot effectively control the three-phase BUS voltages to be completely equal. Therefore, a voltage equalization sub-unit is added in this embodiment.

[0064] In detail, Figure 6Taking time Δt as an example, A, B, and C are the three-phase input phase voltages. At time Δt, after sampling and calculating the three-phase input phase voltages, the absolute values ​​of the three-phase voltages are compared. It is found that phase A has the largest absolute value and is in the positive half-cycle, making it the positive maximum phase and the main phase; phase B has the negative maximum phase; and phase C is the intermediate phase. The difference between the corresponding BUS voltages of the positive and negative maximum phases A and B is used as the error input for the voltage equalization loop. The voltage equalization regulation duty cycle D2 is obtained by calculating the absolute value through the voltage equalization loop (including but not limited to P regulators, PI regulators, and PID regulators). This duty cycle needs to be superimposed onto the final duty cycle according to the voltage equalization regulation direction of each phase.

[0065] Furthermore, the direction of voltage equalization adjustment is determined by the difference between the main phase's BUS voltage and the average value of the three-phase BUS voltage. Specifically, when the difference between the main phase's BUS voltage and the average BUS voltage is greater than a certain specific voltage (i.e., the main phase's BUS voltage is too high), the direction of voltage equalization adjustment for the main phase is "+", and the direction for the other two phases is "-"; when the difference between the main phase's BUS voltage and the average BUS voltage is less than a certain specific voltage... That is, when the main phase BUS voltage is low, the voltage equalization adjustment direction of the main phase is "-", and the voltage equalization adjustment direction of the other two phases is "+"; when the difference between the main phase BUS voltage value and the average BUS voltage is less than 10%, the voltage equalization adjustment direction of the other two phases is 10%. and greater than At that time, no pressure equalization adjustment is performed.

[0066] Detailed, assuming Figure 6 At time Δt, the BUS voltage corresponding to phase A is higher than the average BUS voltage. At this time, the voltage equalization adjustment direction for phase A is "+", while the direction for phases B and C is "-". The duty cycle of phase A is increased by D2 based on the feedforward and current loop duty cycles, while the duty cycles of phases B and C are decreased by D2 based on their original duty cycles. The modulation waveform after adding the voltage equalization strategy is as follows: Figure 7 Since the carrier waves of the positive half-cycle and the negative half-cycle are in opposite directions in this embodiment, the A-phase modulation wave in the positive half-cycle is reversed so that the original comparison values ​​Ua, Ub, and Uc are all shifted downward by ΔU to obtain the comparison values ​​Ua', Ub', and Uc' after voltage equalization. That is, the same amount is superimposed on the modulation wave to ensure the balance of the input current and prevent waveform distortion. Figure 7 As can be seen, the processed modulated wave Ua'<Ua,Ub’> Ub, Uc'>Uc, the driving waveforms obtained by comparing with the carrier wave are shown as Sa', Sb', Sc' in the figure. After adding the voltage equalization control strategy, the driving duty cycle of phase A increases, while the duty cycles of phases B and C decrease, and the difference between the increase and decrease is equal. This shortens the charging time of the BUS capacitor in phase A, resulting in a lower BUS voltage, while lengthening the charging time of the BUS capacitors in phases B and C, resulting in a higher corresponding BUS voltage, thus achieving three-phase BUS voltage balance. If Figure 6 At time Δt, the bus voltage corresponding to the main phase A is lower than the average value of the three-phase bus. Therefore, the direction of voltage equalization adjustment is... Figure 7 Conversely, if the A-phase BUS voltage is equal to the three-phase BUS voltage, no voltage equalization adjustment is performed, and the drive waveforms for each phase remain Sa, Sb, and Sc. The adjustment method for other arbitrary times and other uneven voltage conditions is similar.

[0067] The three-phase voltage equalization control process used in this implementation example is as follows: Figure 8 The main steps include the following:

[0068] Step S801: Based on the sampling of the three-phase input phase voltage, determine the positive maximum phase, the negative maximum phase, and the main phase, where the main phase is the phase with the largest absolute value of the input phase voltage.

[0069] Step S802: Calculate the difference between the BUS voltage corresponding to the positive maximum phase and the negative maximum phase, and use it as the error input of the voltage equalization ring.

[0070] Step S803: Input the error into the equalizing loop for calculation. The equalizing loop can use a PI controller, a PID controller, or other control algorithms. In this implementation example, the absolute value of the output of the equalizing loop is obtained as D2.

[0071] Step S804: Determine the adjustment direction of the drive duty cycle for each phase based on the difference between the main phase BUS voltage and the average value of the three-phase BUS voltage. That is, when the difference between the main phase BUS voltage and the average value of the BUS voltage is greater than a certain specific voltage... When the main phase drive duty cycle is adjusted in the "+" direction, the other two phases are adjusted in the "-" direction; when the difference between the main phase's corresponding BUS voltage value and the average BUS voltage is less than a certain specific voltage... At this time, the adjustment direction of the duty cycle of the main phase drive is "-", and the other two phases are "+"; the difference between the BUS voltage value corresponding to the main phase and the average BUS voltage is less than 1. Furthermore, when the value is greater than the specified value, no equalization adjustment is performed.

[0072] Step S805: Based on the adjustment direction of each phase drive, the absolute value D2 of the equalizing ring output is superimposed on the drive duty cycle of each phase.

[0073] Through the above embodiments, the PWM modulation wave is optimized in the PWM drive subunit to obtain the drive signal, which is then applied to the power switch in the power conversion unit by the drive circuit to control the charging time of each capacitor, thereby achieving the effect of active voltage equalization.

[0074] In this embodiment, only simple calculations and logical judgments are required, making it very suitable for digital control. The controller in the above technical solution includes, but is not limited to, microcontrollers, DSPs, ARMs, etc. This technical solution can be used, but is not limited to, single-phase modular combined three-phase PFC circuits, and can also be used in any rectifier circuit that requires multi-channel voltage equalization. Example

[0075] The power section of this embodiment is the same as that of Embodiment 1, such as... Figure 9 As shown, the power conversion device mainly includes a power supply unit, an inductor unit, a power conversion unit group, and a control unit. The power supply unit includes a three-phase AC source, and the three inductor units, composed of inductors, realize the charging and discharging of the power circuit. The power conversion unit group includes three power conversion units. The three-phase output of the power supply unit is connected in series with the three inductor units. One end of the input of each power conversion unit is connected to its corresponding inductor unit, and the other end is connected together in a star configuration. The output of each power conversion unit is connected to a BUS capacitor. The output BUS voltage of each power conversion unit serves as the power conversion result of the power conversion device.

[0076] like Figure 9 As shown, the control unit samples the input voltage, inductor current, and BUS voltage, and calculates the control signals for each power conversion module through loop control, thereby obtaining a stable BUS voltage. Specifically, the control unit includes a sampling subunit, an analog-to-digital conversion subunit, a voltage loop, a current loop, a voltage equalization subunit, a feedforward subunit, and a PWM drive subunit.

[0077] Specifically, the sampling subunit samples the line voltage of the three-phase power supply, the inductor current of the three-phase inductor, and the BUS voltage of the three-phase BUS through signal conditioning circuits such as operational amplifiers, and sends the sampled analog quantities to the ADC port of the main control chip DSP.

[0078] Furthermore, the analog-to-digital conversion subunit inside the DSP converts the sampled analog signal into a digital signal, restoring the actual voltage and current values, which are then used in the calculations of the feedforward, voltage loop, current loop, and voltage equalization subunits.

[0079] Specifically, the average value of the three-phase BUS voltage is calculated from the sampled voltages, and the difference between this average and the target BUS voltage is used to obtain the error input for the voltage loop. The voltage loop (including but not limited to P-regulators, PI regulators, and PID regulators) is then used to calculate the setpoint for the output current loop. The difference between the current loop setpoint and the real-time sampled phase currents serves as the input to the current loop. The output D1 of the current loop (including but not limited to P-regulators, PI regulators, and PID regulators) is used for fine-tuning the PWM duty cycle.

[0080] The feedforward duty cycle is theoretically determined by the target voltage and the input phase voltage of each phase according to the formula. The calculations are as follows. To ensure voltage balance across the three BUS lines, this embodiment adds the output of the equalizing loop to Vin to participate in the calculation of the feedforward duty cycle. The feedforward duty cycle is changed by adjusting the value of Vin. The sum of the current loop output D1 and the feedforward D0 is compared with the carrier wave to obtain the PWM drive signal for each phase power switch, thereby controlling the on and off of the power switches and achieving BUS voltage equalization.

[0081] Specifically, the error input of the voltage equalization loop is the difference between the BUS voltage corresponding to the positive maximum and the BUS voltage corresponding to the negative maximum. The voltage equalization loop (including but not limited to P regulators, PI regulators, and PID regulators) calculates the output |ΔU|. This is then added to the feedforward calculation for each phase based on the superposition sign.

[0082] Furthermore, the superposition sign is determined by the product of the voltage equalization adjustment direction of the main phase and the input voltage direction. The voltage equalization adjustment direction is determined by the difference between the main phase BUS voltage and the average value of the three-phase BUS. When the difference between the main phase BUS voltage and the average BUS voltage is greater than a certain specific voltage... When the main phase bus voltage is too high, the voltage equalization adjustment direction for the main phase is "-"; when the difference between the corresponding main phase bus voltage and the average bus voltage is less than a certain specific voltage, i.e., when the main phase bus voltage is too low, the voltage equalization adjustment direction for the main phase is "+"; when the difference between the corresponding main phase bus voltage and the average bus voltage is less than a certain specific voltage, the voltage equalization adjustment direction for the main phase is "+"; and greater than When the voltage equalization adjustment direction is "0", no adjustment is made. When the main phase input voltage is in the positive half-cycle, the input voltage direction is "+", and when the main phase input voltage is in the negative half-cycle, the input voltage direction is "-". The product of the main phase voltage equalization adjustment direction and the main phase input voltage direction is the superposition sign of Vin in the feedforward calculation formula for each phase. The superposition value is the output |ΔU| of the voltage equalization loop.

[0083] Specifically, attached Figure 10 At time Δt, the absolute value of the input voltage of phase A is the largest, making it the dominant phase. Assume that at this time, the difference between the bus voltage of phase A and the average value of the three-phase bus is greater than a certain specific voltage. This means the A-phase bus voltage is too high. The voltage equalization adjustment direction is "-", and the main phase input voltage is currently in the positive half-cycle, with the input voltage direction being "+". The product of these two is "-", meaning the sum of all phases has a "-" sign. Therefore, [the following is a continuation of the previous sentence]. Figure 10 At time Δt, all three-phase input voltages shift downwards by |ΔU|. After the shift, the magnitude of the input voltage in phase A decreases, according to the formula... (Where Vin is the magnitude of the instantaneous phase voltage). A decrease in Vin increases the feedforward duty cycle D0, reduces the BUS capacitor charging time, and decreases the A-phase BUS voltage. Simultaneously, the magnitudes of the input voltages after the shift in phases B and C increase, according to the formula... (Where Vin is the magnitude of the instantaneous phase voltage). Increasing Vin decreases the feedforward duty cycle D0, lengthens the charging time of the BUS capacitor, and increases the BUS voltage in phases B and C. This achieves voltage balance among the three phases A, B, and C of the BUS. The adjustment methods at other times and under other uneven voltage conditions are similar.

[0084] The three-phase voltage equalization control process used in this implementation example is as follows: Figure 11 As shown. The main steps include the following:

[0085] Step S1101: Based on the sampling of the three-phase input phase voltage, determine the positive maximum phase, the negative maximum phase, and the main phase, where the main phase is the phase with the largest absolute value of the input phase voltage.

[0086] Step S1102: Calculate the difference between the BUS voltage corresponding to the positive maximum phase and the negative maximum phase, and use it as the error input of the voltage equalization loop;

[0087] In step S1103, the equalizing ring can use a PI controller, a PID controller, or other control algorithms. In this implementation example, the absolute value of the output of the equalizing ring is obtained as |ΔU|.

[0088] Step S1104: Determine the direction of voltage equalization adjustment based on the difference between the main phase BUS voltage and the average value of the three-phase BUS voltage. When the difference between the main phase BUS voltage and the average BUS voltage is greater than a certain specific voltage... When the main phase bus voltage is too high, the voltage equalization adjustment direction of the main phase is "-"; when the difference between the main phase bus voltage value and the average bus voltage is less than a certain specific voltage... That is, when the main phase BUS voltage is low, the main phase voltage equalization adjustment direction is "+"; when the difference between the main phase BUS voltage value and the average BUS voltage is less than 10%, the ... main phase B When the value is greater than 0, the equalization pressure adjustment direction is "0", that is, no adjustment is made.

[0089] Step S1105: Determine the positive and negative half-cycles of the main phase input voltage. During the positive half-cycle, the input voltage direction is "+", and during the negative half-cycle, the input voltage direction is "-".

[0090] Step S1106: Based on the product of the voltage equalization adjustment direction of the main phase and the direction of the input voltage, i.e., the voltage equalization superposition sign, the output of the voltage equalization ring is superimposed on the instantaneous input voltage sampling value Vin of each phase and used to participate in the calculation of the feedforward duty cycle.

[0091] In step S1107, the feedforward duty cycle D0 of each phase is added to the current loop output D1 to obtain the modulation wave of each phase. The modulation wave is then compared with the triangular carrier wave through the PWM drive sub-unit to obtain the drive signal of the power switch of each power conversion unit.

[0092] The above method directly optimizes the feedforward duty cycle to obtain the final drive signal. This drive signal acts on the power switch through the drive circuit, controlling the charging time of each capacitor, thereby achieving active voltage equalization. This method requires only simple calculations and logical judgments, making it very suitable for digital control without increasing hardware costs. The controller in the above technical solution includes, but is not limited to, microcontrollers, DSPs, and ARM processors. This technical solution can be used, but is not limited to, single-phase modular combined three-phase PFC circuits, and can also be used in any rectifier circuit that requires voltage equalization across multiple buses.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0094] Embodiments of the present invention also provide a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0095] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0096] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0097] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0098] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0099] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for equalizing and regulating the bus voltage of a power converter, characterized in that, include: The difference between the BUS voltage of the positive maximum phase and the BUS voltage of the negative maximum phase among the multiple phase voltages of the power converter is used as the error input of the voltage equalization loop to calculate the voltage equalization regulation duty cycle of each phase. The positive maximum phase is the positive maximum phase in the positive half-cycle of the three-phase input phase voltage, and the negative maximum phase is the negative maximum phase in the negative half-cycle of the three-phase input phase voltage. If the difference between the BUS voltage of the main phase and the average value of the BUS voltages of all phases is greater than a first preset voltage, the adjustment direction of the driving duty cycle of each phase is determined to be to reduce the BUS voltage of the main phase, wherein the main phase is the phase with the largest absolute value among the multiple phase voltages. The BUS voltage of each phase is balanced and adjusted according to the adjustment direction of the driving duty cycle of each phase and the equalization adjustment duty cycle of each phase. The power converter includes a three-phase AC power supply, inductor units, and a power conversion unit group. The three-phase outputs of the three-phase AC power supply are connected in series with the three inductor units, and the output terminal of each power conversion unit is the BUS voltage.

2. The method according to claim 1, characterized in that, Before calculating the voltage equalization regulation duty cycle of each phase by using the difference between the BUS voltage of the positive maximum phase and the BUS voltage of the negative maximum phase among the multiple phase voltages of the converter as the error input of the voltage equalization loop, the method further includes: The multiple phase voltages of the converter are sampled.

3. The method according to claim 1, characterized in that, The direction of adjusting the drive duty cycle of each phase based on the difference between the main phase BUS voltage and the average value of the other phase BUS voltages includes at least one of the following: When the difference between the BUS voltage of the main phase and the average value of the BUS voltage of all phases is greater than a first preset voltage, the adjustment direction of the driving duty cycle of the main phase is to lower the BUS voltage of the main phase, and the adjustment direction of the driving duty cycle of other phases is to increase the BUS voltage of other phases. When the difference between the BUS voltage value of the main phase and the average value of the BUS voltage of all phases is less than the second preset voltage, the adjustment direction of the driving duty cycle of the main phase is to increase the BUS voltage of the main phase, and the adjustment direction of the driving duty cycle of other phases is to decrease the BUS voltage of other phases. When the difference between the main phase BUS voltage value and the average value of all phase BUS voltages is greater than the second preset voltage but less than the first preset voltage, the BUS voltage of each phase is not adjusted.

4. The method according to claim 1, characterized in that, The equalization adjustment of the BUS voltage of each phase according to the adjustment direction of the driving duty cycle of each phase and the equalization adjustment duty cycle of each phase includes: According to the adjustment direction of the driving duty cycle of each phase, the voltage equalization adjustment duty cycle of each phase is superimposed with the feedforward duty cycle of each phase and the fine-tuning part of the PWM duty cycle output by the current loop. The corresponding BUS voltage is adjusted according to the duty cycle of each phase after superposition.

5. The method according to claim 1, characterized in that, The equalization adjustment of the BUS voltage of each phase according to the adjustment direction of the driving duty cycle of each phase and the equalization adjustment duty cycle of each phase includes: The output values ​​of the voltage equalization loop of each phase are superimposed on the instantaneous input voltage sampling values ​​of each phase to calculate the feedforward duty cycle of each phase. The feedforward duty cycle of each phase is superimposed with the fine-tuning portion of the PWM duty cycle output by the current loop; The corresponding BUS voltage is adjusted according to the duty cycle of each phase after superposition.

6. The method according to claim 4 or 5, characterized in that, Adjusting the corresponding BUS voltage based on the duty cycle of each phase superposition includes: The modulation wave of each phase is obtained based on the duty cycle after the superposition of each phase; The modulation waves of each phase are converted into PWM drive signals; The PWM drive signal is used to control the power switch of the converter to turn on and off, and to adjust the corresponding BUS voltage.

7. A power converter, characterized in that, It includes a control unit and a power conversion unit, wherein the control unit includes an equalizing ring. The voltage equalization ring is used to calculate the voltage equalization adjustment duty cycle of each phase by using the difference between the BUS voltage of the positive maximum phase and the BUS voltage of the negative maximum phase among the multiple phase voltages of the power converter as an error input. When the difference between the BUS voltage of the main phase and the average value of the BUS voltages of all phases is greater than a first preset voltage, the adjustment direction of the driving duty cycle of each phase is determined to be to reduce the BUS voltage of the main phase. The main phase is the phase with the largest absolute value among the multiple phase voltages, the positive maximum phase is the positive maximum phase in the positive half-cycle of the three-phase input phase voltage, and the negative maximum phase is the negative maximum phase in the negative half-cycle of the three-phase input phase voltage. The power conversion unit is used to balance and adjust the BUS voltage of each phase of the power converter according to the adjustment direction of the driving duty cycle of each phase and the equalization adjustment duty cycle of each phase. The power converter includes a three-phase AC power supply, inductor units, and a power conversion unit group. The three-phase outputs of the three-phase AC power supply are connected in series with the three inductor units, and the output terminal of each power conversion unit is the BUS voltage.

8. The power converter according to claim 7, characterized in that, The control unit further includes: A sampling subunit is used to sample the multiple phase voltages of the converter.

9. The power converter according to claim 7, characterized in that, The equalizing ring determines the adjustment direction of the driving duty cycle of each phase by at least one of the following methods: When the difference between the BUS voltage of the main phase and the average value of the BUS voltage of all phases is greater than a first preset voltage, the adjustment direction of the driving duty cycle of the main phase is to lower the BUS voltage of the main phase, and the adjustment direction of the driving duty cycle of other phases is to increase the BUS voltage of other phases. When the difference between the BUS voltage value of the main phase and the average value of the BUS voltage of all phases is less than the second preset voltage, the adjustment direction of the driving duty cycle of the main phase is to increase the BUS voltage of the main phase, and the adjustment direction of the driving duty cycle of other phases is to decrease the BUS voltage of other phases. When the difference between the main phase BUS voltage value and the average value of all phase BUS voltages is greater than the second preset voltage but less than the first preset voltage, the BUS voltage of each phase is not adjusted.

10. The power converter according to claim 7, characterized in that, The control unit further includes: An analog-to-digital conversion subunit is used to convert the sampled multiple phase voltages from analog signals into digital signals; The feedforward sub-unit is used to calculate the feedforward duty cycle of each phase based on the target voltage and the input phase voltage of each phase. The voltage loop is used to calculate the output current loop setting by using the difference between the average value of the BUS voltage of each phase and the target set BUS voltage as the error input. The current loop is used to output the fine-tuning part of the PWM duty cycle, taking the given current of the current loop and the difference between the currents of each phase as the input of the current loop. The PWM drive subunit is used to superimpose the voltage equalization regulation duty cycle of each phase, the feedforward duty cycle of each phase, and the fine-tuning part of the PWM duty cycle according to the adjustment direction of the driving duty cycle of each phase, obtain the modulation wave of each phase according to the superimposed duty cycle of each phase, convert the modulation wave of each phase into a PWM drive signal, and output it to the power conversion unit.

11. The power converter according to claim 7, characterized in that, The control unit further includes: An analog-to-digital conversion subunit is used to convert the sampled multiple phase voltages from analog signals into digital signals; The voltage loop is used to calculate the output current loop setting by using the difference between the average value of the BUS voltage of each phase and the target set BUS voltage as the error input. The current loop is used to output the fine-tuning part of the PWM duty cycle, taking the given current of the current loop and the difference between the currents of each phase as the input of the current loop. The feedforward subunit is used to superimpose the output value of the voltage equalization loop of each phase onto the instantaneous input voltage sampling value of each phase in order to calculate the feedforward duty cycle of each phase. The PWM drive subunit is used to superimpose the feedforward duty cycle of each phase with the fine-tuning portion of the PWM duty cycle according to the adjustment direction of the drive duty cycle of each phase, obtain the modulation wave of each phase according to the superimposed duty cycle of each phase, convert the modulation wave of each phase into a PWM drive signal and output it to the power conversion unit.

12. The power converter according to claim 10 or 11, characterized in that, The power conversion unit is also used for: The PWM drive signal is used to control the power switch of the converter to turn on and off, and to adjust the corresponding BUS voltage.

13. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 6 when it is run.

14. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method as described in any one of claims 1 to 6.

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