Hot data identification method and storage device thereof

Abstract

Provided are a hot data identification method and a storage device thereof. The provided hot data identification and processing method comprises: obtaining an address accessed by an IO command; if the address accessed by the IO command hits a first entry of a hot data table, accessing a cache unit corresponding to the first entry to process the IO command, and setting the first entry to a front part of the hot data table; and expiring an entry in a rear part of the hot data table.

Description

Technical Field

[0001] This application relates to storage technology, and more specifically, to identifying hot data accessed by received IO commands in a storage device and optimizing the processing of hot data. Background Technology

[0002] Figure 1 A block diagram of the storage device is shown. Storage device 102 is coupled to a host to provide storage capabilities to the host. The host and solid-state storage device 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), UFS (Universal Flash Storage), eMMC (embedded MMC (MultiMediaCard)), Ethernet, Fibre Channel, and wireless communication networks. The host can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] The lifespan of an NVM chip and the reliability of the stored data are related to the number of times it is read / written. Reading data from an NVM chip can cause a "read disturbance" effect, which, when accumulated, increases the bit error rate of the read memory cells. Before data can be written to an NVM chip, an erase operation must be performed. The number of erase-write cycles an NVM chip can withstand is limited, and this number typically represents the chip's lifespan.

[0008] Compared to storage media such as SRAM / DRAM, reading / writing NVM chips takes longer and consumes more power.

[0009] Applications running on a host computer exhibit diverse data access characteristics. Caching techniques have been proposed to temporarily store recently accessed data using high-performance storage media to improve storage system performance. For example, SRAM / DRAM and other storage media can be used as caches for NVM storage media. Summary of the Invention

[0010] The storage space of storage devices is often very large relative to the capacity provided by cache. This results in a relatively small cache, leading to extremely low cache hit rates. Consequently, traditional caching technologies offer limited performance improvements in large-capacity storage devices. Therefore, there is a need to develop caching technologies suitable for large-capacity solid-state storage devices.

[0011] Furthermore, the processing power of the control components in storage devices is severely limited. Due to power consumption and cost constraints, the control components cannot process complex cache management algorithms at high speeds, while the processing latency of I / O commands in solid-state storage devices is typically on the order of a few microseconds to tens of microseconds, and the use of cache cannot significantly affect the processing latency of I / O commands. Therefore, how to achieve low-latency identification and cache management of data to be cached with limited processing power has become an urgent problem to be solved.

[0012] According to embodiments of this application, a hot data identification technology is proposed. Hot data has a higher probability of being accessed by the host in the future compared to other data, thus making it suitable for caching. Furthermore, embodiments of this application also propose a hot data caching management technology. By caching hot data into a cache unit provided by SRAM / DRAM in the storage device, the host's access to hot data is changed from accessing the NVM chip to accessing the cache unit. This reduces the latency of IO command processing, improves the performance of the storage device, reduces the number of read / write operations on the NVM chip, extends the lifespan of the NVM chip, reduces the probability of data errors stored in the NVM chip, and also reduces the power consumption of the storage device.

[0013] According to a first aspect of this application, a first hot data identification and processing method according to the first aspect of this application is provided, comprising: obtaining the address accessed by an IO command; if the address accessed by the IO command matches a first entry in a hot data table, accessing a cache unit corresponding to the first entry to process the IO command, and setting the first entry to the beginning of the hot data table; and evicting entries from the end of the hot data table.

[0014] According to the first hot data identification and processing method of the first aspect of this application, a second hot data identification and processing method according to the first aspect of this application is provided, which further includes: if the address accessed by the IO command does not match any entry in the hot data table, accessing the NVM chip to process the IO command.

[0015] According to the first or second hot data identification and processing method of the first aspect of this application, a third hot data identification and processing method according to the first aspect of this application is provided, wherein if the IO command is a read command and the address accessed by the IO command hits the first entry of the hot data table, data is moved from the cache unit corresponding to the first entry to the host as a response to the read command.

[0016] According to the third hot data identification and processing method of the first aspect of this application, a fourth hot data identification and processing method according to the first aspect of this application is provided, wherein if the IO command is a write command and the address accessed by the IO command hits the first entry of the hot data table, the data to be written by the write command is moved to the cache unit corresponding to the first entry, and the type of the first entry is set to modification (m).

[0017] According to one of the first to fourth hot data identification and processing methods of the first aspect of this application, a fifth hot data identification and processing method according to the first aspect of this application is provided, wherein if the IO command is a read command and the address accessed by the IO command does not hit any entry in the hot data table, the NVM chip is accessed according to the address accessed by the read command to read the data to be accessed by the read command, and the data to be accessed by the read command is provided to the host.

[0018] According to the fifth hot data identification and processing method of the first aspect of this application, a sixth hot data identification and processing method according to the first aspect of this application is provided, which further includes: if the IO command is a write command and the address accessed by the IO command does not hit any entry in the hot data table, writing the data to be written by the write command into the NVM chip.

[0019] According to one of the first to sixth hot data identification and processing methods of the first aspect of this application, a seventh hot data identification and processing method according to the first aspect of this application is provided, further comprising: if the address accessed by the IO command does not hit any entry in the hot data table, further identifying whether the address accessed by the IO command hits an access history table; if the address accessed by the IO command hits a second entry in the access history table, incrementing the count value of the second entry; if the count value of the second entry reaches a threshold, generating a third entry and adding it to the front of the hot data table; obtaining an available cache unit; wherein the third entry records the address accessed by the IO command, and the third entry is also associated with the available cache unit; and accessing the available cache unit to process the IO command.

[0020] According to the seventh thermal data identification and processing method of the first aspect of this application, an eighth thermal data identification and processing method according to the first aspect of this application is provided, which further includes: if the IO command is a read command, the record type in the third entry is shared(s); if the IO command is a write command, the record type in the third entry is modified(m).

[0021] According to the seventh or eighth heat data identification and processing method of the first aspect of this application, a ninth heat data identification and processing method according to the first aspect of this application is provided, which further includes: deleting the second entry from the access history table; or modifying the count value of the second entry to a specified value indicating that it is deleted.

[0022] According to one of the seventh to ninth hot data identification and processing methods of the first aspect of this application, a tenth hot data identification and processing method according to the first aspect of this application is provided, wherein if the IO command is a read command, the data read from the NVM chip according to the address of the read command is stored in the available cache unit; the data is moved from the available cache unit to the host in response to the read command.

[0023] According to one of the seventh to tenth hot data identification and processing methods of the first aspect of this application, an eleventh hot data identification and processing method according to the first aspect of this application is provided, wherein if the IO command is a write command, the data to be written by the write command is stored in the available cache unit.

[0024] According to one of the seventh to eleventh methods for hot data identification and processing according to the first aspect of this application, a twelfth method for hot data identification and processing according to the first aspect of this application is provided, which further includes: if the address accessed by the IO command does not match any entry in the access history table, generating a fourth entry and adding it to the front of the access history table; wherein the fourth entry records the address accessed by the IO command and an initial count value.

[0025] According to one of the first to twelfth hot data identification and processing methods of the first aspect of this application, a thirteenth hot data identification and processing method according to the first aspect of this application is provided, further comprising: obtaining entries to be eliminated from the back of the hot data table; if the type of the entry to be eliminated is modification (m), writing the data of the cache unit corresponding to the entry to be eliminated into the NVM chip, and removing the entry to be eliminated from the hot data table; if the type of the entry to be eliminated is shared (s), removing the entry to be eliminated from the hot data table and discarding the data of the cache unit corresponding to the entry to be eliminated.

[0026] According to one of the seventh to thirteenth thermal data identification and processing methods of the first aspect of this application, a fourteenth thermal data identification and processing method according to the first aspect of this application is provided, which further includes: removing entries from the back of the access history table.

[0027] According to a second aspect of this application, a first storage device according to the second aspect of this application is provided, including a control unit, a DRAM and an NVM chip, wherein the control unit performs one of the first to fourteenth thermal data identification and processing methods according to the first aspect of this application. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0029] Figure 1 This is a block diagram of a storage device in the prior art;

[0030] Figure 2A A block diagram of the control components of a storage device according to an embodiment of this application is shown;

[0031] Figure 2B A schematic diagram illustrating the access history table and hot data table according to an embodiment of this application is shown;

[0032] Figure 3 A flowchart illustrating an operation access history table according to an embodiment of this application is shown;

[0033] Figure 4 A flowchart illustrating the operation of a hot data table and the provision of caching according to embodiments of this application is shown; and

[0034] Figure 5 A flowchart illustrating the processing of IO commands according to an embodiment of this application is shown. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0036] Figure 2A A block diagram of the control components of a storage device according to an embodiment of this application is shown.

[0037] The control unit 104 includes a host interface 210, a command processing unit 240, and a media interface controller 220.

[0038] The control unit 104 is also coupled to multiple cache units and the NVM chip. The multiple cache units are provided, for example, by DRAM. Optionally, the multiple cache units are implemented within the control unit 104, belonging to the same chip as the control unit 104.

[0039] The host interface 210 obtains commands (e.g., I / O commands) from the host and provides them to the command processing unit 240. The command processing unit 240 identifies the meaning of the commands, processes them accordingly, and operates the media interface controller 220 to access the NVM chip.

[0040] According to embodiments of this application, the command processing unit 240 also uses the access history table 220 and the hot data table 230 to identify hot data and optimize the processing of hot data. The access history table 220 and the hot data table 230 are stored, for example, in SRAM or DRAM.

[0041] Access history table 220 contains multiple entries, each recording an address and the number of times it was accessed. The addresses recorded in the entries of access history table 220 are, for example, addresses accessed by I / O commands.

[0042] Hot data table 230 includes multiple entries, each recording an address, type, and cache unit index. The address recorded in the entries of hot data table 230 is, for example, an address accessed by an I / O command; the type indicates whether the data in the cache unit corresponding to the entry is shared (S) or modified (M); and the cache unit index indicates the cache unit corresponding to the entry. Optionally, entries in hot data table 230 may not record cache unit indices, but rather their associated cache unit indices are implied by their position within the hot data table 230. For example, the cache unit index associated with the i-th entry in hot data table 230 might be i.

[0043] Understandably, the I / O commands received by the host interface 210 may access variable-length address ranges. For example, the address range accessed by an I / O command may be an integer multiple of a storage unit of, for example, 512 bytes, 4KB, or other sizes. The command processing unit splits the I / O command into multiple subcommands of 512 bytes, 4KB, or other sizes, such that each subcommand accesses an address range of the same size represented by a single storage unit. According to embodiments of this application, the address of each entry in the history table and each entry in the hot data table also represents an address range of a single storage unit. And for simplicity, unless otherwise specified below, the address range accessed by an I / O command is also an address range of a single storage unit.

[0044] Figure 2BA schematic diagram of an access history table and a hot data table according to an embodiment of this application is shown.

[0045] The access history table stores the history of host I / O commands accessing the storage device over a certain period. In response to receiving an I / O command, the command processing unit 240 extracts the address accessed by the I / O command and populates it into the access history table. The data corresponding to the addresses recorded in the access history table entries does not need to be stored in the cache unit. In addition to populating the access history table according to I / O commands, the command processing unit 240 also processes I / O commands according to normal procedures, such as writing data indicated by the I / O command to the NVM chip or reading data from the NVM chip.

[0046] See Figure 2B The first entry (m, 1) represents that address m was accessed once, while the entry (p, k) represents that address p was accessed k times.

[0047] According to an embodiment of this application, in order to populate the access history table, the processing unit 240 obtains the accessed address (denoted as a) from the received IO commands. It searches the access history table using address (a). If an entry with address a is found in the access history table, the count field of that entry is incremented by 1. If no entry with address a is found in the access history table, a new entry with address a and a count value of 1 is created and inserted at the beginning of the access history table. Thus, entries closer to the beginning of the access history table are those inserted later. An exception is that when an entry with the same address as the address accessed by the IO command exists in the access history table, only the count value of that entry is incremented, without adjusting the entry's position in the access history table.

[0048] The space for the access history table is limited, containing, for example, hundreds or thousands of entries. Optionally, the number of entries in the hot data table and the access history table can be set based on the number of cache units used by the storage device. For example, the number of entries in the hot data table may be the same as or substantially the same as the number of cache units, while the number of entries in the access history table may be several times, tens of times, or hundreds of times greater than the number of entries in the hot data table.

[0049] Because the access history table has limited space, some entries need to be removed to free up space for new entries. According to embodiments of this application, entries are retrieved from the end of the access history table and deleted to remove them. For example, to remove an entry, the last entry in the access history table is deleted. Optionally, the process of removing entries is initiated in response to the access history table being full and a new entry needing to be inserted. Still optionally, the process of removing entries is initiated periodically or under specified circumstances.

[0050] This process adds entries to the access history table from the beginning and removes entries from the end. The time from when an entry is added to the access history table until it is removed is the entry's retention time in the access history table. During the entry's retention time, if other I / O commands access the address of the entry, the entry's count is incremented (by 1).

[0051] By using an access history table and adding entries to the table from the beginning and removing entries from the end, it is unnecessary to record a timestamp for each entry or compare the access times of the entry addresses. This allows for a simple way to obtain the number of times an entry was accessed over a period of time. This number is used as a marker to identify whether the data is hot data according to embodiments of this application.

[0052] Furthermore, there is no need to move entries in the access history table, further simplifying the hot data identification process.

[0053] Optionally, an access history table can be provided using a FIFO (First-In, First-Out) queue, where new entries are added to the head of the FIFO queue, and evicted entries are retrieved from the tail of the FIFO queue. Each entry in the queue can be accessed to increment the count field of the hit entries.

[0054] According to an embodiment of this application, if a processing unit 240 receives one or more I / O commands accessing the address of the entry record during the retention period of the entry recorded in the access history table, the processing unit 240 increments the count field of the entry. The processing unit 240 then checks whether the incremented count value reaches a specified threshold. Entries whose counts reach the specified threshold are identified as associated with hot data.

[0055] exist Figure 2B In the example, the threshold is specified as k. The processing unit 240 receives an IO command to access address p, and increments the (p, k) count field of the entry in the access history table according to address p. The incremented count field value has reached k, thereby identifying the data associated with address p as hot data.

[0056] According to an embodiment of this application, corresponding to identifying an entry (p, k) as associated with hot data, the processing unit 240 retrieves the entry (p, k) from the access history table, generates an entry for the hot data table based on the retrieved entry (p, k), and fills it into the hot data table.

[0057] The entry (p, k) is removed from the access history table, creating a vacancy. All entries preceding this vacancy are then shifted to fill the gap. Optionally, to further reduce the burden on the processing unit operating the access history table, the entry (p, k) is left in the access history table and processed later (e.g., evicted) like other entries. Furthermore, the count field of the entry (p, k) left in the access history table is set to a special value (e.g., -1) to distinguish it from other entries.

[0058] Similar to the operation of accessing the history table, entries for the newly generated hot data table are populated at the beginning of the hot data table. Since the space in the hot data table is limited, some entries need to be removed to free up space for new entries. According to embodiments of this application, entries are retrieved from the end of the hot data table and deleted to remove them.

[0059] Entries are added to the hot data table from the beginning and removed from the end. The period from when an entry is added to the hot data table to when it is removed is the retention time of the entry in the hot data table. The data associated with the address of an entry in the hot data table is the hot data identified according to the embodiments of this application. The data associated with the first entries in the hot data table has the highest heat value because it has been accessed recently, while the data associated with the last entries in the hot data table has the lowest heat value because the data has not been accessed for a period of time.

[0060] According to an embodiment of this application, in response to receiving an IO command c (access address p), an entry for a hot data table is generated from the entry (p, k) retrieved from the access history table. The generated hot data table entry records the address p (from the entry (p, k) retrieved from the access history table, or the IO command c). The type field of the hot data table entry is generated based on whether command c is a read command or a write command. If command c is a read command, the type field of the generated hot data table entry is set to shared(s); if command c is a write command, the type field is set to modified(m). Data corresponding to entries of type modified(m) needs to be written to the NVM chip after cooling down. Data corresponding to entries of type shared(s) is only a copy of the data stored in the NVM chip; when the corresponding data cools down, it does not need to be written to the NVM chip.

[0061] The type cache unit index field of the generated hot data table entry records the index or address of the cache unit associated with that entry. In addition to filling the beginning of the hot data table with the generated entry, the data to be accessed by command c is also filled into the cache unit associated with that entry (indicated by the cache unit index of that entry). If command c is a write command, the cache unit carries the data written by the host to the storage device using command c; if command c is a read command, the data to be read by command c is read from the NVM chip and stored in the cache unit, and then the data in the cache unit is moved to the host.

[0062] According to embodiments of this application, the hot data table also functions as a cache. In response to receiving an IO command, the command processing unit 240 first queries the hot data table to find an entry recording the address accessed by the IO command. If an entry recording the address accessed by the IO command exists in the hot data table, it means the IO command has hit an entry or a cache unit. The hit cache unit is then accessed according to the IO command. If the IO command is a write command, the data to be written by the host to the storage device is written to the hit cache unit, and the type of the hit entry is set to modification (m). If the IO command is a read command, the data in the hit cache unit is provided to the host, and the type of the hit entry is not modified. Writing or reading data from a cache unit is faster than accessing the NVM chip; therefore, by querying the hot data table to check if a cache unit has been hit, the processing of IO commands that have hit cache units is accelerated.

[0063] Furthermore, in response to finding an entry in the hot data table that records the address accessed by the I / O command, the entry's position in the hot data table is moved forward to reflect that the data corresponding to that entry has just been accessed. For example, the entry is moved to the beginning of the hot data table.

[0064] The number of entries in a hot data table is the same as the number of cache units, so the number of entries is not large. Once the hot data table is full, entries and their associated cache units need to be evicted. For example, when the hot data table is full or nearing full, entries in the hot data table are evicted to ensure that there is available space to accommodate new entries. As another example, when the hot data table is full or nearing full, entries in the hot data table are evicted in response to new entries being added to the hot data table.

[0065] To remove entries from the hot data table, entries from the latter part or last part of the hot data table are selected. The data associated with this entry is the least popular data among all the data associated with the hot data table. For the selected entry, if its type is shared(s), it indicates that the data stored on the NVM chip is consistent with the data in the cache unit associated with the entry. Therefore, the entry is deleted (removed from the hot data table), and the data in the cache unit is discarded without writing the data to the NVM chip. If the selected entry's type is modified(m), it indicates that the data stored on the NVM chip is inconsistent with the data in the cache unit associated with the entry. Therefore, the data in the cache unit associated with the entry is written to the NVM chip, and then the entry is deleted.

[0066] Figure 3 A flowchart illustrating an operation access history table according to an embodiment of this application is provided.

[0067] The command processing unit obtains the IO command (310), extracts the address accessed by the IO command, and queries the access history table based on the address to determine whether the access history table is hit (320). If there is an entry in the access history table that records the address accessed by the IO command, it is said that the address of the IO command hits the access history table.

[0068] If the address accessed by the IO command matches entry i (320), the count field of the matched entry i is incremented (by 1) (330). Optionally, the position of entry i in the access history table is not changed. And if the incremented count value of entry i reaches a specified threshold (340), an entry is added to the hot data table according to the IO command and entry i, and entry i is removed from the access history table (350). The entry to be added to the hot data table is generated according to the address accessed by the IO command and whether the IO command is a read command or a write command. Available cache units are also obtained for the IO command. For example, available cache units are allocated, and the index of the allocated cache units is recorded in the generated entry of the hot data table. As another example, the position where the entry is added to the hot data table indicates the available cache units.

[0069] If the IO command is a read command, the type of the generated hot data table entry indicates shared(s). Data is read from the NVM chip according to the address accessed by the IO command, and the read data is stored in the cache unit (370) indicated by the generated hot data table entry. The data is then moved from the cache unit to the host in response to the read command. If the IO command is a write command, the type of the generated hot data table entry indicates modified(m). The data to be written by the IO command is written to the cache unit (380) indicated by the generated hot data table entry. The data is then written from the cache unit to the NVM chip.

[0070] See Figure 3Returning to step 320, if the address of the IO command does not match the access history table, a new entry is generated based on the address accessed by the IO command. The new entry indicates the address of the IO command and the initial count value (e.g., 1). The new entry is added to the beginning of the access history table (322).

[0071] When necessary, old entries are also removed from the last part of the access history table (324).

[0072] Returning to step 340, if the incremented count value of entry i does not reach the specified threshold, the NVM chip is accessed to process the read command. According to embodiments of this application, a cache unit associated with the hot data table is not used to process the IO command. If the IO command is a read command, data is read from the NVM chip according to the address accessed by the IO command and provided to the host. If the IO command is a write command, the data to be written by the IO command is written to the NVM chip.

[0073] Figure 4 A flowchart illustrating the operation of a hot data table and the provision of caching according to an embodiment of this application is shown.

[0074] The command processing unit obtains the IO command (410), extracts the address accessed by the IO command, and queries the access history table based on the address to determine whether the hot data table is hit (420). If there is an entry in the hot data table that records the address accessed by the IO command, it is said that the address of the IO command hits the hot data table.

[0075] If the address accessed by the IO command hits entry i (420) of the hot data table, it means that a cache unit has already been allocated for the address accessed by the IO command. Then, the method of using the allocated cache unit is determined according to whether the IO command is a read command or a write command (430).

[0076] If the IO command is a read command, data is read from the cache unit corresponding to the hit entry i (432), and the read data is moved to the host as a response to the read command, without needing to access the NVM chip based on the address of the read command. Also, there is no need to change the type field of entry i.

[0077] If the IO command is a write command, the data to be written by the write command is moved from the host to the cache unit (434) corresponding to the hit entry i, and the type field of entry i is set to modification (m). The data written to the cache unit corresponding to entry i does not need to be written to the NVM chip immediately, but is written to the NVM chip only after the data cools down and entry i is to be evicted from the hot data table.

[0078] The hit entry i is also moved to the front of the hot data table (440). By moving entry i to the very front of the hot data table, entry i will remain in the hot data table for a longer period of time and will be expected to be hit again.

[0079] When necessary, entries are also evicted from the end of the hot data table (450). The type of the entry to be evicted is obtained. If the type of the entry to be evicted is Modify(m) (452), the data of the cache unit corresponding to the entry to be evicted is written to the NVM chip (454), and the entry to be evicted is removed from the hot data table (456). If the type of the entry to be evicted is Shared(s) (452), the data of the cache unit corresponding to the entry is modified directly without writing the data to the NVM chip, and the entry to be evicted is removed from the hot data table (456).

[0080] Continue reading Figure 4 Returning to step 420, if the address accessed by the IO command does not match any entry in the hot data table, the cache unit associated with the hot data table is not used to process the IO command. If the IO command is a read command (422), data is read from the NVM chip according to the address accessed by the IO command and provided to the host (424). If the IO command is a write command (422), the data to be written by the IO command is written to the NVM chip (426).

[0081] Figure 5 A flowchart illustrating the processing of IO commands according to an embodiment of this application is shown.

[0082] The command processing unit obtains the IO command (510). It determines whether the hot data table has been hit based on the address accessed by the IO command (520).

[0083] If the address accessed by the IO command hits entry i in the hot data table (520), then the cache unit corresponding to entry i is accessed to process the IO command (530). If the IO command is a read command, data is read from the cache unit corresponding to the hit entry i, and the read data is moved to the host as a response to the read command. If the IO command is a write command, the data to be written by the write command is moved from the host to the cache unit corresponding to the hit entry i, and the type field of entry i is set to modification (m). The hit entry i is also moved to the front of the hot data table (540). By moving entry i to the very front of the hot data table, entry i will remain in the hot data table for a longer period of time, and it is expected to be hit again.

[0084] When necessary, entries are also evicted from the end of the hot data table (590). The type of the entry to be evicted is obtained. If the type of the entry to be evicted is Modify (m) (592), the data of the cache unit corresponding to the entry to be evicted is written to the NVM chip (594), and the entry to be evicted is removed from the hot data table (596). If the type of the entry to be evicted is Shared (s) (592), the data of the cache unit corresponding to the entry is modified directly without writing the data to the NVM chip, and the entry to be evicted is removed from the hot data table (596).

[0085] Continue reading Figure 5 Returning to step 520, if the address accessed by the IO command does not match any entry in the hot data table, the IO command is not processed using the cache unit associated with the hot data table. Instead, the IO command is processed, for example, by accessing the NVM chip (550). If the IO command is a read command, data is read from the NVM chip according to the address accessed by the IO command and provided to the host. If the IO command is a write command, the data to be written by the IO command is written to the NVM chip.

[0086] In step 520, if the address accessed by the IO command does not match any entry in the hot data table, the address accessed by the IO command is extracted, and the access history table is queried based on the address to determine whether the access history table is matched (560).

[0087] If the address accessed by the IO command matches an entry hi in the access history table (560), the count field of the matched entry hi is incremented (by 1) (570). And if the incremented count value of entry hi reaches a specified threshold (575), a new entry is added to the hot data table based on the IO command and entry hi, and entry hi is removed from the access history table (580). An available cache unit is also obtained for the IO command. The new entry added to the hot data table is associated with the available cache unit. The available cache unit is accessed to process the IO command. In step 550, the data associated with the accessed NVM chip is moved to the available cache unit. If the IO command is a read command, the data read from the NVM chip based on the address accessed by the IO command is first moved to the available cache unit, and then the data is provided to the host from the cache unit; if the IO command is a write command, the data to be written by the IO command is first stored in the available cache unit, and then the data in the cache unit is written to the NVM chip. Thus, the cache unit records the data corresponding to the address accessed by the IO command.

[0088] If the IO command is a read command, the type of the generated hot data table entry indicates shared(s). If the IO command is a write command, the type of the generated hot data table entry indicates modified(m).

[0089] Continue reading Figure 5Returning to step 560, if the address accessed by the IO command does not match the access history table, a new entry is generated based on the address accessed by the IO command, and the new entry is added to the beginning of the access history table (562). When necessary, old entries are also removed from the end of the access history table (564).

[0090] According to an embodiment of this application, a storage device is also provided, including a controller and a non-volatile memory chip, wherein the controller executes any of the processing methods provided in the embodiments of this application.

[0091] According to embodiments of this application, a program stored on a readable medium is also provided, which, when the controller of the storage device is run, causes the storage device to execute any of the processing methods provided according to embodiments of this application.

[0092] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for hot data identification and processing, comprising: obtaining an address accessed by an IO command; if the address accessed by the IO command hits a first entry of a hot data table, accessing a cache unit corresponding to the first entry to process the IO command, and setting the first entry to a front part of the hot data table; and evicting an entry at a rear part of the hot data table; if the address accessed by the IO command does not hit any entry of the hot data table, and the IO command is a write command, storing data to be written by the IO command in an available cache unit first, and then writing data in the cache unit to a NVM chip, the data in the cache unit recording data corresponding to the address accessed by the IO command; wherein a data associated with an entry at a frontmost part of the hot data table has a highest hotness, and a data associated with an entry at a rearmost part of the hot data table has a lowest hotness. 2.The method of claim 1, further comprising: if the address accessed by the IO command does not hit any entry of the hot data table, accessing the NVM chip to process the IO command. 3.The method of claim 1 or 2, wherein if the IO command is a read command, and the address accessed by the IO command hits the first entry of the hot data table, moving data from the cache unit corresponding to the first entry to a host as a response to the read command; if the IO command is a write command, and the address accessed by the IO command hits the first entry of the hot data table, moving data to be written by the write command to the cache unit corresponding to the first entry, and setting a type of the first entry as modified (m). 4.The method of any one of claims 1-3, further comprising: if the address accessed by the IO command does not hit any entry of the hot data table, further identifying whether the address accessed by the IO command hits a second entry of an access history table; if the address accessed by the IO command hits the second entry of the access history table, incrementing a count value of the second entry; if the count value of the second entry reaches a threshold value, generating a third entry to be added to the front part of the hot data table; obtaining an available cache unit; wherein the third entry records the address accessed by the IO command, and the third entry is further associated with the available cache unit; accessing the available cache unit to process the IO command. 5.The method of claim 4, further comprising: if the IO command is a read command, recording a type as shared (s) in the third entry; if the IO command is a write command, recording a type as modified (m) in the third entry. 6.The method of claim 4 or 5, wherein if the IO command is a read command, storing data read from the NVM chip according to the address of the read command in the available cache unit; moving data from the available cache unit to the host to respond to the read command. 7.The method of any one of claims 4-6, further comprising: if the address accessed by the IO command does not hit any entry of the access history table, generating a fourth entry to be added to a front part of the access history table; wherein the fourth entry records the address accessed by the IO command and an initial count value.

8. The method of any of claims 1-7, further comprising: obtaining an entry to be evicted from a back of the hot data table; if a type of the entry to be evicted is modification (m), writing data of a cache unit corresponding to the entry to be evicted to the NVM chip, and removing the entry to be evicted from the hot data table; if the type of the entry to be evicted is shared (s), removing the entry to be evicted from the hot data table and discarding data of the cache unit corresponding to the entry to be evicted.

9. The method of any of claims 4-8, further comprising: removing an entry from a back of the access history table.

10. A storage device comprising a control component, a DRAM, and an NVM chip, the control component performing the method of any of claims 1-9.

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