Inverter and method for measuring phase current in an electric machine

Abstract

The present disclosure relates to an inverter and a method for measuring phase current in an electric motor. A three-phase load is powered by a DC-AC inverter driven by a PWM (e.g., SVPWM) having a single shunt topology. During the second period of each SVPWM sector, the shunt voltage and branch voltage of the inverter (across the transistor to be calibrated) are measured, and the drain-to-source resistance of the calibration transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibration transistor and the voltage across the calibration transistor measured during the fourth period, the phase current through the calibration transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor, the phase current through the transistor is calculated. From the two calculated phase currents, another phase current can be calculated.

Description

Technical Field

[0001] The present disclosure relates generally to inverters for driving a three-phase motor, and particularly to methods of using a single common shunt resistor to reliably measure phase currents supplied by the inverter to the motor. Background Art

[0002] The phase windings of a three-phase motor can be controlled using pulse width modulation (PWM) signals. To power a three-phase motor using a DC power source such as a battery, the PWM control signal is applied to a three-phase inverter, which in turn powers the three-phase motor. The transistors of the three-phase inverter connect the phase winding taps of the motor to the positive or negative supply voltage rail and ground.

[0003] In order to obtain feedback knowledge for controlling the motor, the current flowing through each phase winding is determined. The phase current measurements are provided to a controller which generates PWM drive signals for the transistors that control the three-phase inverter. Traditionally, the phase current information can be obtained by sensing the voltage drop across a different resistor in series with each phase winding. In some designs, phase current sensing may be performed for only two of the three phase windings, given the fact that the sum of all currents flowing through the phase windings will be zero, and thus by sensing the current flowing through two phase windings, the current flowing through the third phase winding may be calculated.

[0004] Some techniques have been developed based on the use of a single common shunt resistor connected between the DC power source and the inverter. Such techniques may involve measuring the drain to source voltage of the inverter's transistors. Depending on the state of the inverter's transistors, the current of two of the three phase windings may be sensed across the single common shunt resistor.

[0005] These techniques of measuring phase current using a single common shunt resistor have proven to be inaccurate because both sense currents cannot be sensed simultaneously and because the measurement of the drain to source voltage of the transistor is affected by the nonlinearity of the transistor. However, to save costs, it is still desirable to use a single common shunt resistor to measure phase current. Therefore, further development is needed. Summary of the invention

[0006] A DC-AC inverter system for coupling to three phase windings of a motor is disclosed herein. The inverter system includes: a first switch branch coupled between a DC power supply voltage node and an intermediate node, the first switch branch having a first terminal for coupling to a first phase winding of the motor; a second switch branch coupled between the DC power supply voltage node and the intermediate node, the second switch branch having a second terminal for coupling to a second phase winding of the motor; a third switch branch coupled between the DC power supply voltage node and the intermediate node, the third switch branch having a third terminal for coupling to a third phase winding of the motor; a shunt resistor coupled between the intermediate node and ground; and a control circuit.

[0007] The control circuit is configured to apply control signals to the first switching branch, the second switching branch, and the third switching branch according to a space vector pulse width modulation (SVPWM) scheme so that the inverter drives the first phase winding, the second phase winding, and the third phase winding of the motor using a three-phase AC power signal.

[0008] The SVPWM scheme is divided into six sectors, where each sector is divided into a number of periods.

[0009] The control circuit is configured to, during at least some sectors of the SVPWM scheme:

[0010] During a second period: measuring a shunt voltage across the shunt resistor; and measuring a drain-to-source voltage of a first calibration transistor, the first calibration transistor being a transistor of a given switch leg; and

[0011] During a fourth period: measuring the drain-to-source voltage of the first calibration transistor; and measuring the drain-to-source voltage of a measured transistor, the measured transistor being a transistor of the next switching branch;

[0012] determining a drain-to-source resistance of the first calibration transistor based on a resistance of the shunt resistor, a drain-to-source voltage of the first calibration transistor measured during the second period, and a shunt voltage measured during the second period;

[0013] determining a phase current of a given phase winding coupled to a given switching branch based on a drain-to-source voltage of the first calibration transistor and a drain-to-source resistance of the first calibration transistor measured during a fourth time period;

[0014] determining a phase current of a next phase winding coupled to a next switching branch based on the drain-to-source voltage of the measured transistor measured during a fourth period and the drain-to-source resistance of the measured transistor known from a previous sector of the SVPWM scheme; and

[0015] Phase currents of the remaining phase windings coupled to the remaining switching branches are determined based on the phase current of the given phase winding and the phase current of the next phase winding. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram of a power system in which the techniques described herein may be employed;

[0017] Figure 2 is a graph of six-sector space vectors for space vector pulse width modulation (SVPWM);

[0018] Figure 3A-Figure 3F The six sectors of SVPWM are shown in Figure 2. Figure 1 and a graph illustrating sampling points for performing the first phase current determination technique described herein; and

[0019] Figure 4 The fourth sector period of SVPWM is shown in FIG. Figure 1 FIG. 4 is a graph illustrating the operation of a three-phase inverter of a power system of FIG. 1 and showing sampling points for performing the second phase current determination technique described herein. DETAILED DESCRIPTION

[0020] The following disclosure enables those skilled in the art to make and use the technical solutions disclosed herein. Without departing from the spirit and scope of the present disclosure, the general principles described herein can be applied to embodiments and applications other than the embodiments and applications described in detail above. The present disclosure is not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0021] The power system 10 includes a three-phase inverter bridge 12 for supplying power to a motor 11. Figure 1 As shown. The three-phase inverter bridge 12 includes six power switches (n-channel transistors) MN1, MN2, MN3, MN4, MN5 and MN6. Figure 1 An n-channel MOSFET is shown in FIG. 1 , but the power system 10 may utilize any suitable power switch device as long as the voltage drop across the power switch device varies according to the current flowing through the power switch device.

[0022] In particular, the drain of the n-channel transistor MN1 is coupled to the power supply voltage Vcc, its source is coupled to the terminal U, and its gate is coupled to receive the control signal Uh; and the drain of the n-channel transistor MN2 is coupled to the terminal U, its source is coupled to the first terminal of the common shunt resistor Rshunt, and its gate is coupled to receive the control signal Ul. The drain of the n-channel transistor MN3 is coupled to the power supply voltage Vcc, its source is coupled to the terminal V, and its gate is coupled to receive the control signal Vh; and the drain of the n-channel transistor MN4 is coupled to the terminal V, its source is coupled to the first terminal of the common shunt resistor Rshunt, and its gate is coupled to receive the control signal Vl. The drain of the n-channel transistor MN5 is coupled to the power supply voltage Vcc, its source is coupled to the terminal W, and its gate is coupled to receive the control signal Wh; and the drain of the n-channel transistor MN6 is coupled to the terminal W, its source is coupled to the first terminal of the common shunt resistor Rshunt, and its gate is coupled to receive the control signal Wl.

[0023] Three impedance elements Zu, Zv and Zw are respectively located between terminals U, V and W of the three-phase inverter bridge 12 and voltage sources Vswu, Vswv and Vsww. The voltage sources Vswu, Vswv and Vsww are coupled to each other at a central node N. The impedance elements Zu, Zv and Zw and the voltage sources Vswu, Vswv and Vsww represent an equivalent circuit of three phase windings of the motor 11 configured as a Y-connected load driven by the three-phase inverter bridge 12, in which phase currents Iu, Iv and Iw flow.

[0024] A single common current sensing resistor Rshunt is connected between the sources of n-channel transistors MN2 , MN4 , and MN6 and ground, and is therefore used to sense the DC current Ishunt returned to the power supply PSUP.

[0025] The phase current is assumed to be positive when it flows from the terminals U, V and W to the phase winding, and the DC current Ishunt is assumed to be positive when it flows towards ground.

[0026] Complementary pulse width modulation (PWM) signals Uh, Ul and Vh, Vl and Wh, Vl control the high-side transistor and the low-side transistor of each leg of the three-phase bridge 12 (i.e., MN1, MN2 and MN3, MN4 and MN5, MN6, respectively), with dead time insertion to exclude the risk of simultaneous on-state of two transistors of a given leg of the three-phase bridge 12 (which could result in a potentially destructive short circuit).

[0027] The inductive characteristics of the motor 11 load and the resulting phase lag between current and voltage may result in an irreversible reduction in the resulting peak-to-peak voltage of the 120° electrically out-of-phase voltage waveform produced on the phase windings Zu, Zv, Zw when driven by the corresponding PWM signals Uh, Ul and Vh, Vl and Wh, Wl.

[0028] The amplification / filtering / digitization block 14 receives the voltage Vshunt across the resistor Rshunt, the drain-to-source voltage Vu of MN2, the drain-to-source voltage Vv of MN4, and the drain-to-source voltage Vw of MN6 as feedback, conditions these signals, and passes them in a conditioned form to the microcontroller 13. The microcontroller 13 generates control signals Uh, Ul for MN1-MN2, control signals Vh, Vl for MN3-MN4, and control signals Wh, Wl for MN5-MN6. Note that in some cases, amplification and / or filtering may be optional.

[0029] The methods and techniques described herein are for determining the phase currents Iu, Iv, Iw of a motor 11 powered by a three-phase bridge 12 controlled by space vector pulse width modulation (SVPWM). However, the disclosed techniques are applicable to any motor powered by a three-phase inverter controlled by any PWM scheme.

[0030] For each configuration of the low-side transistors MN2 , MN4 , MN6 of the three legs of the three-phase bridge 12 , the current flowing in the shunt resistor Rshunt connected between the sources of MN2 , MN4 and MN6 and ground is shown in Table 1 below.

[0031] Ul(MN2) Vl(MN4) Wl(MN6) Ishunt 0(Disconnected) 0(Disconnected) 0(Disconnected) 0 0(Disconnected) 1 (closed) 1 (closed) IU 0(Disconnected) 0(Disconnected) 1 (closed) -Iw 1 (closed) 0(Disconnected) 1 (closed) Iv 1 (closed) 0(Disconnected) 0(Disconnected) -Iu 1 (closed) 1 (closed) 0(Disconnected) I 0(Disconnected) 1 (closed) 0(Disconnected) -Iv

[0032] As understood by those skilled in the art, SVPWM is a modulation scheme for applying a given voltage vector to the motor by switching the transistors MN1-MN6 of the three-phase bridge 12 in different configurations in the above table for different time periods to simulate a three-phase sinusoidal waveform (a "space vector", which is simply the vector sum of the three phase voltages Vu, Vv, Vw produced by the three-phase bridge 12 when modulated according to SVPWM).

[0033] As also understood by those skilled in the art, a complete cycle of SVPWM modulation is divided into six "sectors". The space vectors used can be Figure 2 As will be seen, each sector contains seven time periods.

[0034] Described herein are techniques for accurately determining the phase currents Iu, Iv, Iw of a three-phase bridge 12 using a single shunt Rshunt topology three-phase bridge 12. From these determined phase currents (used as feedback), the microcontroller 13 can, in some cases, generate control signals Uh, Ul for MN1-MN2, control signals Vh, Vl for MN3-MN4, and control signals Wh, Wl for MN5-MN6 in order to control the motor 11 and enhance the operation of the motor 11.

[0035] First technology (for high motor speeds)

[0036] Now refer to Figure 3A-Figure 3F The first technique is described. Note that reference Figure 3A-Figure 3F The described technique is particularly useful when the speed of the motor is high. In general, the technique works by measuring Vshunt and one of the voltages Vu, Vv, Vw during the second period of each sector of the SVPWM, and calculating the drain-to-source resistance of the transistor (e.g., MN2, MN4, MN6) across which the voltage Vu, Vv, or Vw is measured from those two measured voltages - the drain-to-source resistance can be referred to as the calibrated drain-to-source resistance for that sector of the SVPWM (the sampled drain-to-source resistance of the transistor at that moment, which takes into account various conditions that may affect the drain-to-source resistance, such as temperature, gate current, drain current, etc.), and the corresponding transistor can be referred to as the calibration transistor. Then, during the fourth period of each sector of the SVPWM, the voltage Vu, Vv, or Vw measured during the second period is measured again, and one of the other voltages Vu, Vv, or Vw across the corresponding transistor (e.g., MN2, MN4, MN6) is measured. The transistor corresponding to the voltage read during the fourth period of each sector of the SVPWM can be referred to as the reading transistor.

[0037] The phase current (through the calibration transistor) is calculated using the calibrated drain-to-source resistance and the voltage measured again during the fourth period of this sector of the SVPWM. Then, the phase current (through the read transistor) is calculated using the voltage measured across the other read transistor during the fourth period and the drain-to-source resistance across the read transistor (calculated during the previous sector of the SVPWM). Finally, since the phase currents are known to sum to zero, another phase current can be calculated for the two calculated phase currents for this sector of the SVPWM.

[0038] Therefore, this first technique can be briefly summarized by the following steps performed for each SVPWM sector:

[0039] 1. During the second period of the SVPWM sector, measure Vshunt and the phase voltage (Vu, Vv or Vw) corresponding to the voltage across the transistor to be calibrated.

[0040] 2. Calculate the calibrated drain-to-source resistance RDS of the calibration transistor (MN2, MN4, or MN6) as:

[0041]

[0042] Wherein "calibration transistor" is the transistor calibrated during this sector of the SVPWM, "Rshunt" is the resistance of resistor Rshunt, "Vshunt2" is the voltage across Rshunt during the second period of this sector of the SVPWM, and "Vphase2" is the voltage across the calibration transistor during the second period of this sector of the SVPWM.

[0043] 3. During the fourth period of the SVPWM sector, measure the voltage across the calibration transistor and the voltage across another of the transistors (MN2, MN4, or MN6).

[0044] 4. Calculate the phase current for the calibration transistor as:

[0045] Iphase(calibration transistor) = Vphase4 / Rds(calibration transistor)

[0046] Where "calibration transistor" is the transistor that is calibrated during a sector of the SVPWM, and "Vphase4" is the voltage across the calibration transistor during the fourth period of the sector of the SVPWM.

[0047] 5. Calculate the phase current for the read transistor across which the voltage was measured during step 3 (not the calibration transistor) as:

[0048] Iphase(read transistor) = V(read transistor) / Rds(read transistor)

[0049] Wherein the “read transistor” is the transistor other than the calibration transistor across which the voltage is measured during step 3, wherein “V(read transistor)” is the voltage across the “read transistor” measured during step 3, and wherein “Rds(read transistor)” is the drain-to-source resistance of the “read transistor” calculated when the sector was calibrated during a previous sector of the SVPWM.

[0050] 6. Calculate the phase current for the remaining transistors as:

[0051] Iother=-[Iphase(calibration transistor)+Iphase(reading transistor)]

[0052] Note that the values ​​measured during the second period of the SVPWM sector should be measured simultaneously, substantially simultaneously, or as close in time as possible (e.g., 1 μs or less; the inductance of the motor 10 is higher and the DC voltage VCC is higher). This measurement involves digitizing the measured values ​​by the amplification / filtering / digitization block 14, and the values ​​may be sampled once to produce a digitized version thereof, or may be sampled multiple times and those samples averaged, filtered, dithered, etc. to produce a digitized version.

[0053] In addition, the values ​​measured during the third period of the SVPWM sector should be measured simultaneously, substantially simultaneously, or as close in time as possible. The measurement involves digitizing the measured values ​​by the amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce a digitized version thereof, or can be sampled multiple times and those samples averaged, filtered, jittered, etc. to produce a digitized version.

[0054] The values ​​measured during the fourth period of the SVPWM sector should be measured simultaneously, substantially simultaneously, or as close in time as possible. The measurement involves digitizing the measured values ​​by the amplification / filtering / digitization block 14, and the values ​​may be sampled once to produce a digitized version thereof, or may be sampled multiple times and those samples averaged, filtered, jittered, etc. to produce a digitized version.

[0055] Shown below is a diagram outlining which transistors are calibration transistors and which are read transistors for each sector of the SVPWM when using the first technique.

[0056]

[0057] Note that in this diagram, the selection of the second transistor to be read during the fourth period (e.g., MN4 in sector 1, MN2 in sector 2, MN6 in sector 3, MN4 in sector 4, MN2 in sector 5, and MN6 in sector 6) is performed taking into account the two maximum duty cycles available in each sector. Another transistor (e.g., MN6 in the case of sector 1) could be selected, but its duty cycle might not be long enough to complete sampling of the voltage across that transistor. Thus, those skilled in the art will recognize that this diagram shows an optimized selection of transistors to be read based on this objective, and that other selections are possible based on different objectives, or when using different PWM modulation techniques (as opposed to SVPWM).

[0058] From the graph, it can be understood that the oldest calibrated drain-to-source resistor used is three sectors old.

[0059] Now refer to Figure 3A-Figure 3F The entire cycle of this first technique is shown graphically and mathematically.

[0060] A. First SVPWM sector

[0061] Turning now to the first SVPWM sector, the phase current determination technique continues over seven periods P1-P7. From the beginning of the second period until the end of the sixth period, U1 is high (which can be seen to turn MN2 on), from the beginning of the third period to the end of the fifth period, V1 is high (which can be seen to turn MN4 on), and during the fourth period, W1 is high (which can be seen to turn MN6 on). Wh, Vh and Uh are the complements of W1, V1 and U1, so the operation of transistors MN1, MN3, MN5 is complementary to the operation of transistors MN2, MN4, MN6 described above.

[0062] During the first SVPWM sector, the phase currents Iu, Iv, Iw are calculated as follows, where it should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt as well as Vu, Vv and Vw in the measurement steps described below, and the microcontroller 13 in turn generates control signals Uh, Ul, Vh, Vl, Wh and Wl.

[0063] During the second period, the shunt voltage Vshunt is measured across the shunt resistor Rsh and is at a value of Vu2_sh, and the voltage Vu is measured and is at -Vu2_mos. From this, the drain-to-source voltage of MN2 can be calculated as:

[0064]

[0065] During the fourth period, the voltages Vu and Vv are measured, and at this point, the voltages Vu and Vv are at values ​​of Vu4_mos and Vv4_mos, respectively. Now, the phase currents Iu, Iv, and Iw can be calculated. Specifically, with the value of RdsMN2, the phase current Iu can be calculated as:

[0066] Iu=Vu4_mos / RdsMN2

[0067] With the value RdsMN4 from the last calculation of this value, the phase current Iv can be calculated as:

[0068] Iv=Vv4_mos / RdsMN4

[0069] Since the sum of the phase currents Iu, Iv and Iw is zero, Iw can be calculated as:

[0070] Iw=-(Vu4_mos / RdsMN2+Vv4_mos / RdsMN4)

[0071] The values ​​of Vshunt and Vu measured during the second period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt and Vu by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vshunt and Vu, or may be sampled multiple times and those samples averaged to produce digitized versions of Vshunt and Vu.

[0072] Similarly, the values ​​of Vu and Vv measured during the fourth period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vu and Vv by the amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digitized versions of Vu and Vv, or can be sampled multiple times and those samples are averaged to produce digitized versions of Vu and Vv.

[0073] B. Second SVPWM sector

[0074] Turning now to the second SVPWM sector, the phase current determination technique continues over seven periods P1-P7. It can be seen that from the beginning of the third period until the end of the fifth period, U1 is high (causing MN2 to turn on), from the beginning of the second period to the end of the sixth period, V1 is high (causing MN4 to turn on), and during the fourth period, W1 is high (causing MN6 to turn on). Wh, Vh and Uh are the complements of W1, V1 and U1, so the operation of transistors MN1, MN3, MN5 is complementary to the operation of transistors MN2, MN4, MN6 described above.

[0075] During the second SVPWM sector, the phase currents Iu, Iv, Iw are calculated as follows, where it should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt as well as Vu, Vv and Vw in the measurement steps described below, and the microcontroller 13 in turn generates control signals Uh, Ul, Vh, Vl, Wh and Wl.

[0076] During the second period, the shunt voltage Vshunt is measured across the shunt resistor Rsh, and here, the shunt voltage Vshunt is at a value of Vv2_sh, and the voltage Vv is measured, and the voltage Vv is at -Vv2_mos. From this, the drain-to-source voltage of MN4 can be calculated as:

[0077]

[0078] During the fourth period, the voltages Vu and Vv are measured, and at this point, the voltages Vu and Vv are at values ​​of Vu4_mos and Vv4_mos, respectively. Now, the phase currents Iu, Iv, and Iw can be calculated. Specifically, with the value of RdsMN4, the phase current Iv can be calculated as:

[0079] Iv=Vv4_mos / RdsMN4

[0080] With the value RdsMN2 from the first sector of SVPWM, the phase current Iu can be calculated as:

[0081] Iu=Vu4_mos / RdsMN2

[0082] Since the sum of the phase currents Iu, Iv and Iw is zero, Iw can be calculated as:

[0083] Iw=-(Vu4_mos / RdsMN2+Vv4_mos / RdsMN4)

[0084] The values ​​of Vshunt and Vv measured during the second period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt and Vu by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vshunt and Vv, or may be sampled multiple times and those samples averaged to produce digitized versions of Vshunt and Vv.

[0085] Similarly, the values ​​of Vu and Vv measured during the fourth period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vu and Vv by the amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digitized versions of Vu and Vv, or can be sampled multiple times and those samples are averaged to produce digitized versions of Vu and Vv.

[0086] C. Third SVPWM sector

[0087] Turning now to the third SVPWM sector, the phase current determination technique continues over seven periods P1-P7. It can be seen that during the fourth period, U1 is high (causing MN2 to turn on), from the beginning of the second period to the end of the sixth period, V1 is high (causing MN4 to turn on), and from the beginning of the third period to the end of the fifth period, W1 is high (causing MN6 to turn on). Wh, Vh and Uh are the complements of W1, V1 and U1, so the operation of transistors MN1, MN3, MN5 is complementary to the operation of transistors MN2, MN4, MN6 described above.

[0088] During the third SVPWM sector, the phase currents Iu, Iv, Iw are calculated as follows, where it should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt as well as Vu, Vv and Vw in the measurement steps described below, and the microcontroller 13 in turn generates control signals Uh, Ul, Vh, Vl, Wh and Wl.

[0089] During the second period, the shunt voltage Vshunt is measured across the shunt resistor Rsh, and here, the shunt voltage Vshunt is at a value of Vv2_sh, and the voltage Vv is measured, and the voltage Vv is at -Vv2_mos. From this, the drain-to-source voltage of MN4 can be calculated as:

[0090]

[0091] During the fourth period, the voltages Vv and Vw are measured, and at this point, the voltages Vv and Vw are at values ​​of Vv4_mos and Vw4_mos, respectively. Now, the phase currents Iu, Iv, and Iw can be calculated. Specifically, with the value of RdsMN4, the phase current Iv can be calculated as:

[0092] Iv=Vv4_mos / RdsMN4

[0093] With the value RdsMN6 from the previous sector of SVPWM, the phase current Iw can be calculated as:

[0094] Iw=Vw4_mos / RdsMN6

[0095] Since the sum of the phase currents Iu, Iv and Iw is zero, Iu can be calculated as:

[0096] Iu=-(Vv4_mos / RdsMN4+Vw4_mos / RdsMN6)

[0097] The values ​​of Vshunt and Vv measured during the second period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt and Vu by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vshunt and Vv, or may be sampled multiple times and those samples averaged to produce digitized versions of Vshunt and Vv.

[0098] Similarly, the values ​​of Vv and Vw measured during the fourth period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vv and Vw by the amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digitized versions of Vv and Vw, or can be sampled multiple times and those samples are averaged to produce digitized versions of Vv and Vw.

[0099] D. Fourth SVPWM sector

[0100] Turning now to the fourth SVPWM sector, the phase current determination technique continues over seven periods P1-P7. It can be seen that during the fourth period, U1 is high (causing MN2 to turn on), from the beginning of the third period to the end of the fifth period, V1 is high (causing MN4 to turn on), and from the beginning of the second period to the end of the sixth period, W1 is high (causing MN6 to turn on). Wh, Vh and Uh are the complements of W1, V1 and U1, so the operation of transistors MN1, MN3, MN5 is complementary to the operation of transistors MN2, MN4, MN6 described above.

[0101] During the fourth SVPWM sector, the phase currents Iu, Iv, Iw are calculated as follows, where it should be understood that the amplification / filtering / digitization block 14 digitizes and regulates Vshunt as well as Vu, Vv and Vw in the measurement steps described below, and the microcontroller 13 in turn generates control signals Uh, Ul, Vh, Vl, Wh and Wl.

[0102] During the second period, the shunt voltage Vshunt is measured across the shunt resistor Rsh, and at this point, the shunt voltage Vshunt is at a value of Vw2_sh, and the voltage Vw is measured, and at this point, the voltage Vw is at a value of Vw2_mos. From this, the drain-to-source resistance of MN6 can be calculated as:

[0103]

[0104] During the fourth period, the voltage Vv is measured and at this point is at a value of Vv4_mos, and the voltage Vw is measured and at this point is at a value of Vw4_mos. Now, with the value of RdsMN6, and with the value of RdsMN4 from the previous SVPWM sector, the phase current Iv can be calculated as:

[0105] Iv=Vv4_mos / RdsMN4

[0106] Then, the phase current Iw can be calculated as:

[0107] Iw=Vw4_mos / RdsMN6

[0108] Since the sum of the phase currents Iu, Iv and Iw is zero, Iu can be calculated as:

[0109] Iu=-(Vv4_mos / RdsMN4+Vw4_mos / RdsMN6)

[0110] The values ​​of Vshunt and Vw measured during the second period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt and Vw by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vshunt and Vw, or may be sampled multiple times and those samples averaged to produce digitized versions of Vshunt and Vw.

[0111] The values ​​of Vv and Vw measured during the fourth period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vv and Vw by the amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digitized versions of Vv and Vw, or can be sampled multiple times and those samples are averaged to produce digitized versions of Vv and Vw.

[0112] E. Fifth SVPWM sector

[0113] Turning now to the fifth SVPWM sector, the phase current determination technique continues over seven periods P1-P7. It can be seen that from the beginning of the third period to the end of the fifth period, U1 is high (causing MN2 to turn on), during the fourth period, V1 is high (causing MN4 to turn on), and from the beginning of the second period to the end of the sixth period, W1 is high (causing MN6 to turn on). Wh, Vh and Uh are the complements of W1, V1 and U1, so the operation of transistors MN1, MN3, MN5 is complementary to the operation of transistors MN2, MN4, MN6 described above.

[0114] During the fifth SVPWM sector, the phase currents Iu, Iv, Iw are calculated as follows, where it should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt as well as Vu, Vv and Vw in the measurement steps described below, and the microcontroller 13 in turn generates control signals Uh, Ul, Vh, Vl, Wh and Wl.

[0115] During the second period, the shunt voltage Vshunt is measured across the shunt resistor Rsh, and at this point, the shunt voltage Vshunt is at a value of Vw2_sh, and the voltage Vw is measured, and at this point, the voltage Vw is at a value of Vw2_mos. From this, the drain-to-source resistance of MN6 can be calculated as:

[0116]

[0117] During the fourth period, the voltage Vu is measured and at this point is at a value of Vu4_mos, and the voltage Vw is measured and at this point is at a value of Vw4_mos. Now, with the value of RdsMN6, and with the value of RdsMN2 from the previous SVPWM sector, the phase current Iv can be calculated as:

[0118] Iu=Vu4_mos / RdsMN2

[0119] Then, the phase current Iw can be calculated as:

[0120] Iw=Vw4_mos / RdsMN6

[0121] Since the sum of the phase currents Iu, Iv and Iw is zero, Iv can be calculated as:

[0122] Iv=-(Vu4_mos / RdsMN2+Vw4_mos / RdsMN6)

[0123] The values ​​of Vshunt and Vw measured during the second period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt and Vw by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vshunt and Vw, or may be sampled multiple times and those samples averaged to produce digitized versions of Vshunt and Vw.

[0124] The values ​​of Vu and Vw measured during the fourth period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vu and Vw by the amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digitized versions of Vu and Vw, or can be sampled multiple times and those samples are averaged to produce digitized versions of Vu and Vw.

[0125] F. Sixth SVPWM sector

[0126] Turning now to the sixth SVPWM sector, the phase current determination technique continues over seven periods P1-P7. It can be seen that from the beginning of the second period to the end of the sixth period, U1 is high (causing MN2 to turn on), during the fourth period, V1 is high (causing MN4 to turn on), and from the beginning of the third period to the end of the fifth period, W1 is high (causing MN6 to turn on). Wh, Vh and Uh are complementary to W1, V1 and U1, so the operation of transistors MN1, MN3, MN5 is complementary to the operation of transistors MN2, MN4, MN6 described above.

[0127] During the sixth SVPWM sector, the phase currents Iu, Iv, Iw are calculated as follows, where it should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt as well as Vu, Vv and Vw in the measurement steps described below, and the microcontroller 13 in turn generates control signals Uh, Ul, Vh, Vl, Wh and Wl.

[0128] During the second period, the shunt voltage Vshunt is measured across the shunt resistor Rsh, and at this point, the shunt voltage Vshunt is at a value of Vu2_sh, and the voltage Vu is measured, and at this point, the voltage Vu is at a value of Vu2_mos. From this, the drain-to-source resistance of MN2 can be calculated as:

[0129]

[0130] During the fourth period, the voltage Vu is measured and at this point is at a value of Vu4_mos, and the voltage Vw is measured and at this point is at a value of Vw4_mos. Now, with the value of RdsMN2, and with the value of RdsMN6 from the previous SVPWM sector, the phase current Iu can be calculated as:

[0131] Iu=Vu4_mos / RdsMN2

[0132] Then, the phase current Iw can be calculated as:

[0133] Iw=Vw4_mos / RdsMN6

[0134] Since the sum of the phase currents Iu, Iv and Iw is zero, Iv can be calculated as:

[0135] Iv=-(Vu4_mos / RdsMN2+Vw4_mos / RdsMN6)

[0136] The values ​​of Vshunt and Vu measured during the second period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt and Vu by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vshunt and Vu, or may be sampled multiple times and those samples averaged to produce digitized versions of Vshunt and Vu.

[0137] The values ​​of Vu and Vw measured during the fourth period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vu and Vw by the amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digitized versions of Vu and Vw, or can be sampled multiple times and those samples are averaged to produce digitized versions of Vu and Vw.

[0138] Variation of the first technique (for low motor speeds)

[0139] In view of the above detailed disclosure of how the first technique works, below is a diagram outlining a variation of the first technique to be used when the motor speed is low. The technique remains the same except that the read transistors for some sectors of the SVPWM are changed. Therefore, only the diagram of this variation is given, because those skilled in the art (with the benefit of the above disclosure) will well understand how to implement this variation of the first technique.

[0140]

[0141] First Technology (lower cost variant)

[0142] In view of the above detailed disclosure on how the first technique works, the following is a graph outlining a first variation of the first technique, in which the voltage of one of the phases is never measured.

[0143]

[0144] Second technology

[0145] The second technique will now be described. In general, the technique works by measuring Vshunt and one of the voltages Vu, Vv, Vw during the second period of each sector of the SVPWM, and calculating from those two measured voltages the drain-to-source resistance of the transistor (e.g., MN2, MN4, MN6) across which the voltage Vu, Vv, or Vw is measured - the drain-to-source resistance may be referred to as the first calibrated drain-to-source resistance for that sector of the SVPWM, and the corresponding transistor may be referred to as the first calibration transistor.

[0146] Next, during the third period of each sector of the SVPWM, the technique will continue to measure Vshunt again, measure the corresponding voltage Vu, Vv, or Vw across the first calibration transistor, and measure the voltage Vu, Vv, or Vw across the next transistor to be calibrated (which may be referred to as the second calibration transistor). From these three measured voltages, the drain-to-source resistance of the second calibration transistor may be calculated and may be referred to as the second calibrated drain-to-source resistance.

[0147] Then, during the fourth period of each sector of the SVPWM, the voltage Vu, Vv or Vw measured during the third period is measured again. The transistor corresponding to the voltage read during the fourth period of each sector of the SVPWM may be referred to as a read transistor.

[0148] The phase current flowing through the first calibration transistor is calculated using the first calibrated drain-to-source resistance and the voltage across the first calibration transistor measured again during the fourth period. Then, the phase current flowing through the second calibration transistor is calculated using the second calibrated drain-to-source resistance and the voltage across the second calibration transistor measured again during the fourth period. Finally, since the sum of the phase currents is known to be zero, from the two calculated phase currents for this sector of the SVPWM, the remaining phase currents can be calculated.

[0149] Therefore, the second technique can be briefly summarized by the following steps:

[0150] 1. During the second period of the SVPWM sector, measure Vshunt and the phase voltage (Vu, Vv or Vw) corresponding to the voltage across the first transistor to be calibrated.

[0151] 2. Calculate the calibrated drain-to-source resistance RDS of the first calibration transistor (MN2, MN4 or MN6) as:

[0152]

[0153] Wherein "first calibration transistor" is the first transistor calibrated during this sector of the SVPWM, "Rshunt" is the resistance of resistor Rshunt, "Vshunt2" is the voltage across Rshunt during the second period of this sector of the SVPWM, and "V1phase2" is the voltage across the first calibration transistor during the second period of this sector of the SVPWM.

[0154] 3. During the third period of the SVPWM sector, measure Vshunt, the phase voltage (Vu, Vv, or Vw) corresponding to the voltage across the first calibration transistor, and the phase voltage (Vu, Vv, or Vw) corresponding to the voltage across another transistor in the transistors (MN2, MN4, or MN6), which will become the second calibration transistor.

[0155] 4. Calculate the calibrated drain-to-source resistance RDS of the second calibration transistor (MN2, MN4, or MN6) as:

[0156]

[0157] Wherein "second calibration transistor" is the second transistor calibrated during this sector of VSPWM, "Rshunt" is the resistance of resistor Rshunt, "Vshunt3" is the voltage across Rshunt during the third time period of this sector of SVPWM, "V1phase3" is the voltage across the first calibration transistor during the third time period of this sector of SVPWM, and "V2phase3" is the voltage across the second calibration transistor during the third time period of this sector of SVPWM.

[0158] 5. During a fourth period of the SVPWM sector, measure the voltage across the first and second calibration transistors (MN2, MN4, or MN6).

[0159] 6. Calculate the phase current for the first calibration transistor as:

[0160] Iphase(first calibration transistor)=V1phase4 / Rds(first calibration transistor) where "first calibration transistor" is the first transistor calibrated during this sector of SVPWM, and "V1phase4" is the voltage across the first calibration transistor during the fourth period of this sector of SVPWM.

[0161] 7. Calculate the phase current of the second calibration transistor as:

[0162] Iphase(second calibration transistor)=V2phase4 / Rds(second calibration transistor) where "second calibration transistor" is the second transistor calibrated during this sector of SVPWM, and "V2phase4" is the voltage across the second calibration transistor during the fourth period of this sector of SVPWM.

[0163] 8. Calculate the phase current for the remaining transistors as:

[0164] Iphase(other transistors)=-[Iphase(first calibration transistor)+Iphase(second calibration transistor)]

[0165] Note that the values ​​measured during the second period of the SVPWM sector should be measured simultaneously, substantially simultaneously, or as close in time as possible. The measurement involves digitizing the measured values ​​by the amplification / filtering / digitization block 14, and the values ​​may be sampled once to produce a digitized version thereof, or may be sampled multiple times and those samples averaged to produce a digitized version.

[0166] In addition, the values ​​measured during the third period of the SVPWM sector should be measured simultaneously, substantially simultaneously, or as close in time as possible. The measurement involves digitizing the measured values ​​by the amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce their digitized version, or can be sampled multiple times and those samples are averaged to produce the digitized version.

[0167] The values ​​measured during the fourth period of the SVPWM sector should be measured simultaneously, substantially simultaneously, or as close in time as possible. The measurement involves digitizing the measured values ​​by the amplification / filtering / digitization block 14, and the values ​​may be sampled once to produce a digitized version thereof, or may be sampled multiple times and those samples averaged to produce a digitized version.

[0168] Shown below is a graph outlining which transistors are calibration transistors and which transistors are read transistors for each sector of the SVPWM when using the second technique.

[0169]

[0170] Figure 4 An example SVPWM sector for this second technique is shown in . Here, a fourth SVPWM is shown, and the phase current determination technique continues over seven periods P1-P7. It can be seen that from the beginning of the second period to the end of the sixth period, Wl is high (causing MN6 to turn on), from the beginning of the third period to the end of the fifth period, Vl is high (causing MN4 to turn on), and during the fourth period, Wl is high. Wh, Vh and Uh are the complements of Wl, Vl and Ul, so the operation of transistors MN1, MN3, MN5 is complementary to the operation of transistors MN2, MN4, MN6 described above.

[0171] During the fourth SVPWM sector, the phase currents Iu, Iv, Iw are calculated as follows, where it should be understood that the amplification / filtering / digitization block 14 digitizes and regulates Vshunt as well as Vu, Vv and Vw in the measurement steps described below, and the microcontroller 13 in turn generates control signals Uh, Ul, Vh, Vl, Wh and Wl.

[0172] During the second period, the shunt voltage Vshunt is measured across the shunt resistor Rsh, and at this point, the shunt voltage Vshunt is at a value of Vw2_sh, and the voltage Vw is measured, and at this point, the voltage Vw is at a value of Vw2_mos. From this, the drain-to-source resistance of MN6 can be calculated as:

[0173]

[0174] During the third period, the shunt voltage Vshunt is measured and at this time, the shunt voltage Vshunt is at a value of Vu3_sh, the voltage Vv is measured and at this time, the voltage Vv is at a value of Vv3_mos, and the voltage Vw is measured and at this time, the voltage Vw is at a value of Vw3_mos. Based on this, the drain-to-source resistance of MN4 can be calculated as:

[0175]

[0176] During the fourth period, the voltage Vv is measured and at this point is at a value of Vv4_mos, and the voltage Vw is measured and at this point is at a value of Vw4_mos. Now, with the values ​​of RdsMN6 and RdsMN4, the phase current Iv can be calculated as:

[0177] Iv=Vv4_mos / RdsMN4

[0178] Then, the phase current Iw can be calculated as:

[0179] Iw=Vw4_mos / RdsMN6

[0180] Since the sum of the phase currents Iu, Iv and Iw is zero, Iu can be calculated as:

[0181] Iu=-(Vv4_mos / RdsMN4+Vw4_mos / RdsMN6)

[0182] The values ​​of Vshunt and Vw measured during the second period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt and Vw by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vshunt and Vw, or may be sampled multiple times and those samples averaged to produce digitized versions of Vshunt and Vw.

[0183] Similarly, the values ​​of Vshunt, Vv and Vw measured during the third period should be measured simultaneously, substantially simultaneously or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vshunt, Vv and Vw by the amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digitized versions of Vshunt, Vv and Vw, or can be sampled multiple times and those samples are averaged to produce digitized versions of Vshunt, Vv and Vw.

[0184] Likewise, the values ​​of Vv and Vw measured during the fourth period should be measured simultaneously, substantially simultaneously, or as close in time as possible. In addition, the measurement involves digitizing the analog values ​​of Vv and Vw by the amplification / filtering / digitization block 14, and these analog values ​​may be sampled once to produce digitized versions of Vv and Vw, or may be sampled multiple times and those samples averaged to produce digitized versions of Vv and Vw.

[0185] Second Technology (Lower Cost Variant)

[0186] In view of the above detailed disclosure of how the second technique works, the following is a graph outlining a first variation of the second technique, where the voltage of one of the phases is never measured and where both transistors are not calibrated at each time period.

[0187]

[0188] General notes applicable to both the first and second techniques

[0189] Although the above techniques have been described with respect to the measurement of the voltage across the low-side transistor and the determination of the drain-to-source resistance of the low-side transistor, those skilled in the art will appreciate that these techniques are equally applicable to the high-side transistor.

[0190] Compared to prior art systems utilizing one shunt per phase winding or two shunts per phase winding, the techniques disclosed herein provide reduced power losses, reduced production costs, and eliminate asymmetries in a three-phase inverter bridge.

[0191] Compared to prior art systems that also utilize a shunt, the techniques disclosed herein eliminate the difficulties encountered when reading voltages under boundary conditions and provide simultaneous or substantially simultaneous sampling of two phase voltages (to allow for more accurate results).

[0192] Furthermore, it should be noted that the above techniques can be applied to other PWM modes, such as sine wave, third harmonic, discontinuous SVPWM, etc. Although which measurements are taken during what time period may vary, the concept of transistor calibration described above remains valid.

[0193] Although the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments may be conceived without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A DC-AC inverter system for coupling to three phase windings of an electric machine, the DC-AC inverter system comprising: a first switch branch coupled between a DC supply voltage node and an intermediate node, the first switch branch having a first terminal for coupling to a first phase winding of the motor; a second switch branch coupled between the DC supply voltage node and the intermediate node, the second switch branch having a second terminal for coupling to a second phase winding of the motor; a third switch branch coupled between the DC supply voltage node and the intermediate node, the third switch branch having a third terminal for coupling to a third phase winding of the motor; a shunt resistor coupled between the intermediate node and ground; as well as a control circuit configured to apply control signals to the first switch branch, the second switch branch, and the third switch branch according to a space vector pulse width modulation (SVPWM) scheme to drive the first phase winding, the second phase winding, and the third phase winding of the motor with a three-phase AC power signal; wherein the SVPWM scheme is divided into six sectors, wherein each sector is divided into a plurality of time periods, the plurality of time periods comprising a first time period, a second time period, a third time period and a fourth time period; and wherein the control circuit is configured to, during at least some sectors of the SVPWM scheme: During the second time period of the plurality of time periods: measuring a shunt voltage across the shunt resistor; as well as measuring a drain-to-source voltage of a first calibration transistor, the first calibration transistor being a transistor of a given switch branch; During the fourth time period of the plurality of time periods: measuring the drain-to-source voltage of the first calibration transistor; as well as measuring a drain-to-source voltage of a transistor to be measured, the transistor to be measured being a transistor of the next switch branch; determining a drain-to-source resistance of the first calibration transistor based on a resistance of the shunt resistor, the drain-to-source voltage of the first calibration transistor measured during the second period, and the shunt voltage measured during the second period; determining a phase current of a given phase winding coupled to the given switching branch based on the drain-to-source voltage of the first calibration transistor and the drain-to-source resistance of the first calibration transistor measured during the fourth time period; determining a phase current of a next phase winding coupled to the next switching branch based on the drain-to-source voltage of the measured transistor measured during the fourth time period and a drain-to-source resistance of the measured transistor known from a previous sector of the SVPWM scheme; as well as Phase currents of remaining phase windings coupled to remaining switching branches are determined based on the phase current of the given phase winding and the phase current of the next phase winding.

2. The DC-AC inverter system of claim 1, wherein the first calibration transistor is a low-side transistor of the given switching leg; and wherein the measured transistor is a low-side transistor of the next switching leg.

3. The DC-AC inverter system of claim 1 , wherein the control circuit determines the drain-to-source resistance of the first calibration transistor as: Wherein Rshunt is the resistance of the shunt resistor, V1phase2 is the drain-to-source voltage of the first calibration transistor measured during the second period, and Vshunt2 is the shunt voltage measured during the second period.

4. The DC-AC inverter system of claim 3, wherein the control circuit determines the phase current of the given phase winding as: Iphase1=V1phase4 / Rds(calibration transistor) wherein V1phase4 is the drain-to-source voltage of the first calibration transistor measured during the fourth period, and Rds(calibration transistor) is the drain-to-source resistance of the first calibration transistor.

5. The DC-AC inverter system according to claim 4, wherein the control circuit determines the phase current of the next phase winding as: Iphase2=V2phase4 / Rds(transistor being measured) Wherein V2phase4 is the drain-to-source voltage of the measured transistor measured during the fourth period, and Rds(measured transistor) is the drain-to-source resistance of the measured transistor known from a previous SVPWM sector.

6. The DC-AC inverter system according to claim 5, wherein the control circuit determines the phase currents of the remaining phase windings as: Iphase3=-(Iphase1+Iphase2).

7. A DC-AC inverter system for coupling to three phase windings of an electric machine, the DC-AC inverter system comprising: a first switch branch coupled between a DC supply voltage node and an intermediate node, the first switch branch having a first terminal for coupling to a first phase winding of the motor; a second switch branch coupled between the DC supply voltage node and the intermediate node, the second switch branch having a second terminal for coupling to a second phase winding of the motor; a third switch branch coupled between the DC supply voltage node and the intermediate node, the third switch branch having a third terminal for coupling to a third phase winding of the motor; a shunt resistor coupled between the intermediate node and ground; as well as a control circuit configured to apply control signals to the first switch branch, the second switch branch, and the third switch branch according to a space vector pulse width modulation (SVPWM) scheme to drive the first phase winding, the second phase winding, and the third phase winding of the motor with a three-phase AC power signal; wherein the SVPWM scheme is divided into six sectors, wherein each sector is divided into a plurality of time periods, the plurality of time periods comprising a first time period, a second time period, a third time period and a fourth time period; and wherein the control circuit is configured to, during at least some sectors of the SVPWM scheme: During the second time period of the plurality of time periods: measuring a shunt voltage across the shunt resistor; as well as measuring a drain-to-source voltage of a first calibration transistor, the first calibration transistor being a transistor of a given switch branch; During the third time period of the plurality of time periods: measuring a shunt voltage across the shunt resistor; measuring a drain-to-source voltage of a second calibration transistor, the second calibration transistor being a transistor of a next switching branch; as well as measuring the drain-to-source voltage of the first calibration transistor; During the fourth time period of the plurality of time periods: measuring the drain-to-source voltage of the first calibration transistor; measuring the drain-to-source voltage of the second calibration transistor; as well as measuring the drain-to-source voltage of a measured transistor, wherein the measured transistor is a transistor of the remaining switch branch; determining a drain-to-source resistance of the first calibration transistor based on a resistance of the shunt resistor, the drain-to-source voltage of the first calibration transistor measured during the second period, and the shunt voltage measured during the second period; determining a drain-to-source resistance of the second calibration transistor based on a resistance of the shunt resistor, the drain-to-source resistance of the first calibration transistor, the drain-to-source voltage of the first calibration transistor measured during the fourth time period, the drain-to-source voltage of the second calibration transistor measured during the fourth time period, and the shunt voltage measured during the fourth time period; determining a phase current of a given phase winding coupled to the given switching branch based on the drain-to-source voltage of the first calibration transistor and the drain-to-source resistance of the first calibration transistor measured during the fourth time period; determining a phase current of a next phase winding coupled to the next switching branch based on the drain-to-source voltage of the second calibration transistor and the drain-to-source resistance of the second calibration transistor measured during the fourth time period; as well as Phase currents of the remaining phase windings coupled to the remaining switching branches are determined based on the phase current of the given phase winding and the phase current of the next phase winding.

8. The DC-AC inverter system of claim 7, wherein the first calibration transistor is a low-side transistor of the given switch branch; wherein the second calibration transistor is a low-side transistor of the next switch branch; and wherein the measured transistor is a low-side transistor of the next switch branch.

9. The DC-AC inverter system of claim 7, wherein the control circuit determines the drain-to-source resistance of the first calibration transistor as: Wherein Rshunt is the resistance of the shunt resistor, V1phase2 is the drain-to-source voltage of the first calibration transistor measured during the second period, and Vshunt2 is the shunt voltage measured during the second period.

10. The DC-AC inverter system of claim 9, wherein the control circuit determines the phase current of the given phase winding as: Iphase1=V1phase4 / Rds(first calibration transistor) wherein V1phase4 is the drain-to-source voltage of the first calibration transistor measured during the fourth period, and Rds(first calibration transistor) is the drain-to-source resistance of the first calibration transistor.

11. The DC-AC inverter system of claim 10, wherein the control circuit determines the drain-to-source resistance of the second calibration transistor as: wherein V3phase3 is the drain-to-source voltage of the second calibration transistor measured during the third time period, V1phase3 is the drain-to-source voltage of the first calibration transistor measured during the third time period, Rshunt is the resistance of the shunt resistor, Vshunt3 is the shunt voltage measured during the third time period, and Rds(first calibration transistor) is the drain-to-source resistance of the first calibration transistor.

12. The DC-AC inverter system according to claim 11, wherein the control circuit determines the phase current of the next phase winding as: Iphase2=V2phase4 / Rds(second calibration transistor) wherein V2phase4 is the drain-to-source voltage of the second calibration transistor measured during the fourth period, and Rds(second calibration transistor) is the drain-to-source resistance of the second calibration transistor.

13. The DC-AC inverter system according to claim 12, wherein the control circuit determines the phase currents of the remaining phase windings as: Iphase3=-(Iphase1+Iphase2).

Images