Display device that has performed overcurrent protection operation

Abstract

A display device is disclosed, which includes: a display panel including a plurality of pixels; a controller that generates a gate reference signal; a gate control circuit that outputs a gate driving signal based on the gate reference signal; and a gate driving circuit that provides a gate signal to the plurality of pixels based on the gate driving signal. The gate control circuit includes: a protection enable circuit that detects a first period of the gate reference signal, determines whether the first period of the gate reference signal changes, and generates a protection enable signal when the first period of the gate reference signal does not change; and an overcurrent protection circuit that generates an overcurrent occurrence signal when an overcurrent of the gate driving signal is detected, and stops outputting the gate driving signal based on the overcurrent occurrence signal and the protection enable signal.

Description

Technical Field

[0001] Exemplary embodiments relate to a display device, and more particularly to a display device that performs an overcurrent protection operation. Background Art

[0002] A display device may include: a display panel including a plurality of pixels; and a driver for driving the display panel to display an image. To drive the display panel, the driver may provide various driving voltages to the display panel through driving voltage lines. In the case of a short-circuit defect occurring between the driving voltage lines of the display panel, an overcurrent may flow through the driving voltage lines. Due to the overcurrent in the driving voltage lines, the display panel may not only fail to operate normally but may also be damaged. Summary of the Invention

[0003] To prevent damage to the display panel, the display panel may include an overcurrent protection circuit that detects an overcurrent and stops driving the display panel when the overcurrent is detected. Generally, the overcurrent protection circuit may perform an overcurrent detection operation in response to a reference signal generated by a controller. However, in the case of an abnormal reference signal, the overcurrent protection circuit may perform an abnormal operation, and thus the display panel may not operate normally.

[0004] Some exemplary embodiments provide a display device that can prevent an abnormal operation of an overcurrent protection circuit even when a gate reference signal is abnormal.

[0005] According to an exemplary embodiment, a display device includes: a display panel including a plurality of pixels; a controller that generates a gate reference signal; a gate control circuit that outputs a gate driving signal based on the gate reference signal; and a gate driving circuit that provides a gate signal to the plurality of pixels based on the gate driving signal. The gate control circuit includes: a protection enable circuit that detects a first period of the gate reference signal, determines whether the first period of the gate reference signal changes, and generates a protection enable signal when the first period of the gate reference signal does not change; and an overcurrent protection circuit that generates an overcurrent occurrence signal when an overcurrent of the gate driving signal is detected, and stops outputting the gate driving signal based on the overcurrent occurrence signal and the protection enable signal.

[0006] In an exemplary embodiment, when a time difference between consecutive periods including the first period of the detected gate reference signal is less than a reference time difference, the protection enable circuit may determine that the first period of the gate reference signal does not change.

[0007] In an exemplary embodiment, the protection enable circuit may include: an internal clock generator that generates an internal clock signal; a clock counter that counts the number of clocks of the internal clock signal during each period of the gate reference signal and outputs a count signal representing the counted number of clocks of the internal clock signal; a reference memory that stores a reference period number and a reference clock number difference corresponding to a reference time difference; and a protection enable signal generator that generates a protection enable signal when the clock number difference between the count signals corresponding to the reference period number is less than the reference clock number difference.

[0008] In an exemplary embodiment, the reference period number may be settable.

[0009] In an exemplary embodiment, the reference time difference may be settable.

[0010] In an exemplary embodiment, the protection enable circuit may detect the time interval between adjacent rising edges of the gate reference signal as the first period of the gate reference signal.

[0011] In an exemplary embodiment, the protection enable circuit may detect the time interval between adjacent falling edges of the gate reference signal as the first period of the gate reference signal.

[0012] In an exemplary embodiment, the gate reference signal may include a reference clock signal. The gate control circuit may generate a gate clock signal as a gate drive signal based on the reference clock signal and may output the gate clock signal to the gate drive circuit.

[0013] In an exemplary embodiment, the protection enable circuit may detect consecutive periods of the reference clock signal, may determine whether the time difference between these periods of the detected reference period number of the reference clock signal is less than the reference time difference, and may generate a protection enable signal when the time difference between these periods of the reference clock signal is less than the reference time difference.

[0014] In an exemplary embodiment, the gate reference signal may include a reference start signal. The gate control circuit may generate a gate start signal as a gate drive signal based on the reference start signal and may output the gate start signal to the gate drive circuit.

[0015] In an exemplary embodiment, the protection enable circuit may detect consecutive periods of the reference start signal, may determine whether the time difference between these periods of the detected reference period number of the reference start signal is less than the reference time difference, and may generate a protection enable signal when the time difference between these periods of the reference start signal is less than the reference time difference.

[0016] In an exemplary embodiment, the overcurrent protection circuit may include: an overcurrent detection circuit that detects an overcurrent of the gate drive signal by comparing the current of the gate drive signal with a reference current, and generates an overcurrent occurrence signal when the overcurrent is detected; and a drive stop circuit that generates an output stop signal indicating that the output of the gate drive signal will be stopped based on the overcurrent occurrence signal and a protection enable signal.

[0017] In an exemplary embodiment, the display device may further include a power circuit that generates a gate-on voltage and a gate-off voltage. The gate control circuit may further include a first switch that outputs the gate-on voltage as the gate drive signal, a second switch that outputs the gate-off voltage as the gate drive signal, and a switch control circuit that controls the first switch and the second switch based on a gate reference signal.

[0018] In an exemplary embodiment, the overcurrent protection circuit may generate an output stop signal based on the overcurrent occurrence signal and the protection enable signal, and the switch control circuit may turn off the first switch and the second switch based on the output stop signal.

[0019] In an exemplary embodiment, the power circuit and the gate control circuit may be provided in a power management integrated circuit.

[0020] In an exemplary embodiment, the gate drive circuit may be provided in a peripheral area of the display panel.

[0021] According to an exemplary embodiment, a display device includes: a display panel including a plurality of pixels; a controller that generates a reference start signal and a reference clock signal; a gate control circuit that outputs a gate start signal and a gate clock signal based on the reference start signal and the reference clock signal; and a gate drive circuit that provides a gate signal to the plurality of pixels based on the gate start signal and the gate clock signal. The gate control circuit includes: a protection enable circuit that detects a first period of the reference clock signal, determines whether the first period of the reference clock signal has changed, and generates a protection enable signal when the first period of the reference clock signal has not changed; and an overcurrent protection circuit that generates an overcurrent occurrence signal when an overcurrent of the gate start signal or the gate clock signal is detected, and stops outputting the gate start signal and the gate clock signal based on the overcurrent occurrence signal and the protection enable signal.

[0022] In an exemplary embodiment, when the time difference between consecutive periods including the first period of the detected reference clock signal is less than a reference time difference, the protection enable circuit may determine that the first period of the reference clock signal has not changed.

[0023] According to an exemplary embodiment, a display device includes: a display panel including a plurality of pixels; a controller generating a reference start signal and a reference clock signal; a gate control circuit outputting a gate start signal and a gate clock signal based on the reference start signal and the reference clock signal; and a gate driving circuit providing a gate signal to the plurality of pixels based on the gate start signal and the gate clock signal. The gate control circuit includes: a protection enable circuit detecting a first period of the reference start signal, determining whether the first period of the reference start signal changes, and generating a protection enable signal when the first period of the reference start signal does not change; and an overcurrent protection circuit generating an overcurrent occurrence signal when detecting an overcurrent of the gate start signal or the gate clock signal, and stopping outputting the gate start signal and the gate clock signal based on the overcurrent occurrence signal and the protection enable signal.

[0024] In an exemplary embodiment, when a time difference between consecutive periods including the first period of the detected reference start signal is less than a reference time difference, the protection enable circuit may determine that the first period of the reference start signal does not change.

[0025] As described above, in the display device according to an exemplary embodiment, the protection enable circuit may detect a period of the gate reference signal, and the overcurrent protection circuit may perform an overcurrent protection operation when the period of the gate reference signal does not change and an overcurrent of the gate driving signal is detected. Therefore, even if the gate reference signal is abnormal, an undesired overcurrent protection operation may be prevented or an undesired overcurrent protection operation may not be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Exemplary, non-limiting embodiments will be understood more clearly through the following detailed description in conjunction with the drawings.

[0027] Figure 1 is a block diagram showing a display device according to an exemplary embodiment.

[0028] Figure 2 is shown included in Figure 1 a block diagram of an exemplary embodiment of a gate control circuit in the display device.

[0029] Figure 3 is shown included in Figure 2 a block diagram of an exemplary embodiment of a protection enable circuit in the gate control circuit.

[0030] Figure 4 is a timing diagram according to an exemplary embodiment for describing an example of an operation of a gate control circuit included in a display device.

[0031] Figure 5It is a timing diagram for describing another example of the operation of a gate control circuit included in a display device according to an exemplary embodiment.

[0032] Figure 6 It is a flowchart showing a method for protecting overcurrent according to an exemplary embodiment.

[0033] Figure 7 It is a timing diagram for describing an example of generating a protection enable signal by detecting the period of a reference clock signal according to an exemplary embodiment.

[0034] Figure 8 It is a flowchart showing a method for protecting overcurrent according to an exemplary embodiment.

[0035] Figure 9 It is a timing diagram for describing an example of generating a protection enable signal by detecting the period of a reference start signal according to an exemplary embodiment.

[0036] Figure 10 It is a block diagram of an electronic device including a display device according to an exemplary embodiment. Detailed implementation

[0037] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the teachings herein, a "first element", "component", "region", "layer", or "section" discussed below may be referred to as a second element, component, region, layer, or section. The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one", unless the context clearly indicates otherwise. "At least one" should not be construed as limited to "one" or "a". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when the terms "comprises", "comprising", "includes", and / or "including" are used in this specification, they specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0038] Figure 1 is a block diagram showing a display device according to an exemplary embodiment, Figure 2 is shown as including in Figure 1 a block diagram of an exemplary embodiment of a gate control circuit in the display device, Figure 3 is shown as including in Figure 2 a block diagram of an exemplary embodiment of a protection enable circuit in the gate control circuit, Figure 4 is a timing diagram according to an exemplary embodiment for describing an example of the operation of a gate control circuit included in a display device, and Figure 5 is a timing diagram according to an exemplary embodiment for describing another example of the operation of a gate control circuit included in a display device.

[0039] Referring to Figure 1, the display device 100 according to an exemplary embodiment may include: a display panel 110 including a plurality of pixels PX; a data driver 130 that provides data signals DS to the plurality of pixels PX; a power circuit 140 that generates a voltage for driving the display panel 110; a gate control circuit 150 that generates gate driving signals GDS; a gate driving circuit 160 that provides gate signals GS to the plurality of pixels PX based on the gate driving signals GDS; and a controller 170 that controls the operation of the display device 100.

[0040] The display panel 110 may have a display area 120 in which an image is displayed and a peripheral area 125 adjacent to the display area 120. The display panel 110 may include a plurality of pixels PX located in the display area 120. In some exemplary embodiments, the display panel 110 may be a liquid crystal display (“LCD”) panel, where each pixel PX includes a switching transistor and a liquid crystal capacitor coupled to the switching transistor. In another exemplary embodiment, the display panel 110 may be an organic light emitting diode (“OLED”) display panel, where each pixel PX includes at least two transistors, at least one capacitor, and an OLED. However, the display panel 110 according to the present invention may not be limited to LCD panels and OLED display panels and may be any suitable display panel.

[0041] The data driver 130 may provide the data signals DS to the plurality of pixels PX based on a data control signal DCTRL and output image data ODAT received from the controller 170. In some exemplary embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal and a load signal. In some exemplary embodiments, the data driver 130 may be implemented with one or more data driver integrated circuits (“ICs”). For example, one or more data driver ICs may be mounted on a flexible film coupled to the display panel 110 in a chip on film (“COF”) manner, or may be mounted on the display panel 110 in a chip on glass (“COG”) manner or a chip on plastic (“COP”) manner.

[0042] The power circuit 140 may receive an input voltage from an external power source and may convert the input voltage into a voltage for driving the display panel 110. In some exemplary embodiments, the power circuit 140 may generate a gate on voltage VON and a gate off voltage VOFF based on the input voltage and may provide the gate on voltage VON and the gate off voltage VOFF to the gate control circuit 150. For example, the gate on voltage VON may be, but is not limited to, approximately 30 volts (V), and the gate off voltage VOFF may be, but is not limited to, approximately -10V.

[0043] The gate control circuit 150 may receive a gate reference signal GRS from the controller 170, may generate a gate drive signal GDS based on the gate reference signal GRS, and may provide the gate drive signal GDS to the gate drive circuit 160. As used herein, the term "gate drive signal" refers to a signal provided from the gate control circuit 150 to the gate drive circuit 160 and measured by current and voltage. In some exemplary embodiments, the gate control circuit 150 may receive a gate turn-on voltage VON and a gate turn-off voltage VOFF from the power circuit 140, and may generate a gate drive signal GDS having a voltage level suitable for the gate drive circuit 160 based on the gate turn-on voltage VON and the gate turn-off voltage VOFF.

[0044] In some exemplary embodiments, the gate reference signal GRS may include a reference start signal STV, and the gate control circuit 150 may generate a gate start signal STVP having a voltage level suitable for the gate drive circuit 160 as the gate drive signal GDS by changing the voltage level of the reference start signal STV based on the gate turn-on voltage VON and the gate turn-off voltage VOFF. Further, in some exemplary embodiments, the gate reference signal GRS may include a reference clock signal CPV, and the gate control circuit 150 may generate one or more gate clock signals CKV having a voltage level suitable for the gate drive circuit 160 as the gate drive signal GDS based on the reference clock signal CPV, the gate turn-on voltage VON, and the gate turn-off voltage VOFF. For example, the gate control circuit 150 may receive four reference clock signals CPV, and may generate eight gate clock signals CKV having different phases based on the four reference clock signals CPV. However, according to an exemplary embodiment, the number of gate clock signals CKV output from the gate control circuit 150 may vary.

[0045] In some exemplary embodiments, as Figure 1 shown, the power circuit 140 and the gate control circuit 150 may be provided in a power management integrated circuit ("PMIC") 180. In other exemplary embodiments, the power circuit 140 and the gate control circuit 150 may be implemented with separate integrated circuits.

[0046] The gate driving circuit 160 may sequentially provide the gate signal GS to the plurality of pixels PX row by row based on the gate driving signal GDS. In some exemplary embodiments, the gate driving circuit 160 may receive a gate start signal STVP indicating the start of a scanning operation and one or more gate clock signals CKV having different phases from each other as the gate driving signal GDS, and may sequentially provide the gate signal GS to the plurality of pixels PX row by row based on the gate start signal STVP and the one or more gate clock signals CKV. In some exemplary embodiments, the gate driving circuit 160 may be implemented as an amorphous silicon gate ("ASG") circuit using amorphous silicon thin film transistors ("a-Si TFTs"), and may be integrated in the peripheral region 125 of the display panel 110 as shown in Figure 1 the figure. In other exemplary embodiments, the gate driving circuit 160 may be implemented using one or more gate driver ICs. In addition, the one or more gate driver ICs may be mounted on a flexible film coupled to the display panel 110 in a COF manner, or may be mounted on the display panel 110 in a COG manner or a COP manner.

[0047] The controller 170 (e.g., a timing controller ("TCON")) may receive a control signal CTRL and input image data IDAT from an external host processor (e.g., a graphics processing unit ("GPU") or a graphics card). For example, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. In addition, for example, the input image data IDAT may be, but is not limited to, RGB image data including red image data, green image data, and blue image data. The controller 170 may generate a gate reference signal GRS, a data control signal DCTRL, and output image data ODAT based on the control signal CTRL and the input image data IDAT. The controller 170 may control the operations of the gate control circuit 150 and the gate driving circuit 160 by providing the gate reference signal GRS to the gate control circuit 150, and may control the operation of the data driver 130 by providing the data control signal DCTRL and the output image data ODAT to the data driver 130.

[0048] In the display device 100 according to an exemplary embodiment, the gate control circuit 150 may perform an overcurrent protection operation of stopping driving the display panel 110 by detecting an overcurrent of the gate driving signal GDS supplied to the gate driving circuit 160. As used herein, the term "overcurrent" refers to a current greater than or equal to a reference current. In addition, in order to prevent the overcurrent protection operation from being undesirably performed when the gate reference signal GRS is abnormal, the gate control circuit 150 included in the display device 100 according to an exemplary embodiment may selectively enable the overcurrent protection operation by detecting the period of the gate reference signal GRS. Therefore, in the case where the overcurrent protection operation is enabled, the overcurrent protection operation may be performed when an overcurrent is detected. However, in the case where the overcurrent protection operation is disabled, even if an overcurrent is detected, the overcurrent protection operation may not be performed. To perform these operations, as Figure 2 shown, the gate control circuit 150 may include a first switch 151, a second switch 152, a switch control circuit 153, an overcurrent protection circuit 154, and a protection enable circuit 200.

[0049] The first switch 151 may output a gate-on voltage VON as the gate driving signal GDS in response to a first switch signal SWS1, and the second switch 152 may output a gate-off voltage VOFF as the gate driving signal GDS in response to a second switch signal SWS2. In some exemplary embodiments, as Figure 2 shown, the first switch 151 may be implemented with a p-type transistor, and the second switch 152 may be implemented with an n-type transistor. To control the first switch 151 and the second switch 152, the switch control circuit 153 may generate the first switch signal SWS1 and the second switch signal SWS2 in response to the gate reference signal GRS.

[0050] In the example, the gate reference signal GRS may include a reference start signal STV, and the gate drive signal GDS may include a gate start signal STVP. The switch control circuit 153 may generate a first switch signal SWS1 having a high level and a second switch signal SWS2 having a low level to output a gate-on voltage VON as the gate start signal STVP when the reference start signal STV has a high level, and may generate a first switch signal SWS1 having a low level and a second switch signal SWS2 having a high level to output a gate-off voltage VOFF as the gate start signal STVP when the reference start signal STV has a low level. Accordingly, the gate control circuit 150 may generate a gate start signal STVP having a phase substantially the same as that of the reference start signal STV and having a voltage level suitable for the gate drive circuit 160. For example, when the reference start signal STV may have approximately 3.3V as the high level and approximately 0V as the low level, the gate start signal STVP may have approximately 30V as the high level and approximately -10V as the low level.

[0051] In another example, the gate reference signal GRS may include a reference clock signal CPV, and the gate drive signal GDS may include a gate clock signal CKV. As Figure 4 and Figure 5As shown, the gate control circuit 150 can change the voltage level of the gate clock signal CKV from a high level to a low level or from a low level to a high level at each rising edge 310 to 370 of the reference clock signal CPV. For example, the switch control circuit 153 can generate a first switch signal SWS1 with a low level and a second switch signal SWS2 with a high level to output the gate cut-off voltage VOFF as the gate clock signal CKV at odd-numbered rising edges 310, 330, 350, and 370, and can generate a first switch signal SWS1 with a high level and a second switch signal SWS2 with a low level to output the gate on-voltage VON as the gate clock signal CKV at even-numbered rising edges 320, 340, and 360. Therefore, the gate control circuit 150 can generate a gate clock signal CKV having a voltage level suitable for the gate driver circuit 160 based on the reference clock signal CPV. For example, the reference clock signal CPV can have a high level of about 3.3V and a low level of about 0V, and the gate clock signal CKV can have a high level of about 30V and a low level of about -10V. In addition, in some exemplary embodiments, at the falling edges 410 to 470 of the reference clock signal CPV, the gate control circuit 150 can connect the line for outputting the gate clock signal CKV to the ground wire, or can perform a charge sharing operation on the gate clock signal CKV. In this case, since the gate control circuit 150 can change the voltage level of the gate clock signal CKV from a predetermined voltage level (e.g., the ground voltage level) to a high level or a low level at the rising edges 310 to 370 of the reference clock signal CPV, the power consumption of the gate control circuit 150 can be reduced.

[0052] Although Figure 2 an example of the gate control circuit 150 including two switches 151 and 152 for outputting one gate drive signal GDS is shown, the number of switches included in the gate control circuit 150 may not be limited to Figure 2 this example. In another exemplary embodiment, the number of switches can be determined according to the number of gate drive signals GDS. For example, to output one gate start-up signal STVP and eight gate clock signals CKV as gate drive signals GDS, the gate control circuit 150 can include eighteen switches.

[0053] The overcurrent protection circuit 154 can detect an overcurrent of the gate drive signal GDS, and can perform an overcurrent protection operation to stop driving the display panel 110 in response to detecting the overcurrent when the protection enable signal PES from the protection enable circuit 200 has a high level. To perform these operations, the overcurrent protection circuit 154 can include an overcurrent detection circuit 155 and a drive stop circuit 157.

[0054] The overcurrent detection circuit 155 can measure the current of the gate drive signal GDS, can compare the measured current of the gate drive signal GDS with a reference current, and can generate an overcurrent occurrence signal OCOS indicating that an overcurrent of the gate drive signal GDS is detected when the measured current is greater than or equal to the reference current. In some exemplary embodiments, the overcurrent detection circuit 155 may include, but is not limited to, a current sensor 156 for measuring the current of the gate drive signal GDS.

[0055] In some exemplary embodiments, the overcurrent detection circuit 155 may receive a gate reference signal GRS (e.g., a reference clock signal CPV), and may measure the current of the gate drive signal GDS in response to the gate reference signal GRS to detect an overcurrent of the gate drive signal GDS. For example, in response to the gate reference signal GRS, the overcurrent detection circuit 155 may measure the current of the gate drive signal GDS after a predetermined time from the time point when the gate drive signal GDS changes to a high level. In an example, the overcurrent detection circuit 155 may measure the current of the gate drive signal GDS after a predetermined time from Figure 4 the even-numbered rising edges 320, 340, and 360 of the reference clock signal CPV shown in. When there is no short-circuit defect in the line of the gate clock signal CKV, the current of the gate clock signal CKV may increase rapidly at the even-numbered rising edges 320, 340, and 360 of the reference clock signal CPV, but the current of the gate clock signal CKV may decrease to less than the reference current after a predetermined time. However, when a short-circuit defect occurs in the line of the gate clock signal CKV, the current of the gate clock signal CKV may still remain greater than the reference current even after a predetermined time from the even-numbered rising edges 320, 340, and 360 of the reference clock signal CPV. In this case, the overcurrent detection circuit 155 may determine that an overcurrent of the gate drive signal GDS has occurred, and may generate an overcurrent occurrence signal OCOS indicating that an overcurrent of the gate drive signal GDS is detected.

[0056] In response to an overcurrent occurrence signal OCOS indicating that an overcurrent of a gate drive signal GDS is detected and a protection enable signal PES indicating that an overcurrent protection operation is enabled, a drive stop circuit 157 may generate an output stop signal OSS indicating that the output of the gate drive signal GDS will be stopped. In some exemplary embodiments, the drive stop circuit 157 may include, but is not limited to, an AND gate 158 that generates an output stop signal OSS with a high level by performing an AND operation on the overcurrent occurrence signal OCOS with a high level and the protection enable signal PES with a high level. In some exemplary embodiments, a switch control circuit 153 may turn off a first switch 151 and a second switch 152 in response to the output stop signal OSS with a high level received from the drive stop circuit 157, and thus may stop outputting the gate drive signal GDS. In some exemplary embodiments, the drive stop circuit 157 may also provide the output stop signal OSS to a power circuit 140, and thus, the power circuit 140 may stop generating a voltage for driving a display panel 110 in response to the output stop signal OSS. In other exemplary embodiments, the drive stop circuit 157 may also provide the output stop signal OSS to a controller 170, and thus, the controller 170 may control a display device 100 to stop driving the display panel 110 in response to the output stop signal OSS.

[0057] A protection enable circuit 200 may detect a period of a gate reference signal GRS, may determine whether the period of the gate reference signal GRS changes, and may generate a protection enable signal PES indicating that an overcurrent protection operation is enabled when the period of the gate reference signal GRS does not change. In addition, when the period of the gate reference signal GRS changes, the protection enable circuit 200 may not generate the protection enable signal PES, or may generate a protection enable signal PES with a low level, such that an overcurrent protection circuit 154 may not perform an overcurrent protection operation of stopping outputting the gate drive signal GDS or stopping driving the display panel 110.

[0058] In some exemplary embodiments, when a time difference between consecutive periods of a detected reference period number RT of the gate reference signal GRS is less than a reference time difference, the protection enable circuit 200 may determine that the period of the gate reference signal GRS does not change. Then, the protection enable circuit 200 may generate a protection enable signal PES indicating that an overcurrent protection operation is enabled for the next period. To perform these operations, as Figure 3 shown, the protection enable circuit 200 may include an internal clock generator 220, a clock counter 240, a reference memory 260, and a protection enable signal generator 280.

[0059] The internal clock generator 220 may generate an internal clock signal ICLK having a predetermined clock frequency. The clock counter 240 may count the number of clocks of the internal clock signal ICLK during each period of the gate reference signal GRS, and may output a count signal CS representing the counted number of clocks of the internal clock signal ICLK. The reference memory 260 may store a reference period number RT and a reference clock number difference RD corresponding to the reference time difference. When the clock number difference between the count signals CS corresponding to the number of reference periods RT is less than the reference clock number difference RD, the protection enable signal generator 280 may generate a protection enable signal PES. In some exemplary embodiments, the reference period number RT and / or the reference time difference (or the reference clock number difference RD corresponding to the reference time difference) may be settable. For example, the controller 170 may provide a new reference period number RT and a new reference clock number difference RD to the protection enable circuit 200, and the reference period number RT and the reference clock number difference RD stored in the reference memory 260 of the protection enable circuit 200 may be updated to the new reference period number RT and the new reference clock number difference RD.

[0060] In some exemplary embodiments, the protection enable circuit 200 may detect the time interval between adjacent rising edges of the gate reference signal GRS as the period of the gate reference signal GRS. In Figure 4 the example, the internal clock generator 220 may generate an internal clock signal ICLK, the clock counter 240 may output a count signal CS representing the first number of clocks of the internal clock signal ICLK between the first rising edge 310 and the second rising edge 320 of the gate reference signal GRS, and the protection enable signal generator 280 may store the first number of clocks between the first rising edge 310 and the second rising edge 320 as the first period PD1 of the gate reference signal GRS. In addition, the protection enable signal generator 280 may store the second number of clocks between the second rising edge 320 and the third rising edge 330 as the second period PD2 of the gate reference signal GRS, and may store the third number of clocks between the third rising edge 330 and the fourth rising edge 340 as the third period PD3 of the gate reference signal GRS. When the reference period number RT stored in the reference memory 260 is three periods, the protection enable signal generator 280 may determine whether the difference between the first number of clocks to the third number of clocks is less than the reference clock number difference RD, and when the difference between the first number of clocks to the third number of clocks is less than the reference clock number difference RD, the protection enable signal generator 280 may generate a protection enable signal PES indicating the enabling of the overcurrent protection operation for the next period.

[0061] In addition, the protection enable signal generator 280 may store the number of fourth clocks between the fourth rising edge 340 and the fifth rising edge 350 as the fourth period PD4 of the gate reference signal GRS, and in the case where the number of reference periods RT stored in the reference memory 260 is three periods, it may be determined whether the differences between the second clock number to the fourth clock number are less than the reference clock number difference RD. In the case where the difference between any two of the second clock number to the fourth clock number is greater than or equal to the reference clock number difference RD, for the next period, the protection enable circuit 200 may not generate the protection enable signal PES, or may generate the protection enable signal PES with a low level. Even if an overcurrent of the gate drive signal GDS is detected, the overcurrent protection circuit 154 may not generate the output stop signal OSS in response to the protection enable signal PES with a low level. For example, as Figure 4 shown, in the case where the fourth period PD4 of the gate reference signal GRS is different from the same first period PD1 to the third period PD3, even if the line of the gate clock signal CKV has no short circuit defect, the current of the gate clock signal CKV detected by the overcurrent detection circuit 155 in response to the fifth rising edge 350 may be greater than or equal to the reference current, and thus, the overcurrent detection circuit 155 may generate the overcurrent occurrence signal OCOS. However, the drive stop circuit 157 may not generate the output stop signal OSS based on the protection enable signal PES with a low level. Therefore, even if an abnormal gate reference signal GRS is applied from the controller 170 to the gate control circuit 150, the overcurrent protection operation may not be undesirably performed.

[0062] In this way, when the display device 100 operates, the protection enable circuit 200 may count the number of clocks of the internal clock signal ICLK between adjacent rising edges for each of the periods PD1 to PD6 of the gate reference signal GRS, and determine whether the differences between the number of clocks of the count signals CS corresponding to the number of reference periods RT are less than the reference clock number difference RD at each of the periods PD1 to PD6 of the gate reference signal GRS or at each of the rising edges 310 to 370 of the gate reference signal GRS.

[0063] In other exemplary embodiments, the protection enable circuit 200 may detect the time interval between adjacent falling edges of the gate reference signal GRS as the period of the gate reference signal GRS. In Figure 5In the example, the protection enable circuit 200 can count the number of clocks of the internal clock signal ICLK between the first falling edge 410 and the second falling edge 420 as the first period PD1' of the gate reference signal GRS, can count the number of clocks of the internal clock signal ICLK between the second falling edge 420 and the third falling edge 430 as the second period PD2' of the gate reference signal GRS, can count the number of clocks of the internal clock signal ICLK between the third falling edge 430 and the fourth falling edge 440 as the third period PD3' of the gate reference signal GRS, can count the number of clocks of the internal clock signal ICLK between the fourth falling edge 440 and the fifth falling edge 450 as the fourth period PD4' of the gate reference signal GRS, can count the number of clocks of the internal clock signal ICLK between the fifth falling edge 450 and the sixth falling edge 460 as the fifth period PD5' of the gate reference signal GRS, and can count the number of clocks of the internal clock signal ICLK between the sixth falling edge 460 and the seventh falling edge 470 as the sixth period PD6' of the gate reference signal GRS. In addition, when the display device 100 operates, the protection enable circuit 200 can determine whether the difference between the number of clocks of the count signal CS corresponding to the reference period number RT at each of the periods PD1' to PD6' of the gate reference signal GRS or at each of the falling edges 410 to 470 of the gate reference signal GRS is less than the reference clock number difference RD.

[0064] In the case where the abnormal gate reference signal GRS is applied from the controller 170 to the gate control circuit 150, or in the case where the period of the gate reference signal GRS changes, the overcurrent detection circuit 155 may generate an overcurrent occurrence signal OCOS even if the line of the gate clock signal CKV has no short circuit defect. However, as described above, in the display device 100 according to the exemplary embodiment, the protection enable circuit 200 can detect the period of the gate reference signal GRS, and the overcurrent protection circuit 154 can perform an overcurrent protection operation only when the period of the gate reference signal GRS does not change and an overcurrent of the gate drive signal GDS is detected. Therefore, in the display device 100 according to the exemplary embodiment, even if the gate reference signal GRS is abnormal, an undesired overcurrent protection operation can be prevented.

[0065] Figure 6 is a flowchart showing a method for protecting an overcurrent according to an exemplary embodiment, and Figure 7 is a timing diagram according to an exemplary embodiment for describing an example of generating a protection enable signal by detecting the period of a reference clock signal.

[0066] Referring to Figure 1 、 Figure 2 、 Figure 3 andFigure 6 The gate control circuit 150 may receive a reference start signal STV and a reference clock signal CPV from the controller 170 (S510). The gate control circuit 150 may output a gate start signal STVP and a gate clock signal CKV based on the reference start signal STV and the reference clock signal CPV (S520). The gate drive circuit 160 may provide a gate signal GS to a plurality of pixels PX of the display panel 110 based on the gate start signal STVP and the gate clock signal CKV.

[0067] The protection enable circuit 200 may detect the period of the reference clock signal CPV (S530). For example, in order to detect the period of the reference clock signal CPV, the internal clock generator 220 may generate an internal clock signal ICLK, and the clock counter 240 may count the number of clocks of the internal clock signal ICLK during each period of the reference clock signal CPV.

[0068] If the period of the reference clock signal CPV changes (S540: Yes), the protection enable circuit 200 may not generate a protection enable signal PES and may disable the overcurrent protection operation of the overcurrent protection circuit 154.

[0069] If the period of the reference clock signal CPV does not change (S540: No), the protection enable circuit 200 may generate a protection enable signal PES indicating that the overcurrent protection operation is enabled (S550). The overcurrent detection circuit 155 of the overcurrent protection circuit 154 may generate an overcurrent occurrence signal OCOS when detecting an overcurrent of the gate start signal STVP and / or the gate clock signal CKV (S560). The drive stop circuit 157 of the overcurrent protection circuit 154 may generate an output stop signal OSS in response to the overcurrent occurrence signal OCOS and the protection enable signal PES, and the switch control circuit 153 may control the switches 151 and 152 not to output the gate start signal STVP and the gate clock signal CKV in response to the output stop signal OSS (S570).

[0070] In some exemplary embodiments, when the time difference between consecutive periods of the detected reference period number RT of the reference clock signal CPV is less than the reference time difference, the protection enable circuit 200 may determine that the period of the reference clock signal CPV has not changed. Figure 7 An example where the reference period number RT is three periods is shown. In Figure 7In the example, if the time differences between the first period PD1, the second period PD2, and the third period PD3 of the reference clock signal CPV are less than the reference time difference, the protection enable circuit 200 may generate a protection enable signal PES indicating the enabling of the overcurrent protection operation for the fourth period PD4. The protection enable circuit 200 may determine, at each of the periods PD1 to PD11 of the reference clock signal CPV, whether the time difference between a corresponding number of periods corresponding to the reference period number RT is less than the reference time difference. Whether to enable the overcurrent protection operation for the current period is determined by comparing three previous periods. For example, since the first period PD1, the second period PD2, and the third period PD3 do not have three previous periods, the overcurrent protection operation is disabled for these periods. In another example, in the case where the time difference between any two of the fourth period PD4, the fifth period PD5, and the sixth period PD6 of the reference clock signal CPV is greater than or equal to the reference time difference (for example, the time difference between the sixth period PD6 and each of the fourth period PD4 and the fifth period PD5 is greater than or equal to the reference time difference), the protection enable circuit 200 may not generate the protection enable signal PES, or may generate a protection enable signal PES with a low level so that the overcurrent protection operation is disabled for the next period (the seventh period PD7). In the case where the reference clock signal CPV is abnormal, or in the case where the period of the reference clock signal CPV changes, even if the line of the gate clock signal CKV does not have a short circuit defect, the corresponding overcurrent protection circuit of the conventional display device may undesirably perform the overcurrent protection operation. However, in the display device 100 according to the exemplary embodiment, in the case where the period of the reference clock signal CPV changes, the protection enable circuit 200 may disable the overcurrent protection operation of the overcurrent protection circuit 154, thereby preventing the undesired execution of the overcurrent protection operation. In addition, if the time differences between the eighth period PD8, the ninth period PD9, and the tenth period PD10 of the reference clock signal CPV are less than the reference time difference, the protection enable circuit 200 may generate the protection enable signal PES indicating the enabling of the overcurrent protection operation again for the next period (the eleventh period PD11).

[0071] Figure 8 is a flowchart showing a method for protecting overcurrent according to an exemplary embodiment, and Figure 9 is a timing diagram according to an exemplary embodiment for describing an example of generating a protection enable signal by detecting the period of a reference start signal.

[0072] Referring to Figure 1 、 Figure 2 、 Figure 3 and Figure 8, the gate control circuit 150 may receive a reference start signal STV and a reference clock signal CPV from the controller 170 (S610). The gate control circuit 150 may output a gate start signal STVP and a gate clock signal CKV based on the reference start signal STV and the reference clock signal CPV (S620). The gate drive circuit 160 may provide a gate signal GS to a plurality of pixels PX of the display panel 110 based on the gate start signal STVP and the gate clock signal CKV.

[0073] The protection enable circuit 200 may detect the period of the reference start signal STV (S630). For example, in order to detect the period of the reference start signal STV, the internal clock generator 220 may generate an internal clock signal ICLK, and the clock counter 240 may count the number of clocks of the internal clock signal ICLK during each period of the reference start signal STV.

[0074] If the period of the reference start signal STV changes (S640: Yes), the protection enable circuit 200 may not generate a protection enable signal PES and may disable the overcurrent protection operation of the overcurrent protection circuit 154.

[0075] If the period of the reference start signal STV does not change (S640: No), the protection enable circuit 200 may generate a protection enable signal PES indicating that the overcurrent protection operation is enabled (S650). The overcurrent detection circuit 155 of the overcurrent protection circuit 154 may generate an overcurrent occurrence signal OCOS when detecting an overcurrent of the gate start signal STVP and / or the gate clock signal CKV (S660). The drive stop circuit 157 of the overcurrent protection circuit 154 may generate an output stop signal OSS in response to the overcurrent occurrence signal OCOS and the protection enable signal PES, and the switch control circuit 153 may control the switches 151 and 152 not to output the gate start signal STVP and the gate clock signal CKV in response to the output stop signal OSS (S670).

[0076] In some exemplary embodiments, when the time difference between consecutive periods of the detected reference period number RT of the reference start signal STV is less than the reference time difference, the protection enable circuit 200 may determine that the period of the reference start signal STV has not changed. Figure 9 An example where the reference period number RT is three periods is shown. In Figure 9In the example, if the time differences between the first period PD1, the second period PD2, and the third period PD3 of the reference start signal STV are less than the reference time difference with respect to each other, the protection enable circuit 200 may generate a protection enable signal PES indicating that the overcurrent protection operation is enabled for the next period (the fourth period PD4). The protection enable circuit 200 may determine, at each of the periods PD1 to PD11 of the reference start signal STV, whether the time difference between a corresponding number of periods corresponding to the reference period number RT is less than the reference time difference. In a case where the time difference between any two of the fourth period PD4, the fifth period PD5, and the sixth period PD6 of the reference start signal STV is greater than or equal to the reference time difference, for the next period (the seventh period PD7), the protection enable circuit 200 may not generate the protection enable signal PES, or may generate the protection enable signal PES having a low level. In a case where the reference start signal STV is abnormal, or in a case where the period of the reference start signal STV changes, even if there is no short-circuit defect in the line of the gate clock signal CKV, the corresponding overcurrent protection circuit of a conventional display device may undesirably perform the overcurrent protection operation. However, in the display device 100 according to the exemplary embodiment, in a case where the period of the reference start signal STV changes, the protection enable circuit 200 may disable the overcurrent protection operation of the overcurrent protection circuit 154, thereby preventing the overcurrent protection operation from being undesirably performed. Further, if the time differences between the eighth period PD8, the ninth period PD9, and the tenth period PD10 of the reference start signal STV are less than the reference time difference with respect to each other, the protection enable circuit 200 may generate the protection enable signal PES indicating that the overcurrent protection operation is enabled again for the next period (the eleventh period PD11).

[0077] Figure 10 is a block diagram showing an electronic device including a display device according to an exemplary embodiment.

[0078] Reference Figure 10 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (“I / O”) device 1140, a power supply unit 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0079] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, in some exemplary embodiments, the processor 1110 may be further coupled to an expansion bus, such as a Peripheral Component Interconnect (“PCI”) bus. The processor 1110 may function as a controller 170, a protection enable signal generator 280, etc.

[0080] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0081] The storage device 1130 may be a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply unit 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication link. The memory device 1120 or the storage device 1130 may be used as a reference memory 260.

[0082] The display device 1160 may detect the period of the gate reference signal and may perform an overcurrent protection operation when the period of the gate reference signal does not change and an overcurrent of the gate drive signal is detected. Therefore, in the display device 1160 according to the exemplary embodiment, even if the gate reference signal is abnormal, an undesired overcurrent protection operation may be prevented or an undesired overcurrent protection operation may not be performed.

[0083] The inventive concept can be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, the inventive concept can be applied to a television (“TV”), a digital TV, a 3D TV, a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a personal computer (“PC”), a home appliance, a laptop computer, a personal digital assistant (“PDA”), a portable multimedia player (“PMP”), a digital camera, a music player, a portable game console, a navigation device, etc.

[0084] The foregoing is a description of exemplary embodiments and is not to be construed as limiting thereof. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined by the claims. Therefore, it should be understood that the foregoing is a description of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments as well as other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: A display panel, including a plurality of pixels; A controller, generating a gate reference signal; A gate control circuit, outputting a gate driving signal based on the gate reference signal; And A gate driving circuit, providing a gate signal to the plurality of pixels based on the gate driving signal, wherein, the gate control circuit includes: A protection enable circuit, detecting a first period of the gate reference signal, determining whether the first period of the gate reference signal changes, and generating a protection enable signal when the first period of the gate reference signal does not change; and An overcurrent protection circuit, generating an overcurrent occurrence signal when detecting an overcurrent of the gate driving signal, and stopping outputting the gate driving signal based on the overcurrent occurrence signal and the protection enable signal.

2. The display device according to claim 1, wherein, When a time difference between consecutive periods including the first period of the detected reference period number of the gate reference signal is less than a reference time difference, the protection enable circuit determines that the first period of the gate reference signal does not change.

3. The display device according to claim 2, wherein, The protection enable circuit includes: An internal clock generator, generating an internal clock signal; A clock counter, counting the number of clocks of the internal clock signal during each period of the gate reference signal, and outputting a count signal representing the counted number of clocks of the internal clock signal; A reference memory, storing the reference period number and a reference clock number difference corresponding to the reference time difference; and A protection enable signal generator, generating the protection enable signal when a clock number difference between count signals corresponding to the reference period number is less than the reference clock number difference.

4. The display device according to claim 2, wherein, The reference period number is settable.

5. The display device according to claim 2, wherein, The reference time difference is settable.

6. The display device according to claim 1, wherein, The protection enable circuit detects a time interval between adjacent rising edges of the gate reference signal as the first period of the gate reference signal.

7. The display device according to claim 1, wherein, The protection enable circuit detects a time interval between adjacent falling edges of the gate reference signal as the first period of the gate reference signal.

8. The display device according to claim 1, wherein, The gate reference signal includes a reference clock signal, and wherein, the gate control circuit generates a gate clock signal as the gate driving signal based on the reference clock signal, and outputs the gate clock signal to the gate driving circuit.

9. A display device, comprising: A display panel, including a plurality of pixels; A controller, generating a reference start signal and a reference clock signal; A gate control circuit, outputting a gate start signal and a gate clock signal based on the reference start signal and the reference clock signal; And A gate driving circuit, providing a gate signal to the plurality of pixels based on the gate start signal and the gate clock signal; wherein, the gate control circuit includes: A protection enable circuit, detecting a first period of the reference clock signal, determining whether the first period of the reference clock signal changes, and generating a protection enable signal when the first period of the reference clock signal does not change; and An overcurrent protection circuit generates an overcurrent occurrence signal when detecting an overcurrent of the gate start signal or the gate clock signal, and stops outputting the gate start signal and the gate clock signal based on the overcurrent occurrence signal and the protection enable signal.

10. A display device, comprising: A display panel includes a plurality of pixels; A controller generates a reference start signal and a reference clock signal; A gate control circuit outputs a gate start signal and a gate clock signal based on the reference start signal and the reference clock signal; And A gate driving circuit provides gate signals to the plurality of pixels based on the gate start signal and the gate clock signal; Wherein, the gate control circuit includes: A protection enable circuit detects a first period of the reference start signal, determines whether the first period of the reference start signal changes, and generates a protection enable signal when the first period of the reference start signal does not change; and An overcurrent protection circuit generates an overcurrent occurrence signal when detecting an overcurrent of the gate start signal or the gate clock signal, and stops outputting the gate start signal and the gate clock signal based on the overcurrent occurrence signal and the protection enable signal.

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