Display device

Abstract

A display apparatus is disclosed. The display apparatus includes a substrate including a display area including first and second pixels in a first row and third and fourth pixels disposed in a second row parallel to the first row; a light-transmissive non-display area within the display area; first and second columns parallel to each other and spaced apart from each other and each crossing the non-display area; and a plurality of lines including first and second lines extending along the first row and connected to the first and second pixels, respectively; a first disconnection point in which the first and second lines are spaced apart from each other; third and fourth lines extending along the second row and connected to the third and fourth pixels, respectively; and a second disconnection point in which the third and fourth lines are spaced apart from each other, wherein the first and second disconnection points correspond to the first and second columns, respectively.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2019-0171892, filed on December 20, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device. Background Technology

[0003] The uses of display devices have become diversified. Furthermore, as display devices become thinner and lighter, their applications have expanded even further.

[0004] As the area of ​​the display device expands, various functions have been developed for connecting or linking display devices to other devices. Summary of the Invention

[0005] One or more embodiments include a display device comprising components such as a camera or sensor disposed corresponding to a display area. The display area includes a component region corresponding to the component and having relatively high light transmittance for smooth operation of the component, providing methods for connecting or linking the component to various functions of the display device.

[0006] Additional features will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0007] According to an embodiment, the display device includes a substrate and a plurality of lines. The substrate includes: a display area including a plurality of pixels, the plurality of pixels including a first pixel and a second pixel disposed along a first row, and a third pixel and a fourth pixel disposed along a second row parallel to the first row; a first non-display area within the display area, where light is transmittable to and from the substrate; a first column defined perpendicular to the first row; and a second column defined parallel to and spaced from the first column, wherein the first column and the second column each pass through the first non-display area. The plurality of lines are on the substrate and include: a first line extending along the first row and electrically connected to the first pixel; a second line extending along the first row and electrically connected to the second pixel; a first break point, at which the first line and the second line are spaced apart from each other along the first row; a third line extending along the second row and electrically connected to the third pixel; a fourth line extending along the second row and electrically connected to the fourth pixel; and a second break point, at which the third line and the fourth line are spaced apart from each other along the second row. The first break point corresponds to the first column, and the second break point corresponds to the second column.

[0008] The first line and the third line can each extend from a first scan drive circuit disposed on one side of the substrate, and the second line and the fourth line can each extend from a second scan drive circuit disposed on the opposite side of the substrate.

[0009] The substrate may further include a second non-display area outside the display area, and the first scan driving circuit and the second scan driving circuit may be disposed in the second non-display area.

[0010] Multiple lines may include at least one of scan lines and light emission control lines.

[0011] The plurality of pixels may further include a fifth pixel and a sixth pixel disposed along a third row parallel to the first row, and the plurality of lines may further include: a fifth line extending along the third row and electrically connected to the fifth pixel; a sixth line extending along the third row and connected to the sixth pixel; and a third break point at which the fifth line and the sixth line are spaced apart from each other. The third break point may correspond to a third column parallel to and spaced apart from the first column and passing through a first non-display area.

[0012] The plurality of pixels may further include a seventh pixel and an eighth pixel, which are arranged along a fourth row parallel to the first row and spaced apart from each other by a first non-display area.

[0013] The fourth line can pass through the first non-display area.

[0014] The first and third lines can have different lengths.

[0015] The first and second lines can have different lengths.

[0016] The number of pixels connected to the first line can be different from the number of pixels connected to the third line.

[0017] The widths of the first and third lines can correspond to the lengths of the first and third lines, respectively, so that the planar areas of the first and third lines are equal.

[0018] The first break point and the second break point can be located between two adjacent pixels.

[0019] Each of the plurality of pixels may include a display element, the display element including a pixel electrode, a counter electrode, and a light-emitting layer between the pixel electrode and the counter electrode. The counter electrode may be a single unit corresponding to a display area and may define an aperture corresponding to a first non-display area.

[0020] Embodiments of the display device include: a substrate including a display area comprising a plurality of pixels; and a first non-display area within the display area, where light is transmissible to and from the substrate; and a plurality of lines on the substrate and electrically connected to the plurality of pixels. Within the display area, the plurality of lines extend along a first direction and are parallel to each other, and are arranged adjacent to each other along the first direction and along a second direction intersecting the first direction. The plurality of lines adjacent to each other along the first direction are spaced apart to define breakpoints, and each of the breakpoints corresponds along the second direction to the first non-display area.

[0021] The breakpoint can be set in a Z-shaped pattern within the display area.

[0022] A portion of the multiple lines may extend from the first scan drive circuit, and the remainder of the multiple lines may extend from the second scan drive circuit to define the break point.

[0023] The substrate may further include a second non-display area outside the display area, and the first scan driving circuit and the second scan driving circuit may be located in the second non-display area.

[0024] Two adjacent lines in a plurality of lines may have different lengths from the first scan drive circuit to the break point.

[0025] The width of a portion of the multiple lines can correspond to its length from the first scan drive circuit to the break point, such that the planar areas of a portion of the multiple lines are equal to each other.

[0026] Multiple lines may include at least one of scan lines and light emission control lines. Attached Figure Description

[0027] The above and other features and advantages of embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 This is a schematic perspective view of an embodiment of an electronic display device;

[0029] Figure 2 This is a cross-sectional view of an embodiment of the display device;

[0030] Figure 3 This is a schematic plan view of an embodiment of the display panel;

[0031] Figure 4 It is an equivalent circuit diagram of an embodiment of pixels included in a display panel;

[0032] Figure 5 This is a plan view of an embodiment of the display panel;

[0033] Figure 6 yes Figure 5 An enlarged top view of an embodiment of part VI of the display panel; and

[0034] Figure 7 This is an enlarged cross-sectional view illustrating an embodiment of the display panel. Detailed Implementation

[0035] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only with reference to the accompanying drawings to explain the features of this description.

[0036] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, a and b, a and c, b and c, and all or variations thereof of a, b, and c.

[0037] In the following embodiments, although various elements may be described using terms such as "first," "second," etc., these elements are by no means limited to the above terms.

[0038] In the following embodiments, unless the context clearly indicates a different meaning, the singular usage encompasses the plural usage. As used herein, unless the context clearly indicates otherwise, “a,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both singular and plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as a restrictive “a.” “Or” means “and / or.”

[0039] In the following embodiments, it should be understood that terms such as “comprising” and “having” are intended to indicate the presence of features or elements disclosed in this disclosure and are not intended to exclude the possibility that one or more other features or elements may be present or added.

[0040] In the following embodiments, when a layer, area, or component is referred to as being associated with another element, such as being "on" another layer, area, or component, the layer, area, or component may be directly or indirectly on the other layer, area, or component. That is, for example, intermediate layers, areas, or components may exist. In contrast, when a layer, area, or component is referred to as being associated with another element, such as being "directly" on another layer, area, or component, there are no intermediate layers, areas, or components.

[0041] For ease of illustration, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0042] When embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0043] In this disclosure, "A and / or B" can include "A", "B", or "A and B". Additionally, "at least one of A and B" can include "A", "B", or "A and B". Furthermore, "at least one of A, B, and C" can include "A", "B", "C", "at least one of A and B", "at least one of A and C", "at least one of B and C", or "A, B, and C".

[0044] It will be understood that when a layer, area, or component is referred to as being associated with another element, such as being connected to another layer, area, or component, it can be directly or indirectly connected to that other layer, area, or component. That is, for example, intermediate layers, areas, or components may exist. Similarly, it will be understood that when a layer, area, or component is referred to as being electrically connected to another layer, area, or component, it can be directly or indirectly electrically connected to that other layer, area, or component. That is, for example, intermediate layers, areas, or components may exist. In contrast, when a layer, area, or component is referred to as being associated with another element, such as being “directly connected” to another layer, area, or component, then there are no intermediate layers, areas, or components.

[0045] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are also intended to cover different orientations of the device. For example, if a device in one of the drawings is flipped, it is described as an element “down” to the other element and then oriented “up” to the other element. Thus, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, if a device in one of the figures is flipped, it is described as an element “below” or “under” the other element and then oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the relevant field and the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0047] Exemplary embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of ideal embodiments. Therefore, variations in the shape of the illustrated areas are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the areas illustrated herein, but should include, for example, deviations in shape caused by manufacturing processes. For example, areas illustrated or described as flat may generally have rough and / or non-linear characteristics. Furthermore, illustrated sharp corners may be rounded. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0048] The x, y, and z directions are not limited to three directions within an orthogonal coordinate system, and can be interpreted broadly to include all three directions. For example, the x, y, and z directions can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other but intersect or cross each other.

[0049] Figure 1 This is a schematic perspective view of an embodiment of display device 1. Display device 1 and its components can be arranged in a plane defined by a first direction and a second direction that intersect each other. Figure 1 In this context, for example, the x-direction and y-direction can represent the first direction and the second direction differently. The thickness of the display device 1 and its elements can be defined along a third direction (e.g., the z-direction) that intersects each of the first and second directions.

[0050] Reference Figure 1 The display device 1 may include a first region A1, a second region A2, and a third region A3. One or more layers or elements of the display device 1 may include the first region A1, the second region A2, and the third region A3 corresponding to those described above for the display device 1.

[0051] The first region A1 may include the component 20 included in the display device 1 (see...). Figure 2A planar region corresponding to and having relatively high transmittance. In embodiments, for example, the first region A1 can be understood as a transmissive region through which light emitted from component 20 or light incident on component 20 from outside the display device 1 (e.g., from the viewing side of the display device 1) can be transmitted. In embodiments, for example, the first region A1 can be referred to as a light-transmitting region, component region, sensor region, or opening region OA (see [link to documentation]). Figure 7 ).

[0052] The second region A2 can be defined as having a plurality of pixels P provided (e.g., multiple pixels P (see [reference]). Figure 3 The second region A2 is a planar area. The display device 1 can provide image information from the second region A2 by using light generated and / or emitted from a plurality of pixels P disposed in the second region A2. In an embodiment, for example, the second region A2 may be referred to as the display region DA (see [link to documentation]). Figure 7 ).

[0053] The second region A2 can be configured to be adjacent to and at least partially surround the first region A1. In an embodiment, as shown... Figure 1 As shown, the entirety of the first region A1 can be surrounded by a portion of the second region A2. In the planar diagram, the first region A1 can be a closed region. A boundary can be defined between the portion of the planar region of the second region A2 that excludes the first region A1 and the first region A1.

[0054] The second region A2 may be located inside the third region A3. A boundary may be defined between the remaining planar region of the third region A3 (excluding the planar region of the second region A2) and the second region A2. The total planar region of the third region A3 may correspond to, but is not limited to, the planar region of the display device 1.

[0055] Reference Figure 1 For example, in a top view along the z-direction, the first region A1 can be surrounded by the second region A2, and the second region A2 can be surrounded by the third region A3.

[0056] The third region A3 may include a planar region in which a circuit component is provided to provide electrical signals to a pixel P disposed in the second region A2.

[0057] exist Figure 1 In the middle, the first region A1 and / or the third region A3 can be connected to the non-display region NDA (see Figure 3 Correspondingly, in an embodiment, the first region A1 and / or the third region A3 may not include pixels P that generate and / or emit light. The first region A1 (e.g., a first non-display region) and the third region A3 (e.g., a second non-display region) may be planar regions that do not display images.

[0058] Despite Figure 1 The first region A1 is illustrated as being disposed on one side (e.g., the right side) of the second region A2, which has a substantially rectangular shape, but this disclosure is not limited thereto.

[0059] In embodiments, for example, the planar shape of the first region A1 may be circular or a polygon such as a triangle or pentagon, and the position and number of the first regions A1 within the display device 1 may vary. In embodiments, for example, based on the plane of the second region A2 (e.g., the xy plane), the first region A1 may be positioned on the upper left side of the display device 1, and multiple first regions A1 may be located within the total planar area of ​​the second region A2, which is defined by the outer edge of the second region A2 closest to the third region A3.

[0060] In the following description, although embodiments of the organic light-emitting display device are described as examples of display device 1, the display device 1 disclosed herein is not limited thereto.

[0061] In another embodiment, for example, the display device 1 may be an inorganic light-emitting display device (an inorganic light-emitting display or an inorganic electroluminescent (“EL”) display device) or a quantum dot light-emitting display device.

[0062] In an embodiment, for example, a display element OLED (see [reference]) is included in display device 1. Figure 4 The emitter layer may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0063] The display device 1 described above can be or is included in various types of electronic devices such as mobile phones, laptop computers and smartwatches.

[0064] Figure 2 This is an enlarged cross-sectional view of display device 1. Figure 2 It can correspond to the cross section taken along line I-I' of display device 1.

[0065] Reference Figure 2 The display device 1 may include a display panel 10, an input sensing layer 40 disposed on the display panel 10 and / or an optical function layer 50, and these configurations may be covered by a window 60.

[0066] Window 60 can be stacked with a fixing member (or fixing layer) such as adhesive layer OCA and a lower structure or element layer such as optical functional layer 50 (or input sensing layer 40). Adhesive layer OCA may include optically transparent adhesive.

[0067] Display device 1 may include a component 20 located below display panel 10. Component 20 may face window 60, and there may be a stack of lower structures or component layers between component 20 and window 60. Component 20 may be arranged on the side of display panel 10 opposite to its viewing side.

[0068] Component 20 may include electronic elements (e.g., functional components or devices) that use light to perform functions within the display device 1. In embodiments, for example, component 20 may include electronic devices that use light in various wavelength bands, such as visible light, infrared light, or ultraviolet light, to perform functions. In embodiments, for example, component 20 may include a camera module that acquires image information by using light incident on component 20 from outside the component 20 and / or the display device 1.

[0069] Display panel 10 can provide an image to the outside of display panel 10 by using light emitted from pixel P. Display panel 10 can generate and / or emit light to provide an image. A plurality of pixels P can be disposed in the second region A2, and each of the plurality of pixels P may include a display element OLED and pixel circuitry PC connected to the display element OLED (see [link to relevant documentation]). Figure 4 Display elements for OLEDs may include, for example, organic light-emitting diodes or quantum dot organic light-emitting diodes.

[0070] An input sensing layer 40 may be disposed on a display panel 10. The display panel 10 may face a window 60, and an input sensing layer 40 is provided between the display panel 10 and the window 60. The input sensing layer 40 may sense and / or generate coordinate information based on external input (e.g., touch events on the display device 1 or elements of the display device 1).

[0071] The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may sense external input using mutual capacitance or self-capacitance methods.

[0072] In one embodiment, the input sensing layer 40 may be provided or formed separately from the display panel 10, and then adhered to the display panel 10 by a separate adhesive layer such as an optically clear adhesive. In another embodiment, the input sensing layer 40 may be provided or formed directly on the display panel 10. In another embodiment, for example, the input sensing layer 40 may be provided or formed continuously on the display panel 10 after the operation of forming the display panel 10. In this case, the input sensing layer 40 can be understood as part of the display panel 10, and the adhesive layer used to attach the input sensing layer 40 and the display panel 10 to each other can be removed.

[0073] Although the input sensing layer 40 can be as Figure 2The input sensing layer 40 is located between the display panel 10 and the optical functional layer 50, but it can be positioned above the optical functional layer 50. That is, the display panel 10 can face the input sensing layer 40, and the optical functional layer 50 is located between the display panel 10 and the input sensing layer 40.

[0074] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light incident from the outside of the display panel 10 and / or display device 1 and incident from the viewing side of the display device 1 through the window 60 toward the display panel 10. The anti-reflective layer may include a retarder and / or a polarizer.

[0075] The retarder can be film-type or liquid crystal coated type, and can include λ / 2 retarders and / or λ / 4 retarders. The polarizer can be film-type or liquid crystal coated type. Film-type polarizers can include stretched synthetic resin films, and liquid crystal coated polarizers can include liquid crystals. The retarder and polarizer may further include a protective film. In an embodiment, for example, the retarder and polarizer or protective film can be defined as the base layer of an anti-reflective layer. In another embodiment, the anti-reflective layer can include a black matrix and a color filter. The color filter can be configured considering the color of light emitted from each of the pixels P of the display panel 10.

[0076] In another embodiment, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed in different layers from each other, for example, a stacked structure along the thickness direction. First reflected light and second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can interfere destructively, and therefore, the reflectivity of external light can be reduced.

[0077] The optical functional layer 50 may include a lens layer. The lens layer can improve the light emission efficiency of light emitted from the display panel 10 and / or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include multiple layers having different refractive indices. The optical functional layer 50 may include each of the anti-reflective layers and lens layers described above, or may include a single anti-reflective layer and lens layer.

[0078] In this embodiment, the optical functional layer 50 may be provided or formed sequentially after the operation of providing or forming the display panel 10 and / or the input sensing layer 40. In this case, the adhesive layer used to attach the optical functional layer 50, the display panel 10, and / or the input sensing layer 40 to each other may be removed.

[0079] The display panel 10, the input sensing layer 40, and / or the optical functional layer 50 may include or define an opening corresponding to the first region A1. In this respect, Figure 2The diagram illustrates a structure in which the display panel 10, input sensing layer 40, and optical functional layer 50 each include or define a first hole 10H, a second hole 40H, and a third hole 50H (e.g., first to third holes 10H, 40H, and 50H), and the first to third holes 10H, 40H, and 50H overlap or are aligned with each other. The aligned first to third holes 10H, 40H, and 50H can provide a series of openings or holes corresponding to component 20.

[0080] In another embodiment, at least one of the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include an aperture. In other embodiments, for example, any one or two features of the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include an aperture.

[0081] When the display device 1 is used as a smartwatch or a vehicle dashboard, component 20 can be a member such as a clock hand or a pointer indicating information (e.g., vehicle speed). When the display device 1 includes a clock hand or is used as a vehicle dashboard, component 20 can be exposed to the outside of the display device 1. In this case, with Figure 2 Unlike other windows, window 60 may further include or define an opening corresponding to the first region A1.

[0082] As described above, component 20 may include one or more components 20 related to the function of display panel 10, or may include accessories that enhance the aesthetics of display panel 10 or display device 1.

[0083] Figure 3 This is a schematic plan view of an embodiment of the display panel 10, and Figure 4 This is an equivalent circuit diagram of an embodiment including a pixel P in the display panel 10 according to an embodiment.

[0084] Reference Figure 3 and Figure 4 The display panel 10 may include a plurality of pixels P disposed in a second region A2 (e.g., the outer boundary indicated by the dashed line). Pixel P may include a display element such as an organic light-emitting diode (OLED). Through operation of the OLED (e.g., as a light-emitting element or device), each pixel P may generate and / or emit light of one or more colors selected from red, green, blue, and white light. As described above, pixel P may be a pixel P that emits light of one or more colors selected from red, green, blue, and white light.

[0085] like Figure 4As shown, pixel P may include pixel circuitry PC and a display element OLED electrically connected to pixel circuitry PC. Pixel circuitry PC may include multiple thin-film transistors and storage capacitors Cst. The multiple thin-film transistors and storage capacitors Cst may be connected to signal lines SL, SL-1, EL, and DL, initialization voltage line VL, and drive voltage line PL through which electrical signals are transmitted.

[0086] The multiple thin-film transistors may include a driving thin-film transistor (“TFT”) T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

[0087] The signal lines may include a scan line SL that transmits electrical signals such as a scan signal Sn, a previous scan line SL-1 that transmits electrical signals such as a previous scan signal Sn-1 to a first initialization TFT T4 and a second initialization TFT T7, an emission control line EL (e.g., a light emission control line) that transmits electrical signals such as an emission control signal En to an operation control TFT T5 and an emission control TFT T6, and a data line DL that crosses the scan line SL and transmits electrical signals such as a data signal Dm.

[0088] The driving voltage line PL can transmit electrical signals, such as the driving voltage ELVDD, to the driving TFT T1. The initialization voltage line VL can transmit signals, such as initializing the driving TFT T1 and the pixel electrodes 350 of the display element OLED (see [link]). Figure 7 The initial voltage Vint is the electrical signal.

[0089] The driving gate electrode G1 of driving TFT T1 can be connected to the first storage capacitor plate Cst1 of storage capacitor Cst. The driving source electrode S1 of driving TFT T1 can be connected to the driving voltage line PL via operation control TFT T5, and the driving drain electrode D1 of driving TFT T1 can be electrically connected to the pixel electrode 350 of the display element OLED via emission control TFT T6. Driving TFT T1 can receive the data signal Dm according to the switching operation of switching TFT T2, and can transmit the driving current I... OLED It is supplied to the OLED display element.

[0090] The gate electrode G2 of the switching TFT T2 can be connected to the scan line SL, the source electrode S2 of the switching TFT T2 can be connected to the data line DL, the drain electrode D2 of the switching TFT T2 can be connected to the driving source electrode S1 of the driving TFT T1, and can be connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 can be turned on according to the scan signal Sn received through the scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted to the data line DL to the driving source electrode S1 of the driving TFT T1.

[0091] The compensation gate electrode G3 of the compensation TFT T3 can be connected to the scan line SL, and the compensation source electrode S3 of the compensation TFT T3 can be connected to the driving drain electrode D1 of the driving TFT T1, and can be connected to the pixel electrode 350 of the display element OLED via the emission control TFT T6. The compensation drain electrode D3 of the compensation TFT T3 can be connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 can be turned on according to the scan signal Sn received through the scan line SL, and electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1 to compensate the driving TFT T1.

[0092] The first initialization gate electrode G4 of the first initialization TFT T4 can be connected to the previous scan line SL-1, and the first initialization source electrode S4 of the first initialization TFT T4 can be connected to the second initialization drain electrode D7 and the initialization voltage line VL of the second initialization TFT T7. The first initialization drain electrode D4 of the first initialization TFT T4 can be connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 and transmit the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1 to initialize the voltage of the driving gate electrode G1 of the driving TFT T1.

[0093] The operation control gate electrode G5 of the operation control TFT T5 can be connected to the emitter control line EL, and the operation control source electrode S5 of the operation control TFT T5 can be connected to the drive voltage line PL. The operation control drain electrode D5 of the operation control TFT T5 can be connected to the drive source electrode S1 of the driving TFT T1 and the switch drain electrode D2 of the switching TFT T2.

[0094] The emission control gate electrode G6 of the emission control TFT T6 can be connected to the emission control line EL, and the emission control source electrode S6 of the emission control TFT T6 can be connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3. The emission control drain electrode D6 of the emission control TFT T6 can be electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode 350 of the display element OLED.

[0095] The operation control TFT T5 and the emission control TFT T6 can be turned on according to the emission control signal En received through the emission control line EL, and the driving voltage ELVDD can be transmitted to the display element OLED to allow the driving current I. OLED It flows through the OLED display element.

[0096] The second initialization gate electrode G7 of the second initialization TFT T7 can be connected to the previous scan line SL-1, and the second initialization source electrode S7 of the second initialization TFT T7 can be connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode 350 of the display element OLED. The second initialization drain electrode D7 of the second initialization TFT T7 can be connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, and initialize the pixel electrode 350 of the display element OLED.

[0097] although Figure 4 The figure illustrates a first initialization TFT T4 and a second initialization TFT T7 connected to a previous scan line SL-1, but this disclosure is not limited thereto. In another embodiment, the first initialization TFT T4 may be connected to the previous scan line SL-1 and driven according to a previous scan signal Sn-1, and the second initialization TFT T7 may be connected to a separate signal line (e.g., a subsequent scan line) and driven according to a signal transmitted to that signal line.

[0098] The second storage capacitor plate Cst2 of the storage capacitor Cst can be connected to the driving voltage line PL, and the counter electrode 370 of the display element OLED (see...) Figure 7 It can receive the common voltage ELVSS. Therefore, the OLED display element can receive the driving current I from the driving TFT T1. OLED An image is output by emitting light.

[0099] although Figure 4The figure shows that the compensation TFT T3 and the first initialization TFT T4 have dual gate electrodes, but the compensation TFT T3 and the first initialization TFT T4 may have a single gate electrode.

[0100] Refer again Figure 3 Each pixel P can be electrically connected to a driving circuit disposed in a non-display area NDA. In an embodiment, for example, the driving circuit can be located in a third area A3 surrounding the second area A2. At least one of the following can be disposed in the third area A3: a first scan driving circuit 110 (e.g., a first driving circuit), a second scan driving circuit 120 (e.g., a second driving circuit), a first terminal 140 (e.g., a first terminal area), a data driving circuit 150 (e.g., a third driving circuit), a first power line 160, and a second power line 170.

[0101] The first scan drive circuit 110 can provide a scan signal Sn to each pixel P via the scan line SL. The first scan drive circuit 110 can provide a transmit control signal En to each pixel P via the transmit control line EL.

[0102] The second scan drive circuit 120 can be arranged in parallel with the first scan drive circuit 110, and the second region A2 is between the second scan drive circuit 120 and the first scan drive circuit 110.

[0103] The first portion of pixel P located in the second region A2 can be electrically connected to the first scan drive circuit 110. The second portion of pixel P that is not connected to the first scan drive circuit 110 can be electrically connected to the second scan drive circuit 120.

[0104] In another embodiment, either the first scan drive circuit 110 or the second scan drive circuit 120 may be omitted.

[0105] The first terminal 140 can be disposed on the lower substrate 100 (see...). Figure 7 The first terminal 140 may be exposed to the outside of the display panel 10, for example, by not being covered by an insulating layer, and may be electrically connected to a printed circuit board (PCB) outside the display panel 10. The second terminal PCB-P (e.g., the second terminal area) of the printed circuit board PCB may be electrically connected to the first terminal 140 of the display panel 10.

[0106] The printed circuit board (PCB) can transmit electrical signals or power from a controller (not shown) to the display panel 10. The PCB can also transmit electrical signals, such as control signals generated by the controller, to the first scan drive circuit 110 and the second scan drive circuit 120. That is, electrical signals can be transmitted from outside the display panel 10 to the display panel 10 at the first terminal 140 via the second terminal PCB-P, but is not limited thereto. Each of the first terminal 140 and the second terminal PCB-P may include a terminal pad through which the electrical signals are transmitted. Terminal pads may be provided in multiples within corresponding terminals or terminal areas.

[0107] The controller can provide a first power supply voltage (e.g., drive voltage ELVDD) and a second power supply voltage (e.g., common voltage ELVSS) to the first power line 160 and the second power line 170 respectively via the first connection line 161 and the second connection line 171.

[0108] A first power supply voltage can be provided to each pixel P via a drive voltage line PL connected to the first power supply line 160, and a second power supply voltage can be provided to the counter electrode 370 of each pixel P connected to the second power supply line 170.

[0109] The data driving circuit 150 can be electrically connected to the data line DL. The data signal Dm of the data driving circuit 150 can be provided to each pixel P through the connection line 151 connected to the first terminal 140 and the data line DL connected to the connection line 151.

[0110] although Figure 3 The figure shows the data driving circuit 150 disposed on a printed circuit board (PCB), but in another embodiment, the data driving circuit 150 may be disposed within the display panel 10, for example, on the lower substrate 100. In an embodiment, for example, the data driving circuit 150 may be disposed between the first terminal 140 and the first power line 160.

[0111] The first power line 160 may include a first sub-line 162 and a second sub-line 163, both extending parallel to the x-direction, with a second region A2 between the first sub-line 162 and the second sub-line 163. A drive voltage line PL may extend to intersect the second region A2 and connect to the first sub-line 162 and the second sub-line 163. The drive voltage line PL may connect the first sub-line 162 and the second sub-line 163 to each other. The second power line 170 may partially surround the second region A2 in a ring shape, with one side open (e.g., Figure 3 (At the bottom of the view). As described above, the first power line 160 can provide a first power supply voltage to each pixel P, and the second power line 170 can provide a second power supply voltage to each pixel P.

[0112] Figure 5 This is a top view of an embodiment of the display panel 10, and is also shown in detail. Figure 3 The diagram shows the configuration structure of the display panel 10, which is set to multiple lines L (e.g., multiple lines L). Figure 6 yes Figure 5 A magnified top view of area VI of display panel 10.

[0113] Reference Figure 5 and Figure 6 The display panel 10 may include a driving circuit disposed in a third region A3 of the lower substrate 100 and multiple lines L extending from the driving circuit and electrically connected to a pixel P disposed in a second region A2.

[0114] In an embodiment, for example, multiple lines L may include references Figure 3 and Figure 4 The described scan line SL, transmit control line EL, data line DL, drive voltage line PL, and initialization voltage line VL are at least one of them.

[0115] Figure 5 The middle figure shows a first scan drive circuit 110 and a second scan drive circuit 120 disposed in the third region A3, and multiple lines L extending from the first scan drive circuit 110 or the second scan drive circuit 120 into the second region A2. In this case, the multiple lines L may correspond to at least one of the scan line SL and the emission control line EL.

[0116] The first region A1 may be located within the planar region of the second region A2 of the lower substrate 100. The first region A1 is adjacent to the component 20 included below the display panel 10 (see [link]). Figure 2 A corresponding planar region with relatively high transmittance, and the pixel P or the line L connected to the pixel P may not be provided in the first region A1. Due to the relatively high transmittance, the light transmittance of the layer passing through the display panel 10 in the first region A1 can be greater than the light transmittance of the layer passing through the display panel 10 in other regions such as the second region A2 and / or the third region A3, but is not limited thereto.

[0117] In the top view, the line L connecting to pixel P located in the second region A2 can bypass the first region A1, outside of it. (See reference...) Figure 5 and Figure 6Line L extends along the x-direction to define its direction of extension. In an embodiment, line L may extend along the outer edge of the first region A1 to be adjacent to the first region A1 along the y-direction, or it may terminate at the outer edge of the first region A1 to break away from another line L. The end of line L may correspond to and meet the outer edge of the first region A1, but is not limited thereto.

[0118] When multiple lines L bypass the first region A1 by being positioned along the outer edge of the first region A1 at its peripheral portion, a non-display area NDA can be defined or formed at the peripheral portion of the first region A1 due to the bypassed lines. Therefore, in one or more embodiments, a portion of the multiple lines L can be broken at the boundary of the first region A1 to reduce the non-display area NDA and maximize the planar area of ​​the second region A2 where the pixel P is disposed.

[0119] The first region A1 can be disposed on one side of the second region A2. In an embodiment, for example, the first region A1 can be disposed offset relative to the center of the lower substrate 100 to the left or right side of the lower substrate 100 of the display panel 10.

[0120] When a first region A1 is positioned to one side of a second region A2 and at least one of the scan line SL and the emission control line EL is broken at the first region A1, a resistance-capacitance (“RC”) delay may occur based on the difference in length between the two lines L, located on the left and right sides respectively, relative to the break point of the line L. Each pixel P connected to a corresponding line L in the broken lines L can have different brightness characteristics.

[0121] In an embodiment, for example, such as Figure 5 As shown, when the first region A1 is set on the right side within the second region A2, under the same light output conditions, the pixel P connected to the left side of the first region A1 can output light with a relatively larger brightness value compared to the pixel P connected to the right side of the first region A1.

[0122] Therefore, a compensation design, such as gamma compensation, can be applied to the display panel 10 to minimize the brightness difference between pixels P on opposite sides of the break point caused by the broken line portion.

[0123] According to various embodiments of this disclosure, the display panel 10 may have a structure in which all lines L in the second region A2 are disconnected to facilitate the application of compensation design.

[0124] like Figure 5 and Figure 6As shown, multiple lines L can extend parallel to each other along a first direction (e.g., the x-direction) and can be electrically connected to pixels P arranged in a row along the first direction corresponding to each line L.

[0125] Reference Figure 5 and Figure 6 Within a display area (e.g., second area A2), multiple lines L extend parallel to each other along a first direction (e.g., the x-direction) and are arranged adjacent to each other along the first direction and along a second direction (e.g., the y-direction) that intersects the first direction. The multiple lines L adjacent to each other along the first direction are spaced apart to define breakpoints, and each of the breakpoints corresponds to the first area A1 along the second direction.

[0126] Lines L can each be broken within the second region A2 at locations such as adjacent to the outer edge of the first region A1, and spaced apart from the outer edge along a second direction (e.g., the y-direction) intersecting the first direction. The break points can be... Figure 5 The area corresponding to the WA1 range shown (e.g., the break area) is included in the second region A2. The WA1 range extends along a second direction from each of the opposite outer edges of the first region A1 and extends to the outer edge of the second region A2. The WA1 range has a dimension (e.g., width) along the first direction corresponding to the dimension along the first direction of the first region A1.

[0127] The second region A2 can define a plane. Along the plane, the locations where line L breaks can be irregularly or randomly set within the range WA1. In other words, the break points of line L can be set in a zigzag pattern along the range WA1. Therefore, based on the break points of line L, adjacent lines L along the second direction may not correspond to each other.

[0128] Each part of the disconnect line L can be electrically connected to the drive circuits in the first scan drive circuit 110 and the second scan drive circuit 120.

[0129] In one embodiment, the broken portion of line L, for example, the portion to the left of the break point (e.g., the first line portion), can be connected to the first scan drive circuit 110. Additionally, the remaining broken portion of line L, for example, the portion to the right of the break point (e.g., the second line portion), can be connected to the second scan drive circuit 120.

[0130] The two lines L arranged parallel to each other along the second direction may include a first disconnection point and a second disconnection point that are spaced apart from the first scan drive circuit 110 at different distances.

[0131] According to an embodiment, the break point of line L can be irregularly located within the range of WA1, so that the brightness difference between pixels P located on opposite sides of the break point can be minimized.

[0132] In the following text, reference will be made to Figure 6 This disclosure is described in detail.

[0133] A first line L1 may be electrically connected to a plurality of pixels P, including a plurality of first pixels P1 (e.g., first pixels). A second line L2 may be electrically connected to a plurality of pixels P, including a plurality of second pixels P2 (e.g., second pixels). Figure 5 and Figure 6 In the middle, the row can extend along the x-direction.

[0134] A first pixel connected to the same line L1 and a second pixel connected to the same line L2 can be arranged side-by-side along the first row R1. The facing ends of the first line L1 and the second line L2 can be spaced apart from each other along the first row R1 at a first location SP1 (e.g., a first break point). Since the first region A1 is positioned closer to one side of the display panel 10, the two lines L arranged in the same row, for example, the first line L1 (e.g., having a first length) and the second line L2 (e.g., having a second length), can have different lengths. The length is defined along the extension direction of the line L, i.e., the x-direction. That is, along the same row, the first length and the second length are different.

[0135] The third line L3 can be electrically connected to a plurality of pixels P, including multiple third pixels P3 (e.g., third pixels). The fourth line L4 can be electrically connected to a plurality of pixels P, including multiple fourth pixels P4 (e.g., fourth pixels).

[0136] A third pixel connected to the same line in the third line L3 and a fourth pixel connected to the same line in the fourth line L4 can be arranged side by side along the second line R2, which is parallel to the first line R1. The opposite ends of the third line L3 and the fourth line L4 can be spaced apart from each other along the second line R2 at a second location SP2 (e.g., a second break point).

[0137] Additionally, the fifth line L5 can be electrically connected to a plurality of pixels P, including a plurality of fifth pixels P5 (e.g., fifth pixels), and the sixth line L6 can be electrically connected to a plurality of pixels P, including a plurality of sixth pixels P6 (e.g., sixth pixels).

[0138] A fifth pixel connected to the same line in the fifth line L5 and a sixth pixel connected to the same line in the sixth line L6 can be arranged side by side along the third line R3, which is parallel to the first line R1. The opposite ends of the fifth line L5 and the sixth line L6 can be spaced apart from each other along the third line R3 at a third point SP3 (e.g., the third break point).

[0139] The first location SP1 can be located in the first column C1, which extends intersecting (e.g., orthogonally) to the first row R1. The second location SP2 can be located in the second column C2, which extends intersecting (e.g., orthogonally) to the second row R2. The first column C1 and the second column C2 can be parallel to each other and may not intersect each other. The third location SP3 can be located in the third column C3, which extends intersecting (e.g., orthogonally) to the third row R3, and the third column C3 can be parallel to each of the first column C1 and the second column C2.

[0140] The virtual extensions of each of the first column C1, the second column C2, and the third column C3 can pass through and extend through the first region A1. In other words, each of the first point SP1 spaced apart from each other by the first line L1 and the second line L2, the second point SP2 spaced apart from each other by the third line L3 and the fourth line L4, and the third point SP3 spaced apart from each other by the fifth line L5 and the sixth line L6 can be located in different columns. Each of the first point SP1, the second point SP2, and the third point SP3 can be located within the second region A2 within the range WA1. In an embodiment, for example, along the first row R1, the first pixel P1 and the second pixel P2 face each other with a first break point between the first pixel P1 and the second pixel P2, and along the second row R2, the third pixel P3 and the fourth pixel P4 face each other with a second break point between the third pixel P3 and the fourth pixel P4.

[0141] The seventh line L7 can be electrically connected to a plurality of pixels P, including multiple seventh pixels P7 (e.g., seventh pixels). The eighth line L8 can be electrically connected to a plurality of pixels P, including multiple eighth pixels P8 (e.g., eighth pixels). The seventh pixels connected to the seventh line L7 and the eighth pixels connected to the eighth line L8 can be arranged side by side along a fourth line R4 parallel to the first line R1 and passing through the first region A1. The ends of the seventh line L7 and the eighth line L8 facing each other can be spaced apart from each other by the first region A1.

[0142] Line L is connected to the pixel P located on the left side based on the position of the first region A1, for example... Figure 6The first line L1, the third line L3, the fifth line L5, and the seventh line L7 (e.g., the first line) can extend from the first scan drive circuit 110 disposed on the left side of the third region A3. Additionally, the line L connected to the pixel P disposed on the right side based on the position of the first region A1, for example, Figure 6 The second line L2, the fourth line L4, the sixth line L6, and the eighth line L8 (e.g., the second line) can extend from the second scan drive circuit 120 located on the right side of the third region A3. Each of the lines extending from the respective drive circuit can terminate at a position corresponding to the first region A1 (i.e., within the range of WA1) to define the break point of the multiple lines L.

[0143] Two adjacent lines in a line L extending from the first scan driving circuit 110, such as a first line L1 and a third line L3 adjacent along the y-direction, may have different lengths in a direction away from the first scan driving circuit 110 (e.g., along the x-direction). Furthermore, the number of first pixels connected to the first line L1 and the number of third pixels connected to the third line L3 may be different. Similarly, two adjacent lines in a line L extending from the second scan driving circuit 120, such as a second line L2 and a fourth line L4 adjacent along the y-direction, may also have different lengths in a direction away from the second scan driving circuit 120 (e.g., along the x-direction) and may each be connected to different numbers of pixels P.

[0144] The line width is taken orthogonally to the extension direction of line L. The line widths of two adjacent lines can be different from each other. In an embodiment, for example, the first line L1 can have a first width HL1, the third line L3 can have a third width HL3, and the fifth line L5 can have a fifth width HL5.

[0145] The width of each line L can correspond to the length of each line. In an embodiment, for example, when the length of the first line L1 from the first scan drive circuit 110 to the first location SP1 (e.g., the first length) is less than the length of the third line L3 from the first scan drive circuit 110 to the second location SP2 (the third length), the width HL1 of the first line L1 can be greater than the width HL3 of the third line L3. Additionally, when the length of the first line L1 from the first scan drive circuit 110 to the first location SP1 is greater than the length of the fifth line L5 from the first scan drive circuit 110 to the third location SP3 (e.g., the fifth length), the width HL1 of the first line L1 can be less than the width HL5 of the fifth line L5.

[0146] In embodiments, for example, the planar area occupied by each of the plurality of lines L (e.g., the product of the dimensions along the x and y directions) can be substantially the same as each other. That is, the length and width of the lines L are inversely proportional to each other to define the same planar area as described above. (Refer to...) Figure 6For example, along the first row R1, the first line L1 has a first length and a first width that define the first plane area of ​​the first line L1, and along the second row R2, the third line L3 has a third length and a third width that define the third plane area of ​​the third line L3. The first length of the first line L1 and the third length of the third line L3 are different from each other, and the first plane area and the third plane area are equal to each other.

[0147] Figure 7 This figure shows an enlarged cross-sectional view of an embodiment of the display panel 10. Figure 7 Can be with Figure 6 The cross-sectional views of the seventh pixel P7 and the eighth pixel P8 correspond to each other.

[0148] Reference Figure 7 The display panel 10 may include a lower substrate 100, an upper substrate 200, and a display layer 300 (e.g., an image display layer) between the upper substrate 200 and the lower substrate 100.

[0149] Display layer 300 may include a plurality of pixels P, including a seventh pixel P7 and an eighth pixel P8. Each of the pixels P may include a pixel circuit PC and a display element OLED electrically connected to the pixel circuit PC, the pixel circuit PC including a thin-film transistor (TFT). Pixels P may be disposed in a second region A2, and two pixels P adjacent to the periphery of the first region A1, such as the seventh pixel P7 and the eighth pixel P8, may be disposed in the second region A2, while being spaced apart from each other by the first region A1.

[0150] A thin-film transistor (TFT) may include a semiconductor layer A, a gate electrode G, a source electrode S, and a drain electrode D. The semiconductor layer A may include amorphous silicon, polycrystalline silicon, or organic semiconductor materials.

[0151] Semiconductor layer A may include amorphous silicon. In another embodiment, semiconductor layer A may include an oxide semiconductor, including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and / or zinc (Zn). In embodiments, for example, semiconductor layer A may include oxide semiconductors such as indium gallium zinc oxide (“IGZO”), zinc tin oxide (“ZTO”), and zinc indium oxide (“ZIO”).

[0152] A gate electrode G may be disposed above a semiconductor layer A, and a gate insulating layer 310 (e.g., a first insulating layer) may be disposed between the gate electrode G and the semiconductor layer A. The gate electrode G may comprise molybdenum (Mo), aluminum (Al), copper (Cu), and / or Ti, and may comprise a single layer or multiple layers. In an embodiment, the gate electrode G may comprise a single layer of Mo.

[0153] The gate insulating layer 310 may include silicon oxide (SiO2) or silicon nitride (SiN). x Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) are included.

[0154] The source electrode S and / or drain electrode D can be disposed above the gate electrode G, and an interlayer insulating layer 320 (e.g., a second insulating layer) is disposed between the gate electrode G and the source electrode S and / or drain electrode D, respectively. The source electrode S and / or drain electrode D may include Mo, Al, Cu, or Ti, and may comprise a single layer or multiple layers. In an embodiment, the source electrode S and / or drain electrode D may comprise multiple layers of Ti / Al / Ti.

[0155] The planarization layer 330 may cover the upper surface of the source electrode S and / or the drain electrode D, and may have a flat top surface, so that the pixel electrode 350 may be provided or formed as flat.

[0156] Planarization layer 330 may comprise a single layer or multiple layers of organic material. Planarization layer 330 may comprise benzocyclobutene (“BCB”), polyimide, hexamethyldisiloxane (“HMDSO”), common commercial polymers such as poly(methyl methacrylate”) (“PMMA”) or polystyrene (“PS”), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof. Planarization layer 330 may comprise inorganic material.

[0157] The planarization layer 330 may include silicon oxide (SiO2) and silicon nitride (SiN). x Materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) can be used. When the planarization layer 330 includes inorganic materials, chemical planarization polishing can be performed. The planarization layer 330 can include both organic and inorganic materials.

[0158] Pixel electrode 350 may be a (semi-)transparent electrode or a reflective electrode. In embodiments, pixel electrode 350 may include a reflective material layer, such as a film comprising silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), Cr, or combinations thereof, and a transparent or semi-transparent electrode layer provided or formed on the reflective material layer. The transparent or semi-transparent electrode layer may include at least one selected from indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (“ZnO”), indium oxide (In2O3), indium gallium oxide (“IGO”), and aluminum zinc oxide (“AZO”). In embodiments, pixel electrode 350 may include a stacked structure having ITO / Ag / ITO.

[0159] A pixel defining film 340 (e.g., a pixel defining layer) can be disposed on the planarization layer 330. The pixel defining film 340 can define the emission region (e.g., a light emitting region) of pixel P by defining an opening corresponding to a portion of pixel electrode 350. Additionally, the pixel defining film 340 can increase the distance between the edge of pixel electrode 350 and the opposing electrode 370 above pixel electrode 350 to prevent the generation of electric arcs or the like at the edge of pixel electrode 350. For example, using a spin-coating method, the pixel defining film 340 can comprise or be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin.

[0160] The intermediate layer 360 of the OLED display element may include an organic emitting layer (e.g., a light emitting layer). The organic emitting layer may include organic materials, including fluorescent or phosphorescent materials that emit colored light such as red, green, blue, or white light. The organic emitting layer may include relatively low molecular weight organic materials or polymeric organic materials, and functional layers such as a hole transport layer (“HTL”), a hole injection layer (“HIL”), an electron transport layer (“ETL”), or an electron injection layer (“EIL”) may be further selectively disposed above or below the organic emitting layer. The intermediate layer 360 may be discretely configured with patterns corresponding respectively to each of the plurality of pixel electrodes 350. However, this disclosure is not limited thereto. The intermediate layer 360 may be modified in various ways, such as including a monomeric layer above each of the plurality of pixel electrodes 350.

[0161] The counter electrode 370 can be a transparent electrode or a reflective electrode. In embodiments, the counter electrode 370 can be a transparent or semi-transparent electrode and can include a metallic material in a thin film having a relatively small work function, including lithium (Li), calcium (Ca), lithium fluoride (LiF) / Ca, LiF / Al, Al, Ag, Mg, and combinations thereof. Additionally, a transparent conductive oxide (“TCO”) film such as ITO, IZO, ZnO, or In2O3 can be further disposed on the metallic thin film. The counter electrode 370 can be disposed on the intermediate layer 360 and the pixel defining film 340. The counter electrode 370 can be provided or formed integrally to cover multiple display elements OLED and can include or define a hole 370H corresponding to the first region A1.

[0162] Reference Figure 7 The pixel circuit PC and / or display element OLED may not be disposed in the first region A1. The pixel circuit PC of each of the seventh pixel P7 and the eighth pixel P8 adjacent to the periphery of the first region A1 can be spaced apart from each other by a first hole 300H corresponding to the first region A1. In addition, the display elements OLED of the seventh pixel P7 and the eighth pixel P8 can be separated from each other around the first hole 300H corresponding to the first region A1.

[0163] The first aperture 300H may be provided or formed through the thickness of multiple layers included in the display layer 300. In an embodiment, the first aperture 300H may penetrate each layer within a stacked structure including a gate insulating layer 310, an interlayer insulating layer 320, a planarization layer 330, a pixel defining film 340, and a counter electrode 370. In an embodiment, for example, the first aperture 300H may include a hole defined in each of the gate insulating layer 310, the interlayer insulating layer 320, the planarization layer 330, the pixel defining film 340, and the counter electrode 370 that overlap or align with each other.

[0164] The width W300 (e.g., the first width) of the first hole 300H can be defined by the width of the hole with the smallest size among the holes defined in the gate insulating layer 310, the interlayer insulating layer 320, the planarization layer 330, the pixel defining film 340, and the counter electrode 370, respectively. The width W300 can be the minimum distance between the facing side surfaces of the layers within the stacked structure defining the first hole 300H. In this respect, although... Figure 7 The figure shows that the width of the hole in the gate insulating layer 310 defines the first hole 300H, but in another embodiment, the planarization layer 330 may cover the facing side surfaces of the gate insulating layer 310 and the interlayer insulating layer 320 below the planarization layer 330 at the first hole 300H, and the first hole 300H may be defined by the width of the hole defined in the planarization layer 330.

[0165] The width W300 of the first aperture 300H may be greater than the width W0 (e.g., a second width) of the component 20 corresponding to the first region A1 and included below the lower substrate 100. The width W0 may be the maximum dimension of the component 20 in the same direction along the width W300. The first aperture 300H may be provided or formed to not absorb or reflect light emitted from the component 20 and / or light incident on the component 20.

[0166] According to embodiments of this disclosure, pixel P may have the same characteristics as referenced pixel P. Figure 7 The seventh pixel P7 or the eighth pixel P8 have the same structure.

[0167] According to various embodiments of the present disclosure, a display device 1 can be provided that maximizes the display area DA and improves display characteristics.

[0168] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features in each embodiment should generally be taken into account for other similar features in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: a substrate, including: a display area, including: a first non-display area, within the display area, and at which light is transmittable to and from the substrate; and a plurality of pixels, including: a first pixel and a second pixel, disposed along a first row, the first row extending along a first direction, and a third pixel and a fourth pixel, disposed along a second row parallel to the first row; each of the first row and the second row is adjacent to the first non-display area along a second direction intersecting the first direction; a first column, defined as perpendicular to the first row; and a second column, defined as parallel to and spaced apart from the first column, wherein the first column and the second column each pass through the first non-display area; and a plurality of lines on the substrate and including: a first line, extending along the first row and electrically connected to the first pixel; a second line, extending along the first row and electrically connected to the second pixel; a first disconnection point at which the first line and the second line are spaced apart from each other along the first row; a third line, extending along the second row and electrically connected to the third pixel; a fourth line, extending along the second row and electrically connected to the fourth pixel; and a second disconnection point at which the third line and the fourth line are spaced apart from each other along the second row, wherein the first disconnection point corresponds to the first column, and the second disconnection point corresponds to the second column, wherein within the display area, along the first row, the first line has a first length, along the second row, the third line has a third length, and the first length of the first line and the third length of the third line are different from each other. 2.The display device of claim 1, further comprising first and second scan driving circuits facing each other, the display area being between the first and second scan driving circuits, wherein, the first and third lines each extend from the first scan driving circuit, and the second and fourth lines each extend from the second scan driving circuit. 3.The display device of claim 2, wherein, the substrate further includes a second non-display area outside the display area, and the first and second scan driving circuits are in the second non-display area. 4.The display device of claim 1, further comprising scan lines and light emission control lines on the substrate and electrically connected to the plurality of pixels, wherein the plurality of lines further include the scan lines provided as a plurality of lines, the light emission control lines provided as a plurality of lines, or the scan lines and the light emission control lines. 5.The display device of claim 1, wherein, within the display area, the plurality of pixels further include a fifth pixel and a sixth pixel, the fifth and sixth pixels being disposed along a third row parallel to the first row, The substrate further includes a third column parallel to and spaced apart from the first column, the third column passing through the first non-display region, and Within the display region, the plurality of lines further includes: a fifth line extending along the third row and electrically connected to the fifth pixel; a sixth line extending along the third row and electrically connected to the sixth pixel; and a third disconnection point at which the fifth line and the sixth line are spaced apart from each other along the third row, wherein the third disconnection point corresponds to the third column.

6. The display device of claim 1, wherein, Within the display region, the plurality of pixels further includes a seventh pixel and an eighth pixel, the seventh pixel and the eighth pixel being disposed along a fourth row parallel to the first row, and the seventh pixel and the eighth pixel are spaced apart from each other, the first non-display region being between the seventh pixel and the eighth pixel.

7. The display device of claim 6, wherein the fourth row passes through the first non-display region.

8. The display device of claim 1, wherein, Within the display region, along the first row, the first line has a first length and the second line has a second length, and the first length of the first line and the second length of the second line are different from each other.

9. The display device of claim 1, wherein, Within the display region, the first pixels are provided as a plurality, including a plurality of first pixels connected to the first line, the third pixels are provided as a plurality, including a plurality of third pixels connected to the third line, and a number of the first pixels connected to the first line is different from a number of the third pixels connected to the third line.

10. The display device of claim 1, wherein, Within the display region, in a top view, along the first row, the first line has a first length and a first width defining a first planar area of the first line, along the second row, the third line has a third length and a third width defining a third planar area of the third line, the first length of the first line and the third length of the third line are different from each other; and the first planar area and the third planar area are equal to each other.

11. The display device of claim 1, wherein, along the first row, the first pixel and the second pixel face each other, the first disconnection point being between the first pixel and the second pixel, and along the second row, the third pixel and the fourth pixel face each other, the second disconnection point being between the third pixel and the fourth pixel.

12. The display device of claim 1, wherein, each of the plurality of pixels includes a display element including a pixel electrode, a counter electrode, and a light emission layer between the pixel electrode and the counter electrode, and the counter electrode includes a single body corresponding to each of the plurality of pixels within the display region, and defines a hole corresponding to the first non-display region.

13. A display device, comprising: a substrate including: a display region including a plurality of pixels; and a first non-display region, within the display region, and at which light is transmissible to and from the substrate; and a plurality of lines on the substrate and electrically connected to the plurality of pixels, wherein, within the display region, the plurality of lines extend along a first direction and are parallel to each other, are disposed adjacent to each other along the first direction and along a second direction intersecting the first direction, and are adjacent to the first non-display region along the second direction, the plurality of lines adjacent to the first non-display region along the second direction and adjacent to each other along the first direction are spaced apart from each other along the first direction to define disconnection points, and each of the disconnection points corresponds to the first non-display region along the second direction, wherein the plurality of lines include first lines and second lines adjacent to each other along the first direction and defining the disconnection points, and the first lines adjacent to each other along the second direction differ from each other in length.

14. The display device of claim 13, wherein, Within the display region, the disconnection points are disposed in a zigzag pattern.

15. The display device of claim 13, further comprising first and second scan driving circuits facing each other, the display region being between the first and second scan driving circuits, wherein, the first lines each extend from the first scan driving circuit, and the second lines each extend from the second scan driving circuit toward a respective first line, wherein the first lines are spaced apart from the second lines to define the disconnection points, respectively.

16. The display device of claim 15, wherein, the substrate further includes a second non-display region outside the display region, and the first and second scan driving circuits are in the second non-display region.

17. The display device of claim 15, wherein, Within the display region, the first lines are disposed along the second direction, and the first lines adjacent to each other along the second direction each have the length taken from the first scan driving circuit to a respective disconnection point.

18. The display device of claim 15, wherein, Within the display region, in a top view, the first lines are disposed along the second direction, and for the first lines adjacent to each other along the second direction, each first line has a first length and a first width defining a first planar area, and the first planar areas of the first lines adjacent to each other along the second direction are equal to each other.

19. The display device of claim 13, further comprising, on the substrate, scan lines and light emission control lines electrically connected to the plurality of pixels, wherein the plurality of lines further include the scan lines provided as a plurality of lines, the light emission control lines provided as a plurality of lines, or the scan lines and the light emission control lines.

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