Display device

Abstract

The present disclosure relates to a display device. An embodiment of the present invention relates to a display device comprising: a substrate; a gate insulating layer located on the substrate; a semiconductor layer located on the gate insulating layer and comprising a first semiconductor; a source electrode and a drain electrode located on the first semiconductor; and a data line located on the gate insulating layer, the gate insulating layer comprising a first portion overlapping the data line and a second portion located around the first portion, the second portion being thinner than the first portion.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0002] Display devices such as liquid crystal display (LCD) and organic light emitting diode display (OLED) have a display panel including a plurality of pixels that can display images. Each pixel includes a pixel electrode that receives a data signal, and the pixel electrode is connected to at least one transistor to receive the data signal.

[0003] The transistor included in the display panel may include a gate electrode, a semiconductor, a source electrode and a drain electrode. Depending on the manufacturing method of the transistor, the morphology of the semiconductor may be different. For example, a mask may be used to pattern the semiconductor of the transistor together with the patterning of the source electrode and the drain electrode. Alternatively, the semiconductor of the transistor may be patterned separately from the patterning of the source electrode and the drain electrode, and may also be patterned using a mask independent of the mask used in the patterning of the source electrode and the drain electrode.

[0004] When the semiconductor of the transistor is patterned together with the source electrode and the drain electrode, a semiconductor layer may remain under the data line, and quality defects such as horizontal crosstalk or waterfall phenomenon may occur due to the semiconductor layer protruding outward from the edge of the data line.

[0005] On the contrary, when the semiconductor of the transistor is patterned using a mask different from that of the source electrode and the drain electrode, the alignment margin between the semiconductor and the source electrode and the drain electrode needs to be fully considered, the size of the transistor will become larger, and in a structure in which transistors located in a pixel column are alternately connected to different data lines, there may be a problem of horizontal stripe stains due to the distribution of the kickback voltage. Summary of the invention

[0006] The present disclosure is to solve such a problem and to provide a display device that can prevent quality defects such as horizontal crosstalk or a waterfall phenomenon, reduce the size of transistors, and reduce the spread of a kick-back voltage.

[0007] A display device involved in one embodiment of the present invention includes: a substrate; a gate insulating layer located on the substrate; a semiconductor layer located on the gate insulating layer and including a first semiconductor; a source electrode and a drain electrode located on the first semiconductor; and a data line located on the gate insulating layer, the gate insulating layer including a first portion overlapping with the data line and a second portion located around the first portion, the thickness of the second portion being thinner than the thickness of the first portion.

[0008] The first semiconductor may have an edge position that is aligned with an edge position of the source electrode and is located outside the edge position of the source electrode.

[0009] Alternatively, only the gate insulating layer may be disposed between the data line and the substrate, and the semiconductor layer may not be disposed.

[0010] It may be that the display device further includes a gate line located on the substrate and crossing the data line, and the semiconductor layer further includes a second semiconductor located in a region where the gate line crosses the data line.

[0011] It may be that the source electrode includes: a straight portion extending in a direction different from the direction in which the data line extends; and a curved portion connected to the straight portion, and the semiconductor layer also includes a first protrusion having a shape protruding from one side of the first semiconductor, and the first protrusion overlaps a portion of the straight portion of the source electrode adjacent to the curved portion.

[0012] The first protrusion may have an edge position aligned with an edge position of a portion of the straight portion of the source electrode that is adjacent to the bent portion.

[0013] It may be that the display device further includes a gate line located on the substrate and crossing the data line, the gate line includes a gate electrode, and the first protrusion overlaps with an edge position of the gate electrode.

[0014] It may be that the display device further includes a gate line located on the substrate and crossing the data line, and the semiconductor layer further includes a second protrusion having a shape protruding from another side of the first semiconductor, and the second protrusion overlaps with an edge position of the gate line.

[0015] The second protrusion may include an edge position aligned with an edge position of at least a portion of the drain electrode that does not overlap with the first semiconductor.

[0016] It may be that the display device further includes a sustaining electrode located between the substrate and the gate insulating layer, the drain electrode includes an extension portion overlapping the sustaining electrode, and the semiconductor layer is not located between the extension portion and the substrate.

[0017] A display device involved in one embodiment of the present invention includes: a substrate; a gate line located on the substrate; a gate insulating layer located on the gate line; a semiconductor layer located on the gate insulating layer and including a first semiconductor; a source electrode and a drain electrode located on the first semiconductor; and a data line located on the gate insulating layer, the first semiconductor having an edge position that is parallel to the edge position of the source electrode and located outside the edge position of the source electrode, the semiconductor layer is not located between the data line and the substrate, and the semiconductor layer also includes a second semiconductor located in the area where the gate line and the data line intersect.

[0018] It may be that the source electrode includes: a straight portion extending in a direction different from the direction in which the data line extends; and a curved portion connected to the straight portion, and the semiconductor layer also includes a first protrusion having a shape protruding from one side of the first semiconductor, and the first protrusion overlaps a portion of the straight portion of the source electrode adjacent to the curved portion.

[0019] The first protrusion may have an edge position aligned with an edge position of a portion of the straight portion of the source electrode that is adjacent to the bent portion.

[0020] The gate line may include a gate electrode, and the first protrusion overlaps an edge position of the gate electrode.

[0021] The semiconductor layer further includes a second protrusion having a shape protruding from another side of the first semiconductor layer, and the second protrusion overlaps an edge position of the gate line.

[0022] The second protrusion may have an edge position aligned with an edge position of at least a portion of the drain electrode that does not overlap with the first semiconductor.

[0023] A method for manufacturing a display device involved in an embodiment of the present invention includes: a step of forming a gate line including a gate electrode on a substrate; a step of forming a gate insulating layer on the gate line; a step of forming a semiconductor layer on the gate insulating layer and etching the semiconductor layer to form a first opening; a step of stacking a conductive material on the semiconductor layer to form a conductive layer and etching the conductive layer using a first mask pattern located on the conductive layer as a mask to form a data line and an electrode; and a step of etching the semiconductor layer using the first mask pattern or a second mask pattern with a portion of the first mask pattern removed as a mask, wherein the data line is formed at a position overlapping with the first opening, and an edge position of the first opening and an edge position of the data line are separated from each other.

[0024] It may be that the first mask pattern includes a first part and a second part having different thicknesses from each other, the second mask pattern does not include a thinner part of the first part and the second part, and the manufacturing method of the display device also includes a step of using the second mask pattern as a mask to etch the electrode to form a source electrode and a drain electrode facing each other.

[0025] It may be that the manufacturing method of the display device also includes the step of forming a sustaining electrode line including a sustaining electrode on the substrate, and in the step of etching the semiconductor layer to form a first opening, a second opening included in the semiconductor layer is also formed, the drain electrode includes an extended portion overlapping with the sustaining electrode, the extended portion is formed at a position overlapping with the second opening, and the edge position of the second opening and the edge position of the extended portion are separated from each other.

[0026] It may be that in the step of etching the semiconductor layer using the first mask pattern or the second mask pattern with a portion of the first mask pattern removed as a mask, a first semiconductor having an edge position parallel to and outside the edge position of the source electrode is formed.

[0027] (Effects of the Invention)

[0028] According to the embodiments of the present invention, a display device can be provided which prevents quality defects such as horizontal crosstalk or a waterfall phenomenon, can reduce the size of a transistor, and can reduce the spread of a kick-back voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a planar configuration diagram of a pixel of a display device according to an embodiment of the present invention.

[0030] Figure 2 It means that the line IIa-IIb was intercepted. Figure 1 A cross-sectional view of the display device shown,

[0031] Figure 3 It means that the line IIIa-IIIb was taken. Figure 1 A cross-sectional view of the display device shown,

[0032] Figure 4 is a plan view of a display device in one process of a method for manufacturing a display device according to an embodiment of the present invention,

[0033] Figure 5 It means that the Figure 4 A cross-sectional view of the display device shown,

[0034] Figure 6 It means that the line VIa-VIb is intercepted. Figure 4 A cross-sectional view of the display device shown,

[0035] Figure 7 yes Figure 4 A plan view of a display device in a subsequent process of the display device shown in FIG.

[0036] Figure 8 It means that the VIIIa-VIIIb line was taken. Figure 7 A cross-sectional view of the display device shown,

[0037] Fig. 9 It is taken along line IXa-IXb. Figure 7 A cross-sectional view of the display device shown,

[0038] Fig.10 yes Figure 7 A plan view of a display device in a subsequent process of the display device shown in FIG.

[0039] Fig.11 It means that the Fig.10 A cross-sectional view of the display device shown,

[0040] Fig.12 It is taken along line XIIa-XIIb. Fig.10 A cross-sectional view of the display device shown,

[0041] Fig.13 yes Fig.11 A cross-sectional view of a display device in a subsequent process of the display device shown,

[0042] Fig.14 yes Fig.12 A cross-sectional view of a display device in a subsequent process of the display device shown,

[0043] Fig.15 yes Fig.10A plan view of a display device in a subsequent process of the display device shown in FIG.

[0044] Fig.16 It means that the XVIa-XVIb line is intercepted. Fig.15 A cross-sectional view of the display device shown,

[0045] Fig.17 It means that the XVIIa-XVIIb line was taken. Fig.15 A cross-sectional view of the display device shown,

[0046] Fig.18 yes Fig.15 A plan view of a display device in a subsequent process of the display device shown in FIG.

[0047] Fig.19 It means that the XIXa-XIXb line was intercepted. Fig.18 A cross-sectional view of the display device shown,

[0048] Fig. 20 It means that the Fig.18 A cross-sectional view of the display device shown,

[0049] Fig.21 is a plan view of a display device in one process of a method for manufacturing a display device according to an embodiment of the present invention,

[0050] Fig. 22 is a planar configuration diagram of a pixel of a display device according to an embodiment of the present invention.

[0051] Fig.23 is a cross-sectional view of a data line and its surroundings of a display device according to an embodiment of the present invention,

[0052] Fig.24 It is a plan view of a display device according to an embodiment of the present invention.

[0053] (Explanation of symbols)

[0054] 3: liquid crystal layer; 11, 21: alignment film; 24, 150a, 150b, 150c, 150d, 185, 235: opening; 31: liquid crystal molecules; 50: mask pattern; 100, 200, 300: display panel; 110, 210: substrate; 121: gate line; 131: sustain electrode line; 137, 177, 197: extension; 140: gate insulating layer; 150: semiconductor layer; 154, 155: semiconductor; 1 54a, 154b, 154c: protrusion; 163, 164, 165: ohmic contact layer; 171: data line; 173: source electrode; 175: drain electrode; 180a, 180b, 250: insulating layer; 191: pixel electrode; 220: light shielding part; 230: color filter; 270: common electrode; 400a, 400b: gate driving unit; 500: data driving unit; 600: signal control unit; 1000: display device. DETAILED DESCRIPTION

[0055] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various forms and is not limited to the embodiments described herein.

[0056] In order to clearly describe the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0057] In addition, in the drawings, the size and thickness of each component are arbitrarily shown for the sake of convenience of explanation, and the present invention is not necessarily limited to the illustrated case. In the drawings, the thickness is enlarged to clearly show each layer and region. In addition, in the drawings, the thickness of some layers and regions is exaggerated for the sake of convenience of explanation.

[0058] In addition, when a layer, film, region, plate or other part is located on or above another part, it includes not only the case where it is directly located on the other part, but also the case where there is another part in between. On the contrary, when a part is directly located on another part, it means that there is no other part in between. In addition, being located on or above a part that becomes a reference means being located above or below the part that becomes a reference, and does not necessarily mean being located above or above in the opposite direction of gravity.

[0059] Throughout the specification, when a certain part includes a certain constituent element, unless otherwise stated, it does not exclude other constituent elements but means that other constituent elements may be included.

[0060] Throughout the specification, "in a plan view" refers to a situation when observing a plane parallel to two directions intersecting each other (for example, the first direction DR1 and the second direction DR2) (referred to as on a plane), and "in a cross-sectional view" refers to a situation when observing a plane cut along a direction perpendicular to the plane parallel to the first direction DR1 and the second direction DR2 (for example, the third direction DR3). In addition, when two components overlap, unless otherwise specified, it means that the two components overlap in the third direction DR3 (for example, the direction perpendicular to the upper surface of the substrate).

[0061] First, refer to Figures 1 to 3 , describing a display device according to an embodiment of the present invention.

[0062] Figure 1 is a planar configuration diagram of a pixel of a display device according to an embodiment of the present invention. Figure 2 It means that the line IIa-IIb was intercepted. Figure 1 A cross-sectional view of the display device shown, Figure 3 It means that the line IIIa-IIIb was taken. Figure 1 A cross-sectional view of the display device shown.

[0063] A display device according to an embodiment of the present invention may include a plurality of pixels PX, and each pixel PX may include: a display unit capable of displaying an image; and a pixel circuit unit including at least one transistor.

[0064] The display device involved in one embodiment of the present invention may be a liquid crystal display device, an organic light emitting display device, an electrophoretic display device, an electrowetting display device, a micro light emitting diode (Micro LED) display device, a quantum dot light emitting diode (QLED) display device, a quantum dot organic light emitting diode (QD-OLED) display device, etc. In the present disclosure, a liquid crystal display device is used as an example for description.

[0065] The display device may include a first substrate 110 , and a display portion and a pixel circuit portion may be formed on the first substrate 110 .

[0066] A gate conductive layer including a plurality of gate lines 121 may be disposed on the first substrate 110 .

[0067] Each gate line 121 may transmit a gate signal and may extend long substantially in a direction parallel to the first direction DR1. Each gate line 121 may include a plurality of gate electrodes 124. The gate line 121 may have an opening 24 between two gate electrodes 124 adjacent to each other in the first direction DR1.

[0068] The gate conductive layer may further include a plurality of sustaining electrode lines 131. The sustaining electrode lines 131 may be away from the gate lines 121 and may transmit a certain voltage. Each sustaining electrode line 131 may include a transverse portion 131a, an expansion portion 137 and a longitudinal portion 133.

[0069] The transverse portion 131 a may extend long substantially in a direction parallel to the first direction DR1 .

[0070] The transverse portion 131a may include an expansion portion 137 located at each pixel PX. The expansion portion 137 may also be referred to as a sustain electrode.

[0071] The longitudinal portion 133 may extend from the transverse portion 131a substantially in the second direction DR2. The longitudinal portion 133 may be located at left and right sides of each pixel PX.

[0072] The sustain electrode line 131 may further include a transverse portion 131b. The transverse portion 131b may be away from the transverse portion 131a and extend substantially long in the first direction DR1. The longitudinal portion 133 may be located between the two transverse portions 131a and 131b and may be connected to the two transverse portions 131a and 131b.

[0073] A gate insulating layer 140 may be provided on the gate conductive layer. The gate insulating layer 140 may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), insulating materials such as silicon oxynitride.

[0074] A semiconductor layer including a semiconductor 154 may be disposed on the gate insulating layer 140. The semiconductor layer may include semiconductor materials such as amorphous silicon, polycrystalline silicon, or metal oxide.

[0075] The semiconductors 154 may be located on the gate electrodes 124 , and may respectively overlap the gate electrodes 124 in a plan view (or in a direction perpendicular to the upper surface of the first substrate 110 ).

[0076] Ohmic contact layers 163 and 165 may be provided on the semiconductor layer. The ohmic contact layers 163 and 165 may include n-type impurities such as phosphorus doped at a high concentration. + Hydrogenated amorphous silicon or silicide, etc.

[0077] A data conductive layer including a plurality of data lines 171 , a plurality of source electrodes 173 , and a plurality of drain electrodes 175 may be disposed on the ohmic contact layers 163 , 165 and the gate insulating layer 140 .

[0078] Each data line 171 may transfer a data voltage, and may extend long in a direction substantially parallel to the second direction DR2 to cross the gate line 121 .

[0079] The source electrode 173 located at each pixel PX can be electrically connected to the corresponding data line 171 to receive the transmission of the data voltage. Each source electrode 173 may include: a straight portion 173a extending from the corresponding data line 171 in a direction substantially parallel to the first direction DR1; and a bent portion 173b connected to the straight portion 173a. The bent portion 173b may be bent in a substantially U-shaped shape, for example, and overlap the gate electrode 124. However, the shape of the source electrode 173 is not limited to that shown in the figure.

[0080] The drain electrode 175 is away from the data line 171 and the source electrode 173 .

[0081] Each drain electrode 175 may face the source electrode 173 in a region overlapping the gate electrode 124 and the semiconductor 154, and may include a rod-shaped portion including a side end portion surrounded by the bent portion 173b of the source electrode 173. The drain electrode 175 may include an expansion portion 177 located at the other side end portion of the rod-shaped portion. The expansion portion 177 may be located at an upper side of the gate line 121 in a plan view.

[0082] In a plan view, the expansion 177 may overlap with the expansion 137 of the sustain electrode line 131. The expansion 177 of the drain electrode 175 and the expansion 137 of the sustain electrode line 131 may form a sustain capacitor capable of maintaining a charged voltage of the pixel PX, wherein the expansion 177 of the drain electrode 175 and the expansion 137 of the sustain electrode line 131 overlap with each other with the gate insulating layer 140 interposed therebetween.

[0083] The opening 24 of the gate line 121 may overlap with the data line 171 crossing the gate line 121 to reduce signal delay caused by coupling between the gate line 121 and the data line 171 .

[0084] The ohmic contact layers 163 and 165 exist only between the semiconductor 154 thereunder and the data conductive layer thereover, and can reduce the contact resistance therebetween.

[0085] At least one of the gate conductive layer and the data conductive layer may include at least one of metals such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta) and alloys thereof.

[0086] The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor Q as a switching element together with the overlapping semiconductor 154. A channel of the thin film transistor Q is formed in the semiconductor 154 between the source electrode 173 and the drain electrode 175. The thin film transistor Q is included in the pixel circuit portion of the pixel PX.

[0087] In an embodiment of the present invention, the planar shape of the semiconductor 154 has an edge position substantially parallel to and located outside the outer edge position of the source electrode 173, wherein the source electrode 173 and the drain electrode 175 face each other with the channel sandwiched therebetween. Specifically, the semiconductor 154 may include an edge position substantially parallel to and located outside the outer envelope of the curved portion 173b of the source electrode 173.

[0088] The distance between the edge of the semiconductor 154 and the outer edge of the source electrode 173 may be, for example, about 0.5 micrometers to 2.5 micrometers. The distance between the edge of the semiconductor 154 and the outer edge of the source electrode 173 may be substantially constant.

[0089] The semiconductor layer may further include a protrusion 154a overlapping a portion of the straight portion 173a of the source electrode 173 adjacent to the curved portion 173b. The protrusion 154a may have an edge position that is aligned with and located outside an edge position of a portion of the straight portion 173a of the source electrode 173 adjacent to the curved portion 173b. The protrusion 154a may have a shape that protrudes from one side of the semiconductor 154. The protrusion 154a may also be omitted.

[0090] Reference Figure 1 The semiconductor layer may further include an island-shaped semiconductor 155 located at a portion where the data line 171 and the gate line 121 overlap and cross each other. The semiconductor 155 may include an edge position substantially aligned with an edge position of the overlapped data line 171.

[0091] At the intersection of the data line 171 and the gate line 121, a short circuit may occur between the data line 171 and the gate line 121 due to the height difference between the data line 171 and the gate line 121. However, according to this embodiment, since the semiconductor 155 is located at the intersection of the gate line 121 and the data line 171, the short circuit between the data line 171 and the gate line 121 can be prevented.

[0092] According to the present embodiment, there is no semiconductor layer below the extended portion 177 of the data line 171 and the drain electrode 175, and the extended portion 177 of the data line 171 and the drain electrode 175 may not overlap with the semiconductor layer. In addition, there is no semiconductor layer formed outside the edge position of the extended portion 177 of the data line 171 and the drain electrode 175. Therefore, it is possible to prevent the parasitic capacitance that may be generated when there is a semiconductor layer protruding outside the edge position of the extended portion 177 of the data line 171 and the drain electrode 175 and the quality defects such as horizontal crosstalk or waterfall caused by light reaction.

[0093] At the same time, the semiconductor 154 including the channel has an edge position substantially aligned with the edge position of the outer contour of the data conductive layer including the source electrode 173 and located outside the edge position of the outer contour of the source electrode 173. That is, the semiconductor 154 has a structure that is self-aligned with the edge position of the data conductive layer including the source electrode 173. Thus, the size of the thin film transistor Q can be reduced.

[0094] A first insulating layer 180a may be disposed on the data conductive layer, and a plurality of color filters 230 may be disposed on the first insulating layer 180a. The color filter 230 may display one of basic colors such as three primary colors of red, green, and blue or four primary colors. In a plan view, a plurality of color filters 230 displaying basic colors different from each other may be alternately arranged in the first direction DR1.

[0095] The color filter 230 may have an opening 235 located on the expansion 177 of the drain electrode 175 .

[0096] Two adjacent color filters 230 may overlap each other at a boundary between two pixels PX adjacent to each other along the first direction DR1 .

[0097] A second insulating layer 180 b may be disposed on the color filter 230 .

[0098] The first insulating layer 180a and the second insulating layer 180b may include silicon nitride (SiN x ), silicon oxide (SiO x), inorganic insulating materials such as silicon oxynitride and / or organic insulating materials. For example, the first insulating layer 180a may include an inorganic insulating material, and the second insulating layer 180b may include an organic insulating material. In this case, the upper surface of the second insulating layer 180b may be substantially flat. The second insulating layer 180b may function as a covering film relative to the color filter 230, may prevent the color filter 230 from being exposed, and may prevent impurities such as pigments included in the color filter 230 from flowing into the liquid crystal layer 3.

[0099] The first and second insulating layers 180a and 180b may have openings 185 located on and overlapping the expansion 177 of the drain electrode 175. The openings 185 may be located within the openings 235 of the color filter 230 in a plan view.

[0100] A plurality of pixel electrodes 191 may be disposed on the second insulating layer 180b. The pixel electrodes 191 may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), a metal thin film, or the like.

[0101] Reference Figure 1 The overall shape of each pixel electrode 191 may be, for example, approximately rectangular, and a portion of the pixel electrode 191 may be removed.

[0102] Specifically, each pixel electrode 191 may include a transverse stem portion 192 , a longitudinal stem portion 193 , a plurality of branch portions 194 , and an expansion portion 197 .

[0103] The transverse stems 192 may extend generally in a direction parallel to the first direction DR1, and the longitudinal stems 193 may extend generally in a direction parallel to the second direction DR2 to cross the transverse stems 192. The transverse stems 192 and the longitudinal stems 193 crossing and connected to each other may jointly form a cross shape.

[0104] The plurality of branches 194 may protrude and extend from the transverse stem 192 or the longitudinal stem 193 and may extend in a direction inclined with respect to the first direction DR1 and the second direction DR2. The pixel electrodes 191 between adjacent branch portions 194 are removed to form gaps.

[0105] The expansion 197 may overlap the expansion 177 of the drain electrode 175 in plan view. The expansion 197 may be electrically connected to the expansion 177 of the drain electrode 175 through the openings 185 of the first insulating layer 180a and the second insulating layer 180b, so that the pixel electrode 191 may receive the data voltage from the drain electrode 175.

[0106] The shape of the pixel electrode 191 is not limited to that shown in the figure, and may have various shapes.

[0107] Reference Figure 2 and Figure 3 The display device involved in one embodiment of the present invention may be a liquid crystal display device, which may include a first display panel 100 and a second display panel 200 facing each other, and a liquid crystal layer 3 located between the first display panel 100 and the second display panel 200. The first display panel 100 may include a first substrate 110 on which the thin film transistor Q and the pixel electrode 191 described above are formed, and the second display panel 200 may include a second substrate 210. When the first substrate 110 is set as the center and the upper side is set, it refers to the upper side of the surface facing the liquid crystal layer 3 side of the two surfaces of the first substrate 110, and when the second substrate 210 is set as the center and the lower side is set, it refers to the lower side of the surface facing the liquid crystal layer 3 side of the two surfaces of the second substrate 210.

[0108] Regarding the second display plate 200 , a light blocking member 220 may be provided under the second substrate 210 .

[0109] The light shielding member 220 is mainly located between the pixel electrodes 191 adjacent to each other in the second direction DR2, and can shield light leakage between the adjacent pixel electrodes 191. The light shielding member 220 can overlap with the pixel circuit portion including the thin film transistor Q.

[0110] On the other hand, the longitudinal portion 133 of the sustain electrode line 131 described above may overlap most of a space between two pixel electrodes 191 adjacent in the first direction DR1 , thereby shielding light leakage between the pixel electrodes 191 adjacent in the first direction DR1 .

[0111] As described above, a lattice-shaped light shielding portion may be formed by the light shielding member 220 and the longitudinal portion 133 of the sustain electrode line 131. The light shielding portion may prevent light leakage between adjacent pixels PX. The display portion of each pixel PX may be a region surrounded by the light shielding portion and capable of displaying light.

[0112] An insulating layer 250 is disposed below the light shielding member 220 , and a common electrode 270 may be disposed below the insulating layer 250 .

[0113] The insulating layer 250 may include an inorganic insulating material and / or an organic insulating material. The insulating layer 250 may prevent the light shielding member 220 from being exposed and may prevent carbon black and other materials included in the light shielding member 220 from flowing into the liquid crystal layer 3 .

[0114] The common electrode 270 may be continuously formed on most of the lower side of the second substrate 210. The common electrode 270 may include a transparent conductive material such as ITO, IZO, or a metal such as aluminum, silver, chromium, or an alloy thereof.

[0115] Different from the above description, the color filter 230 may also be located between the second substrate 210 and the common electrode 270 .

[0116] The liquid crystal layer 3 may include liquid crystal molecules 31 having anisotropic dielectric constants. The liquid crystal molecules 31 may be aligned such that their major axes are perpendicular or at an acute angle to the surfaces of the first and second substrates 110 and 210 in the absence of an electric field in the liquid crystal layer 3 .

[0117] An alignment film 11 may be disposed on the pixel electrode 191 and the second insulating layer 180b, and an alignment film 21 may be disposed under the common electrode 270. The two alignment films 11 and 21 may be vertical alignment films.

[0118] As described above Figures 1 to 3 Refer to Figures 4 to 20 , describing a method for manufacturing a display device according to an embodiment of the present invention.

[0119] Figure 4 is a plan view of a display device in one process of a method for manufacturing a display device according to an embodiment of the present invention, Figure 5 It means that the Figure 4 A cross-sectional view of the display device shown, Figure 6 It means that the line VIa-VIb is intercepted. Figure 4 A cross-sectional view of the display device shown.

[0120] Reference Figures 4 to 6 A conductive material such as metal is stacked and patterned on the insulating first substrate 110 by sputtering or the like, thereby forming a gate conductive layer including gate lines 121 and sustain electrode lines 131. The patterning method may utilize a photolithography process (photolithography) of etching the conductive layer using a photolithography mask or the like.

[0121] then, Figure 7 yes Figure 4 A plan view of a display device in a subsequent process of the display device shown in FIG. Figure 8 It means that the VIIIa-VIIIb line was taken. Figure 7 A cross-sectional view of the display device shown, Fig. 9 It is taken along line IXa-IXb. Figure 7 A cross-sectional view of the display device shown.

[0122] Reference Figures 7 to 9 A silicon nitride (SiN) layer is formed on the first substrate 110 having the gate conductive layer. x ), silicon oxide (SiO x ), silicon oxynitride and other insulating materials to form the gate insulating layer 140.

[0123] Then, a semiconductor material such as amorphous silicon, polycrystalline silicon, or metal oxide is stacked on the gate insulating layer 140 to form a semiconductor layer 150. Then, the semiconductor layer 150 is patterned to form a plurality of openings 150a, 150b, and 150c. The patterning method may utilize a photolithography process of etching the semiconductor layer 150 using a photolithography mask, etc. This process is referred to as the first etching of the semiconductor layer 150.

[0124] The opening 150a corresponds to the data line 171 described above and may extend substantially in the second direction DR2 along a region where the data line 171 is to be formed, and may have a width W1 in the first direction DR1 greater than a width of the data line 171 in the first direction DR1.

[0125] As shown in the figure, the opening 150a may not overlap the gate line 121. However, differently from this, the opening 150a may also cross the gate line 121 and extend long in the second direction DR2.

[0126] The opening 150b may be provided corresponding to the pixel circuit portion, and may be located between two adjacent openings 150a in the second direction DR2 in a plan view. The opening 150b may be away from the opening 150a. Alternatively, when the opening 150a extends to cross the gate line 121, the opening 150b may be connected to the opening 150a as a whole.

[0127] The width W2 of the opening 150b in the first direction DR1 may be greater than the width W1 of the opening 150a in the first direction DR1, but is not limited thereto. According to other embodiments, the width W2 of the opening 150b in the first direction DR1 may also be the same as the width W1 of the opening 150a in the first direction DR1.

[0128] The opening 150c may be disposed between two adjacent openings 150a in the first direction DR1. The opening 150c may be away from the adjacent opening 150a or may be connected thereto as a whole. The opening 150c may be disposed corresponding to the expansion portion 177 of the drain electrode 175 to be formed later.

[0129] The patterned semiconductor layer 150 may further include an opening 150d protruding from a lower side of the opening 150c. The opening 150d may be provided corresponding to a portion of a rod-shaped portion of a drain electrode 175 to be formed later.

[0130] then, Fig.10 yes Figure 7 A plan view of a display device in a subsequent process of the display device shown in FIG. Fig.11 It means that the Fig.10 A cross-sectional view of the display device shown, Fig.12 It is taken along line XIIa-XIIb. Fig.10 A cross-sectional view of the display device shown.

[0131] Reference Figures 10 to 12 , n-type impurities are applied to the upper part of the semiconductor layer 150 to form an ohmic contact layer 164, and a conductive material such as a metal is stacked thereon by a method such as sputtering and patterned to form a data conductive layer including a data line 171 and an electrode 174. The patterning method may utilize a photolithography process using a photolithography mask to perform etching, etc.

[0132] The photolithography process of the data conductive layer is described in more detail, that is, a photosensitive material such as a photoresist is stacked on the stacked conductive material layer, and the photosensitive material layer is exposed using a half-tone photomask. Thus, a mask pattern 50 having a thickness that varies with position can be formed. The mask pattern 50 may include a first portion 51 and a second portion 52 that is thinner than the first portion 51. The second portion 52 may be formed corresponding to the channel of the thin film transistor Q described above.

[0133] The mask pattern 50 is used as a mask to etch the stacked conductive material layers. Figures 10 to 12 As shown in FIG. 1 , a data conductive layer including a data line 171 and an electrode 174 is formed. The electrode 174 may include the source electrode 173 and the drain electrode 175 described above, and a portion corresponding to a channel between the source electrode 173 and the drain electrode 175 .

[0134] The interval D1 between the edge of the data line 171 and the edge of the opening 150a of the semiconductor layer 150 may be greater than 0, for example, may be approximately greater than 1.5 microns and approximately less than 2.5 microns. Similarly, the interval between the edge of the extension 177 included in the drain electrode 175 and the edge of the opening 150c of the semiconductor layer 150 may also be greater than 0, for example, may be approximately greater than 1.5 microns and approximately less than 2.5 microns.

[0135] then, Fig.13 yes Fig.11A cross-sectional view of a display device in a subsequent process of the display device shown, Fig.14 yes Fig.12 A cross-sectional view of a display device in a subsequent process of the display device shown, Fig.15 yes Fig.10 A plan view of a display device in a subsequent process of the display device shown in FIG. Fig.16 It means that the XVIa-XVIb line is intercepted. Fig.15 A cross-sectional view of the display device shown, Fig.17 It means that the XVIIa-XVIIb line was taken. Fig.15 A cross-sectional view of the display device shown.

[0136] Reference Fig.13 and Fig.14 The mask pattern 50 is etched back to remove the second portion 52 and form a first portion 51 a with a reduced thickness.

[0137] Next, refer to Figures 15 to 17 , the semiconductor layer 150 is etched for the second time using the first portion 51a of the mask pattern 50 as a mask. Thus, the semiconductor layer 150 not covered by the first portion 51a of the mask pattern 50 located on the data conductive layer is removed, and only the semiconductor layer 150 slightly larger than the data conductive layer may remain. Thus, a semiconductor layer including the semiconductor 154, the semiconductor 155, and the protrusion 154a may be formed.

[0138] In the above description Figure 7 In the embodiment, the size and shape of the protrusion 154a may be different according to the size and shape of the opening 150b of the semiconductor layer 150. For example, if the right edge of the opening 150b is close to the edge of the electrode 174, the protrusion 154a may not be formed. As in the present embodiment, if the right edge of the opening 150b is sufficiently far away from the edge of the electrode 174, the protrusion 154a may be formed. Fig.15 Protrusion 154a is shown.

[0139] Alternatively, the semiconductor layer 150 may be etched using the mask pattern 50 before the second portion 52 is removed as a mask, thereby forming a semiconductor layer including the semiconductor 154 , the semiconductor 155 , and the protruding portion 154 a .

[0140] then, Fig.18 yes Fig.15 A plan view of a display device in a subsequent process of the display device shown in FIG. Fig.19 It means that the XIXa-XIXb line was intercepted. Fig.18 A cross-sectional view of the display device shown, Fig. 20 It means that the Fig.18 A cross-sectional view of the display device shown.

[0141] Reference Figures 18 to 20 , using the first portion 51 a of the mask pattern 50 as a mask, the electrode 174 of the data conductive layer is etched to form a source electrode 173 and a drain electrode 175 that are away from each other and face each other, wherein the channel of the thin film transistor Q is sandwiched between the source electrode 173 and the drain electrode 175. Then, the exposed ohmic contact layer 164 is etched to form ohmic contact layers 163 and 165 located between the semiconductor 154 and the source electrode 173 and the drain electrode 175.

[0142] Thus, the above-described Figures 1 to 3 As described above, the semiconductor 154 can be patterned using the same mask pattern 50 or the first portion 51a of the mask pattern 50 used in patterning the source electrode 173 and the drain electrode 175. Thus, the semiconductor 154 formed with a channel and the source electrode 173 and the drain electrode 175 do not exist in different island shapes, but the semiconductor 154 can have an edge position that is substantially parallel to the outer edge position of the data conductive layer including the source electrode 173 and is located outside the outer edge position of the source electrode 173. That is, the semiconductor 154 has a structure that is aligned (self-aligned) with the edge position of the data conductive layer including the source electrode 173. Thus, the alignment margin between the semiconductor 154 and the source electrode 173 and the drain electrode 175 (or the electrode 174) can be ignored, so the size of the thin film transistor Q can be reduced.

[0143] According to the prior art, when the semiconductor 154 and the data conductive layer are etched together using one mask pattern, the semiconductor layer will also remain under the data line 171 included in the data conductive layer. However, according to an embodiment of the present invention, the semiconductor layer is first etched to remove the semiconductor layer under the data line 171 and the extended portion 177 of the drain electrode 175, and the semiconductor layer is secondly etched using a mask pattern for patterning the electrode 174 or the source electrode 173 and the drain electrode 175. Therefore, it can be formed so that only the semiconductor 154 with a channel is aligned with the electrode 174 or the source electrode 173 and the drain electrode 175 (self-aligned). Therefore, while achieving the effect of reducing the alignment margin between the semiconductor 154 and the source electrode 173 and the drain electrode 175 (or the electrode 174) and reducing the size of the thin film transistor Q, the influence of light and poor display caused by the semiconductor layer under the data line 171 can be prevented.

[0144] The following is similar to the above description. Figure 1 Reference Fig.21 and Fig. 22 , describing a method for manufacturing a display device according to an embodiment of the present invention and a display device formed by the manufacturing method.

[0145] Fig.21 is a plan view of a display device in one process of a method for manufacturing a display device according to an embodiment of the present invention, Fig. 22 It is a planar configuration diagram of one pixel of a display device according to an embodiment of the present invention.

[0146] Reference Fig.21 , the above mentioned Figure 7 The semiconductor layer 150 is formed by forming an opening 150d. Fig. 22 As shown in the figure, it may have a protrusion 154b protruding from the upper side of the semiconductor 154. The protrusion 154b may overlap with at least a portion of the rod-shaped portion of the drain electrode 175 that does not overlap with the semiconductor 154. The protrusion 154b may have an edge position that is parallel to and outside the edge position of at least a portion of the rod-shaped portion of the drain electrode 175 that does not overlap with the semiconductor 154.

[0147] The protrusion 154b may overlap with a portion where the rod-shaped portion of the drain electrode 175 and the gate line 121 intersect each other. The portion where the rod-shaped portion of the drain electrode 175 intersects with the edge of the gate line 121 may cause a short circuit defect between the drain electrode 175 and the gate line 121 due to a height difference with the gate line 121. However, according to the present embodiment, since the protrusion 154b is located at the intersection region of the gate line 121 and the rod-shaped portion of the drain electrode 175, a short circuit defect between the drain electrode 175 and the gate line 121 can be prevented.

[0148] In this embodiment, the Figures 7 to 9 The shape or size of the opening 150b of the semiconductor layer 150 formed in the process shown in the figure may be different. Figure 7 Compared with the width W2 of the opening 150b in the first direction DR1, Fig.21 In the illustrated embodiment, the width W3 of the opening 150 b in the first direction DR1 may be smaller.

[0149] The semiconductor layer of the display device thus formed is as follows Fig. 22 As shown, it can have a length greater than that described above. Figures 1 to 3 The protrusion 154a of the semiconductor layer 150 shown in FIG. 1 is longer than the protrusion 154c in the first direction DR1. The protrusion 154c may be as shown in FIG. Fig. 22As shown, the protrusion 154c has a shape protruding from one side of the semiconductor 154. The protrusion 154c may have an edge position overlapping with a portion of the straight portion 173a of the source electrode 173 adjacent to the curved portion 173b and aligned with and located outside the edge position of a portion of the straight portion 173a of the source electrode 173 adjacent to the curved portion 173b.

[0150] The protrusion 154c may also overlap with the edge of the opening 24 of the gate line 121 or the edge of the gate electrode 124. That is, the protrusion 154c may overlap with the portion where the straight portion 173a of the source electrode 173 and the edge of the opening 24 or the edge of the gate electrode 124 intersect each other. The portion where the straight portion 173a of the source electrode 173 intersects with the edge of the opening 24 or the edge of the gate electrode 124 may cause a short circuit defect between the source electrode 173 and the gate line 121 due to the height difference with the gate conductive layer. However, according to the present embodiment, since the protrusion 154c is located at the intersection area of ​​the straight portion 173a of the source electrode 173 and the edge of the opening 24 or the edge of the gate electrode 124, the short circuit defect between the source electrode 173 and the gate line 121 can be prevented.

[0151] The following is similar to the above description. Figure 1 Reference Fig.23 The structure around the data line of a display device according to an embodiment of the present invention will be described.

[0152] Fig.23 FIG. 1 is a cross-sectional view of a display device and its surroundings according to an embodiment of the present invention.

[0153] Reference Fig.23 In the display device formed by the method for manufacturing a display device according to an embodiment of the present invention as described above, the thickness of the lower portion of the data line 171 and the peripheral gate insulating layer 140 may vary depending on the position.

[0154] exist Fig.23 In the figure, the area overlapping with the data line 171 is called area D, the area located on the outside of area D and overlapping with the mask pattern 50 or the first part 51a described above is called area C, the area located on the outside of area C and not overlapping with the mask pattern 50 or the first part 51a is called area B, and the remaining area located on the outside of area B is called area A.

[0155] Fig.23 The B region, C region and D region shown are included in the above-described Figures 7 to 9The opening 150a is formed by first etching the semiconductor layer 150 in the manufacturing process shown. In the step of forming the opening 150a, when the semiconductor layer 150 corresponding to the B region, the C region, and the D region is first etched, a portion of the gate insulating layer 140 may be etched. Therefore, the thickness of the gate insulating layer 140 in the B region, the C region, and the D region may be thinner than the thickness of the gate insulating layer 140 in the A region.

[0156] exist Fig.23 In the B and C regions shown, a portion of the gate insulating layer 140 around the data line 171 may be etched during the process of forming the data conductive layer including the data line 171 and the electrode 174. At this time, the gate insulating layer 140 in the A region may not be etched due to the presence of the semiconductor layer 150.

[0157] Fig.23 The A area and the B area shown correspond to the Figures 15 to 17 In the manufacturing process shown in FIG. 1 , the semiconductor layer 150 is etched for the second time using the mask pattern 50 or the first portion 51a of the etched mask pattern 50 as a mask. Therefore, a portion of the gate insulating layer 140 corresponding to the A region and the B region can be etched. Therefore, the thickness of the A region and the B region of the gate insulating layer 140 can be further reduced. In addition, in the above description Figures 18 to 20 In the manufacturing process shown, in the process of etching the ohmic contact layer 164 using the first portion 51 a of the mask pattern 50 as a mask, a portion of the gate insulating layer 140 corresponding to the A region and the B region may be further etched.

[0158] Thus, in a plan view, the thickness H1 of the gate insulating layer 140 corresponding to the B region slightly away from the data line 171 may be smaller than the thicknesses H3, H2, and H4 of the gate insulating layer 140 corresponding to the A region, the C region, and the D region. The thickness H3 of the gate insulating layer 140 corresponding to the A region may be greater than, less than, or equal to the thickness H2 of the gate insulating layer 140 corresponding to the C region. The thickness H4 of the gate insulating layer 140 corresponding to the D region may be slightly greater than or equal to the thickness H2 of the gate insulating layer 140 corresponding to the C region.

[0159] Below, refer to Fig.24 A display device according to an embodiment of the present invention will be described.

[0160] Fig.24 It is a plan view of a display device according to an embodiment of the present invention.

[0161] Reference Fig.24A display device 1000 according to an embodiment of the present invention includes a display panel 300, which includes a display area DA and a peripheral area PA located outside the display area DA. The display panel 300 includes the first substrate 110 of the display device described above.

[0162] The display area DA is a region where an image based on an input image signal may be displayed, and includes a plurality of pixels PX, a plurality of gate lines 121 , and a plurality of data lines 171 .

[0163] The pixel PX is a basic unit for displaying an image, and each pixel PX may include at least one transistor and a pixel electrode electrically connected to the transistor as described above. A plurality of pixels PX may be regularly arranged in rows and columns, for example.

[0164] In order to display various colors, each pixel PX can display one of the primary colors, so that an image of a desired color can be recognized by the spatial and temporal sum of these primary colors. The primary colors may include, for example, three primary colors, namely red, green, and blue, and may further include white.

[0165] The gate lines 121 may transmit gate signals including a gate-on voltage and a gate-off voltage. A plurality of gate lines 121 may be sequentially arranged substantially side by side in the second direction DR2, and each gate line 121 may be substantially long extended in the first direction DR1.

[0166] The data line 171 may transfer a data voltage corresponding to an input image signal. A plurality of data lines 171 may be arranged substantially in a direction parallel to the first direction DR1, and each data line 171 may extend substantially in a long direction in the second direction DR2.

[0167] Reference Fig.24 , transistors (such as the thin film transistors Q described above) included in a plurality of pixels PX located in a pixel column extending in the second direction DR2 may be alternately connected to the two data lines 171. For example, the transistors of the plurality of pixels PX in each pixel column may be alternately electrically connected to the two data lines 171 in units of one pixel row (or cycle). According to other embodiments, the transistors of the plurality of pixels PX in each pixel column may also be alternately connected to the two data lines 171 in units of two or more pixel rows (or cycles).

[0168] According to other embodiments, a plurality of pixels PX in one pixel column may also be electrically connected to the same data line 171 .

[0169] The peripheral area PA may be a region where most of the image is not displayed, and may be a region adjacent to the periphery of the display area DA. For example, the peripheral area PA may surround the display area DA.

[0170] The peripheral area PA may include a gate driver (400a, 400b).

[0171] The gate driving unit ( 400 a , 400 b ) may be electrically connected to the plurality of gate lines 121 to apply a gate signal. Figure 1 The example in which the first gate driving unit 400a is provided in the peripheral area PA located on the left side of the display area DA and the second gate driving unit 400b is provided in the peripheral area PA located on the right side is shown. The gate driving unit (400a, 400b) generates a gate signal including a gate-on voltage and a gate-off voltage, and can sequentially apply the gate signal to the plurality of gate lines 121 along a direction parallel to the second direction DR2.

[0172] The gate driving unit (400a, 400b) may include a transistor that can be directly formed in the peripheral area PA in the same process as the thin film transistor Q in the display area DA, and a wiring or electrode located at the same layer as the data line 171. Therefore, the at least one transistor included in the gate driving unit (400a, 400b) and the wiring or electrode connected thereto and located at the same layer as the data line 171 may also have the same structure as described above. Figures 1 to 3 The thin film transistor Q shown has the same structure and features as the data line 171 .

[0173] One of the first gate driving part 400 a and the second gate driving part 400 b may be omitted.

[0174] The display device 1000 according to an embodiment of the present invention may further include a data driver 500 and a signal controller 600 .

[0175] The data driving part 500 is electrically connected to the plurality of data lines 171. The data driving part 500 may selectively apply data voltages as grayscale voltages corresponding to input image signals to corresponding data lines 171 according to the control of the signal control part 600.

[0176] The signal control unit 600 may output control signals GCS and DCS to the gate driving unit ( 400 a , 400 b ) and the data driving unit 500 to control the gate driving unit ( 400 a , 400 b ) and the data driving unit 500 .

[0177] The data driving part 500 and / or the signal control part 600 may be mounted in the peripheral area PA of the display panel 300 in the form of a plurality of driving chips or mounted on a flexible printed circuit film or printed circuit substrate electrically connected to the display panel 300 .

[0178] As described above Figure 1 Refer to Fig.24 In the case where the thin film transistors Q included in a plurality of pixels PX located in a pixel column are alternately electrically connected to two data lines 171, if the semiconductor 154 is formed not to be aligned with the edge position of the data conductive layer including the source electrode 173 but is formed by a separate mask pattern, an alignment error of the semiconductor 154 relative to the data conductive layer including the source electrode 173 may occur. In the case where such an alignment error occurs, differences may occur in characteristics such as a kick-back voltage between the thin film transistor Q connected to the data line 171 located on the left side with respect to a pixel column as a reference and the thin film transistor Q connected to the data line 171 located on the right side. The kick-back voltage may represent a voltage change at the output terminal of the thin film transistor Q caused by a change in a gate signal applied to the gate terminal of the thin film transistor Q. As a result, display defects such as horizontal stripes may occur. However, according to the present embodiment, since the semiconductor 154 has a structure that is aligned (self-aligned) with the edge position of the data conductive layer including the source electrode 173, even in the case of Fig.24 In the connection structure between the pixel PX and the data line 171 shown, it is also possible to prevent the dispersion of characteristics such as the kick-back voltage.

[0179] The embodiments of the present invention are described in detail above, but the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts of the present invention defined in the claims also fall within the scope of the present invention.

Claims

1. A display device, comprising: substrate; A gate insulating layer, located on the substrate; A semiconductor layer, located on the gate insulating layer and comprising a first semiconductor; A source electrode and a drain electrode, located on the first semiconductor; as well as A data line is located on the gate insulating layer, The gate insulating layer includes a first portion overlapping the data line, a second portion located around the first portion, and a third portion located outside the second portion. The thickness of the second portion is greater than 0 and thinner than the thickness of the first portion, The thickness of the third portion is greater than the thickness of the second portion.

2. The display device according to claim 1, wherein: The first semiconductor has an edge position that is aligned with and outside the edge position of the source electrode.

3. The display device according to claim 2, wherein: Only the gate insulating layer is disposed between the data line and the substrate, and the semiconductor layer is not disposed.

4. The display device according to claim 3, further comprising: a gate line, located on the substrate and crossing the data line, The semiconductor layer further includes a second semiconductor located in a region where the gate line crosses the data line.

5. The display device according to claim 3, wherein: The source electrode includes: a straight portion extending in a direction different from the direction in which the data line extends; and a curved portion connected to the straight portion. The semiconductor layer further includes a first protrusion having a shape protruding from one side of the first semiconductor, The first protrusion overlaps a portion of the straight portion of the source electrode that is adjacent to the bent portion.

6. The display device according to claim 5, wherein: The first protrusion has an edge position aligned with an edge position of a portion of the straight portion of the source electrode adjacent to the bent portion.

7. The display device according to claim 6, further comprising: a gate line, located on the substrate and crossing the data line, The gate line includes a gate electrode, The first protrusion overlaps with an edge position of the gate electrode.

8. The display device according to claim 6, further comprising: a gate line, located on the substrate and crossing the data line, The semiconductor layer further includes a second protrusion having a shape protruding from the other side of the first semiconductor, The second protrusion overlaps with an edge position of the gate line.

9. The display device according to claim 8, wherein: The second protrusion includes an edge position aligned with an edge position of at least a portion of the drain electrode that does not overlap with the first semiconductor.

10. The display device according to claim 8, further comprising: A sustain electrode is located between the substrate and the gate insulating layer, The drain electrode includes an extension portion overlapping the sustain electrode, The semiconductor layer is not located between the extension portion and the substrate.

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