Display device

Abstract

A display device is disclosed, comprising: a display panel including pixels defined by intersections between gate lines and data lines formed in a pixel area; a data driver, which sequentially outputs data signals in each sub-horizontal period in a horizontal period and outputs a selection signal including a transistor conduction period corresponding to the sub-horizontal period; and a distributor, which includes a transistor connected to each of the data lines and is switched according to the selection signal to output the data signal sequentially output from each source channel to the connected data line, wherein the transistor conduction period in the selection signal is different from the sub-horizontal period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0176125, filed on December 27, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that can reduce EMI noise of a data driver while maintaining a current voltage level. Background Art

[0004] The display device is used to display a screen in various types of devices other than a television or a monitor, such as a notebook computer, a tablet computer, a smart phone, a portable display device, and a portable information device.

[0005] As processing technology and driving circuit technology of display devices have developed, pixels per inch (PPI) have been increasing, and thus high-resolution display devices have been realized.

[0006] The display device includes a display panel, a data driver integrated circuit (D-IC) and a gate driver integrated circuit (G-IC) for driving the display panel, and a timing controller (T-con) for controlling the IC. The T-con can be arranged outside the IC, but can also be arranged inside the IC.

[0007] The display panel is defined by a plurality of data lines and a plurality of gate lines, and includes pixels having thin film transistors. The D-IC sequentially supplies data voltages to the data lines, and the G-IC supplies scan signals to the gate lines.

[0008] A source channel of the D-IC outputting a data voltage may be connected to a data line through a connection line, and one source channel may be connected to a plurality of data lines to reduce the number of source channels of the D-IC.

[0009] To this end, a distributor is provided between the source channel and the data line, the distributor including a transistor connected to each data line, operating according to a selection signal MUX_S from the D-IC. If the transistor is turned on by the selection signal MUX_S, the data voltage output from the source channel is supplied to the data line connected to the turned-on transistor.

[0010] In the display device of the related art, since the selection signal MUX_S is output based on the scanning signal with a fixed period, the selection signal MUX_S has no choice but to be output in one horizontal period 1H of the scanning signal with a fixed period of 1H. Similarly, the data signal Source has no choice but to be output with a fixed period of 1H.

[0011] at the same time, Figure 1 is a view showing an example of converting a square wave having a periodicity T into a frequency spectrum.

[0012] like Figure 1 As shown, if a square wave with a certain periodicity T is converted into a spectrum, then as the fundamental frequency ω o The low frequency band has a peak component, and the high frequency component 3ω o , 5ω o 7ω o ,…’s amplitude gradually decreases.

[0013] The torque ripple generated at the low frequency band of the square wave acts as an EMI noise element, and if the line to which the square wave signal is applied increases within a certain range and the square wave level increases, the EMI noise increases in proportion.

[0014] As described above, since the selection signal MUX_S and the data signal Source are square waves with periodicity, EMI noise problems may occur even in D-ICs. In addition, since the number of transistors provided in the distributor has recently increased to reduce the number of source channels of the D-IC, a solution to the EMI noise problem has been released to stably drive the transistors.

[0015] In order to solve the EMI noise problem, the level of the selection signal MUX_S needs to be lowered, but a minimum voltage swing of 20V is required to drive the transistor, and thus there is a limitation in solving the EMI noise problem by lowering the level of the selection signal MUX_S.

[0016] The disclosed content of the above-mentioned background technology is owned by the inventor of the present disclosure in designing the content of this specification, or is technical information obtained through the process of designing this specification, but it cannot be regarded as known technology disclosed to the general public before providing this specification. Summary of the invention

[0017] The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a display device which can reduce EMI noise of a data driver while maintaining the level of a selection signal at a current voltage.

[0018] In addition to the objects of the present disclosure as described above, additional objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0019] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a display device, which includes: a display panel including pixels formed in a pixel area and defined by intersections between gate lines and data lines; a data driver, which sequentially outputs data signals in each sub-horizontal period in a horizontal period, and outputs a selection signal including a transistor conduction period corresponding to the sub-horizontal period; and a distributor, which includes a transistor connected to each data line and switches according to the selection signal to output the data signal sequentially output from each source channel to the connected data line, wherein the transistor conduction period in the selection signal is different from the sub-horizontal period.

[0020] In addition to the aspects described above, details of various embodiments according to the present disclosure are included in the following description and drawings.

[0021] According to the present disclosure, a selection signal having changed the phase of a reference selection signal having a transistor turn-on period synchronized with a sub horizontal period is supplied to a distributor including transistors for performing supply and supply cutoff of a data signal between a data driver and a data line.

[0022] Therefore, since the transistor turn-on period of the selection signal is not synchronized with the sub horizontal period and the selection signal does not have a square wave with a constant period, the selection signal can be maintained at a current voltage level and the EMI noise problem can be solved at the same time.

[0023] In addition to the effects of the present disclosure as described above, additional advantages and features of the present disclosure will be clearly understood by those skilled in the art from the above description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0025] Figure 1 is a view showing an example of converting a square wave having a period T into a frequency spectrum;

[0026] Figure 2 is a view showing an example of a display device according to an embodiment of the present disclosure;

[0027] Figure 3 It is shown that the Figure 2 The equivalent circuit diagram of the LCD pixel structure of each pixel;

[0028] Figure 4It is shown that the Figure 3 The equivalent circuit diagram of the LCD pixel structure of each pixel;

[0029] Figure 5 is a timing diagram of a scan signal, first to third selection signals, and a data signal in a display device according to an embodiment of the present disclosure;

[0030] Figure 6 is a view showing elements of any one source channel of a source output circuit according to an embodiment of the present disclosure;

[0031] Figure 7 is a view showing elements of a multiplexer of a distributor according to an embodiment of the present disclosure;

[0032] Figure 8 is a view showing elements of a timing controller of a display device according to an embodiment of the present disclosure;

[0033] Fig. 9 It is shown Figure 8 A view of the output waveform of each element of the timing controller;

[0034] Fig. 10A is a graph showing a measurement result of EMI noise generated during operation of a data driver in a case where an output period of a selection signal is fixed as in the related art; and

[0035] Fig. 10B is a graph showing a measurement result of EMI noise generated during the operation of a data driver in a case where an output period of a selection signal is changed as in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The advantages and features of the present disclosure and its implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and these embodiments will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0037] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore the present disclosure is not limited to the details shown. Throughout the text, similar reference numerals refer to similar elements. In the following description, when it is determined that the detailed description of the relevant known functions or structures does not necessarily make the main points of the present disclosure difficult to understand, the detailed description will be omitted.

[0038] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may also be present unless “only” is used. Terms in the singular form may include plural forms unless noted otherwise.

[0039] When constructing an element, although there is no explicit description, the element is constructed to include an error range.

[0040] In describing a positional relationship, for example, when the positional order is described as “on,” “above,” “below,” and “beside,” unless “only” or “between” is used, a case where there is no contact therebetween may be included.

[0041] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to easily describe the relationship of one or more elements to another or more elements as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientations depicted in the accompanying drawings. For example, if the device shown in the figure is inverted, a device described as being arranged "below" or "below" another device may be arranged "above" the other device. Thus, the exemplary term "below or below" may include both "below or below" and "above" orientations. Similarly, the exemplary term "above" or "upper" may include both "above" and "below or below" orientations.

[0042] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0043] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0044] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first, second, and third elements and each element of the first, second, and third elements.

[0045] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be coupled or combined with each other in part or in whole, and can interoperate and be driven technically differently from each other. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0046] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are shown in different drawings.

[0047] Hereinafter, a display device according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 2 is a view showing an example of a display device according to an embodiment of the present disclosure.

[0049] The display device of the present disclosure may be a display device that can embody color, such as a liquid crystal display (LCD) device, an organic light emitting display (OLED), an electrophoretic display (EPD), a plasma display panel device (PDP), a field emission display (FED) device, an electroluminescent display (ELD) device, and an electrowetting display (EWD) device.

[0050] like Figure 2 As shown, the display device according to an embodiment of the present disclosure may include but is not limited to a display panel 100, a gate driver 200, a timing controller 300, a source output circuit 400, a selection signal output circuit 500, and a distributor 600. The timing controller 300, the source output circuit 400, and the selection signal output circuit 500 may be embodied as an integrated circuit constituting a data driver D-IC.

[0051] For description, in the present disclosure, one source channel S of the source output circuit 400 may be connected to three data lines through one multiplexer 610 of the distributor 600, thereby providing n / 3 number of source channels S1 to S(n / 3) (n is the total number of data lines) in the source output circuit 400. However, one multiplexer 610 may be connected to two data lines or four or more data lines.

[0052] The display panel 100 is provided with gate lines GL1 to GLm, data lines DL1 to DLn, and pixels P formed per pixel area defined by intersections between the gate lines GL1 to GLm and the data lines DL1 to DLn. Figure 2 It is shown that the pixel P is formed in the display area 110 of the display panel 100, and the selection signal output circuit 500 and the distributor 600 are provided outside the display panel 100, but all or some of the selection signal output circuit 500 and the distributor 600 and all or some of the elements of the selection signal output circuit 500 may be provided in a non-display area of ​​the panel 100.

[0053] Figure 3 It is shown that the Figure 2 The equivalent circuit diagram of the LCD pixel structure of each pixel, and Figure 4It is shown that the Figure 3 Equivalent circuit diagram of the LCD pixel structure of each pixel.

[0054] Each pixel P is independently driven by a TFT. As the TFT, an amorphous silicon (A-Si) TFT, a polysilicon TFT, an oxide TFT, or an organic TFT may be used.

[0055] For example, if the display panel 100 is an LCD panel, Figure 3 As shown, each pixel P includes a TFT connected to the gate line GL and the data line DL, and a liquid crystal capacitor Clc and a storage capacitor Cst connected in parallel between the TFT and the common electrode.

[0056] The liquid crystal capacitor Clc charges a differential voltage between a data signal supplied to a pixel electrode through a TFT and a common voltage Vcom supplied to a common electrode, and controls light transmittance by driving liquid crystal according to the charged voltage. The storage capacitor Cst stably maintains a voltage charged in the liquid crystal capacitor Clc.

[0057] Different from the above case, if the display panel 100 is an OLED panel, Figure 4 As shown, each pixel P may be provided with a pixel circuit including an OLED connected between a high potential power line EVDD and a low potential power line EVSS, first and second switching TFTs ST1 and ST2, a driving TFT DT, and a storage capacitor Cst that independently drives the OLED.

[0058] The OLED includes an anode connected to the driving TFT DT, a cathode connected to a low potential voltage EVSS, and a light emitting layer between the anode and the cathode, and generates light in proportion to the amount of current supplied from the driving TFT DT.

[0059] The first switch TFT ST1 is driven by a gate signal of one gate line GLa to supply a data voltage from a corresponding data line to a gate node of the driving TFT DT, and the second switch TFT ST2 is driven by a gate signal of another gate line GLb to supply a reference voltage from a reference line RL to a source node of the driving TFT DT. The second switch TFT ST2 also serves as a path for outputting a current from the driving TFT DT to the reference line RL in a sensing mode.

[0060] The storage capacitor Cst connected between the gate electrode and the source electrode of the driving TFT DT charges a differential voltage between a data voltage supplied to the gate electrode of the driving TFT DT through the first switching TFT ST1 and a reference voltage supplied to the source electrode of the driving TFT DT through the second switching TFT ST2, and supplies the charged voltage as a driving voltage of the driving TFT DT during a period in which the first switching TFT ST1 and the second switching TFT ST2 are turned off.

[0061] The driving TFT DT controls current supplied from the high potential power EVDD according to the driving voltage supplied from the storage capacitor Cst to supply current proportional to the driving voltage to the OLED, thereby causing the OLED to emit light.

[0062] The gate driver 200 sequentially turns on the gate turn-on signal S G_ON The scan signal is output to each of the m number of gate lines GL1 to GLm.

[0063] In this case, the gate turn-on signal S G_ON represents a voltage that can turn on the switching TFTs connected to the gate lines GL1 to GLm, and maintains the gate turn-on signal S G_ON The period is called a horizontal period 1H.

[0064] The voltage that can turn off the switching TFT is called the gate cutoff signal S G_OFF , and the gate turn-on signal S G_ON and gate cutoff signal S G_OFF Collectively referred to as scanning signals.

[0065] If the switch thin film transistor is N-type, the gate conduction signal S G_ON is a high level voltage, and the gate cutoff signal S G_OFF If the switch thin film transistor is a P-type, the gate conduction signal S G_ON is a low level voltage, and the gate cutoff signal S G_OFF is a high level voltage.

[0066] The data driver D_IC receives image data and a timing signal synchronized with the image data from the host system 1, for example, converts the received image data into a data voltage, outputs a data voltage in each sub-horizontal period through an output channel by dividing a horizontal period 1H into a plurality of sub-horizontal periods, and outputs a selection signal MUX_s to a distributor including a transistor connected to each data line.

[0067] The host system 1 is an electronic device embedded with a display device to output images through the display device. For example, the host system 1 can be a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer, a home theater system, a telephone system, etc.

[0068] In this embodiment, the data driver D_IC may include a timing controller 300 , a source output circuit 400 , and a selection signal output circuit 500 , but is not limited thereto.

[0069] In this embodiment, although the data driver D_IC includes the timing controller 300 and the selection signal output circuit 500 , at least one of the timing controller 300 and the selection signal output circuit 500 may be implemented separately from the data driver D_IC, and the data driver D_IC may be implemented only by the source output circuit 400 .

[0070] As described above, the following description will be made based on that one source channel S constituting the source output circuit 400 is connected to three data lines through one multiplexer 610 of the distributor 600 and thus n / 3 number of source channels S1 to S(n / 3) (n is the total number of data lines) are provided in the source output circuit 400.

[0071] The timing controller 300 outputs a gate control signal GCS for controlling the operation timing of the gate driver 200 and a data control signal DCS for controlling the operation timing of the source output circuit 400 through various timing signals (e.g., vertical synchronization signal, horizontal synchronization signal, clock signal, etc.) supplied from the host system 1.

[0072] The timing controller 300 samples image data input from the host system 1 and then realigns the sampled image data, supplies a data voltage to the source output circuit 400, and outputs a selection signal MUX_s for controlling an operation timing of a distributor 600 including transistors connected to each data line.

[0073] At this time, the timing controller 300 changes the phase of the reference selection signal MUX_ref to generate a phase-shifted selection signal MUX_s and outputs the generated signal. That is, the selection signal MUX_s is a signal phase-shifted from the reference selection signal MUX_ref.

[0074] According to the setting, the timing controller 300 may phase-shift the reference selection signal MUX_s per data line with respect to one frame image, and may phase-shift the reference selection signal MUX_s per frame.

[0075] The timing controller 300 may positively phase-shift the reference selection signal MUX_ref by FPS, and negatively phase-shift (delay) the reference selection signal MUX_ref.

[0076] The selection signal MUX_s may be phase-changed to shift to the transistor-on voltage level before a time period in the reference selection signal MUX_ref to shift to the transistor-on voltage level, and may be phase-changed to shift to the transistor-on voltage level after a time period in the reference selection signal MUX_ref to shift to the transistor-on voltage level.

[0077] The selection signal MUX_s may be phase-changed to shift to the transistor-off voltage level before a time period in which the reference selection signal MUX_ref shifts to the transistor-off voltage level, and may be phase-changed to shift to the transistor-off voltage level after a time period in which the reference selection signal MUX_ref shifts to the transistor-off voltage level.

[0078] The time period shifted to the transistor-on voltage level ("first shift time period") may be a rising edge, and the time period shifted to the transistor-off voltage level ("second shift time period") may be a falling edge. The period between the first shift time period and the second shift time period is the transistor-on period (transistor-on period Ton), and the period between the second shift time period and the next first shift time period is the transistor-off period (transistor-off period Toff).

[0079] Figure 5 1 is a timing diagram of a scan signal Gate, first to third selection signals MUX_1 , MUX_2 and MUX_3 , and a data signal Source in a display device according to an embodiment of the present disclosure.

[0080] refer to Figure 5 , the first to third selection signals MUX_1, MUX_2 and MUX_3 may be fixed to a period 1H which is the same as a horizontal period 1H of the scanning signal in the prior art, but Figure 5 The first to third selection signals MUX_1 , MUX_2 , and MUX_3 in FIG. 5 may be forward phase-shifted or reverse phase-shifted, and thus have no periodicity.

[0081] That is, in the prior art, the transistor-on period Ton in the first to third selection signals MUX_1, MUX_2, and MUX_3 is the same as the first to third sub-horizontal periods SH1, SH2, and SH3 preset in one horizontal period 1H of the scan signal. However, the transistor-on period Ton in the first to third selection signals MUX_1, MUX_2, and MUX_3 according to an embodiment of the present disclosure may be phase-changed, and thus may not be the same as the first to third sub-horizontal periods SH1, SH2, and SH3 preset in one horizontal period 1H of the scan signal.

[0082] In detail, the selection signal MUX_s may be phase-changed so that a shift time period to the transistor-on voltage level may be before a start time period of the sub horizontal period SH or may be after a start time period of the sub horizontal period SH.

[0083] The selection signal MUX_s may be phase-changed so that a shift time period to the transistor-off voltage level may be before an end time period of the sub horizontal period SH or may be after an end time period of the sub horizontal period SH.

[0084] In the selection signal MUX_s, an interval T between the nth first shift time period and the (n+1)th first shift time period may be longer or shorter than one horizontal period 1H of the scan signal.

[0085] In the selection signal MUX_s, an interval T between the nth first shift time period and the (n+1)th first shift time period may be different from an interval between the (n+1)th first shift time period and the (n+2)th first shift time period.

[0086] A start time period of the transistor on period Ton of each of the first to third selection signals MUX_1 , MUX_2 , and MUX_3 corresponding to the sub horizontal periods SH1 , SH2 , and SH3 in one horizontal period 1H may be different from a start time period of each of the sub horizontal periods SH1 , SH2 , and SH3 .

[0087] For example, the start time period of the transistor turn-on period Ton of the first selection signal MUX_1 corresponding to the first sub-horizontal period SH1 in one horizontal period 1H may be before or after the start time period of the first sub-horizontal period SH1, the start time period of the transistor turn-on period Ton of the second selection signal MUX_2 corresponding to the second sub-horizontal period SH2 in one horizontal period 1H may be before or after the start time period of the second sub-horizontal period SH2, and the start time period of the transistor turn-on period Ton of the third selection signal MUX_3 corresponding to the third sub-horizontal period SH3 in one horizontal period 1H may be before or after the start time period of the third sub-horizontal period SH3.

[0088] Will refer to Figures 8 to 10B A more detailed description of the elements and operation of the timing controller 300 is described.

[0089] The source output circuit 400 converts the image data sent from the timing controller 300 into positive data voltages and negative data voltages corresponding to a predetermined polarity inversion pattern, divides one horizontal period 1H into a plurality of sub-horizontal periods of one horizontal period 1H for supplying a scan signal to the gate line GL, and outputs a data voltage corresponding to one horizontal line.

[0090] To this end, the source output circuit 400 may include a plurality of source channels S1 to S(n / 3) that convert image data into data voltages and output the converted data voltages by using a gamma voltage supplied from a gamma voltage generator (not shown), wherein each source channel S is connected to the multiplexer 610 of the distributor 600.

[0091] Figure 6 is a view showing elements of any one source channel S of the source output circuit 400 according to an embodiment of the present disclosure. Figure 6 The elements can be similarly applied to source channels S1 to S(n / 3).

[0092] refer to Figure 6 , the source channel S of the source output circuit 400 may include a shift register 410, a latch 420, a digital-to-analog converter DAC 430, and an output buffer 440, but is not limited to this embodiment.

[0093] The shift register 410 generates a sampling signal by using the data control signals SSC, SSP, etc. received from the timing controller 300 .

[0094] The latch 420 latches the digital image data Data sequentially received from the timing controller 300 , and simultaneously outputs the digital image data to the digital-to-analog converter DAC 430 .

[0095] The digital-to-analog converter 430 simultaneously converts the image data transmitted from the latch 420 into a positive or negative data voltage and outputs the converted data voltage. That is, the digital-to-analog converter 430 converts the image data into a positive or negative data voltage (data signal) by using the polarity control signal POL transmitted from the timing controller 300 and outputs the converted data voltage.

[0096] The output buffer 440 outputs the positive or negative data voltage transmitted from the digital-to-analog converter 430 to the data line DL according to the source output enable signal SOE transmitted from the timing controller 300 .

[0097] At this time, the output buffer 440 sequentially outputs the first data voltage, the second data voltage, and the third data voltage in the first sub-horizontal period, the second sub-horizontal period, and the third sub-horizontal period of the source output enable signal SOE.

[0098] The selection signal output circuit 500 is an element for receiving the selection signal MUX_s from the timing controller 300 and outputting the received signal to the distributor 600 , and may include a digital-to-analog converter.

[0099] In this embodiment, the selection signal output circuit 500 outputs three selection signals MUX_1 , MUX_2 , and MUX_3 through three output terminals P1 , P2 , and P3 , but is not limited to this embodiment.

[0100] The distributor 600 receives the data voltage from the source output circuit 400, receives the selection signal MUX_s from the selection signal output circuit 500, and switches according to the selection signal MUX_s to sequentially output the data voltage input from one source channel S per sub horizontal period to their corresponding different data lines DL1 to DLd.

[0101] The distributor 600 includes a plurality of multiplexers 610 respectively connected to the source channels S1 to S(n / 3) of the source output circuit 400 , wherein the number of the multiplexers 610 may be set in different ways according to the number of the source channels S of the source output circuit 400 .

[0102] Figure 7 is a view showing elements of a multiplexer 610 of a distributor 600 according to an embodiment of the present disclosure.

[0103] although Figure 7 The multiplexer 610 implemented to connect one source channel S1 with each of three data lines is shown, and one multiplexer 610 may be implemented to connect one source channel S1 with two data lines or four or more data lines.

[0104] although Figure 7 It is shown that the first data line DL1 of the three data lines is connected to the red pixel R, the second data line DL2 is connected to the green pixel G and the third data line DL3 is connected to the blue pixel B. This construction corresponds to the pixel P including a red pixel, a green pixel and a blue pixel, and the pixels connected to each data line are not limited to the case of this embodiment.

[0105] The multiplexer 610 includes a first transistor TR1 connected between the source channel S1 and the first data line DL1 , a second transistor TR2 connected between the source channel S1 and the second data line DL2 , and a third transistor TR3 connected between the source channel S1 and the third data line DL3 .

[0106] The first transistor TR1 is turned on according to the first selection signal MUX_1 from the selection signal output circuit 500 , the second transistor TR2 is turned on according to the second selection signal MUX_2 from the selection signal output circuit 500 , and the third transistor TR3 is turned on according to the third selection signal MUX_3 from the selection signal output circuit 500 .

[0107] The first data voltage output through the first transistor TR1 is a red data voltage, the second data voltage output through the second transistor TR2 is a green data voltage, and the third data voltage output through the third transistor TR3 is a blue data voltage, but the types of the first to third data voltages may be changed according to the colors of the pixels connected to the first to third data lines DL1 to DL3.

[0108] Referenced above Figures 1 to 7 The elements of a display device according to an embodiment of the present disclosure and the operation for each element are described. Figures 8 to 10B The timing controller 300 of the display device according to one embodiment of the present disclosure is described in more detail.

[0109] Figure 8 is a view showing elements of a timing controller 300 of a display device according to an embodiment of the present disclosure, and Fig. 9 It is shown Figure 8 FIG. 1 is a view of the output waveform of each element of the timing controller 300 .

[0110] refer to Figure 8 and Fig. 9 The timing controller 300 may include a basic reference signal output circuit 310, a period reference signal output circuit 320, an inverter 330, a delay selection signal output circuit 340, a first AND gate 350, a second AND gate 360, an OR gate 370 and a phase-locked loop PLL 380, and its elements are not limited to this embodiment.

[0111] The basic reference signal output circuit 310 outputs a reference selection signal MUX_ref and a reference data signal Source_ref, wherein the reference selection signal MUX_ref is output to the delay selection signal output circuit 340 and the first AND gate 350 , and the reference data signal Source_ref is output to the phase-locked loop PLL 380 .

[0112] In addition, the basic reference signal output circuit 310 outputs the data signal Source returned from the phase locked loop PLL 380 to the source output circuit 400 , and the data signal Source is a reference data signal Source_ref phase-synchronized with the selection signal MUX_s output from the OR gate 370 through the phase locked loop 380 .

[0113] The period reference signal output circuit 320 outputs a period reference signal T_ref for determining a use period of the selection signal MUX_s finally output from the timing controller 300 .

[0114] The periodic reference signal T_ref output from the periodic reference signal output circuit 320 may be selected from among a plurality of periodic reference signals T_ref, and the outputted periodic reference signal T_ref may be changed among the plurality of periodic reference signals T_ref.

[0115] Fig. 9 Output waveforms of elements when the waveforms of the reference selection signals MUX_ref are identical to each other and different periodic reference signals T_ref are output are shown.

[0116] As from Fig. 9 As noted in , if the waveforms of the reference selection signals MUX_s are identical to each other, the waveform of the first selection signal MUX_s1 when the first period reference signal T_ref1 is output and the waveform of the second selection signal MUX_s2 when the second period reference signal T_ref2 is output are varied.

[0117] That is, the selection signal MUX_s finally output from the timing controller 300 is changed according to the period reference signal T_ref output from the period reference signal output circuit 320 .

[0118] Therefore, it is necessary to control which one of the plurality of periodic reference signals T_ref is output from the periodic reference signal output circuit 320, and the periodic reference signal T_ref to be output from the periodic reference signal output circuit 320 may be automatically determined according to the internal clock.

[0119] Alternatively, although the basic reference signal output circuit 310 may output a control signal for changing the period reference signal T_ref to the period reference signal output circuit 320 according to a preset reference, the method for selecting the period reference signal is not limited to this embodiment.

[0120] The inverter 330 inverts the period reference selection signal T_ref output from the period reference signal output circuit 320 to output an inverted period reference signal T_ref_B.

[0121] The delayed selection signal output circuit 340 delays the reference selection signal MUX_ref from the base reference signal output circuit 310 to output a delayed reference selection signal D_MUX_ref.

[0122] The first AND gate 350 performs an AND operation by using the reference selection signal MUX_ref output from the base reference signal output circuit 310 and the period reference signal T_ref output from the period reference signal output circuit 320 as inputs.

[0123] The second AND gate 360 ​​performs an AND operation by using the inverted periodic reference signal T_ref_B output from the inverter 330 and the delayed reference selection signal D_MUX_ref output from the delay selection signal output circuit 340 as inputs.

[0124] The OR gate 370 performs an OR operation by using the first output signal OUT1 from the first AND gate 350 and the second output signal OUT2 output from the second AND gate 360 ​​as inputs.

[0125] The signal output by the OR gate 370 is the selection signal MUX_s, which is the final output of the timing controller 300 .

[0126] The selection signal MUX_s output from the OR gate 370 is output to the selection signal output circuit 500 and Figure 8 Phase-locked loop 380.

[0127] The phase locked loop 380 receives the reference data signal Source_ref output from the basic reference signal output circuit 310 and the selection signal MUX_s output from the OR gate 370 , synchronizes the reference data signal Source_ref with the selection signal MUX_s, and outputs a synchronization signal.

[0128] The reference data signal (“data signal”) Source outputted by being phase-synchronized with the selection signal MUX_s by means of the phase-locked loop 380 is returned to the basic reference signal output circuit 310 .

[0129] Fig. 10A is a graph showing a measurement result of EMI noise generated during operation of a data driver in a case where an output period of a selection signal is fixed as in the related art, and Fig. 10B is a graph showing a measurement result of EMI noise generated during the operation of a data driver in a case where an output period of a selection signal is changed like an embodiment of the present disclosure.

[0130] As from Fig. 10A and Fig. 10B As noted in , if the output period of the selection signal is changed, the EMI noise is reduced in the AM bandwidth of 0.53 MHZ to 1.71 MHZ.

[0131] A display device according to an embodiment of the present disclosure will be described below.

[0132] A display device according to an embodiment of the present disclosure may include: a display panel including pixels formed in a pixel area and defined by intersections between gate lines and data lines; a data driver that sequentially outputs data signals in each sub-horizontal period in one horizontal period and outputs a selection signal, the selection signal including a transistor on period corresponding to the sub-horizontal period; and a distributor including a transistor connected to each data line and switched according to the selection signal to output data signals sequentially output from each source channel to the connected data lines, the transistor on period in the selection signal being possibly different from the sub-horizontal period.

[0133] According to an embodiment of the present disclosure, the data driver may output a selection signal by changing the phase of a reference selection signal having a transistor turn-on period synchronized with a sub horizontal period.

[0134] According to an embodiment of the present disclosure, the data driver may change the phase of the reference selection signal to allow the first shift time period shifted to the transistor-on voltage level to be before or after the start time period of the sub horizontal period.

[0135] According to an embodiment of the present disclosure, the data driver may change the phase of the reference selection signal to allow the second shift time period shifted to the transistor-off voltage level to be before or after the end time period of the sub horizontal period.

[0136] According to an embodiment of the present disclosure, the data driver may change the phase of the reference selection signal to allow an interval between an nth first shift time period and an (n+1)th first shift time period in one selection signal to be different from one horizontal period.

[0137] According to an embodiment of the present disclosure, the data driver can change the phase of the reference selection signal to allow the interval between the nth first shift time period and the (n+1)th first shift time period in a selection signal to be different from the interval between the (n+1)th first shift time period and the (n+2)th first shift time period.

[0138] According to an embodiment of the present disclosure, a horizontal period may include a first sub-horizontal period, a selection signal may include a transistor on-period corresponding to the first sub-horizontal period, and a data driver may change the phase of a reference selection signal to allow a start time period of a transistor on-period corresponding to a first sub-horizontal period of an nth horizontal period and a start time period of a transistor on-period corresponding to a first sub-horizontal period of an (n+1)th horizontal period to be arranged differently relative to the first sub-horizontal period of the one horizontal period.

[0139] According to an embodiment of the present disclosure, a horizontal period may include a first sub-horizontal period, a selection signal includes a transistor on period corresponding to the first sub-horizontal period, and a data driver may change the phase of a reference selection signal to allow a start time period of a transistor on period corresponding to a first sub-horizontal period of an n-th horizontal period to be shifted to before a start time period of a first sub-horizontal period of an n-th horizontal period, and to allow a start time period of a transistor on period corresponding to a first sub-horizontal period of an (n+1)-th horizontal period to be shifted to after a start time period of a first sub-horizontal period of an (n+1)-th horizontal period.

[0140] According to an embodiment of the present disclosure, a horizontal period may include a first sub-horizontal period, a selection signal may include a transistor on period corresponding to the first sub-horizontal period, and a data driver may change the phase of a reference selection signal to allow a start time period of a transistor on period corresponding to a first sub-horizontal period of an nth horizontal period to be shifted to after a start time period of the first sub-horizontal period of the nth horizontal period, and to allow a start time period of a transistor on period corresponding to a first sub-horizontal period of an (n+1)th horizontal period to be shifted to before a start time period of the first sub-horizontal period of an (n+1)th horizontal period.

[0141] According to an embodiment of the present disclosure, a horizontal period may include a first, a second and a third sub-horizontal period, the selection signal may include a first selection signal, a second selection signal and a third selection signal, the first selection signal includes a first transistor on-period corresponding to the first sub-horizontal period, the second selection signal includes a second transistor on-period corresponding to the second sub-horizontal period, the third selection signal includes a third transistor on-period corresponding to the third sub-horizontal period, and the data driver may change the phase of the reference selection signal to allow a start time period of the first transistor on-period to be different from a start time period of the first sub-horizontal period, allow a start time period of the second transistor on-period to be different from a start time period of the second sub-horizontal period, and allow a start time period of the third transistor on-period to be different from a start time period of the third sub-horizontal period.

[0142] According to an embodiment of the present disclosure, a data driver may include a timing controller that outputs a data signal and a selection signal, and the timing controller may output a selection signal that changes the phase of a reference selection signal to allow a transistor turn-on period of the reference selection signal to be different from a sub-horizontal period, and synchronize the reference data signal with the phase-changed selection signal to output a data signal.

[0143] According to an embodiment of the present disclosure, the timing controller may change the phase of the reference selection signal of each data line for one frame of an image, or change the phase of the reference selection signal for each image frame.

[0144] According to an embodiment of the present disclosure, the timing controller may change the phase of the reference selection signal to be shifted to the transistor-on voltage level before or after the time period of the reference selection signal to be shifted to the transistor-on voltage level.

[0145] According to an embodiment of the present disclosure, the timing controller may change the phase of the reference selection signal to be shifted to the transistor-off voltage level before or after the time period of the reference selection signal to be shifted to the transistor-off voltage level.

[0146] According to an embodiment of the present disclosure, a timing controller may include: a basic reference signal output circuit, which outputs a reference selection signal and a reference data signal; a periodic reference signal output circuit, which outputs a periodic reference signal; an inverter, which outputs an inverted periodic reference signal by using the periodic reference signal as an input; a delayed selection signal output circuit, which delays and outputs a reference selection signal; a first AND gate, which performs an AND operation by using the reference selection signal and the periodic reference signal as inputs; a second AND gate, which performs an AND operation by using the inverted periodic reference signal and the delayed reference selection signal as inputs; an OR gate, which performs an OR operation by using the output of the first AND gate and the output of the second AND gate as inputs to output a selection signal; and a phase-locked loop, which receives a reference data signal and a selection signal, and synchronizes the reference data signal with the selection signal to output a synchronization signal.

[0147] According to an embodiment of the present disclosure, a basic reference signal output circuit may output a reference selection signal selected from a plurality of reference selection signals.

[0148] It will be apparent to those skilled in the art that the above disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications and variations may be made to the disclosure without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and it is intended that all variations or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the disclosure.

[0149] The various embodiments described above may be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If it is necessary to adopt the concepts of various patents, applications, and publications to provide other embodiments, various aspects of the embodiments may be modified.

[0150] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A display device, comprising: A display panel including pixels formed in a pixel area defined by intersections between gate lines and data lines; a data driver that sequentially outputs a data signal in each sub-horizontal period in one horizontal period and outputs a selection signal including a transistor conduction period corresponding to the sub-horizontal period; as well as a distributor including a transistor connected to each of the data lines and switching according to the selection signal to output the data signal sequentially output from each source channel to the connected data line, The first transistor cut-off period of the first selection signal in the selection signal is different from the second transistor cut-off period of the second selection signal in the selection signal. Wherein, each of the selection signals does not have periodicity.

2. The display device according to claim 1, wherein: The data driver outputs the selection signal by changing a phase of a reference selection signal having a turn-on period of the transistor synchronized with the sub horizontal period.

3. The display device according to claim 2, wherein: The data driver changes the phase of the reference selection signal to allow a first shift time period to shift to a transistor-on voltage level to be before or after a start time period of the sub horizontal period.

4. The display device according to claim 2, wherein: The data driver changes the phase of the reference selection signal to allow a second shift time period shifted to a transistor-off voltage level to be before or after an end time period of the sub horizontal period.

5. The display device according to claim 2, wherein: The data driver changes the phase of the reference selection signal to allow an interval between an nth first shift time period and an (n+1)th first shift time period in one selection signal to be different from the one horizontal period.

6. The display device according to claim 2, wherein: The data driver changes the phase of the reference selection signal to allow an interval between an nth first shift time period and an (n+1)th first shift time period in one selection signal to be different from an interval between the (n+1)th first shift time period and an (n+2)th first shift time period.

7. The display device according to claim 2, wherein: The one horizontal period includes a first sub-horizontal period, the selection signal includes a transistor on period corresponding to the first sub-horizontal period, and the data driver changes the phase of the reference selection signal to allow a start time period of the transistor on period corresponding to the first sub-horizontal period of the nth horizontal period and a start time period of the transistor on period corresponding to the first sub-horizontal period of the (n+1)th horizontal period to be arranged differently relative to the first sub-horizontal period of the one horizontal period.

8. The display device according to claim 2, wherein: The one horizontal period includes a first sub-horizontal period, the selection signal includes a transistor on period corresponding to the first sub-horizontal period, and the data driver changes the phase of the reference selection signal to allow the start time period of the transistor on period corresponding to the first sub-horizontal period of the nth horizontal period to be shifted before the start time period of the first sub-horizontal period of the nth horizontal period, and to allow the start time period of the transistor on period corresponding to the first sub-horizontal period of the (n+1)th horizontal period to be shifted after the start time period of the first sub-horizontal period of the (n+1)th horizontal period.

9. The display device according to claim 2, wherein: The one horizontal period includes a first sub-horizontal period, the selection signal includes a transistor on period corresponding to the first sub-horizontal period, and the data driver changes the phase of the reference selection signal to allow the start time period of the transistor on period corresponding to the first sub-horizontal period of the nth horizontal period to be shifted to after the start time period of the first sub-horizontal period of the nth horizontal period, and to allow the start time period of the transistor on period corresponding to the first sub-horizontal period of the (n+1)th horizontal period to be shifted to before the start time period of the first sub-horizontal period of the (n+1)th horizontal period.

10. The display device according to claim 2, wherein: The one horizontal period includes a first sub-horizontal period, a second sub-horizontal period, and a third sub-horizontal period, the selection signal includes a first selection signal, a second selection signal, and a third selection signal, the first selection signal includes a first transistor-on period corresponding to the first sub-horizontal period, the second selection signal includes a second transistor-on period corresponding to the second sub-horizontal period, the third selection signal includes a third transistor-on period corresponding to the third sub-horizontal period, and The data driver changes the phase of the reference selection signal to allow a start time period of the first transistor turn-on period to be different from a start time period of the first sub-horizontal period, to allow a start time period of the second transistor turn-on period to be different from a start time period of the second sub-horizontal period, and to allow a start time period of the third transistor turn-on period to be different from a start time period of the third sub-horizontal period.

11. The display device according to claim 1, wherein: The data driver includes a timing controller that outputs the data signal and the selection signal, and the timing controller outputs the selection signal with the phase of a reference selection signal changed to allow a transistor conduction period of the reference selection signal to be different from the sub-horizontal period, and synchronizes the reference data signal with the phase-changed selection signal to output the data signal.

12. The display device according to claim 11, wherein: The timing controller changes the phase of the reference selection signal of each data line for one frame of an image, or changes the phase of the reference selection signal for each image frame.

13. The display device according to claim 11, wherein: The timing controller changes a phase of the reference selection signal to be shifted to the transistor-on voltage level before or after a time period of the reference selection signal shifted to the transistor-on voltage level.

14. The display device according to claim 11, wherein: The timing controller changes a phase of the reference selection signal to be shifted to the transistor-off voltage level before or after a time period of the reference selection signal shifted to the transistor-off voltage level.

15. The display device according to claim 11, wherein: The timing controller comprises: a basic reference signal output circuit, which outputs the reference selection signal and the reference data signal; A periodic reference signal output circuit, which outputs a periodic reference signal; an inverter which outputs an inverted periodic reference signal by using the periodic reference signal as an input; a delay selection signal output circuit, which delays and outputs the reference selection signal; a first AND gate that performs an AND operation by using the reference selection signal and the periodic reference signal as inputs; a second AND gate that performs an AND operation by using the inverted periodic reference signal and the delayed reference selection signal as inputs; An OR gate which outputs a selection signal by performing an OR operation using the output of the first AND gate and the output of the second AND gate as inputs; and A phase locked loop receives the reference data signal and the selection signal and synchronizes the reference data signal with the selection signal to output a synchronization signal.

16. The display device according to claim 15, wherein: The basic reference signal output circuit outputs a reference selection signal selected from a plurality of reference selection signals.

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