Latch circuit, memory device and method

Abstract

The present disclosure relates to a latch circuit, a memory device and a method. A latch circuit includes: a latch clock generator configured to generate a latch clock signal based on a clock signal and a first enable signal; and an input latch coupled to the latch clock generator to receive the latch clock signal. The input latch is configured to generate a latch output signal based on the latch clock signal and the input signal. In response to the first enable signal having a disable logic level, the latch clock generator is configured to set the logic level of the latch clock signal to a corresponding disable logic level without considering the clock signal.

Description

Technical Field

[0001] The present invention relates to latch circuits, memory devices and methods. Background Art

[0002] Processors and memory are various parts of electronic devices. The performance of memory (e.g., capacity, access speed, etc.) affects the overall performance of electronic devices. Power consumption is a design consideration for memory, especially in advanced electronic devices. Summary of the invention

[0003] According to one embodiment of the present disclosure, a latch circuit is provided, comprising: a latch clock generator, the latch clock generator being configured to generate a latch clock signal based on a clock signal and a first enable signal; and an input latch, the input latch being coupled to the latch clock generator to receive the latch clock signal, the input latch being configured to generate a latch output signal based on the latch clock signal and an input signal; wherein, in response to the first enable signal having a disable logic level, the latch clock generator is configured to set the logic level of the latch clock signal to a corresponding disable logic level without considering the clock signal.

[0004] According to another embodiment of the present disclosure, a memory device is provided, comprising: a memory unit; and a control circuit, the control circuit being coupled to control the operation of the memory unit, the control circuit comprising: a latch clock generator, the latch clock generator being configured to generate a latch clock signal based on a clock signal and an enable signal; and an input latch, the input latch being coupled to the latch clock generator to receive the latch clock signal, the input latch being configured to generate a latch output signal based on the latch clock signal and an input signal; wherein the enable signal corresponds to at least one of the following: a chip enable signal for enabling or disabling the memory device, or a write enable signal for enabling or disabling writing to the memory unit.

[0005] According to another embodiment of the present disclosure, a method for operating a memory device having a memory unit is provided, the method comprising: generating a latch clock signal based on a clock signal and an enable signal; and generating a latch output signal for controlling the operation of the memory unit based on the latch clock signal and an input signal, wherein, in the generating of the latch clock signal, in response to the enable signal having a disable logic level, the logic level of the latch clock signal is set to a corresponding disable logic level without considering the clock signal, and in the generating of the latch output signal, in response to the corresponding disable logic level of the latch clock signal, the logic level of the latch output signal remains unchanged without considering the input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a schematic block diagram of a latch circuit according to some embodiments.

[0008] Figure 1B include Figure 1A Timing diagram of various signals in the latch circuit.

[0009] Figure 2 is a schematic block diagram of a memory device according to some embodiments.

[0010] Figure 3A is a schematic block diagram of a latch circuit according to some embodiments.

[0011] Figure 3B include Figure 3A Timing diagram of various signals in the latch circuit.

[0012] Figure 4A is a schematic block diagram of a latch circuit according to some embodiments.

[0013] Figure 4B include Figure 4A Timing diagram of various signals in the latch circuit.

[0014] Figure 5A is a schematic circuit diagram of an example circuit implementation of a latched clock generator according to some embodiments.

[0015] Figure 5B is with Figure 5A The corresponding truth table of the latch clock generator.

[0016] Figure 5C Including Figure 5A Timing diagram of various signals in the latch circuit of the latch clock generator.

[0017] Figure 6 is a flow chart of a method according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0019] Latches are used in various electronic devices, including but not limited to memory. Latches are configured to receive input signals and clock signals. The latch is configured to pass the input signal to the output of the latch in response to a first logic level (e.g., logic "low") of the clock signal, which is referred to as the "pass" state of the latch. The latch is also configured to keep the output unchanged in response to a second logic level (e.g., logic "high") of the clock signal, which is referred to as the "hold" state of the latch. In some other methods, when a function or circuit of an electronic device is not needed or is to be disabled, the latch corresponding to the function or circuit still passes the input signal to the output of the latch. When the corresponding function or circuit is to be disabled, this signal transfer consumes power unnecessarily. To solve this problem, in some embodiments, an enable signal is provided to a clock generator, which is configured to generate a clock signal for the latch. When the enable signal has a disable logic level to disable the function or circuit corresponding to the latch, the clock generator is configured to set the clock signal to a logic level corresponding to the "hold" state of the latch. As a result, the output of the latch remains unchanged, while the function or circuit corresponding to the latch is disabled. In one or more embodiments, this signal retention reduces power consumption. Some embodiments achieve power consumption reduction through fewer logic elements without additional requirements for chip area. In at least one embodiment, noise to / from other circuits in the electronic device is reduced.

[0020] Figure 1A1 is a schematic block diagram of a latch circuit 100 according to some embodiments. The latch circuit 100 includes a latch clock generator 110 and an input latch 120. The latch clock generator 110 is configured to generate a latch clock signal Latch_CKD based on a clock signal Internal_CLK and a signal Enable. The input latch 120 is coupled to the latch clock generator 110 to receive the latch clock signal Latch_CKD, and is configured to generate a latch output signal Latch_Output based on the latch clock signal Latch_CKD and an input signal Latch_Input. Figure 1A In the example configuration of , the signal Enable and the clock signal Internal_CLK are input to the latch clock generator 110. However, other configurations fall within the scope of various embodiments. For example, in at least one embodiment, the clock signal Internal_CLK is generated in the latch clock generator 110.

[0021] In some embodiments, at least one of the latch clock generator 110 or the input latch 120 includes circuit elements that are coupled to perform the functions and / or operations described herein. Examples of such circuit elements include, but are not limited to, transistors, diodes, capacitors, resistors. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with elevated source / drains, and the like. In one or more embodiments, the circuit elements of at least one of the latch clock generator 110 or the input latch 120 are coupled to form one or more logic elements. Examples of logic elements include, but are not limited to, inverters (NOT), AND, OR, NAND, NOR, XOR, XNOR. Reference Figure 5A An example configuration of latch clock generator 110 is described. In some embodiments, input latch 120 includes a latch as described herein. An example latch configuration is a D latch. Other configurations fall within the scope of various embodiments.

[0022] Figure 1B The timing diagram of various signals in the latch circuit 100 according to some embodiments is included. The signal Enable has a disable logic level (e.g., at 132) for disabling functions or circuits associated with the latch circuit 100 in the electronic device. The signal Enable also has an enable logic level (e.g., at 131 and 133) for enabling functions or circuits associated with the latch circuit 100 in the electronic device. Figure 1BIn the example in Figure 1, the disable logic level of the signal Enable is logic "high", such as Figure 1B The label “H” in the figure is disabled, and the enable logic level of the signal Enable is logic “low”. Other configurations (for example, when the disable logic level is logic “low” and the enable logic level is logic “high”) fall within the scope of various embodiments.

[0023] The clock signal Internal_CLK has a logic level that periodically switches between logic “high” at 140 , 142 , 144 , 146 and logic “low” at 141 , 143 , 145 according to a clock frequency.

[0024] In response to the signal Enable having an enable logic level, the latch clock generator 110 is configured to switch the logic level of the latch clock signal Latch_CKD according to the clock signal Internal_CLK. For example, when the signal Enable has an enable logic level at 131, 133, the logic level of the latch clock signal Latch_CKD switches between a logic "high" at 150, 156 (corresponding to a logic "high" at 140, 146 of the clock signal Internal_CLK, respectively) and a logic "low" at 151, 155 and 157 (corresponding to a logic "low" at 141, 145 of the clock signal Internal_CLK, respectively).

[0025] In addition, in response to the signal Enable having a disable logic level, the latch clock generator 110 is configured to set the logic level of the latch clock signal Latch_CKD to a corresponding disable logic level. For example, when the signal Enable has a disable logic level at 132, the logic level of the latch clock signal Latch_CKD is set to logic "high" at 152, regardless of the clock signal Internal_CLK switching between logic "high" at 142, 144 and logic "low" at 143. The logic "high" of the latch clock signal Latch_CKD is a disable logic level because it corresponds to the "hold" state of the input latch 120 and disables the logic level switching at the output of the input latch 120, as described herein. Figure 1B In the example in , the rising edge of the signal Enable between 131 and 132 causes the corresponding rising edge of the latch clock signal Latch_CKD between 151 and 152, and the falling edge of the signal Enable between 132 and 133 causes the corresponding falling edge of the latch clock signal Latch_CKD between 152 and 155. As a result, the logic level of the latch clock signal Latch_CKD is set to logic "high" at 152, corresponding to the disable logic level of the signal Enable at 132.

[0026] The latch clock signal Latch_CKD is provided from the latch clock generator 110 to the input latch 120 to be used as a clock signal of the input latch 120. Figure 1B In the example configuration in , when the logic level of the latch clock signal Latch_CKD is logic "high", the input latch 120 is in the "hold" state, and when the logic level of the latch clock signal Latch_CKD is logic "low", the input latch 120 is in the "pass" state. Other configurations (e.g., when the logic level of the latch clock signal Latch_CKD is logic "high", the input latch 120 is in the "pass" state, and when the logic level of the latch clock signal Latch_CKD is logic "low", the input latch 120 is in the "hold" state) fall within the scope of various embodiments.

[0027] As described herein, when the signal Enable has an enable logic level, the logic level of the latch clock signal Latch_CKD is switched according to the clock signal Internal_CLK. In response to the switched logic level of the latch clock signal Latch_CKD, the input latch 120 is configured to switch the logic level of the latch output signal Latch_Output according to the input signal Latch_Input. For example, when the signal Enable has an enable logic level at 131, the input latch 120 is in a "hold" state when the latch clock signal Latch_CKD is logic "high" at 150, and the input latch 120 is in a "pass" state when the latch clock signal Latch_CKD is logic "low" at 151. Figure 1BIn the example in, the input signal Latch_Input is a differential signal, including two component signals with opposite logic levels. When one of the two component signals switches from logic "high" to logic "low" and the other component signal switches from logic "low" to logic "high", the logic level of the input signal Latch_Input switches at 161, 162, and 163. Similarly, the latch output signal Latch_Output is also a differential signal. When the input latch 120 is in a "hold" state corresponding to the logic "high" of the latch clock signal Latch_CKD at 150, the logic level of the input signal Latch_Input switches at 161. This logic level switch 161 of the input signal Latch_Input is maintained by the input latch 120, and is output as a logic level switch 171 of the latch output signal Latch_Output when the input latch 120 is in a "transfer" state corresponding to the logic "low" of the latch clock signal Latch_CKD at 151. Similarly, the logic level switch 163 of the input signal Latch_Input is held by the input latch 120 (which is in the "hold" state corresponding to the logic "high" of the latch clock signal Latch_CKD at 156), and is output as the logic level switch 173 of the latch output signal Latch_Output when the input latch 120 is in the "pass" state corresponding to the logic "low" of the latch clock signal Latch_CKD at 157. In other words, when the signal Enable has an enable logic level, the input latch 120 passes the input signal Latch_Input.

[0028] As described herein, when the signal Enable has a disabled logic level, the logic level of the latch clock signal Latch_CKD is set to a corresponding disabled logic level. In response to the corresponding disabled logic level of the latch clock signal Latch_CKD, the input latch 120 is configured to keep the logic level of the latch output signal unchanged, regardless of the input signal. For example, when the signal Enable has a disabled logic level at 132, the input latch 120 is in a "hold" state corresponding to the corresponding disabled logic level (i.e., logic "high") of the latch clock signal Latch_CKD at 152. The "hold" state is maintained and the latch output signal Latch_Output is unchanged, regardless of the logic level switch 162 of the input signal Latch_Input during the disabled time period 175 (corresponding to the disabled logic level of the signal Enable at 132). In other words, when the signal Enable has a disabled logic level, the input latch 120 does not pass the input signal Latch_Input.

[0029] In contrast, in a comparison circuit according to other methods, when the enable signal in the comparison circuit has a disabled logic level, the logic level of the latch clock signal is set to a logic "low" corresponding to the "pass" state of the latch of the comparison circuit. As a result, the latch of the comparison circuit passes the input signal even during a disabled time period corresponding to the disabled logic level of the enable signal. Due to unnecessary logic level switching at the output of the latch during the disabled time period, the comparison circuit consumes extra power unnecessarily. The latch circuit 100 according to some embodiments avoids this additional, unnecessary power consumption by keeping the output of the input latch 120 unchanged during the disabled time period 175. The latch circuit according to some embodiments is applicable to various circuits and / or electronic devices (wherein the latch is included and disabled within a specific time period to reduce power consumption). An example electronic device, i.e., a memory device, is described herein.

[0030] Figure 2 2 is a schematic block diagram of a memory device 200 according to some embodiments. The memory device 200 includes at least one memory cell MC and a control circuit 202 coupled to control the operation of the memory cell MC. Figure 2 In the example configuration in , the memory device 200 includes a plurality of memory cells MC arranged in a plurality of columns and rows in a memory array 204. The memory device 200 also includes a plurality of (e.g., m) word lines WL1 to WLm extending along the rows of the memory cells MC, and a plurality of (e.g., n) bit lines BL1 to BLn extending along the columns of the memory cells MC. Each memory cell MC is coupled to the control circuit 202 through at least one word line and at least one bit line. Examples of word lines include, but are not limited to, read word lines (for transmitting the address of the memory cell MC to be read from), and write word lines (for transmitting the address of the memory cell MC to be written to). In at least one embodiment, a group of word lines is configured to be used as both read word lines and write word lines. Examples of bit lines include read bit lines (for transmitting data read from the memory cell MC indicated by the corresponding word line), and write bit lines (for transmitting data to be written to the memory cell MC indicated by the corresponding word line). In at least one embodiment, a group of bit lines is configured to be used as both read bit lines and write bit lines. In one or more embodiments, each memory cell MC is coupled to a pair of bit lines referred to as a bit line and a bit bar.

[0031] exist Figure 2In the example configuration of , the control circuit 202 includes a clock network 206, a latch circuit 210, a decoder 212, a word line driver 214, a latch circuit 220, a write driver 222, and a sense amplifier (SA) 224. The clock network 206 is configured to generate one or more clock signals for other elements of the control circuit 202. The latch circuit 210 is configured to latch the address of one or more memory cells MC to be accessed (e.g., to be read or written) in the memory array 204. The decoder 212 is configured to decode the address output by the latch circuit 210. The word line driver 214 is coupled to drive one or more bit lines corresponding to the address decoded by the decoder 212 to access the corresponding memory cell MC. The data read from the accessed memory cell MC is obtained through the corresponding bit line and sensed by the SA 224. In at least one embodiment, the control circuit 202 also includes a latch circuit for latching the read data output by the SA 224. The data of the memory cell MC to be accessed is latched by the latch circuit 220 and output to the write driver 222, which is coupled to drive one or more bit lines to write the data into the corresponding memory cell MC. The control circuit 202 also includes one or more input / output (I / O) ports or pins (not shown) for one or more signals (e.g., address signals, data signals, control signals, etc.). The control circuit 202 also includes a control chip (not shown) configured to control other components of the memory device 200. The described memory device configuration is an example, and other memory device configurations fall within the scope of various embodiments. In at least one embodiment, the memory device is a static random access memory (SRAM). Other types of memory fall within the scope of various embodiments.

[0032] In some embodiments, one or more of the latch circuits 210, 220, or any other latch circuits (not shown) included in the memory device 200 correspond to the latch circuits 210, 220, or any other latch circuits (not shown) included in the memory device 200. Figure 1A and / or Figure 1B The latch circuit 100 is described.

[0033] In an example, the latch circuit 210 receives a clock signal from the clock network 206, a chip enable signal CEB, and an address signal ADDRESS. The clock signal from the clock network 206 corresponds to the address of Figure 1A-1B The clock signal Internal_CLK described, the signal CEB corresponds to the Figure 1A-1B The signal Enable described above and the signal ADDRESS correspond to the Figure 1A-1B210 is a memory device 200 that receives an input signal Latch_Input as described above. The latch circuit 210 outputs an output signal 211 corresponding to the latch output signal Latch_Output. The signal CEB is a signal for enabling or disabling the memory device 200. In at least one embodiment, the signal CEB is received from an external circuit through an I / O pin or port of the memory device 200. When the signal CEB has an enable logic level (e.g., logic "low"), the latch circuit 210 latches the address in the signal Address according to the clock signal, and transmits the latched address as an output signal 211 for the decoder 212 and the word line driver 214, as described herein. When the signal CEB has a disable logic level (e.g., logic "high"), the latch circuit 21 keeps its output unchanged regardless of the signal address, thereby saving power consumption in at least one embodiment, as described herein.

[0034] In another example, the latch circuit 220 receives a clock signal from the clock network 206, at least one of the signal CEB or the write enable signal WEB, and at least one of the data signal DATA or the bit write mask signal BWEB. The clock signal from the clock network 206 corresponds to the Figure 1A-1B At least one of the clock signal Internal_CLK, the signal CEB or the signal WEB described corresponds to the Figure 1A-1B The signal Enable described in the embodiment of the present invention corresponds to the signal DATA or the signal BWEB (referred to herein as the signal DATA / BWEB) corresponding to the signal DATA. Figure 1A-1B The latch circuit 220 outputs an output signal 221 corresponding to the latch output signal Latch_Output.

[0035] Signal WEB is a signal for enabling or disabling writing to one or more memory cells MC. Signal DATA includes data to be written to one or more memory cells MC. Signal BWEB is a signal for controlling selective writing to one or more memory cells MC (e.g., selective writing to one or more memory bits in a memory word). When signal CEB and / or signal WEB have an enabling logic level (e.g., logic "low"), latch circuit 220 latches signal DATA / BWEB according to the clock signal and passes the latched signal as output signal 221 for writing driver 222, as described herein. When signal CEB and / or signal WEB have a disabling logic level (e.g., logic "high"), latch circuit 220 keeps its output unchanged, regardless of signal DATA / BWEB, thereby saving power consumption in at least one embodiment, as described herein.

[0036] Figure 3Ais a schematic block diagram of a latch circuit 300 according to some embodiments. In some embodiments, the latch circuit 300 corresponds to one or more of the latch circuit 210, the latch circuit 220, or any other latch circuit (not shown) included in the memory device 200. The latch circuit 300 includes the latch clock generator 110, the input latch 120, and the enable latch 330. The enable latch 330 is a latch having the signal WEB as its input signal, the clock signal Internal_CLK as its clock signal, and the enable signal WEBX as its output signal. As a latch, the enable latch 330 is configured to hold the signal WEB, or pass the signal WEB, according to different logic levels of the clock signal Internal_CLK, as described herein. The enable signal WEBX is input from the enable latch 330 to the latch clock generator 110, and corresponds to the enable signal WEBX with respect to Figure 1A and / or Figure 1B The signal DATA / BWEB is input to the input latch 120 and corresponds to the signal Enable described in the description. Figure 1A and / or Figure 1B The described input signal Latch_Input. The described configurations are examples, and other configurations fall within the scope of various embodiments. For example, in at least one embodiment, the signal CEB is provided as an input signal to the enable latch 330 (instead of the signal WEB or in combination with the signal WEB). In at least one embodiment, the signal ADDRESS is provided as an input signal to the input latch 120 (instead of the input signal DATA / BWEB).

[0037] Figure 3BA timing diagram of various signals in the latch circuit 300 according to some embodiments is included. The signal WEB has a disable logic level (e.g., logic "high") at 322 and an enable logic level (e.g., logic "low") at 321, 323. The enable latch 330 passes or holds the signal WEB according to the clock signal Internal_CLK. For example, when the logic level of the clock signal Internal_CLK is logic "low" at 141, the rising edge of the signal WEB between 321 and 322 is passed to the output of the enable latch 330. As a result, the enable signal WEBX has a corresponding rising edge between the logic "low" at 331 and the logic "high" at 332. In addition, the falling edge of the signal WEB between 322 and 323 is held when the logic level of the clock signal Internal_CLK is logic "high" at 144, and is then passed to the output of the enable latch 330 when the logic level of the clock signal Internal_CLK changes to logic "low" at 145. As a result, the enable signal WEBX has a corresponding falling edge between a logic "high" at 332 and a logic "low" at 333. The enable signal WEBX corresponds to the signal Enable, and is used by the latch clock generator 110 together with the clock signal Internal_CLK to generate the latch clock signal Latch_CKD, which is then used by the input latch 120 to hold or pass the signal DATA / BWEB to output the latch output signal Latch_Output, as described with respect to Figure 1A and / or Figure 1B During the disable time period 175 corresponding to the disable logic level of the enable signal WEBX at 332, the logic level of the latch output signal Latch_Output remains unchanged. As a result, power consumption is reduced in at least one embodiment compared to comparison circuits according to other methods, such as with respect to Figure 1A and / or Figure 1B as described.

[0038] from Figure 3B As can be seen in FIG. 3 , the duration of the disable logic level of signal WEB at 322 is shorter than the duration of the disable logic level of enable signal WEBX at 332. If signal WEB is provided directly to latch clock generator 110 without enable latch 330, disable time period 175 will be shorter than if enable latch 330 is included and enable signal WEBX is provided to latch clock generator 110. Including enable latch 330 in latch circuit 300 effectively makes the disable time period corresponding to signal WEB longer and further reduces power consumption.

[0039] Figure 4A4 is a schematic block diagram of a latch circuit 400 according to some embodiments. In some embodiments, the latch circuit 400 corresponds to one or more of the latch circuit 210, the latch circuit 220, or any other latch circuit (not shown) included in the memory device 200. The latch circuit 400 includes a latch clock generator 110, an input latch 120, and an OR gate 440. The OR gate 440 has the signal CEB and the signal WEB as its input signals, and is configured to generate the signal Enable based on the signal CEB and the signal WEB.

[0040] Figure 4B Included are timing diagrams of various signals in latch circuit 400 according to some embodiments. Figure 3B As described, signal WEB has a disable logic level (e.g., logic “high”) at 322, and has an enable logic level (e.g., logic “low”) at 321, 323. Signal CEB has a disable logic level (e.g., logic “high”) at 442, and has an enable logic level (e.g., logic “low”) at 441, 443. OR gate 440 generates signal Enable at logic “high” when either signal CEB or signal WEB is at logic “high”, such that signal Enable has logic “high” at 132, and has logic “low” at 131, 133. In addition to the generation of signal Enable from signal CEB and signal WEB as described, Figure 4B and Figure 1B Further different: the clock signal Internal_CLK is disabled during the disable logic level at the logic "high" of the signal CEB, which disables the memory device including the latch circuit 400. In addition, the latch circuit 400 operates in a manner similar to the latch circuit 100 and maintains the logic level of the latch output signal Latch_Output unchanged during the disable time period 175 corresponding to the disable logic level of the signal Enable. As a result, power consumption is reduced in at least one embodiment compared to comparison circuits according to other methods, such as with respect to Figure 1A and / or Figure 1B as described.

[0041] from Figure 4BAs can be seen in FIG. 4 , the duration of the disable logic level of signal Enable corresponds to the combination of the durations of the disable logic levels of signal CEB and signal WEB. If each of signal CEB or signal WEB is provided to latch clock generator 110 separately as an enable signal, then the disable time period 175 will be shorter than when signal CEB and signal WEB are combined by OR gate 440 to generate signal Enable for latch clock generator 110. Including OR gate 440 to combine signal CEB and signal WEB effectively makes the disable time period (for holding the output of input latch 120) longer and further reduces power consumption.

[0042] Figure 5A 1 is a schematic circuit diagram of an example circuit implementation of a latch clock generator 500 according to some embodiments. In some embodiments, the latch clock generator 500 corresponds to a latch clock generator of one or more of the latch circuits 100, 300, 400, 210, 220, or any other latch circuit included in the memory device. The latch clock generator 500 includes transistors M1-M5, inverters INV1-INV3, and a NAND gate. Transistors M1 and M2 are coupled in series between a voltage supply node VDD and a node CKAWT_B. Transistors M3 and M4 are coupled in parallel between node CKAWT_B and node ENC. The gate terminals of transistors M1 and M3 are coupled to a node CLK, and the gate terminals of transistors M2 and M4 are coupled to a node CKP3. The signal on the node CLK corresponds to an external clock signal provided to the latch clock generator 500, for example, from a clock network described herein. The signal on the node CKP3 is an inverted signal of the external clock signal on the node CLK. The transistor M5 is coupled between the node VDD and the node CKAWT_B. The gate terminal of the transistor M5 is coupled to the node EN. The signal on the node EN is another enable signal. The signal on the node CKAWT_B corresponds to the clock signal Internal_CLK described herein.

[0043] Inverter INV1 has an input coupled to node WEB to receive signal WEB, and an output coupled to node WEB1B to output an inverted signal of signal WEB thereto. Signal WEB corresponds to signal Enable described herein. In at least one embodiment, signal WEB is an example enable signal. In some embodiments, another enable signal (e.g., signal CEB) (instead of signal WEB, or in combination with signal WEB) is provided to the input of inverter INV1, as described herein.

[0044] The NAND gate has a first input coupled to the node CKAWT_B, a second input coupled to the node WEB1B, and an output at which the result of the NAND operation on the signals at the node CKAWT_B and the node WEB1B is output. The output of the NAND gate is coupled to the node CKD through the inverters INV2 and INV3 coupled in series. The signal at the node CKD corresponds to the latch clock signal Latch_CKD described herein.

[0045] Figure 5B is corresponding to Figure 5A 510 of a latched clock generator 500. Columns 512-514 of the truth table 510 include the corresponding logic levels of various signals at nodes WEB, EN, WEB1B, CKD in the latched clock generator 500. For simplicity, the signal at each node is referred to by the same name as the node. In columns 512-514, "0" represents a logic "low", "1" represents a logic "high", "0=>1" represents a rising edge from a logic "low" to a logic "high", and "1=>0" represents a falling edge from a logic "high" to a logic "low". In column 514, "CKD" indicates that the signal CKD maintains its current logic level.

[0046] Column 515 in truth table 510 includes the "hold" and "transfer" states of a D latch in a latch circuit having latch clock generator 500. The D latch is coupled to receive signal CKD as its clock signal and corresponds to input latch 120 described herein. The latch circuit including the D latch and latch clock generator 500 corresponds to one or more of latch circuit 100, latch circuit 300, latch circuit 400, latch circuit 210, latch circuit 220, or any other latch circuit included in a memory device.

[0047] Column 516 in the truth table 510 includes the operation of a memory device including a latch circuit having a D latch and a latch clock generator 500. The operation in column 516 is determined by the logic levels of the signal WEB and the signal EN. For example, the "write" in column 516 indicates that when the signal EN has an enable logic level at a logic "high" and the signal WEB has an enable logic level at a logic "low" or experiences a rising edge from a logic "low" to a logic "high", the memory device is enabled to perform a write operation for writing one or more corresponding memory cells. In other cases, the "non-write" in column 516 indicates that the memory device does not perform a write operation in the corresponding memory cell.

[0048] As can be seen from rows 517 and 518 of truth table 510, when both signal EN and signal WEB have a disable logic level (logic "low" and logic "high", respectively), the D latch is in a "hold" state and prevents its input signal from passing to its output and avoids unnecessary logic level switching at its output. As a result, power consumption is reduced in at least one embodiment. Figure 5C This situation is further described.

[0049] Figure 5C 5 includes timing diagrams of various signals in a latch circuit having a latch clock generator 500. A latch circuit (such as Figure 5B ) includes a D latch corresponding to the input latch 120. Figure 5C In the embodiment, the external clock signal CLK includes a plurality of clock pulses according to the clock frequency. The signal WEB corresponds to the Figure 1B The signal Enable described above has a logic "high" disable logic level at 532 and a logic "low" enable logic level at 531 and 533. The signal CKAWT_B corresponds to the Figure 1B The clock signal Internal_CLK described herein includes a plurality of clock pulses (corresponding to the clock pulses of the external clock signal CLK) when the signal EN has an enable logic level of logic “high”. Figure 5C 510). When the signal EN has a disabled logic level of logic "low", the signal CKAWT_B has a logic level of logic "high" at 542. When the signal EN and the signal WEB both have the disabled logic levels described with respect to rows 517 and 518 in the truth table 510, corresponding to Figure 5C The NAND gate is connected to the inverted signal WEB1B ( Figure 5C ) and the signal CKAWT_B perform a NAND operation, and output a signal CKD, which is related to Figure 1B The logic level of the signal CKD is logic "high" at 552, corresponding to the situation when both the signal EN and the signal WEB have a disabled logic level. The signal CKD is provided to the D latch corresponding to the input latch 120 as a clock signal, and causes the D latch to keep its output signal D-Latch_Output unchanged at 575, regardless of the logic level switching 562, 563 in its input signal D-Latch_Input. As a result, in at least one embodiment, unnecessary logic level switching when both the signal EN and the signal WEB have a disabled logic level is avoided, and power consumption is reduced.

[0050] In some embodiments, by including at least one enable signal in the generation of the clock signal of the latch, when the enable signal has a disabled logic level, the output of the latch is maintained unchanged regardless of the input signal of the latch. As a result, power consumption is reduced in at least one embodiment. In one or more embodiments, the DATA / BWEB pin power is reduced by about

[0051] In some embodiments, including at least one enable signal in the generation of the clock signal of the latch is implemented by fewer standard logic elements (e.g., OR gates, NAND gates, inverters, etc.). As a result, in at least one embodiment, additional requirements for power consumption and / or chip area can be negligible. In one or more embodiments, additional elements (for including at least one enable signal in the generation of the clock signal of the latch) can be placed in the layout of a pre-existing latch clock generator without increasing the chip area.

[0052] In some embodiments, by reducing or preventing signal switching at the output of the latch when the enable signal has a disabled logic level, coupling noise is reduced, which in turn results in better (shorter) timing. For example, in at least one embodiment, coupling noise from write true (WT) and / or write complement (WC) lines on corresponding bit lines is reduced, saving approximately 11% of timing.

[0053] Figure 6 is a flow chart of method 600 according to some embodiments. In at least one embodiment, method 600 is performed by one or more of latch circuit 100, latch circuit 300, latch circuit 400, latch circuit 210, latch circuit 220, or any other latch circuit included in a memory device.

[0054] At operation 615, a latch clock signal is generated based on the clock signal and the enable signal. For example, a latch clock signal Latch_CKD is generated based on the clock signal Internal_CLK and the signal Enable, as shown in FIG. Figure 1A and / or Figure 1B As described. In addition, in response to the enable signal having a disabled logic level, the logic level of the latch clock signal is set to a corresponding disabled logic level without regard to the clock signal. For example, when the signal Enable has a disabled logic level (e.g., a logic "high" at 132), the logic level of the latch clock signal Latch_CKD is set to a corresponding disabled logic level (e.g., a logic "high" at 152) without regard to the clock signal Internal_CLK, as described with respect to Figure 1B as described.

[0055] At operation 625, a latch output signal for controlling the operation of the memory cell is generated based on the latch clock signal and the input signal. For example, the latch output signal Latch_Output for controlling the operation of the memory cell is generated based on the latch clock signal Latch_CKD and the input signal Latch_Input. In addition, in response to the disabled logic level of the latch clock signal, the logic level of the latch output signal remains unchanged regardless of the input signal. For example, when the latch clock signal Latch_CKD has a disabled logic level (e.g., a logic "high" at 152), the logic level of the latch output signal Latch_Output remains unchanged (e.g., at 175) regardless of the input signal Latch_Input, as described with respect to Figure 1B as described.

[0056] In at least one embodiment, all operations 615, 625 are performed automatically without user input or intervention.

[0057] The described methods and algorithms include example operations and do not necessarily require that they be performed in the order shown. According to the spirit and scope of the embodiments of the present disclosure, operations may be appropriately increased, replaced, reordered, and / or eliminated. Embodiments in which different features and / or different embodiments are combined fall within the scope of the present disclosure and will be apparent to those of ordinary skill in the art after reading the present disclosure.

[0058] In some embodiments, a latch circuit includes: a latch clock generator configured to generate a latch clock signal based on a clock signal and a first enable signal; and an input latch coupled to the latch clock generator to receive the latch clock signal. The input latch is configured to generate a latch output signal based on the latch clock signal and the input signal. In response to the first enable signal having a disable logic level, the latch clock generator is configured to set the logic level of the latch clock signal to a corresponding disable logic level without considering the clock signal.

[0059] In some embodiments, a memory device includes: a memory cell; and a control circuit coupled to control the operation of the memory cell. The control circuit includes: a latch clock generator configured to generate a latch clock signal based on a clock signal and an enable signal; and an input latch coupled to the latch clock generator to receive the latch clock signal. The input latch is configured to generate a latch output signal based on the latch clock signal and the input signal. The enable signal corresponds to at least one of the following: a chip enable signal for enabling or disabling the memory device, or a write enable signal for enabling or disabling writing to the memory cell.

[0060] In some embodiments, a method of operating a memory device having a memory cell includes: generating a latched clock signal based on a clock signal and an enable signal; and generating a latched output signal for controlling the operation of the memory cell based on the latched clock signal and an input signal. In generating the latched clock signal, in response to the enable signal having a disable logic level, the logic level of the latched clock signal is set to a corresponding disable logic level regardless of the clock signal. In generating the latched output signal, in response to the corresponding disable logic level of the latched clock signal, the logic level of the latched output signal remains unchanged regardless of the input signal.

[0061] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments or examples introduced herein and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0062] Example 1. A latch circuit, comprising: a latch clock generator, the latch clock generator being configured to generate a latch clock signal based on a clock signal and a first enable signal; and an input latch, the input latch being coupled to the latch clock generator to receive the latch clock signal, the input latch being configured to generate a latch output signal based on the latch clock signal and an input signal; wherein, in response to the first enable signal having a disable logic level, the latch clock generator is configured to set the logic level of the latch clock signal to a corresponding disable logic level without regard to the clock signal.

[0063] Example 2. The latch circuit of Example 1, wherein, in response to the corresponding disable logic level of the latch clock signal, the input latch is configured to maintain the logic level of the latch output signal unchanged regardless of the input signal.

[0064] Example 3. A latch circuit according to Example 2, wherein, in response to the first enable signal having an enable logic level different from the disable logic level, the latch clock generator is configured to switch the logic level of the latch clock signal according to the clock signal, and in response to the switched logic level of the latch clock signal, the input latch is configured to switch the logic level of the latch output signal according to the input signal.

[0065] Example 4. The latch circuit according to Example 1 further includes: an enable latch, which is configured to generate the first enable signal based on the clock signal and the second enable signal, wherein the latch clock generator is coupled to the enable latch to receive the first enable signal.

[0066] Example 5. The latch circuit according to Example 1 further includes: an OR gate configured to generate the first enable signal based on the second enable signal and the third enable signal, wherein the latch clock generator is coupled to the OR gate to receive the first enable signal.

[0067] Example 6. A latch circuit according to Example 1, wherein the latch clock generator includes: an inverter, the inverter being configured to generate an inverted signal of the first enable signal, and a NAND gate, the NAND gate being coupled to the inverter to receive the inverted signal of the first enable signal, and the NAND gate being configured to generate the latch clock signal based on the clock signal and the inverted signal of the first enable signal.

[0068] Example 7. The latch circuit of Example 1, wherein the latch clock generator is configured to generate the latch clock signal based on the clock signal, the first enable signal, and a second enable signal.

[0069] Example 8. A latch circuit according to Example 7, wherein, in response to each of the first enable signal and the second enable signal having a disable logic level, the latch clock generator is configured to set the logic level of the latch clock signal to a corresponding disable logic level, and in response to the corresponding disable logic level of the latch clock signal, the input latch is configured to maintain the logic level of the latch output signal unchanged regardless of the input signal.

[0070] Example 9. A latch circuit according to Example 8, wherein, in response to the second enable signal having an enable logic level different from the disable logic level of the second enable signal, the latch clock generator is configured to maintain the logic level of the latch clock signal unchanged or set the logic level of the latch clock signal to a disable logic level according to the first enable signal, and in response to the unchanged logic level or the disable logic level of the latch clock signal, the input latch is configured to maintain the logic level of the latch output signal unchanged regardless of the input signal.

[0071] Example 10. A memory device, comprising: a memory cell; and a control circuit, the control circuit being coupled to control the operation of the memory cell, the control circuit comprising: a latch clock generator, the latch clock generator being configured to generate a latch clock signal based on a clock signal and an enable signal; and an input latch, the input latch being coupled to the latch clock generator to receive the latch clock signal, the input latch being configured to generate a latch output signal based on the latch clock signal and an input signal; wherein the enable signal corresponds to at least one of the following: a chip enable signal for enabling or disabling the memory device, or a write enable signal for enabling or disabling writing to the memory cell.

[0072] Example 11. A memory device according to Example 10, wherein the input signal includes one of the following: a data signal including data to be written to the memory cell, a bit write mask signal for controlling selective writing to the memory cell, or an address signal including an address of the memory cell.

[0073] Example 12. A memory device according to Example 10, wherein the control circuit further includes an enable latch, the enable latch being configured to: receive the clock signal and the write enable signal, and generate the enable signal based on the clock signal and the write enable signal, and the latch clock generator is coupled to the enable latch to receive the enable signal.

[0074] Example 13. The memory device of Example 12, wherein the input signal comprises one of: a data signal comprising data to be written to the memory cell, or a bit write mask signal for controlling selective writing to the memory cell.

[0075] Example 14. A memory device according to Example 10, wherein the control circuit further includes an OR gate, the OR gate being configured to: receive the chip enable signal and the write enable signal, and generate the enable signal based on the chip enable signal and the write enable signal, and the latch clock generator being coupled to the OR gate to receive the enable signal.

[0076] Example 15. A memory device according to Example 10, wherein the enable signal is the write enable signal, and the input signal includes one of the following: a data signal including data to be written to the memory cell, or a bit write mask signal for controlling selective writing to the memory cell.

[0077] Example 16. A memory device according to Example 10, wherein the latch clock generator includes a NAND gate, which is configured to: receive an inverted signal of the write enable signal and the clock signal, and generate a signal corresponding to the latch clock signal based on the inverted signal of the write enable signal and the clock signal.

[0078] Example 17. A method for operating a memory device having a memory cell, the method comprising: generating a latch clock signal based on a clock signal and an enable signal; and generating a latch output signal for controlling the operation of the memory cell based on the latch clock signal and an input signal, wherein, in the generating of the latch clock signal, in response to the enable signal having a disable logic level, the logic level of the latch clock signal is set to a corresponding disable logic level without regard to the clock signal, and in the generating of the latch output signal, in response to the corresponding disable logic level of the latch clock signal, the logic level of the latch output signal remains unchanged without regard to the input signal.

[0079] Example 18. A method according to Example 17, wherein, in the generating of the latch clock signal, in response to the enable signal having an enable logic level different from the disable logic level, the logic level of the latch clock signal is switched according to the clock signal, and in the generating of the latch output signal, in response to the switched logic level of the latch clock signal, the logic level of the latch output signal is switched according to the input signal.

[0080] Example 19. The method of Example 17, wherein the enable signal corresponds to at least one of: a chip enable signal for enabling or disabling the memory device, or a write enable signal for enabling or disabling writing to the memory cell.

[0081] Example 20. A method according to Example 19, wherein the input signal includes one of the following: a data signal including data to be written to the memory cell, a bit write mask signal for controlling selective writing to the memory cell, or an address signal including an address of the memory cell.

Claims

1. A latch circuit, comprising: a latch clock generator configured to generate a latch clock signal based on the clock signal, the first enable signal, and the second enable signal; as well as an input latch coupled to the latch clock generator to receive the latch clock signal, the input latch being configured to generate a latch output signal based on the latch clock signal and an input signal; wherein, in response to the first enable signal having a disable logic level, the latch clock generator is configured to set the logic level of the latch clock signal to a corresponding disable logic level without regard to the clock signal, The first enable signal and the second enable signal are independent of each other.

2. The latch circuit according to claim 1, wherein: In response to the corresponding disable logic level of the latch clock signal, the input latch is configured to maintain the logic level of the latch output signal unchanged regardless of the input signal.

3. The latch circuit according to claim 2, wherein: In response to the first enable signal having an enable logic level different from the disable logic level, The latch clock generator is configured to switch a logic level of the latch clock signal according to the clock signal, and In response to the switched logic level of the latch clock signal, the input latch is configured to switch the logic level of the latch output signal according to the input signal.

4. The latch circuit according to claim 1, wherein: In response to each of the first enable signal and the second enable signal having a disable logic level, The latch clock generator is configured to set the logic level of the latch clock signal to a corresponding disable logic level, and In response to the corresponding disable logic level of the latch clock signal, the input latch is configured to maintain the logic level of the latch output signal unchanged regardless of the input signal.

5. The latch circuit according to claim 4, wherein: In response to the second enable signal having an enable logic level different from the disable logic level of the second enable signal, The latch clock generator is configured to maintain the logic level of the latch clock signal unchanged or set the logic level of the latch clock signal to a disable logic level according to the first enable signal, and In response to the unchanged logic level of the latch clock signal or the disabled logic level, the input latch is configured to maintain the logic level of the latch output signal unchanged regardless of the input signal.

6. A memory device comprising: Memory unit; as well as a control circuit coupled to control the operation of the memory cell, the control circuit comprising: a latch clock generator configured to generate a latch clock signal based on the clock signal and the enable signal; and an input latch coupled to the latch clock generator to receive the latch clock signal, the input latch being configured to generate a latch output signal based on the latch clock signal and an input signal; The enable signal corresponds to at least one of the following: A chip enable signal, used to enable or disable the memory device, or A write enable signal, used to enable or disable writing to the memory cell; Wherein, the control circuit further includes an OR gate, and the OR gate is configured as follows: receiving the chip enable signal and the write enable signal, and The enable signal is generated based on the chip enable signal and the write enable signal, and the latch clock generator is coupled to the OR gate to receive the enable signal.

7. The memory device according to claim 6, wherein: The input signal includes one of the following: a data signal, comprising data to be written into the memory cell, A bit write mask signal for controlling the selective writing of the memory cell, or The address signal includes the address of the memory unit.

8. The memory device according to claim 6, wherein: The control circuit further includes an enable latch, wherein the enable latch is configured to: receiving the clock signal and the write enable signal, and generating the enable signal based on the clock signal and the write enable signal, and The latch clock generator is coupled to the enable latch to receive the enable signal.

9. The memory device according to claim 8, wherein: The input signal includes one of the following: A data signal comprising the data to be written to the memory cell, or A bit write mask signal is used to control the selective writing to the memory cell.

10. The memory device according to claim 6, wherein: The enable signal is the write enable signal, and The input signal includes one of the following: A data signal comprising the data to be written to the memory cell, or A bit write mask signal is used to control the selective writing to the memory cell.

11. The memory device according to claim 6, wherein: The latch clock generator includes a NAND gate configured as follows: receiving an inverted signal of the write enable signal and the clock signal, and A signal corresponding to the latch clock signal is generated based on the inverted signal of the write enable signal and the clock signal.

12. A method of operating a memory device having a memory cell, the method comprising: generating a second enable signal based on the clock signal and the first enable signal; generating a latch clock signal based on the clock signal and the second enable signal; as well as generating a latch output signal for controlling the operation of the memory cell based on the latch clock signal and an input signal, in, In said generating said latch clock signal, in response to the second enable signal having a disable logic level, the logic level of the latched clock signal is set to a corresponding disable logic level regardless of the clock signal, In said generating said latch output signal, In response to the corresponding disable logic level of the latch clock signal, the logic level of the latch output signal remains unchanged regardless of the input signal, In said generating the second enable signal: A duration of the disable logic level of the second enable signal is longer than a duration of the disable logic level of the first enable signal.

13. The method according to claim 12, wherein: In said generating said latch clock signal, In response to the second enable signal having an enable logic level different from the disable logic level, the logic level of the latch clock signal is switched according to the clock signal, and In said generating said latch output signal, In response to the switched logic level of the latch clock signal, the logic level of the latch output signal is switched according to the input signal.

14. The method according to claim 12, wherein: The second enable signal corresponds to at least one of the following: A chip enable signal, used to enable or disable the memory device, or A write enable signal is used to enable or disable writing to the memory cell.

15. The method according to claim 14, wherein: The input signal includes one of the following: a data signal, comprising data to be written into the memory cell, A bit write mask signal for controlling the selective writing of the memory cell, or The address signal includes the address of the memory unit.

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