Electronic display with in-pixel compensation and oxide drive transistor

Abstract

The present disclosure relates to an electronic display with in-pixel compensation and oxide drive transistors. The display pixel may include an organic light emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconductor oxide transistor to mitigate threshold voltage hysteresis, thereby improving the first frame response at high refresh rates, reducing undesired brightness jumps at low refresh rates, and reducing image retention. The gate setting transistor may also be implemented as a semiconductor oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconductor oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this manner can support in-pixel threshold voltage compensation and a conduction bias stress phase to further mitigate hysteresis.

Description

[0001] This patent application claims priority to U.S. Patent Application No. 17 / 075,587 filed on October 20, 2020 and U.S. Provisional Patent Application No. 62 / 953,054 filed on December 23, 2019, which are hereby incorporated by reference in their entirety. Background Art

[0002] The present disclosure relates generally to electronic devices having displays and, more particularly, to display driver circuits for displays such as organic light emitting diode displays.

[0003] Electronic devices often include displays. For example, cellular phones and portable computers include displays for presenting information to users.

[0004] Displays, such as organic light emitting diode displays, have an array of display pixels based on light emitting diodes. In this type of display, each display pixel includes a light emitting diode and a thin film transistor for controlling the application of signals to the light emitting diode to generate light.

[0005] The organic light emitting diode display pixel includes a driving thin film transistor connected to a data line via an access thin film transistor. The access transistor may have a gate terminal that receives a scan signal via a corresponding scan line. Image data on the data line may be loaded into the display pixel by asserting the scan signal to turn on the access transistor. The display pixel also includes a current source transistor that provides current to the organic light emitting diode to generate light.

[0006] The transistors in the pixels of an organic light emitting diode display may be subject to process, voltage and temperature (PVT) variations. Due to such variations, the transistor threshold voltage may vary between different display pixels. The variation in transistor threshold voltage may cause the display pixel to produce an amount of light that does not match the target image. It is in this context that the embodiments of this article are generated. Summary of the invention

[0007] An electronic device may include a display having an array of display pixels. The display pixels may be organic light emitting diode display pixels. Each display pixel may include an organic light emitting diode (OLED) that emits light, a drive transistor coupled in series with the OLED, a first emission transistor and a second emission transistor coupled in series with the drive transistor and the OLED, a gate voltage setting transistor coupled between a gate terminal and a drain terminal of the drive transistor, a single storage capacitor coupled across the gate terminal of the drive transistor and the anode terminal of the OLED, a data loading transistor coupled between the source terminal of the drive transistor and a data line, and an initialization transistor coupled to the anode terminal of the OLED.

[0008] The drive transistor, the gate voltage setting transistor, and the initialization transistor may be implemented as a semiconductor oxide transistor, while the emission transistor and the data loading transistor may be implemented as a p-type silicon transistor (e.g., a PMOS LTPS thin film transistor). Implementing the drive transistor as a semiconductor oxide transistor alleviates the drive transistor threshold voltage hysteresis to improve the first frame response at a high refresh rate, reduces the undesired brightness jump at a low refresh rate, and reduces image retention. Implementing the gate voltage setting transistor as a semiconductor oxide transistor reduces leakage at the gate terminal of the drive transistor. Implementing the initialization transistor as a semiconductor oxide transistor allows at least one of the initialization transistor and the emission transistor to be controlled by a shared emission signal to reduce routing complexity. In addition, having only two types of thin film transistors (e.g., only having semiconductor oxide transistors and p-type silicon transistors) reduces the total number of photolithography masks required, thereby helping to minimize manufacturing costs.

[0009] During normal operation, the display pixel may undergo an initialization phase during which the initialization transistor is turned on to reset the anode terminal of the OLED. The initialization phase may be followed by one or more on-bias stress phases during which the data loading transistor is activated to at least partially load some data voltage onto the drive transistor. The optional on-bias stress phase may help to further mitigate drive transistor hysteresis and improve first frame response. The on-bias stress phase may be followed by a threshold voltage sampling and data loading phase, followed by an emission phase. During the emission phase, the current flowing through the OLED will be independent of the drive transistor threshold voltage due to the elimination of the threshold voltage within the pixel.

[0010] Semiconductor oxide transistors such as semiconductor oxide drive transistors may be formed above silicon transistors. A storage capacitor may be stacked above the semiconductor oxide drive transistor so that the top plate of the storage capacitor at least partially covers the gate conductor of the semiconductor oxide drive transistor. Constructed in this manner, the storage capacitor provides electrical shielding to reduce pixel crosstalk while also providing light shielding to prevent stray light from affecting the operation of the semiconductor oxide drive transistor. If desired, any one or more of the semiconductor oxide transistors may have a dual gate configuration having a top gate conductor and a bottom gate conductor. The bottom gate conductor may serve as an additional light shield and may optionally be coupled to a source terminal or a gate terminal of the semiconductor oxide transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram of an illustrative electronic device with a display according to an embodiment.

[0012] Figure 2is a diagram of an exemplary display such as an organic light emitting diode display having an organic light emitting diode display pixel array according to an embodiment.

[0013] Figure 3A is a circuit diagram of an exemplary display pixel having a semiconducting oxide drive transistor according to an embodiment.

[0014] Figure 3B is to show the operation according to the embodiment Figure 3A A timing diagram of one suitable approach for display pixels is shown in FIG.

[0015] Figure 3C is shown according to the embodiment for driving Figure 3A Illustration of an exemplary arrangement of gate driver circuitry for a display pixel array of the type shown.

[0016] Figure 3D , Figure 3E and Figure 3F is to show the operation according to the embodiment Figure 3A Timing diagrams for various suitable modes for display pixels are shown.

[0017] Figure 4A is a circuit diagram of an exemplary display pixel having a semiconductor oxide drive transistor and a silicon initialization transistor according to an embodiment.

[0018] Figure 4B is to show the operation according to the embodiment Figure 4A A timing diagram of one suitable approach for display pixels is shown in FIG.

[0019] Figure 5A is a circuit diagram of an illustrative display pixel having an emission transistor and an initialization transistor controlled by a common emission signal according to an embodiment.

[0020] Figure 5B is to show the operation according to the embodiment Figure 5A A timing diagram of one suitable approach for display pixels is shown in FIG.

[0021] Figure 6 is a circuit diagram of an exemplary display pixel having an initialization transistor and an emission transistor controlled by a common emission signal according to an embodiment.

[0022] Fig. 7A is a circuit diagram of an exemplary display pixel controlled using two dedicated emission signals per row according to an embodiment.

[0023] Figure 7B is to show the operation according to the embodiment Fig. 7A A timing diagram of one suitable approach for display pixels is shown in FIG.

[0024] Fig. 8A is a circuit diagram of a portion of a display pixel having a semiconducting oxide drive transistor coupled to a storage capacitor according to an embodiment.

[0025] Figure 8B According to the implementation plan Fig. 8A A cross-sectional side view of a suitable arrangement of display pixels.

[0026] Figure 8C According to the implementation plan Fig. 8A 0026] A cross-sectional side view of another suitable arrangement for a display pixel in which a storage capacitor is stacked above a semiconducting oxide drive transistor.

[0027] Fig.8D is a top layout view showing how a bottom gate terminal of a semiconducting oxide drive transistor may be connected to its source terminal according to an embodiment.

[0028] Fig. 8E is a top layout view showing how a bottom gate terminal of a semiconducting oxide drive transistor may be connected to its top gate terminal according to an embodiment.

[0029] Fig. 9 According to the embodiment shown Figure 3A A cross-sectional side view of a portion of a display pixel in which two semiconductor oxide transistors are formed in different layers in the display stackup. DETAILED DESCRIPTION

[0030] Figure 1 An exemplary electronic device of the type that may have an organic light emitting diode (OLED) display is shown in FIG. Figure 1 As shown, the electronic device 10 may have a control circuit 11. The control circuit 11 may include storage and processing circuits for supporting the operation of the device 10. The storage and processing circuits may include storage devices, such as hard disk drive storage devices, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. The processing circuit in the control circuit 11 can be used to control the operation of the device 10. The processing circuit may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio codec chips, application-specific integrated circuits, programmable integrated circuits, etc.

[0031] Input-output circuitry in device 10, such as input-output devices 12, may be used to allow data to be provided to device 10, and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, click wheels, scroll wheels, track pads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user may control the operation of device 10 by providing commands via input-output devices 12 and may receive status information and other output from device 10 using the output resources of input-output devices 12.

[0032] Input-output devices 12 may include one or more displays, such as display 14. Display 14 may be a touch screen display that includes a touch sensor for acquiring touch input from a user, or display 14 may be insensitive to touch. The touch sensor of display 14 may be based on an array of capacitive touch sensor electrodes, an acoustic touch sensor structure, a resistive touch component, a force-based touch sensor structure, a light-based touch sensor, or other suitable touch sensor arrangements.

[0033] Control circuitry 11 may be used to run software, such as operating system code and application programs, on device 10. During operation of device 10, software running on control circuitry 11 may display images on display 14 in an input-output device.

[0034] Figure 2 is a diagram of an exemplary display such as an organic light emitting diode display 14 having an array of organic light emitting diode display pixels 22. Figure 2 As shown, display 14 may have one or more layers, such as substrate 24. Layers such as substrate 24 may be formed of a planar rectangular layer of material such as a planar glass layer. Display 14 may have a display pixel array 22 for displaying images to a user. Display pixel array 22 may be formed of rows and columns of display pixel structures on substrate 24. These structures may include thin film transistors, such as polysilicon thin film transistors, semiconductor oxide thin film transistors, etc. There may be any suitable number of rows and columns in the display pixel 22 array (e.g., ten or more, one hundred or more, or one thousand or more).

[0035] A display driver circuit, such as a display driver integrated circuit 16, may be coupled to a conductive path, such as a metal trace on substrate 24, using solder or a conductive adhesive. Display driver integrated circuit 16 (sometimes referred to as a timing controller chip) may include communication circuitry for communicating with system control circuitry via path 25. Path 25 may be formed by traces on a flexible printed circuit or other cable. System control circuitry may be located on a main logic board in an electronic device, such as a cellular phone, computer, television, set-top box, media player, portable electronic device, or other electronic device that is using display 14. During operation, system control circuitry may provide information to display driver integrated circuit 16 regarding an image to be displayed on display 14 via path 25. To display an image on display pixels 22, display driver integrated circuit 16 may provide clock signals and other control signals to display driver circuits, such as row driver circuit 18 and column driver circuit 20. Row driver circuit 18 and / or column driver circuit 20 may be formed by one or more integrated circuits and / or one or more thin film transistor circuits on substrate 24.

[0036] Row driver circuits 18 may be located on both the left and right edges of display 14, on only a single edge of display 14, or elsewhere in display 14. During operation, row driver circuits 18 may provide row control signals on horizontal lines 28 (sometimes referred to as row lines, “scan” lines, or “emission” lines). Thus, row driver circuits 18 may sometimes be referred to as scan line driver circuits or emission line driver circuits. Row driver circuits 18 may also be used to provide other row control signals, if desired.

[0037] Column driver circuits 20 may be used to provide data signals D from display driver integrated circuit 16 to a plurality of corresponding vertical lines 26. Column driver circuits 20 may sometimes be referred to as data line driver circuits or source driver circuits. Vertical lines 26 are sometimes referred to as data lines. During compensation operations, column driver circuits 20 may optionally use paths such as vertical lines 26 to provide reference voltages, initialization signals, or other suitable bias voltage signals. During programming operations, lines 26 are used to load display data into display pixels 22.

[0038] Each data line 26 is associated with a corresponding column of display pixels 22. Multiple groups of horizontal signal lines 28 extend horizontally through the display 14. Power paths and other lines may also provide signals to the pixels 22. Each group of horizontal signal lines 28 is associated with a corresponding row of display pixels 22. The number of horizontal signal lines in each row can be determined by the number of transistors in the display pixels 22 that are independently controlled by the horizontal signal lines. Display pixels of different configurations can be operated by different numbers of control lines, data lines, power lines, scan lines, emission lines, reference voltage lines, initialization lines, etc.

[0039] Row driver circuitry 18 may assert control signals on row lines 28 in display 14. For example, driver circuitry 18 may receive clock signals and other control signals from display driver integrated circuit 16 and may assert control signals in each row of display pixels 22 in response to the received signals. Rows of display pixels 22 may be processed sequentially, with processing for each frame of image data starting at the top of the display pixel array and ending at the bottom of the array (as an example). When a scan line in a row is asserted, control signals and data signals provided by circuitry 16 to column driver circuitry 20 instruct circuitry 20 to demultiplex and drive the associated data signal D onto data line 26, thereby programming the display pixels in the row with the display data appearing on data line D. The display pixels are then able to display the loaded display data.

[0040] In practice, transistors in display pixels 22 may be subject to process, voltage and temperature (PVT) variations. Due to such variations, the transistor threshold voltage between different display pixels 22 may vary and may cause the pixel 22 to produce an amount of light that does not match the desired image. FIG. 3 is a circuit diagram of an exemplary organic light emitting diode display pixel 22 in a display 14, which is operable to support "in-pixel" threshold voltage compensation (e.g., a pixel configured to internally offset any threshold voltage dependency without any external current sensing operation). As shown in FIG. 3, the display pixel 22 may include an organic light emitting diode such as OLED 304, a storage capacitor such as capacitor Cst1, a drive transistor such as transistor Tdrive, a gate voltage setting transistor such as transistor Tgd coupled across the gate (G) and drain (D) terminals of the drive transistor, a first emission transistor such as transistor Tem1, a second emission transistor such as transistor Tem2, a data loading transistor such as transistor Tdata, and an initialization transistor such as transistor Tini.

[0041] The pixel 22 may also be coupled to a positive power supply terminal 300 on which a positive power supply voltage VDDEL is provided and a ground power supply terminal 302 on which a ground power supply voltage VSSEL is provided. The positive power supply voltage VDDEL may be 3V, 4V, 5V, 6V, 7V, 2V to 8V, or any suitable positive power supply voltage level. The ground power supply voltage VSSEL may be 0V, +1V, -1V, -2V, -3V, -4V, -5V, -6V, -7V, or any suitable ground or negative power supply voltage level. The drive transistor Tdrive, emission transistors Tem1 and Tem2, and a diode 304 may be coupled in series between power lines 300 and 302. The drive transistor Tdrive may have a drain terminal (labeled Node1), a gate terminal (labeled Node2), and a source terminal (labeled Node3). In Figure 3AIn the example of , the first emission transistor Tem1 may be coupled between the power supply terminal 300 and Node1, and the second emission transistor Tem2 may be coupled between Node3 and the anode terminal of the diode 304. The terms "source" terminal and "drain" terminal of a transistor are sometimes used interchangeably, and thus may be referred to as "source-drain" terminals.

[0042] The first emission transistor Tem1 has a gate terminal configured to receive an emission signal EMEM(n+1) via an emission line 312', and the second emission transistor Tem2 has a gate terminal configured to receive an emission signal EM(n) via an emission line 312. The symbol "(n)" indicates that the corresponding signal is generated using a gate driver associated with that row of display pixels, while the symbol "(n+1)" indicates that the corresponding signal is generated using a gate driver associated with a subsequent row in the display pixel array. Both emission transistors Tem1 and Tem2 must be turned on at the same time in order for the emission current to flow through the drive transistor to the diode 304. The state of the drive transistor Tdrive controls the amount of current that flows from the terminal 300 to the terminal 302 through the diode 304, and therefore controls the amount of light emitted from the diode 304 of the display pixel 22. The organic light emitting diode 304 may have an associated parasitic capacitance C OLED (not shown).

[0043] Storage capacitor Cst1 may have a first terminal coupled to Node2 and a second terminal coupled to the anode terminal of diode 304. Image data loaded into pixel 22 may be at least partially stored on pixel 22 by using capacitor Cst1 to hold charge throughout the emission phase.

[0044] The transistor Tgd may have a drain terminal coupled to Node1, a gate terminal configured to receive a scan signal SCAN1(n) via a first scan line 314-1, and a source terminal coupled to Node2. The signal SCAN1(n) may be asserted (e.g., driven high or temporarily pulsed high) to turn on the n-type transistor Tgd, thereby short-circuiting the drain terminal and the gate terminal of the transistor Tdrive. The transistor configuration in which both the gate terminal and the drain terminal are short-circuited is sometimes referred to as a "diode-connected" arrangement. Therefore, the gate-setting transistor Tgd may sometimes be referred to as a diode-connected transistor.

[0045] The data loading transistor Tdata may have a source terminal coupled to the data line 310, a gate terminal configured to receive the scan control signal SCAN2(n) via the second scan line 314-2, and a drain terminal coupled to Node3. Configured in this manner, the signal SCAN2(n) may be asserted (e.g., driven low or temporarily pulsed low) to turn on the transistor Tdata, thereby allowing the data signal from the data line 310 to be loaded onto Node3.

[0046] Initialization transistor Tini may have a drain terminal coupled to the anode terminal of diode 304, a gate terminal configured to receive transmit signal EM(n) via transmit line 312, and a source terminal coupled to initialization line 308. Initialization line 308 may be used to provide an initialization voltage Vini (e.g., a negative voltage such as -1V, -2V, -3V, -4V, -5V, -6V, or other suitable voltage) to help turn off diode 304 when diode 304 is not in use. Configured in this manner, transmit signal EM(n) may be driven high or temporarily pulsed high to turn on transistor Tini, thereby setting the anode terminal to initialization voltage Vini.

[0047] exist Figure 3A In the example of , the gate setting transistor Tgd, the drive transistor Tdrive, and the initialization transistor Tini can be implemented using semiconductor oxide transistors (e.g., transistors having an n-type channel formed by a semiconductor oxide such as indium gallium zinc oxide or IGZO or indium tin zinc oxide or ITZO). The remaining transistors Tem1, Tem2, and Tdata can be thin film transistors (TFTs) formed by semiconductors such as silicon (e.g., polysilicon channels deposited using a low temperature process, sometimes referred to as LTPS or low temperature polysilicon). The semiconductor oxide transistors in pixel 22 are represented by circles surrounding those transistors. Semiconductor oxide transistors exhibit relatively lower leakage than silicon transistors, so implementing transistor Tgd as a semiconductor oxide transistor can help prevent current from leaking at the gate terminal of transistor Tdrive and will help reduce flicker.

[0048] According to an embodiment, implementing the drive transistor Tdrive as a semiconductor oxide transistor can help provide an improved first frame response for high refresh rate operation (e.g., a display operating at a refresh rate of at least 60 Hz, at least 120 Hz, at least 240 Hz, etc.), can help reduce undesirable brightness jumps for low refresh rate operation (e.g., a display operating at a refresh rate of 1 Hz, 2 Hz, 1 Hz-10 Hz, less than 30 Hz, less than 60 Hz, or other low rates), and can help reduce image retention (i.e., the phenomenon in which a current image refuses to change to a new image).

[0049] As described above, the amount of emission current flowing through each display pixel depends on the threshold voltage of the drive transistor. The drive transistor threshold voltage may also vary according to the current value of the gate-to-source voltage Vgs of the drive transistor. For example, when Vgs increases from low to high, the drive transistor threshold voltage may exhibit a first average level, but when Vgs decreases from high to low, it may exhibit a second average level different from the first average level, thereby producing a different current-voltage (IV) characteristic curve. This dependence of the threshold voltage on the actual Vgs value is sometimes referred to as transistor "hysteresis", and if not careful, the hysteresis may adversely affect the performance of the display pixel.

[0050] Since the threshold voltage of transistor Tdrive can experience hysteresis, forming the drive transistor as a top-gate semiconductor oxide transistor can help reduce hysteresis (e.g., a top-gate IGZO transistor experiences less threshold voltage hysteresis than a silicon transistor). In this case, it may be advantageous to form all of the semiconductor oxide transistors Tdrive, Tgd, and Tini as top-gate oxide transistors to help simplify the manufacturing steps. Semiconductor oxide transistors exhibit greater current sensitivity to temperature changes than silicon transistors, so having a semiconductor oxide drive transistor Figure 3A Pixels 22 of the type shown are used in electronic devices that require a well-controlled or manageable temperature distribution across the display.

[0051] In addition, implementing transistor Tini as a semiconductor oxide transistor enables transistors Tem2 and Tini to be controlled by the same signal EM(n), because driving EM(n) low turns on Tem2 while turning off Tini, and vice versa. Sharing the signal EM(n) enables fewer row control lines to be formed, which reduces routing complexity. Forming pixel 22 using only n-type semiconductor oxide transistors and only p-type silicon transistors eliminates the need to form complementary n-type silicon transistors, which can help significantly reduce the number of masks required to manufacture pixel 22 and reduce costs.

[0052] From display driver circuits such as Figure 2 The control signals of the row driver circuit 18 are provided to the control terminals, such as the row control lines 312, 312', 314-1 and 314-2. The semiconductor oxide transistors in the pixel 22 (e.g., transistors Tdrive, Tgd and Tini) are n-channel devices and are "high-state active" devices that are turned on by asserting or driving their corresponding gate control voltages high. In contrast, the p-channel silicon transistors in the pixel 22 (e.g., transistors Tem1, Tem2 and Tdata) are "low-state active" devices that are turned on by asserting or driving their corresponding gate control voltages low.

[0053] Combination Figure 3A The pixel structures shown and described are merely illustrative and are not intended to limit the scope of the embodiments of the present invention. If desired, any one or more of the transistors Tem1, Tem2, and Tdata may be implemented as n-type silicon transistors or semiconductor oxide transistors; any one or more of the transistors Tdrive, Tgd, and Tini may be implemented as n-type or p-type silicon transistors; the pixel 22 may include one or more additional capacitors; the pixel 22 may include more than six TFTs or less than six TFTs; the pixel 22 may be controlled by more than two or less than two scanning control lines; the pixel 22 may be controlled by more than two or less than two emission control lines; to name just a few alternative arrangements.

[0054] During a data refresh cycle, the display pixel 22 can operate in at least four types of phases, such as: (1) an initialization / reset phase, (2) a conduction bias stress phase, (3) a threshold voltage sampling and data programming phase, and (4) an emission phase - not necessarily in this order. Figure 3B is a timing diagram illustrating relevant signal waveforms applicable to display pixels 22 for a given row of pixels (n) during a data refresh cycle.

[0055] Before time t1, the emission signals EM(n) and EM(n+1) are both low, thereby turning on the emission transistors Tem1 and Tem2, so that the pixel 22 is in the emission phase. At time t1, the signal EM(n) is driven high, thereby turning off the transistor Tem2 and temporarily stopping the emission. Driving high EM(n) also turns on the transistor Tini to load the initialization voltage Vini onto the anode terminal of the diode 304 (that is, the anode terminal is set to Vini). Therefore, the period from time t1 to t2 is sometimes referred to as the "initialization" or "anode reset" phase. During the anode reset period, the signal SCAN1(n) is also pulsed high for less than a row time (<1H), thereby turning on the transistor Tgd. Since the transistor Tem1 is still turned on, the activation transistor Tgd will pull Node2 up to VDDEL. Operating in this way, at the end of the initialization phase, the voltage across the storage capacitor Cst1 will be reset to a predetermined voltage difference (VDDEL-Vini).

[0056] In some cases, the drive transistor threshold voltage Vth may shift, such as when the display 14 transitions from a black image to a white image or when transitioning from one grayscale level to another. This shift in the drive transistor Vth (sometimes referred to herein as thin film transistor "hysteresis") can result in a reduction in brightness that is otherwise referred to as "first frame dimming." For example, a saturation current Ids waveform as a function of the Vgs of the drive transistor for a black frame may be slightly offset from a target Ids waveform as a function of the Vgs of the drive transistor for a white frame. Without performing the on-bias stress, the sampled Vth will correspond to the black frame and will therefore deviate from the target Ids waveform by a considerable margin. By performing the on-bias stress, the sampled Vth will correspond to Vdata and will therefore be closer to the target curve. Performing an on-bias stress phase using a data signal to bias the Vgs of the drive transistor prior to sampling Vth can therefore help mitigate hysteresis and improve first frame response. Thus, the on-bias stress phase can be defined as the operation of applying a suitable bias voltage directly to the drive transistor during the non-emitting phase (e.g., such as by turning on a data loading transistor or turning on an initialization transistor). At time t3, signal SCAN2(n) is driven low, thereby turning on transistor Tdata to load some non-zero data value (e.g., data intended for at least some previous rows in the display pixel array, such as rows (n-2) and (n-1)) onto Node3. Pre-biasing the source terminal of the drive transistor prior to the actual data programming cycle between t4-t5 can help mitigate Vth hysteresis and prevent first frame dimming.

[0057] At time t4, signal SCAN1 (n) is pulsed high, thereby temporarily activating transistor Tgd. Since signal SCAN2 (n) remains low during this period, transistor Tdata loads the actual data signal intended for row n into the corresponding pixel 22, so that the voltage at Node3 will be equal to Vdata. Since the drive transistor is currently in a diode connection configuration (because Tgd is turned on to short the gate terminal and the drain terminal), the drive transistor pulls its gate voltage down to (Vdata + Vth), where Vth represents the threshold voltage of the drive transistor. At this point, the voltage across capacitor Cst1 is now set to (Vdata + Vth-Vini). When operating in this manner, the drive transistor threshold voltage Vth has been successfully sampled, and Vdata has been successfully programmed / written to the storage capacitor Cst1. Therefore, the time period from t4 to t5 can be referred to as the Vth sampling and data programming phase. At time t5, signal SCAN1(n) is driven low to turn off transistor Tgd, and signal SCAN2(n) is driven high to turn off transistor Tdata, terminating the Vth sampling and data writing phase.

[0058] At time t6, signals EM(n) and EM(n+1) are both low, turning on transistors Tem1 and Tem1, and thus starting the emission phase. During the emission period, Node3 can be pulled up to VDDEL. Therefore, the resulting gate-to-source voltage Vgs of transistor Tdrive will be some function of (Vdata+Vth–Vini) sampled by storage capacitor Cst1. Since the final emission current is proportional to Vgs minus Vth, the emission current will be independent of Vth because (Vgs-Vth) will equal (Vdata+Vth–Vini–Vth), where Vth cancels. This operating scheme of internally sampling and canceling the drive transistor threshold voltage is sometimes referred to as "in-pixel" threshold voltage compensation.

[0059] Figure 3A An example of involves reusing transmit signals from adjacent rows (eg, signal EM(n+1) may be borrowed and used in row n). Figure 3C is shown for driving Figure 3A Schematic diagram of an exemplary arrangement of gate driver circuitry for a display pixel array of the type shown. Figure 3C As shown, each row may have its own dedicated SCAN1 (SC1) and SCAN2 (SC2) driver circuits. However, the EM driver circuits may be shared between adjacent rows. Figure 3C In the example of FIG. 1 , the EM(n+1) driver circuit may control both the nth row and the (n+1)th row; the EM(n+2) driver circuit may drive both the (n+1)th row and the (n+2)th row; the EM(n+3) driver may be routed to both the (n+2)th row and the (n+3)th row; etc. Using such a staggered sharing pattern to drive the display pixel array may help reduce the display bezel width.

[0060] As above combined Figure 3A As mentioned, implementing the drive transistor as a semiconducting oxide transistor may already help to mitigate any undesirable hysteresis. Figure 3B The on-bias stress (OBS) phase shown can help further suppress any remaining hysteresis. In cases where hysteresis has been managed at acceptable levels by using a semiconductor oxide drive transistor, the on-bias stress phase can be skipped to help increase the speed of the overall refresh operation and reduce power consumption. Figure 3D It is shown Figure 3A A timing diagram of another suitable manner of operating pixel 22 of the type shown is shown. Figure 3A compared to, Figure 3D The operation does not include the on-bias stress phase.

[0061] Before time t1, the emission signals EM(n) and EM(n+1) are both low, thereby turning on the emission transistors Tem1 and Tem2, so that the pixel 22 is in the emission phase. At time t1, the signal EM(n) is driven high, thereby turning off the transistor Tem2 and temporarily stopping the emission. The driving high signal EM(n) also turns on the transistor Tini to load the initialization voltage Vini to the anode terminal of the diode 304 (that is, the anode terminal is set to Vini). Therefore, the period from time t1 to t2 is sometimes referred to as the "initialization" or "anode reset" phase. During the anode reset period, the signal SCAN1(n) is also raised to high, thereby turning on the transistor Tgd.

[0062] At time t3, signal SCAN2(n) is pulsed low, turning on transistor Tdata to load the desired data value onto Node3. Since signal SCAN1(n) remains high during this period, the drive transistor remains in a diode connection configuration, so both the data signal Vdata and the drive transistor threshold voltage Vth will be sampled onto storage capacitor Cst1. At time t4, signal SCAN1(n) is driven low to turn off transistor Tgd, while signal SCAN2(n) is driven high to turn off transistor Tdata, terminating the Vth sampling and data programming phase. At time t5, signals EM(n) and EM(n+1) are both low to start the emission phase. Figure 3D In the example of FIG. 4 , signal SCAN1(n) remains high from the beginning of the initialization phase until the end of the data programming phase (ie, from time t1 until t4 ).

[0063] Figure 3E is a timing diagram illustrating another suitable manner for operating pixel 22 during a data refresh cycle. Figure 3B The operation shown, Figure 3E The operation shown also includes a turn-on bias stress phase, but is implemented using different scan line behaviors. Before time t1, the emission signals EM(n) and EM(n+1) are both low, so the emission transistors Tem1 and Tem2 are both turned on during the emission phase. At time t1, the signal EM(n) is driven high, thereby turning off the transistor Tem2 and temporarily stopping the emission. Driving high EM(n) also turns on the transistor Tini to load the initialization voltage Vini onto the anode terminal of the diode 304 (that is, the anode terminal is set to Vini). Therefore, the period from time t1 to t2 is sometimes referred to as the "initialization" or "anode reset" phase. During the anode reset period, the signal SCAN1(n) is also pulsed high, thereby turning on the transistor Tgd. Since the transistor Tem1 is still turned on, the activation transistor Tgd will pull Node2 up to VDDEL.

[0064] At time t3, signal SCAN2(n) is pulsed low, turning on transistor Tdata to load some non-zero data value (e.g., data signals intended for at least some previous rows in the display pixel array) onto Node3. Pre-biasing the source terminal of the drive transistor prior to the actual data programming cycle between t4-t5 can help mitigate Vth hysteresis and improve first frame response. This on-bias stress (OBS) phase can last from the start of the SCAN2(n) pulse at time t3 until the signal SCAN1(n) is driven high at time t4.

[0065] At time t4, signal SCAN1(n) is pulsed high, thereby temporarily activating transistor Tgd. At t5, signal SCAN2(n) is pulsed low to perform the Vth sampling and data writing phase. When signal SCAN2(n) is low from time t5-t6, transistor Tdata is turned on to load the actual data signal intended for row n into the corresponding pixel 22, so that the voltage at Node3 will be equal to Vdata. Since the drive transistor is currently in a diode connection configuration (because Tgd is turned on to short the gate terminal and the drain terminal), the drive transistor pulls its gate voltage down to (Vdata+Vth), where Vth represents the threshold voltage of the drive transistor. At this point, the voltage across capacitor Cst1 is now set to (Vdata+Vth-Vini) and starts from the in-pixel Vth compensation. At time t7, signals EM(n) and EM(n+1) are both low to start the emission phase.

[0066] Figure 3F It is shown Figure 3A A timing diagram of another suitable way of operating pixel 22 of the type shown. Figure 3F The operation is similar to combining Figure 3E Operation as shown and described, but with the Vth sampling and data programming phase immediately following the on-bias stress phase. This can be accomplished by aligning the second low pulse in SCAN2(n) with the rising edge of signal SCAN1(n) (eg, see time t*).

[0067] Figure 4A is a circuit diagram showing another suitable arrangement of display pixels 22 . Figure 4A The pixel structure is similar to the combination of Figure 3A The pixel structure shown and described above, but the initialization transistor is implemented using a p-type silicon transistor instead. Figure 4AAs shown, the initialization transistor, such as transistor Tini', is a p-channel silicon transistor. Since the initialization transistor Tini' should not be turned on during the emission phase, the initialization transistor Tini' cannot be controlled by the signal EM(n), but is controlled using an inverted version of the signal EM(n) represented as signal EMB(n). When configured in this manner, transistors Tem2 and Tini' will never be turned on at the same time (for example, when transistor Tem2 is turned on, transistor Tini' will be turned off, and vice versa). The remaining components and connections of the pixel 22 are similar to those already combined Figure 3A The components and connections are described and do not need to be repeated in detail.

[0068] Figure 4B It shows the operation Figure 4A A timing diagram of one suitable approach for a display pixel is shown. Figure 4B The waveform is similar to the combined Figure 4A The waveform shown and described above, but with the additional signal EMB(n). Figure 4B As shown, signal EMB(n) is an inverted version of signal EM(n). Configured in this manner, transistor Tinit' will be turned on by a low signal EMB(n) from the beginning of the initialization period until signal EMB(n) is driven high at time t' before the emission phase. The initialization / anode reset phase, the OBS phase, and the Vth sampling and data programming phase can be combined as described above. Figure 3B The above is performed in the manner described and need not be repeated in detail.

[0069] Figure 5A is a circuit diagram showing yet another suitable implementation of a display pixel 22 having at least two initialization transistors. Figure 5A As shown, the pixel 22 may include a transistor Tem1, a transistor Tdrive, a transistor Tem2, and a diode 304 coupled in series between power supply terminals 300 and 302. The storage capacitor Cst1 may be coupled between Node2 and the anode terminal of the diode 304. The transistor Tgd controlled by the signal SCAN1(n) on the scan line 314-1 may be coupled across Node1 and Node2. The transistor Tdata controlled by the signal SCAN2(n) on the scan line 314-2 may be coupled to Node3. The pixel 22 may include a first initialization transistor Tini1 coupled to the anode terminal of the diode 304. Figure 5A In the example of FIG. 1 , transistors Tgd, Tdrive, and Tini1 may all be implemented as semiconductor oxide transistors (see the transistors surrounded by circles), while all the remaining transistors are implemented as p-type silicon transistors. However, this configuration is merely illustrative. In general, Figure 5AAny portion of pixel 22 may be implemented as a semiconductor oxide transistor and / or an n-type / p-type silicon transistor.

[0070] exist Figure 5A In the example of , transistors Tem1, Tem2, and Tini1 have gate terminals that are all configured to receive an emission signal EM(n). Sharing the signal EM(n) among the three transistors in this manner eliminates the need to have another emission signal in row n. However, when arranged in this manner, transistor Tem1 cannot pull Node1 to VDDEL during the non-emission phase when the signal EM(n) is driven high. Therefore, the pixel 22 may have a second initialization transistor Tin2 coupled between the power terminal 300 and Node1. The second initialization transistor Tin2 may be a p-type silicon transistor like the remaining silicon transistors within the pixel, and may be controlled by a signal SCAN2(n-1) routed from the previous pixel row via routing path 314-2'. The signal SCAN2(n-1) may be pulsed low during the non-emission phase to help set Node1 to VDDEL during the initialization / anode reset phase. In Figure 5B The timing diagram shows the operation Figure 5A One such way of implementing pixel 22 .

[0071] Before time t0, the emission signal EM (n) is low, thereby turning on the emission transistors Tem1 and Tem2, so that the pixel 22 is in the emission stage. At time t0, the signal EM (n) is driven high to temporarily stop the emission. At time t1, the signal SCAN1 (n) is driven high to turn on the transistor Tgd, and the signal SCAN2 (n-1) is pulse modulated to be low to temporarily activate the second initialization transistor Tini2. In this way, both the transistors Tgd and Tini2 are turned on to initialize the pixel 22 by setting Node1 to the positive power supply voltage VDDEL. During this period, the signal EM (n) is also high, which enables the first initialization transistor Tini1 to load the initialization voltage Vini to the anode terminal of the diode 304 (that is, the anode terminal is set to Vini). Therefore, the period from time t1 to t2 is sometimes referred to as the "initialization" or "anode reset" stage.

[0072] At time t3, signal SCAN2(n) is pulsed low, turning on transistor Tdata to load the desired data value D(n) onto Node3. Since signal SCAN1(n) remains high during this period, the drive transistor remains in a diode connection configuration, so both the data signal Vdata and the drive transistor threshold voltage Vth will be sampled onto storage capacitor Cst1. At time t4, signal SCAN1(n) is driven low to turn off transistor Tgd, while signal SCAN2(n) is driven high to turn off transistor Tdata, thereby ending the Vth sampling and data programming phase. At time t5, signal EM(n) is driven low to start the emission phase.

[0073] exist Figure 5B In the example of , the Vth sampling and data programming phases are immediately followed by the initialization phase. This is exemplary only and is not intended to limit the scope of the embodiments of the present invention. If desired, one or more OBS phases may be inserted between the initialization phase and the data programming phase, and / or one or more OBS phases may be inserted between the data programming phase and the emission phase.

[0074] Figure 6 is a circuit diagram showing another suitable arrangement of display pixels 22 . Figure 6 The pixel structure is similar to the combination of Figure 5A The pixel structure shown and described above, but the first initialization transistor Tini' is implemented using a p-type silicon transistor instead. Figure 6 As shown, the initialization transistor, such as transistor Tini', is a p-channel silicon transistor. Since the initialization transistor Tini' should not be turned on during the emission phase, the initialization transistor Tini' should no longer be controlled by the signal EM(n), but rather by an inverted version of the signal EM(n) represented as signal EMB(n). When configured in this manner, transistors Tem2 and Tini' will never be turned on at the same time (e.g., when transistor Tem2 is turned on, transistor Tini' will be turned off, and vice versa). The remaining components and connections of the pixel 22 are similar to those already incorporated. Figure 5A The components and connections are described and need not be repeated in detail to avoid obscuring the embodiments of the invention. Figure 6 The operation of the pixel 22 is Figure 5B The timing diagrams shown are identical, except that an additional inverted emission signal EMB(n) controls transistor Tini1 ′.

[0075] Fig. 7A Another suitable arrangement of display pixels 22 is shown. Fig. 7A The display pixel 22 has a Figure 3AThe pixel structure is similar to that shown in FIG. 1 , except that the first emission transistor Tem1 is configured to receive the second emission signal EM2(n) with the emission line 312″. In other words, row n has two dedicated emission lines 312 and 312″. The remaining components and connections of the pixel 22 are similar to those already combined. Figure 3A The components and connections described are the same and need not be repeated in detail in order not to obscure the embodiments of the invention.

[0076] Figure 7B is to show the operation according to the embodiment Fig. 7A A timing diagram of one suitable approach for a display pixel is shown in . Prior to time t1 , emission signals EM1 ( n ) and EM2 ( n ) are both low, so transistors Tem1 and Tem2 are both conductive, allowing emission current to flow from transistor Tdrive down through diode 304 .

[0077] The initialization / anode reset phase occurs from time t1 to t2. At time t1, the signal EM1(n) is driven high for ten row cycles (10H) to turn off the second emission transistor Tem2, while the signal SCAN1(n) is driven high for two row cycles (2H) to turn on the gate setting transistor Tgd. Since the signal EM2(n) is still low, the transistor Tem1 is still turned on, which pulls Node2 up to VDDEL. During this period, the high EM1(n) signal also turns on the transistor Tini, which is loaded to the anode terminal of the diode 304 at the initialization voltage Vini. The initialization / AR reset phase terminates when the signal EM2(n) is driven high for up to four row cycles (4H) at time t2 to disable the transistor Tem1.

[0078] The on-bias stress (OBS) phase occurs from time t3 to t4. At time t3, signal SCAN2(n) is pulsed low to temporarily activate transistor Tdata, thereby loading some non-zero data value onto Node3. Vth and data sampling has not yet occurred, with transistor Tgd currently in the off state (i.e., Node2 is still at the previously initialized level of VDDEL). As described above in conjunction with Figure 3B As described above, performing pre-stress in this manner can help alleviate drive transistor Vth hysteresis and improve first frame response.

[0079] The Vth sampling and data writing phase occurs from time t5 to t6. At time t5, signal SCAN2(n) is high, and signal EM2(n) is driven high for four row cycles (4H), while signal SCAN1(n) is high. Operating in this manner, when transistor Tem1 is turned off (e.g., thereby allowing Node1 to change voltage levels) and when transistor Tgd is turned on to place transistor Tdrive in a diode connection configuration (e.g., thereby biasing Node1 and Node2 to [Vdata+Vth]), the desired data signal intended for row n can be loaded onto Node3 using transistor Tdata. Thus, at the end of the data programming phase at time t6, the values ​​of Vdata and Vth will be sampled onto storage capacitor Cst1. At time t7, signals EM1(n) and EM2(n) are both driven low, and a corresponding amount of emission current will be allowed to flow through OLED 304.

[0080] Fig. 8A FIG. 2 is a circuit diagram showing only a portion of a display pixel 22. Fig. 8A As shown, the pixel 22 may include at least the OLED 304, a transistor Tdrive (e.g., a drive transistor implemented as a semiconductor oxide transistor), a storage capacitor Cst1 coupled across the gate terminal of the drive transistor and the anode terminal of the OLED 304, and an emission transistor Tem (e.g., a transistor implemented as a p-type silicon transistor) coupled in series with the drive transistor and the OLED 304. In general, the pixel 22 may include an additional transistor coupled to the gate terminal of the drive transistor, to the drain terminal of the drive transistor, to the source terminal of the drive transistor, and / or to the anode terminal of the OLED (as indicated by the ellipse). In general, the first terminal of the storage capacitor (i.e., the terminal connected to the gate terminal of the transistor Tdrive) may be considered a high impedance node because no current can actually flow into the gate terminal of the transistor Tdrive, while the second terminal of the storage capacitor (i.e., the terminal connected to the anode terminal of the OLED) may be considered a low impedance node because it sits along the path of the emission current.

[0081] Figure 8B It is shown Fig. 8A A cross-sectional side view of a suitable arrangement of display pixels 22 is shown. Figure 8BAs shown, the pixel 22 may include a substrate such as a polyimide substrate 800, one or more buffer layers 802 formed on the substrate, an active silicon material such as an LTPS material 804 formed on the buffer layer 802, a first gate insulating (GI1) layer 806 formed on the silicon material, a first gate conductor (GE1) layer 808 formed on the first gate insulating layer 806, a first interlayer dielectric (ILD1) film 810 formed on the first gate conductor layer 808, and a second gate conductor (GE2) formed on the layer 810. layer 812, a second interlayer dielectric (ILD2) film 814 formed above the second gate conductor layer 812, an active semiconductor oxide material such as an IGZO material 816 formed on the layer 814, a second gate insulation (GI2) layer 818 formed above the semiconductor oxide (IGZO) material 816, an oxide gate (OxGE) layer 820 formed above the second gate insulation layer 818, and a third interlayer dielectric (Ox-ILD) film 822 formed above the oxide gate layer 820 and the capping layer 814.

[0082] exist Figure 8B In the example of , at least one planarization layer PLN is formed above layer 822. However, this arrangement is merely exemplary and is not intended to limit the scope of the embodiments of the present invention. If desired, at least two planarization layers may be implemented in the entire display stack. Such dual planarization layer structures that can be used are described in detail in Ono et al. (co-owned U.S. patent application No. 15 / 729,330 filed on October 10, 2017), which is incorporated herein by reference in its entirety. The anode terminal may be formed on one or more planarization layers PLN. The pixel defining layer PDL may be formed above the anode layer. Pixel 22 may include other pixel structures not shown and described herein, such as an emission layer, a cathode layer, and an encapsulation layer, so as not to obscure the embodiments of the present invention.

[0083] exist Figure 8B In the stacked structure of , the semiconductor oxide transistor Tdrive is formed above the silicon transistor Tem. The drive transistor Tdrive may also have a bottom gate light shield formed using layer 812. Specifically, the storage capacitor Cst1 has a first terminal implemented using layer 808 and a second terminal implemented using layer 812. The top gate conductor 820 of the transistor Tdrive is coupled to the first terminal of the storage capacitor, as schematically shown by dashed paths 890-1 and 890-2. The second terminal of the storage capacitor is coupled to the transistor Tem and the anode terminal through the associated source-drain contact vias.

[0084] exist Figure 8BIn the arrangement of , a large parasitic capacitance Cx may exist between the gate conductor 820 of transistor Tdrive and the anode terminal of an adjacent pixel 22'. This parasitic capacitance may cause undesirable crosstalk between adjacent pixels. Pixel crosstalk generated in this manner may disturb the voltage at the gate terminal of transistor Tdrive, which is particularly susceptible to noise since transistor Tdrive is a high impedance node. Therefore, it is desirable to provide an improved method for mitigating pixel crosstalk at the gate terminal of a semiconductor oxide transistor Tdrive.

[0085] According to the implementation scheme, Figure 8C 1 shows a cross section in which a storage capacitor is stacked on top of a semiconductor oxide drive transistor. Figure 8C As shown, the pixel 22 may include a substrate / carrier such as a polyimide substrate 800, one or more buffer layers 802 formed on the substrate, an active silicon material such as an LTPS material 804 formed on the buffer layer 802, a first gate insulating (GI1) layer 806 formed on the silicon material 804, a first gate conductor (GE1) layer 808 formed on the first gate insulating layer 806, an interlayer dielectric (ILD) film 811 formed on the first gate conductor layer 808, and an active semiconductor oxide material such as IGZO formed on the layer 811. material 816, a second gate insulating (GI2) layer 818 formed over the semiconductor oxide IGZO material 816, an oxide gate (OxGE) layer 820 formed over the second gate insulating layer 818, a first oxide interlayer dielectric (Ox-ILD1) film 822 formed over the oxide gate layer 820 and the capping layer 808, another gate conductor (GE2) layer 823 formed on the layer 822, and a second oxide interlayer dielectric (Ox-ILD2) film 825 formed over the gate layer 823 and the capping layer 822. Layer 811 is sometimes referred to as an oxide buffer layer.

[0086] exist Figure 8B In the example of , at least one planarization layer PLN is formed above layer 825. However, this arrangement is merely exemplary and is not intended to limit the scope of the embodiments of the present invention. If desired, at least two planarization layers may be implemented in the entire display stack. Such dual planarization layer structures that can be used are described in detail in Ono et al. (co-owned U.S. patent application No. 15 / 729,330 filed on October 10, 2017), which is incorporated herein by reference in its entirety. The anode terminal may be formed on one or more planarization layers PLN. The pixel defining layer PDL may be formed above the anode layer. Pixel 22 may include other pixel structures not shown and described herein, such as an emission layer, a cathode layer, and an encapsulation layer, so as not to obscure the embodiments of the present invention.

[0087] exist Figure 8CIn the stacked structure of 808, the semiconductor oxide transistor Tdrive is formed above the silicon transistor Tem. The drive transistor Tdrive may also have a bottom gate structure formed using layer 808. If desired, the bottom gate structure may be used as a light shield and / or an active bottom gate in a dual-gate semiconductor oxide transistor. In one suitable arrangement, the bottom gate conductor may be shorted to the associated source terminal of the drive transistor (see, e.g., Fig. 8A 880-1 in ) or may be connected to the associated gate terminal of the drive transistor (see e.g. Fig. 8A The bottom gate structure of the semiconductor oxide drive transistor and the top gate conductor of the silicon transistor Tem may also be formed from the same conductive layer (eg, using layer 808).

[0088] Fig.8D is a top layout view showing how the bottom gate terminal of a semiconductor oxide drive transistor can be connected to its source terminal. Fig.8D As shown, the source of transistor Tdrive can be coupled to its bottom gate structure GE1 by forming contact holes 830 and 832, as shown by the dashed connection path 880-1. Contact hole 832 can be manufactured simultaneously with contact hole 830. Layer 834 can represent the source terminal of transistor Tdrive. Layer 808 can represent the bottom gate layer of transistor Tdrive. Layer 816 can represent a semiconductor oxide material (e.g., IGZO, ITZO, etc.). Layer 840 can represent a GE2 layer, which can be connected to the source of transistor Tdrive during the emission phase. Layer 820 can represent the top gate conductor of transistor Tdrive. Layer 842 can represent the drain terminal of transistor Tdrive. Layer 844 can represent the gate terminal of transistor Tdrive.

[0089] Fig. 8E is a top layout view showing how the bottom gate terminal of a semiconductor oxide drive transistor can be connected to its top gate terminal. Fig. 8E As shown, the top gate structure of transistor Tdrive can be coupled to its bottom gate structure by forming contact holes 830 and 832, as shown by the dashed line connection path 880-2. Contact hole 832 can be manufactured simultaneously with contact hole 830. Layer 834 can represent the source terminal of transistor Tdrive. Layer 808 can represent the bottom gate layer of transistor Tdrive. Layer 816 can represent a semiconductor oxide material (e.g., IGZO, ITZO, etc.). Layer 840 can represent a GE2 layer. Layer 820 can represent the top gate conductor of transistor Tdrive. Layer 842 can represent the drain terminal of transistor Tdrive. Layer 844 can represent the gate terminal of transistor Tdrive.

[0090] See again Figure 8C, the storage capacitor Cst1 can be stacked above the semiconductor oxide transistor Tdrive. Configured in this manner, the gate layer 820 serves as both the gate conductor of the transistor Tdrive and the bottom plate of the capacitor Cst1. The topmost gate layer 823 can serve as the top plate of the capacitor Cst1. The bottom position of the capacitor Cst1 can be coupled to the corresponding anode terminal of the pixel 22, as shown in the schematic connection path 892. In this arrangement, the gate conductor of the semiconductor oxide transistor Tdrive is now covered and shielded by the topmost gate layer 823. This is also Fig.8D and Fig. 8E , where the shielding layer 840 is wider than the footprint of the top gate conductor 820 of Tdrive. Therefore, any parasitic capacitance with neighboring pixels will only couple to the bottom plate of capacitor Cst1, which is a low impedance node and is connected to Figure 8B The gate layer 840 may be relatively less susceptible to pixel crosstalk than the embodiments described above. In addition, the gate layer 840 may provide additional light shielding from the above-mentioned transistor Tdrive, which may allow for more flexible patterning of the anode layer. The shield 840 may also help prevent or mitigate hydrogen penetration into the channel of the transistor Tdrive. In a suitable embodiment, the top capacitor electrode 840 may include different stacked metals. For example, the top capacitor electrode may be formed using a hydrogen shielding material such as titanium or tungsten or other suitable hydrogen barrier material, which may optionally be combined with a relatively high conductivity material such as molybdenum, aluminum, copper, silver or other relatively conductive metals.

[0091] In other words, forming capacitor Cst1 directly above semiconductor oxide transistor Tdrive can help provide the following technical advantages: (1) electrical shielding of the oxide gate conductor to mitigate any potential pixel crosstalk issues, (2) optical shielding of the semiconductor oxide transistor to allow more flexible anode layer patterning, and (3) shielding hydrogen from penetrating into the channel region of the semiconductor oxide transistor.

[0092] Figure 8B and Figure 8C The display stack structure shown can be applied to any of the pixel arrangements shown in Figures 3 to 7. In general, any of the various semiconductor oxide transistors in the display pixel 22 can have Figure 8C The dual gate structure shown in FIG. 1 and the gate conductors of these transistors may optionally use a Figure 8C Where the display pixel 22 includes more than one capacitor, any additional capacitors may be stacked above one or more of the semiconductor oxide transistors or stacked above one or more of the LTPS transistors to provide the desired electrical and / or optical protection.

[0093] Fig. 9 It is shown Figure 3A A cross-sectional side view of a portion of a display pixel of FIG. 1 , wherein two semiconductor oxide transistors are formed in different layers in the display stack. Fig. 9 As shown, the first semiconductor oxide transistor Toxide1 may have its active semiconductor oxide layer (labeled as 816-1) formed directly on the first gate insulation (GI1) layer 806, and the second semiconductor oxide transistor Toxide2 may have its active semiconductor oxide layer (labeled as 816-2) formed directly on the oxide buffer layer 811. In other words, layer 816-1 may be formed above layer 816-2, and conversely, layer 816-2 is formed below layer 816-1. Although the oxide layers of transistor Toxide1 and transistor Toxide2 are formed in different layers, the gate 820 of transistor Toxide1 and the gate 820 of transistor Toxide2 may be formed in the same layer. The second gate insulation (GI2) layer 818 may be formed immediately below the gate layer 820. The first oxide ILD layer 822 may be formed above the layer 820, and the second oxide ILD layer 825 may be formed on the layer 822. The transistor Toxide1 may have a gate insulator thickness that is greater than, less than, or equal to the gate insulator thickness of the transistor Toxide2.

[0094] In one suitable arrangement, Toxide1 may represent the drive transistor Tdrive, and Toxide2 may represent the gate setting transistor Tgd, the initialization transistor Tini, or any other semiconductor oxide transistor (if present) in the pixel 22. In another suitable arrangement, Toxide2 may represent the drive transistor Tdrive, and Toxide1 may represent the gate setting transistor Tgd, the initialization transistor Tini, or any other semiconductor oxide transistor (if present) in the pixel 22. Fig. 9 In the example of , the storage capacitor Cst may have a bottom plate formed using the oxide gate layer 820 and a top plate formed using the gate metal layer 823 .

[0095] Fig. 9 The example of only one planarization layer is shown. However, this arrangement is merely exemplary and is not intended to limit the scope of the embodiments of the present invention. If desired, at least two planarization layers can be implemented in the entire display stack. Such dual planarization layer configurations that can be used are described in detail in Ono et al. (commonly owned U.S. Patent Application No. 15 / 729,330 filed on October 10, 2017), which is incorporated herein by reference in its entirety. In addition, Fig. 9The example of FIG. 1 shows a storage capacitor Cst1 formed laterally relative to the semiconductor oxide transistors Toxide1 and Toxide2 (see, for example, capacitor Cst1 having one electrode formed using OxGE and another electrode formed using GE2). This configuration is also merely exemplary. If desired, Figure 8B Arrangements of the type shown stack storage capacitor Cst1 on top of Toxide1 or Toxide2 to provide enhanced electrical, optical and hydrogen penetration shielding.

[0096] According to an embodiment, a display pixel is provided, which includes an organic light emitting diode having an anode terminal and a cathode terminal; a semiconductor oxide driving transistor coupled in series with the organic light emitting diode, the semiconductor oxide driving transistor having a gate terminal, a drain terminal and a source terminal; and a storage capacitor having a first terminal coupled to the gate terminal of the semiconductor oxide driving transistor and a second terminal coupled to the anode terminal of the organic light emitting diode.

[0097] According to another embodiment, a display pixel includes a semiconducting oxide gate voltage setting transistor coupled across a drain terminal and a gate terminal of a semiconducting oxide drive transistor.

[0098] According to another embodiment, a display pixel includes an initialization line on which an initialization voltage is provided; and a semiconductor oxide initialization transistor coupled between the initialization line and an anode terminal of an organic light emitting diode.

[0099] According to another embodiment, a display pixel includes an initialization line on which an initialization voltage is provided; and a semiconductor oxide initialization transistor coupled between the initialization line and an anode terminal of an organic light emitting diode.

[0100] According to another embodiment, a display pixel includes a p-type silicon emission transistor coupled in series between a semiconductor oxide drive transistor and an anode terminal of an organic light emitting diode.

[0101] According to another embodiment, the p-type silicon emission transistor and the semiconductor oxide initialization transistor are configured to receive an emission control signal generated by an emission control circuit.

[0102] According to another embodiment, a display pixel includes a positive power supply line; and an additional p-type silicon emitter transistor coupled in series between the positive power supply line and the semiconducting oxide drive transistor.

[0103] According to another embodiment, a display pixel includes a data line; and a p-type silicon data loading transistor coupled between the data line and a source terminal of a semiconducting oxide drive transistor.

[0104] According to another embodiment, a display pixel includes a first scan line configured to provide a first scan signal to the semiconductor oxide gate voltage setting transistor; and a second scan line configured to provide a second scan signal to the p-type silicon data loading transistor.

[0105] According to another embodiment, a storage capacitor is stacked over the semiconducting oxide drive transistor to provide shielding for the semiconducting oxide drive transistor.

[0106] According to another embodiment, a semiconductor oxide drive transistor includes an active semiconductor oxide material; a top gate conductor formed above the active semiconductor oxide material; and a bottom gate conductor formed below the active semiconductor oxide material and coupled to a selected one of a gate terminal or a source terminal of the semiconductor oxide drive transistor.

[0107] According to an embodiment, a display is provided, which includes a silicon transistor; a semiconductor oxide transistor formed above the silicon transistor; and a storage capacitor stacked above the semiconductor oxide transistor, the storage capacitor being configured to reduce pixel crosstalk and prevent hydrogen from penetrating into a channel of the semiconductor oxide transistor by at least partially shielding the semiconductor oxide transistor.

[0108] According to another embodiment, a storage capacitor has a first terminal directly connected to the gate terminal of the semiconducting oxide transistor and a second terminal directly connected to the drain terminal of the silicon transistor.

[0109] According to another embodiment, the semiconducting oxide transistor has a bottom gate conductor and the silicon transistor has a top gate conductor, and the bottom gate conductor of the semiconducting oxide transistor and the top gate conductor of the silicon transistor are formed from the same conductive layer.

[0110] According to another embodiment, a semiconducting oxide transistor includes a first gate conductor; and a second gate conductor coupled to a selected one of a gate terminal or a source terminal of the semiconducting oxide transistor.

[0111] According to another embodiment, a semiconducting oxide transistor has a gate conductor configured as a bottom plate of a storage capacitor.

[0112] According to another embodiment, a storage capacitor has a top plate covering a gate conductor of a semiconducting oxide transistor, and the top plate of the storage capacitor provides electrical and optical shielding for the semiconducting oxide transistor.

[0113] According to an embodiment, a display is provided, which includes an organic light emitting diode having an anode terminal and a cathode terminal; a first semiconductor oxide transistor, the first semiconductor oxide transistor having a semiconductor oxide material formed in a first layer and having a first gate conductor, the first semiconductor oxide transistor including a driving transistor coupled to the anode terminal of the light emitting diode; and a second semiconductor oxide transistor, the second semiconductor oxide transistor having a semiconductor material formed in a second layer different from the first layer and having a second gate conductor.

[0114] According to another embodiment, the first gate conductor and the second gate conductor are formed in the same gate layer.

[0115] According to another embodiment, a display includes a first gate metal formed below a semiconductor material of a first semiconductor oxide transistor; and a second gate metal, wherein the second gate metal is formed below the semiconductor material of the second semiconductor oxide transistor, and the first gate metal and the second gate metal are formed in the same gate metal layer.

[0116] According to another embodiment, the display includes only one planarization layer formed between the anode terminal and the first gate conductor.

[0117] According to another embodiment, the first material is above or below the second material.

[0118] According to another embodiment, a display includes a storage capacitor having a first terminal formed in the same gate layer as the first gate conductor.

[0119] According to another embodiment, a storage capacitor has a second terminal formed in a metal layer above the first terminal.

[0120] According to an embodiment, a method of operating a display pixel is provided, the display pixel including an organic light emitting diode, a semiconductor oxide driving transistor, a storage capacitor and a semiconductor oxide initialization transistor, the method including: during an initialization phase, loading an initialization voltage onto an anode terminal of the organic light emitting diode using the semiconductor oxide initialization transistor; and during a threshold voltage and data programming phase, configuring the semiconductor oxide driving transistor in a diode-connected arrangement to sample a data signal and a threshold voltage of the semiconductor oxide driving transistor onto the storage capacitor.

[0121] According to another embodiment, configuring the semiconducting oxide drive transistor in a diode-connected arrangement includes using a semiconducting oxide gate voltage setting transistor to short together a gate terminal and a drain terminal of the semiconducting oxide drive transistor.

[0122] According to another embodiment, the display pixel further includes a data loading transistor, and the method further includes: applying a data signal to the semiconducting oxide drive transistor using the data loading transistor during the on-bias stress phase, while turning off the semiconducting oxide drive transistor to mitigate threshold voltage hysteresis associated with the semiconducting oxide drive transistor.

[0123] According to another embodiment, the display pixels include only thin film transistors selected from the group consisting of: semiconducting oxide transistors and p-type silicon transistors.

[0124] According to an embodiment, a display is provided, comprising a semiconductor oxide transistor having a channel; and a storage capacitor stacked above the semiconductor oxide transistor, wherein a first electrode of the storage capacitor is co-configured with a gate of the semiconductor oxide transistor, and wherein a second electrode of the storage capacitor is configured above the first electrode of the storage capacitor to reduce pixel crosstalk to the gate of the semiconductor oxide transistor by at least partially shielding the semiconductor oxide transistor and mitigate hydrogen penetration into the channel of the semiconductor oxide transistor.

[0125] According to another embodiment, the display further includes an additional semiconducting oxide transistor having a semiconducting oxide layer formed over the semiconducting oxide layer of the semiconducting oxide transistor.

[0126] According to another embodiment, the display further comprises an additional semiconductor oxide transistor having a semiconductor oxide layer formed below the semiconductor oxide layer of the semiconductor oxide transistor. According to another embodiment, the gate of the semiconductor oxide transistor and the gate of the additional semiconductor oxide transistor are formed in the same layer, wherein the semiconductor oxide transistor has a first gate insulator having a first thickness, and wherein the additional semiconductor oxide transistor has a second gate insulator having a second thickness, the second thickness being less than the first thickness.

[0127] According to another embodiment, a gate of a semiconductor oxide transistor and a gate of an additional semiconductor oxide transistor are formed in the same layer, wherein the semiconductor oxide transistor has a first gate insulator having a first thickness, and wherein the additional semiconductor oxide transistor has a second gate insulator having a second thickness, the second thickness being greater than the first thickness.

[0128] According to another embodiment, the second electrode of the storage capacitor includes a plurality of different metals.

[0129] The foregoing is merely illustrative, and various modifications may be made by those skilled in the art without departing from the scope and spirit of the embodiments described. The foregoing embodiments may be implemented independently or in any combination.

Claims

1. A display pixel, comprising: an organic light emitting diode having an anode terminal and a cathode terminal; a semiconductor oxide drive transistor coupled in series with the organic light emitting diode, wherein the semiconductor oxide drive transistor has a gate terminal, a drain terminal, and a source terminal; a silicon data loading transistor coupled to the first source-drain terminal of the semiconductor oxide drive transistor, wherein the silicon data loading transistor is configured to receive a control signal that is pulsed a plurality of times during a data refresh cycle; a semiconductor oxide diode-connect transistor coupled to a gate terminal of the semiconductor oxide drive transistor and configured to receive an additional control signal having a first value during a first pulse of the control signal and having a second value different from the first value during a second pulse of the control signal; and A storage capacitor has a first terminal coupled to the gate terminal of the semiconducting oxide drive transistor and a second terminal coupled to the anode terminal of the organic light emitting diode.

2. The display pixel of claim 1 , further comprising: A semiconducting oxide gate voltage setting transistor is coupled across the drain terminal and the gate terminal of the semiconducting oxide driving transistor.

3. The display pixel of claim 1 , further comprising: an initialization line, on which an initialization voltage is provided; and A semiconductor oxide initialization transistor is coupled between the initialization line and the anode terminal of the organic light emitting diode.

4. The display pixel of claim 2, further comprising: an initialization line, on which an initialization voltage is provided; and A semiconductor oxide initialization transistor is coupled between the initialization line and the anode terminal of the organic light emitting diode.

5. The display pixel of claim 4, further comprising: A p-type silicon emission transistor is coupled in series between the semiconductor oxide drive transistor and the anode terminal of the organic light emitting diode. 6 . The display pixel of claim 5 , wherein the p-type silicon emission transistor and the semiconductor oxide initialization transistor are configured to receive emission control signals generated by an emission control circuit.

7. The display pixel of claim 5, further comprising: Positive power line; an additional p-type silicon emitter transistor coupled in series between the positive power supply line and the semiconductor oxide drive transistor; a data line, wherein the silicon data loading transistor is of p-type, and the silicon data loading transistor is coupled between the data line and the source terminal of the semiconductor oxide driving transistor; a first scan line configured to provide a first scan signal to the semiconductor oxide gate voltage setting transistor; and A second scan line is configured to provide a second scan signal to the silicon data loading transistor.

8. The display pixel of claim 1 wherein the storage capacitor is stacked over the semiconducting oxide drive transistor to provide shielding for the semiconducting oxide drive transistor.

9. The display pixel of claim 1 , wherein the semiconducting oxide drive transistor comprises: Active semiconductor oxide materials; a top gate conductor formed over the active semiconductor oxide material; and A bottom gate conductor is formed below the active semiconducting oxide material and coupled to a selected one of the gate terminal or the source terminal of the semiconducting oxide drive transistor.

10. A method of operating pixels in a given pixel row, the pixels comprising a light emitting diode, a drive transistor, a gate setting transistor, an initialization transistor, and a data loading transistor, the method comprising: activating the gate setting transistor by asserting a first scan signal and activating the initialization transistor by deactivating a firing signal to perform an initialization operation; When the first scan signal is asserted, activating the data loading transistor by asserting a second scan signal to perform threshold voltage sampling and data programming operations; asserting the transmit signal prior to a transmit operation; asserting an additional emission signal from another pixel row different from the given pixel row to activate emission transistors in the pixels during the initialization operation and the emission operation, wherein the additional emission signal is deactivated during the threshold voltage sampling and data programming operations; as well as Prior to the threshold voltage sampling and the data programming operation, when the first scan signal is invalidated and the emission signal and the additional emission signal are invalidated, a bias stress operation is performed by first asserting the second scan signal to activate the data loading transistor and then negating the second scan signal to deactivate the data loading transistor.

11. The method according to claim 10, further comprising: generating a first pulse in the second scanning signal to start the bias stress operation; as well as A second pulse is generated in the second scan signal to start the threshold voltage sampling and the data programming operations.

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