Power grid protection circuit and method

Abstract

The present invention provides a power grid protection circuit and method. The over- and under-voltage detection circuit can implement the functions of over-voltage detection and under-voltage detection. The over-voltage detection and under-voltage detection share pins, and the entire circuit only requires one input port, reducing the scale and complexity of the circuit and facilitating maintenance. Moreover, since the m cycles of the first comparison signal and the second comparison signal are detected respectively when the first enable signal is valid, at this time, the obtained first characteristic signal and the second characteristic signal can be used to generate a classification signal indicating whether the power grid is over-voltage or under-voltage, realizing over- and under-voltage detection to control the on-off of the power grid. It can resist non-continuous time interference, prevent misoperation caused by interference, improve the detection accuracy and anti-interference ability. Further, the over- and under-voltage detection circuit is integrated with the leakage protection circuit, so that the power grid protection circuit has both the functions of leakage protection and over- and under-voltage detection, and is simple to apply, has high precision and strong anti-interference ability.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and particularly to a power grid protection circuit and method. Background Art

[0002] With the improvement of people's living standards, more attention is paid to the safety of electricity use. Now, many electrical products are equipped with leakage protectors. The leakage protectors use dedicated leakage protection circuits, but the additional protection functions of existing leakage protection circuits are not perfect.

[0003] At present, the load of the power grid varies greatly at different times, and the power grid voltage fluctuates greatly. In addition, line faults may also cause power grid voltage fluctuations. If the power grid voltage is too high or too low, some electrical appliances may not work properly or even be damaged. The existing solution is to separately design overvoltage and undervoltage protection circuits, which are generally built with discrete components. The circuit scale is large and complex, the maintenance is difficult, the cost is high, the accuracy is low, and the anti-interference ability is poor. Summary of the Invention

[0004] The purpose of the present invention is to provide a power grid protection circuit and method to solve the problems such as the lack of overvoltage and undervoltage protection in electrical products and the single function of the leakage protection circuit.

[0005] To achieve the above purpose, the present invention provides a power grid protection circuit, including: an over-undervoltage detection circuit, and the over-undervoltage detection circuit includes:

[0006] A signal acquisition module, configured to sample the AC voltage of the power grid to obtain a sampled voltage signal;

[0007] A basic signal generation module, configured to generate an undervoltage threshold voltage and an overvoltage threshold voltage;

[0008] A first voltage comparison module, connected to the signal acquisition module and the basic signal generation module, configured to compare the sampled voltage signal with the undervoltage threshold voltage and the overvoltage threshold voltage respectively to obtain a first comparison signal and a second comparison signal; and,

[0009] A control circuit, connected to the first voltage comparison module, configured to detect the m cycles of the first comparison signal and the second comparison signal respectively when a first enable signal is valid to obtain a first characteristic signal and a second characteristic signal, and generate a classification signal indicating whether the power grid is overvoltage or undervoltage according to the first characteristic signal and the second characteristic signal, where m≥1.

[0010] Optionally, the first enable signal is a periodic signal. Each period of the first enable signal includes a detection time and a clearing time. The first enable signal is valid during the detection time and invalid during the clearing time. The detection time is greater than m periods of the first comparison signal and m periods of the second comparison signal.

[0011] Optionally, latch the active levels of the first characteristic signal and the second characteristic signal until the end of the detection time of each period of the first enable signal, and clear the active levels of the first characteristic signal and the second characteristic signal during the clearing time of each period of the first enable signal.

[0012] Optionally, the control circuit includes:

[0013] A periodic anti-interference detection module, connected to the first voltage comparison module, for detecting m periods of the first comparison signal and the second comparison signal respectively when the first enable signal is valid, to obtain a first characteristic signal and a second characteristic signal;

[0014] An edge detection module, connected to the periodic anti-interference detection module, for performing edge detection on the first characteristic signal and the second characteristic signal respectively, to obtain a first classification signal indicating whether the first characteristic signal has a rising edge / falling edge and a second classification signal indicating whether the second characteristic signal has a rising edge / falling edge; and,

[0015] A classification module, connected to the edge detection module, for performing a logical operation on the first classification signal and the second classification signal to obtain the classification signal.

[0016] Optionally, the periodic anti-interference detection module performs edge detection on m periods of the first comparison signal and the second comparison signal respectively when the first enable signal is valid, to obtain the first characteristic signal indicating whether each period of the first comparison signal has a rising edge / falling edge within m periods and the second characteristic signal indicating whether each period of the second comparison signal has a rising edge / falling edge within m periods.

[0017] Optionally, the first voltage comparison module also compares the sampled voltage signal with the power frequency threshold voltage to obtain a power frequency signal indicating the magnitude relationship between the sampled voltage signal and the power frequency threshold voltage;

[0018] And, the control circuit further includes:

[0019] A counter module, connected to the periodic anti-interference detection module and the first voltage comparison module, for generating the first enable signal according to the power frequency signal.

[0020] Optionally, the counter module includes:

[0021] A frequency division unit, connected to the first voltage comparison module, for performing p-frequency division on the power frequency signal n times to obtain n-level frequency division signals, where n, p ≥ 2; and

[0022] A logic operation unit, connected to the frequency division unit, for performing logic operations on the second-level to n-level frequency division signals to obtain the first enable signal.

[0023] Optionally, the pulse width of the first enable signal is equal to the sum of the pulse widths of the second-level to n-level frequency division signals.

[0024] Optionally, the control circuit further includes:

[0025] A power-on self-check module, connected to the first voltage comparison module, the counter module, and the periodic anti-interference detection module, for performing edge detection on q cycles of the power frequency signal according to the power-on reset signal, and generating a valid second enable signal to control the counter module and the periodic anti-interference detection module to start working when each cycle of the q cycles of the power frequency signal has a rising edge / falling edge, where q ≥ 1.

[0026] Optionally, the rising edge of the second enable signal is separated from the rising edge of the n-level frequency division signal by g cycles of the power frequency signal, where g and n satisfy the following relationship:

[0027] g = 2 (n-1) .

[0028] Optionally, the power-on self-check module has s flip-flops, where s ≥ 1, and q and s satisfy the following relationship:

[0029] q = 2 (s-1) .

[0030] Optionally, the classification module is further connected to the counter module, receives the n-level frequency division signal, and performs a logic operation on the first classification signal and the second classification signal, and then performs a logic operation on the result of the logic operation and the n-level frequency division signal to obtain the classification signal.

[0031] Optionally, the classification module includes:

[0032] An exclusive NOR gate, connected to the edge detection module, for performing an exclusive NOR operation on the first classification signal and the second classification signal; and

[0033] An AND gate, connected to the counter module and the XNOR gate, is used to perform an AND operation on the result of the XNOR operation and the nth-stage frequency division signal to obtain the classification signal.

[0034] Optionally, the periodic anti-interference detection module has r flip-flops, where 1 < r ≤ n - 1, and m and r satisfy the following relationship:

[0035] m = 2 (r-1) 。

[0036] Optionally, the signal acquisition module includes:

[0037] A rectification unit, used to rectify the AC voltage of the power grid to obtain a rectified signal; and,

[0038] A voltage division unit, connected to the rectification unit, is used to divide the rectified signal to obtain the sampled voltage signal.

[0039] Optionally, the basic signal generation module includes:

[0040] A reference voltage generation unit, used to generate a reference voltage; and,

[0041] A voltage stabilization unit, connected to the reference voltage generation unit, is used to generate the undervoltage threshold voltage, overvoltage threshold voltage, and power frequency threshold voltage according to the reference voltage;

[0042] A regulated power supply, connected to the reference voltage generation unit, is used to generate a constant power supply voltage according to the reference voltage.

[0043] Optionally, the basic signal generation module further includes:

[0044] A power-on reset unit, used to generate the power-on reset signal.

[0045] Optionally, the power grid protection circuit further includes a leakage protection circuit, and the leakage protection circuit is used to detect whether the power grid is leaking and jointly control the on / off of the power grid according to the leakage detection result and the classification signal.

[0046] Optionally, the leakage protection circuit includes:

[0047] A signal amplification module, connected to the power grid, is used to amplify the leakage voltage of the power grid to obtain a voltage amplification signal;

[0048] A second voltage comparison module, connected to the signal amplification module, is used to compare the voltage amplification signal with a reference voltage to obtain a third comparison signal; and,

[0049] A logic processing module, connected to the over-voltage and under-voltage detection circuit and the second voltage comparison module, is configured to perform a logic operation on the third comparison signal and the classification signal to obtain a control signal for controlling the on / off of the power grid.

[0050] Optionally, the leakage protection circuit further includes:

[0051] A delay module, connected to the logic processing module, is configured to delay the control signal and then output it; and,

[0052] A driving module, connected to the delay module, is configured to enhance the driving ability of the delayed control signal and then output it.

[0053] Optionally, the leakage protection circuit, the basic signal generation module, the first voltage comparison module, and the control circuit are integrated on the same chip.

[0054] Optionally, the leakage protection circuit and the over-voltage and under-voltage detection circuit are integrated on the same chip.

[0055] The present invention further provides a power grid protection method, including:

[0056] Sampling the AC voltage of the power grid to obtain a sampled voltage signal;

[0057] Comparing the sampled voltage signal with an under-voltage threshold voltage and an over-voltage threshold voltage respectively to obtain a first comparison signal and a second comparison signal; and,

[0058] When a first enable signal is valid, detecting m cycles of the first comparison signal and the second comparison signal respectively to obtain a first characteristic signal and a second characteristic signal, and generating a classification signal indicating whether the power grid is over-voltage or under-voltage according to the first characteristic signal and the second characteristic signal, where m≥1.

[0059] Optionally, the first enable signal is a periodic signal. Each cycle of the first enable signal includes a detection time and a clearing time. The first enable signal is valid during the detection time and invalid during the clearing time. The detection time is greater than m cycles of the first comparison signal and m cycles of the second comparison signal.

[0060] Optionally, latching the valid levels of the first characteristic signal and the second characteristic signal until the end of the detection time of each cycle of the first enable signal, and clearing the valid levels of the first characteristic signal and the second characteristic signal during the clearing time of each cycle of the first enable signal.

[0061] Optionally, the step of generating the classification signal according to the first characteristic signal and the second characteristic signal includes:

[0062] Perform edge detection on the first characteristic signal and the second characteristic signal to obtain a first classification signal indicating whether the first characteristic signal has a rising edge / falling edge and a second classification signal indicating whether the second characteristic signal has a rising edge / falling edge; and,

[0063] Perform a logical operation on the first classification signal and the second classification signal to obtain the classification signal.

[0064] Optionally, when the first enable signal is valid, perform edge detection on m cycles of the first comparison signal and the second comparison signal respectively to obtain the first characteristic signal for indicating whether each cycle of the first comparison signal has a rising edge / falling edge within m cycles and obtain the second characteristic signal for indicating whether each cycle of the second comparison signal has a rising edge / falling edge within m cycles.

[0065] Optionally, when comparing the sampled voltage signal with the undervoltage threshold voltage and the overvoltage threshold voltage respectively, also compare the sampled voltage signal with the power frequency threshold voltage to obtain a power frequency signal indicating the magnitude relationship between the sampled voltage signal and the power frequency threshold voltage, and generate the first enable signal according to the power frequency signal.

[0066] Optionally, the step of generating the first enable signal according to the power frequency signal includes:

[0067] Perform p-frequency division on the power frequency signal n times to obtain n levels of frequency division signals, where n, p ≥ 2; and,

[0068] Perform a logical operation on the second-level frequency division signal to the n-level frequency division signal to obtain the first enable signal.

[0069] Optionally, the pulse width of the first enable signal is equal to the sum of the pulse widths of the second-level frequency division signal to the n-level frequency division signal.

[0070] Optionally, before performing detection on m cycles of the first comparison signal and the second comparison signal respectively when the first enable signal is valid, further include:

[0071] Perform edge detection on q cycles of the power frequency signal according to the power-on reset signal, and generate a valid second enable signal when each cycle of the power frequency signal has a rising edge / falling edge within q cycles, and generate the first enable signal according to the second enable signal and the power frequency signal, where q ≥ 1.

[0072] Optionally, the rising edge of the second enabling signal and the nth-stage frequency division signal are separated by g cycles of the power frequency signal, where g and n satisfy the following relationship:

[0073] g = 2 (n-1) 。

[0074] Optionally, after performing a logical operation on the first classification signal and the second classification signal, a logical operation is performed on the result of the logical operation and the nth-stage frequency division signal to obtain the classification signal.

[0075] Optionally, the steps of performing a logical operation on the first classification signal and the second classification signal include:

[0076] Performing an exclusive NOR operation on the first classification signal and the second classification signal; and,

[0077] Performing an AND operation on the result of the exclusive NOR operation and the nth-stage frequency division signal to obtain the classification signal.

[0078] Optionally, it further includes:

[0079] Detecting whether the power grid is leaking electricity, and jointly controlling the on / off of the power grid according to the leakage detection result and the classification signal.

[0080] Optionally, the steps of jointly controlling the on / off of the power grid according to the leakage detection result and the classification signal include:

[0081] Amplifying the leakage voltage of the power grid to obtain a voltage amplification signal;

[0082] Comparing the voltage amplification signal with a reference voltage to obtain a third comparison signal representing the magnitude relationship between the voltage amplification signal and the reference voltage; and,

[0083] Performing a logical operation on the third comparison signal and the classification signal to obtain a control signal for controlling the on / off of the power grid.

[0084] The power grid protection circuit and method provided by the present invention have the following beneficial effects:

[0085] 1) The over- and under-voltage detection circuit can implement the functions of over-voltage detection and under-voltage detection. The over-voltage detection and under-voltage detection share pins, and the entire circuit only requires one input port, reducing the scale and complexity of the circuit and facilitating maintenance.

[0086] 2) When detecting the m cycles of the first comparison signal and the second comparison signal respectively when the first enabling signal is valid, at this time, the obtained first characteristic signal and the second characteristic signal can be used to generate a classification signal indicating whether the power grid is overvoltage or undervoltage, realizing over-undervoltage detection; moreover, since the m cycles of the first comparison signal and the second comparison signal are detected, it can resist the interference of non-continuous time, prevent misoperation caused by interference, ensure no tripping during the instantaneous overvoltage and instantaneous undervoltage fluctuations of the power grid, and improve the detection accuracy and anti-interference ability.

[0087] 3) Latch the valid levels of the first characteristic signal and the second characteristic signal until the end of the detection time of each cycle of the first enabling signal, and clear the valid levels of the first characteristic signal and the second characteristic signal at the clearing time of each cycle of the first enabling signal, which will not affect the detection of the next cycle;

[0088] 4) Integrate the over-undervoltage detection circuit and the leakage protection circuit together, so that the power grid protection circuit has both the functions of leakage protection and over-undervoltage detection, and has simple application, high precision and strong anti-interference ability; moreover, the leakage protection circuit and the over-undervoltage detection circuit can be integrated on the same chip, reducing the complexity of the system, being more user-friendly to application technicians, and facilitating system testing and operation and maintenance at the same time. Description of the Drawings

[0089] Figure 1 It is a flowchart of the power grid protection method provided in Embodiment 1 of the present invention;

[0090] Figure 2a It is a circuit diagram of the power grid protection circuit provided in Embodiment 1 of the present invention;

[0091] Figure 2b It is a circuit diagram of the over-undervoltage detection circuit provided in Embodiment 1 of the present invention;

[0092] Figure 3a It is a circuit timing diagram of the over-undervoltage detection circuit provided in Embodiment 1 of the present invention when the power grid is at normal voltage;

[0093] Figure 3b It is a circuit timing diagram of the over-undervoltage detection circuit provided in Embodiment 1 of the present invention when the power grid is overvoltage;

[0094] Figure 3c It is a circuit timing diagram of the over-undervoltage detection circuit provided in Embodiment 1 of the present invention when the power grid is undervoltage;

[0095] Figure 4 It is an application diagram of the power grid protection circuit provided in Embodiment 1 of the present invention;

[0096] Figure 5aThe circuit timing diagram of the over- and under-voltage detection circuit provided in Embodiment 2 of the present invention when the power grid is at normal voltage;

[0097] Figure 5b The circuit timing diagram of the over- and under-voltage detection circuit provided in Embodiment 2 of the present invention when the power grid is over-voltage;

[0098] Figure 5c The circuit timing diagram of the over- and under-voltage detection circuit provided in Embodiment 2 of the present invention when the power grid is under-voltage.

[0099] Wherein, the reference numerals are:

[0100] 10 - Signal acquisition module; 20 - Basic signal generation module; 21 - Power-on reset unit; 22 - Reference voltage generation unit; 23 - Voltage stabilization unit; 24 - Regulated power supply; 30 - First voltage comparison module; 40 - Power-on self-check module; 50 - Counter module; 60 - Periodic anti-interference detection module; 70 - Edge detection module; 80 - Classification module; 90 - Signal amplification module; 100 - Delay module; 110 - Driver module; 120 - Power supply module; 130 - Induction module; 140 - Tripping module;

[0101] D1 - Diode; R1 - First voltage-dividing resistor; R2 - Second voltage-dividing resistor; Comp1 - First comparator; Comp2 - Second comparator; Comp3 - Third comparator; Comp4 - Fourth comparator; Vsamp - Sampling voltage signal; POR - Power-on reset signal; POST - Second enable signal; Vref - Reference voltage; Vunder - Under-voltage threshold voltage; Vover - Over-voltage threshold voltage; Vth - Power frequency threshold voltage; Phase - Power frequency signal; Clear - First enable signal; Validation - Third enable signal; VA - First comparison signal; VB - Second comparison signal; VERA - First characteristic signal; VERB - Second characteristic signal; QA - First classification signal; QB - Second classification signal; Ocheck - Classification signal; AmpOut - Voltage amplification signal; Ctrl - Control signal; Output - Driver signal; L - Live wire of the power grid; N - Neutral wire of the power grid; Input - Leakage voltage. Detailed implementation manners

[0102] The following will describe the detailed implementation manners of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0103] Embodiment 1

[0104] Figure 1The flowchart of the power grid protection method provided by this embodiment. As Figure 1 shown, the power grid protection method includes:

[0105] Step S100: Sample the AC voltage of the power grid to obtain a sampled voltage signal Vsamp;

[0106] Step S200: Compare the sampled voltage signal Vsamp with an undervoltage threshold voltage Vunder and an overvoltage threshold voltage Vover respectively to obtain a first comparison signal VA and a second comparison signal VB; and,

[0107] Step S300: Detect m cycles of the first comparison signal VA and the second comparison signal VB respectively when a first enable signal Clear is valid to obtain a first characteristic signal VERA and a second characteristic signal VERB, and generate a classification signal Ocheck indicating whether the power grid is overvoltage or undervoltage according to the first characteristic signal VERA and the second characteristic signal VERB, where m≥1.

[0108] Based on this, this embodiment also provides a power grid protection circuit for executing the power grid protection method. Figure 2a The circuit diagram of the power grid protection circuit provided by this embodiment, Figure 2b The circuit diagram of the over- and under-voltage detection circuit provided by this embodiment, as Figure 2a and Figure 2b shown, the power grid protection circuit is characterized by including: an over- and under-voltage detection circuit, and the over- and under-voltage detection circuit includes:

[0109] A signal acquisition module 10 for sampling the AC voltage of the power grid to obtain a sampled voltage signal Vsamp;

[0110] A basic signal generation module 20 for generating an undervoltage threshold voltage Vunder and an overvoltage threshold voltage Vover;

[0111] A first voltage comparison module 30 connected to the signal acquisition module 10 and the basic signal generation module 20 for comparing the sampled voltage signal Vsamp with the undervoltage threshold voltage Vunder and the overvoltage threshold voltage Vover respectively to obtain a first comparison signal VA and a second comparison signal VB; and,

[0112] The control circuit is connected to the first voltage comparison module 30 and is configured to detect m periods of the first comparison signal VA and the second comparison signal VB respectively when the first enable signal Clear is valid, so as to obtain a first characteristic signal VERA and a second characteristic signal VERB, and generate a classification signal Ocheck indicating whether the power grid is overvoltage or undervoltage according to the first characteristic signal VERA and the second characteristic signal VERB, where m≥1.

[0113] It can be seen that the signal acquisition module 10 in this embodiment is configured to execute step S100 of the power grid protection method, the basic signal generation module 20 and the first voltage comparison module 30 are configured to execute step S200 of the power grid protection method, and the control circuit is configured to execute step S300 of the power grid protection method. This embodiment integrates the overvoltage protection and undervoltage protection functions in one circuit, enabling one circuit to implement the functions of overvoltage detection and undervoltage detection. The overvoltage detection and undervoltage detection share pins, and the entire circuit only requires one input port, reducing the scale and complexity of the circuit and facilitating maintenance.

[0114] Next, Figure 2a and Figure 2b will be used to elaborate in detail on the power grid protection method and the power grid protection circuit provided in this embodiment. It should be understood that this embodiment only provides a power grid protection circuit for executing the power grid protection method. In other embodiments, other circuits may also be used to execute the power grid protection method, which will not be elaborated here too much.

[0115] First, step S100 is executed to sample the AC voltage of the power grid to obtain the sampled voltage signal Vsamp.

[0116] Specifically, the signal acquisition module 10 includes a rectification unit and a voltage division unit. The rectification unit is connected to the power grid and is configured to receive the AC voltage of the power grid and rectify the AC voltage of the power grid, thereby outputting a rectified signal. The voltage division unit is connected to the rectification unit and is configured to receive the rectified signal and divide the rectified signal to obtain the sampled voltage signal Vsamp.

[0117] In this embodiment, when rectifying the AC voltage of the power grid to obtain the rectification signal, half-wave rectification is performed on the AC voltage of the power grid. Based on this, the rectification unit is a diode D1. The positive electrode of the diode D1 serves as the input end of the rectification unit and is connected to the power grid; the negative electrode of the diode D1 serves as the output end of the rectification unit and is connected to the voltage division unit. It should be understood that half-wave rectification can be achieved by using the diode D1, which simplifies the circuit, saves costs, and does not require a large-capacitance capacitor during signal acquisition, retaining the characteristics of the AC signal of the power grid and significantly improving the detection accuracy.

[0118] In this embodiment, the rectification signal is divided by resistance voltage division to obtain the sampling voltage signal Vsamp. Based on this, the voltage division unit includes a first voltage division resistor R1 and a second voltage division resistor R2. The first voltage division resistor R1 and the second voltage division resistor R2 are connected in series between the output end of the rectification unit and the ground terminal. The node between the first voltage division resistor R1 and the second voltage division resistor R2 serves as the output end of the voltage division unit to output the sampling voltage signal Vsamp.

[0119] Further, step S200 is executed to compare the sampling voltage signal Vsamp with the undervoltage threshold voltage Vunder and the overvoltage threshold voltage Vover respectively to obtain a first comparison signal VA and a second comparison signal VB.

[0120] Specifically, the basic signal generation module 20 includes a power-on reset unit 21, a reference voltage generation unit 22, a voltage stabilization unit 23, and a regulated power supply 24. When the over-undervoltage detection circuit is powered on, the power-on reset unit 21 generates a power-on reset signal POR, and the power-on reset signal POR is used to control the modules in the over-undervoltage detection circuit to perform power-on reset, which will be described below. The reference voltage generation unit 22 is used to generate a reference voltage Vref. The voltage stabilization unit 23 is connected to the reference voltage generation unit 22 and is used to generate the undervoltage threshold voltage Vunder, the overvoltage threshold voltage Vover, and the power frequency threshold voltage Vth according to the reference voltage Vref. The regulated power supply 24 is connected to the reference voltage generation unit 22 and is used to generate a constant power supply voltage VDD according to the reference voltage Vref to supply power to each module in the over-undervoltage detection circuit. For example, the power supply voltage VDD is provided for the reference voltage generation unit 22 to ensure the stability of the reference voltage Vref output by the reference voltage generation unit 22, and further ensure the stability of the undervoltage threshold voltage Vunder, the overvoltage threshold voltage Vover, and the power frequency threshold voltage Vth. The reference voltage Vref is used to provide a reference value for the power supply voltage VDD to control the magnitude of the power supply voltage VDD.

[0121] Further, the first voltage comparison module 30 includes a first comparator Comp1, a second comparator Comp2, and a third comparator Comp3. Among them, the negative input terminal of the first comparator Comp1 is used to receive the undervoltage threshold voltage Vunder, the positive input terminal of the first comparator Comp1 is connected to the voltage dividing unit and is used to receive the sampled voltage signal Vsamp. The first comparator Comp1 compares the undervoltage threshold voltage Vunder with the sampled voltage signal Vsamp and outputs a first comparison signal VA representing the magnitude relationship between the undervoltage threshold voltage Vunder and the sampled voltage signal Vsamp. Similarly, the negative input terminal of the second comparator Comp2 is used to receive the overvoltage threshold voltage Vover, the positive input terminal of the second comparator Comp2 is connected to the voltage dividing unit and is used to receive the sampled voltage signal Vsamp. The second comparator Comp2 compares the overvoltage threshold voltage Vover with the sampled voltage signal Vsamp and outputs a second comparison signal VB representing the magnitude relationship between the overvoltage threshold voltage Vover and the sampled voltage signal Vsamp. The negative input terminal of the third comparator Comp3 is used to receive the power frequency threshold voltage Vth, the positive input terminal of the third comparator Comp3 is connected to the output terminal of the voltage dividing unit and is used to receive the sampled voltage signal Vsamp. The third comparator Comp3 compares the power frequency threshold voltage Vth with the sampled voltage signal Vsamp and outputs a power frequency signal Phase representing the magnitude relationship between the power frequency threshold voltage Vth and the sampled voltage signal Vsamp. The frequency of the power frequency signal Phase can also represent the frequency of the sampled voltage signal Vsamp at the same time.

[0122] In this embodiment, the sampled voltage signal Vsamp is provided to the positive input terminals of the first comparator Comp1, the second comparator Comp2, and the third comparator Comp3, while the under-voltage threshold voltage Vunder, the over-voltage threshold voltage Vover, and the power-frequency threshold voltage Vth are respectively provided to the negative input terminals of the first comparator Comp1, the second comparator Comp2, and the third comparator Comp3. When the sampled voltage signal Vsamp is greater than the under-voltage threshold voltage Vunder, the first comparison signal VA output by the first comparator Comp1 is at a high level. Conversely, when the sampled voltage signal Vsamp is less than the under-voltage threshold voltage Vunder, the first comparison signal VA output by the first comparator Comp1 is at a low level. Similarly, when the sampled voltage signal Vsamp is greater than the over-voltage threshold voltage Vover, the second comparison signal VB output by the second comparator Comp2 is at a high level. Conversely, when the sampled voltage signal Vsamp is less than the over-voltage threshold voltage Vover, the second comparison signal VB output by the second comparator Comp2 is at a low level. Similarly, when the sampled voltage signal Vsamp is greater than the power-frequency threshold voltage Vth, the power-frequency signal Phase output by the third comparator Comp3 is at a high level. Conversely, when the sampled voltage signal Vsamp is less than the power-frequency threshold voltage Vth, the power-frequency signal Phase output by the third comparator Comp3 is at a low level.

[0123] It should be understood that as an alternative embodiment, the sampled voltage signal Vsamp can also be provided to the negative input terminals of the first comparator Comp1, the second comparator Comp2, and the third comparator Comp3, while the under-voltage threshold voltage Vunder, the over-voltage threshold voltage Vover, and the power-frequency threshold voltage Vth are respectively provided to the positive input terminals of the first comparator Comp1, the second comparator Comp2, and the third comparator Comp3, which will not be explained one by one here.

[0124] Next, step S300 is executed. When the first enable signal Clear is valid, m cycles of the first comparison signal VA and the second comparison signal VB are respectively detected to obtain a first characteristic signal VERA and a second characteristic signal VERB, and a classification signal Ocheck indicating whether the power grid is over-voltage or under-voltage is generated according to the first characteristic signal VERA and the second characteristic signal VERB, where m≥1.

[0125] Specifically, the control circuit includes a power-on self-check module 40, a counter module 50, a periodic anti-interference detection module 60, an edge detection module 70, and a classification module 80.

[0126] The power-on self-check module 40 is configured to perform edge detection on q cycles of the industrial frequency signal Phase according to the power-on reset signal POR, and generate a valid second enable signal POST when each of the q cycles of the industrial frequency signal has a rising edge / falling edge, so as to control the counter module 50 and the periodic anti-interference detection module 60 to start working, where q≥1.

[0127] Specifically, the power-on self-check module 40 is connected to the third comparator Comp3 and the power-on reset unit 21, and is configured to receive the industrial frequency signal Phase and the power-on reset signal POR. The power-on self-check module 40 performs power-on reset when receiving the power-on reset signal POR, and performs edge detection on q cycles of the industrial frequency signal Phase under the control of the power-on reset signal POR, and outputs a second enable signal POST characterizing whether each of the q cycles of the industrial frequency signal Phase has a rising edge / falling edge. In this embodiment, when each of the q cycles of the industrial frequency signal Phase has a rising edge / falling edge, it indicates that the power grid starts to work. At this time, the second enable signal POST is at a high level and the second enable signal POST is valid; conversely, when any one of the q cycles of the industrial frequency signal Phase does not have a rising edge / falling edge, it indicates that the power grid has not started to work. At this time, the second enable signal POST is at a low level and the second enable signal POST is invalid, but it is not limited thereto.

[0128] The power-on self-check module 40 can improve the reliability of the entire circuit. In some embodiments, the power-on self-check module 40 can be omitted.

[0129] The power-on self-check module 40 includes s flip-flops, and s flip-flops are used to perform edge detection on q cycles of the industrial frequency signal Phase, where s≥1, and q and s satisfy the following relationship:

[0130] q = 2 (s-1) 。

[0131] In this embodiment, s = 3, that is to say, the power-on self-check module 40 detects 4 consecutive cycles of the industrial frequency signal Phase. If each of the 4 cycles of the power-on self-check module 40 has a rising edge / falling edge (the method of judging the falling edge is adopted in this embodiment), the second enable signal POST jumps to a high level.

[0132] Further, the counter module 50 is configured to generate the first enable signal Clear according to the industrial frequency signal Phase.

[0133] Specifically, the counter module 50 is connected to the power-on self-test module 40 and the third comparator Comp3, and is configured to receive the second enable signal POST and the power frequency signal Phase respectively. When the counter module 50 receives the valid second enable signal POST, it starts counting to obtain g cycles of the power frequency signal Phase, and outputs a valid third enable signal Validation after g cycles of the power frequency signal Phase, that is, the rising edge interval between the second enable signal POST and the third enable signal Validation is g cycles of the power frequency signal Phase.

[0134] Specifically, the counter module 50 includes a frequency division unit and a logic operation unit. The frequency division unit is connected to the third comparator Comp3 and the power-on self-test module 40, and is configured to receive the power frequency signal Phase and the second enable signal POST. When the second enable signal POST is at a high level (valid), the counter module 50 starts to work, performs p-frequency division on the power frequency signal Phase n times to obtain n-level frequency division signals, where n, p ≥ 2. The logic operation unit is connected to the frequency division unit and is configured to perform a logic operation on the second-level to n-level frequency division signals and output the first enable signal Clear.

[0135] The first enable signal Clear is a periodic signal. Each period of the first enable signal Clear includes a detection time and a clearing time. The first enable signal Clear is valid during the detection time and invalid during the clearing time. When the first enable signal Clear is invalid, the first characteristic signal VERA and the second characteristic signal VERB are cleared.

[0136] In this embodiment, g and n satisfy the following relationship:

[0137] g = 2 (n-1) 。

[0138] Optionally, when the counter module 50 receives the valid second enable signal POST, it starts counting to obtain g cycles of the power frequency signal Phase, and outputs the n-level frequency division signal after g cycles of the power frequency signal Phase, and uses the n-level frequency division signal as the third enable signal Validation for output. The function of the third enable signal Validation will be described below.

[0139] Further, the logic operation unit is an OR gate. The OR gate performs an OR operation on the second-stage frequency division signal to the nth-stage frequency division signal to obtain the first enable signal Clear. At this time, the first enable signal Clear is a periodic signal, and the pulse width of the first enable signal Clear is the sum of the pulse widths of the second-stage frequency division signal to the nth-stage frequency division signal. Therefore, after dividing the industrial frequency signal Phase and performing a logic operation on the divided frequency signals, the pulse width of the first enable signal Clear increases, so that the detection time of each period of the first enable signal Clear is greater than m periods of the first comparison signal VA and m periods of the second comparison signal VB.

[0140] In this embodiment, p = 2 and n = 4. That is to say, the frequency division unit divides the industrial frequency signal Phase by 2 four times to obtain the first-stage frequency division signal (2 1 ), the second-stage frequency division signal (2 2 ), the third-stage frequency division signal (2 3 ), and the fourth-stage frequency division signal (2 4 ). The first enable signal Clear is a signal obtained by performing an OR operation on the second-stage frequency division signal (2 2 ), the third-stage frequency division signal (2 3 ), and the fourth-stage frequency division signal (2 4 ). The third enable signal Validation is the fourth-stage frequency division signal (2 4 ).

[0141] It should be understood that in some embodiments, the counter module 50 can be omitted, and the first enable signal Clear can be designed and input into the periodic anti-interference detection module 60 from the outside.

[0142] Further, the periodic anti-interference detection module 60 is configured to detect m periods of the first comparison signal VA and the second comparison signal VB respectively when the first enable signal Clear is valid to obtain a first characteristic signal VERA and a second characteristic signal VERB, and clear the first characteristic signal VERA and the second characteristic signal VERB when the first enable signal Clear is invalid. It should be understood that since the pulse width of each period of the first enable signal Clear is greater than m periods of the first comparison signal VA and m periods of the second comparison signal VB, when the periodic anti-interference detection module 60 performs edge detection on m periods of the first comparison signal VA and the second comparison signal VB within each period of the first enable signal Clear, the situation of insufficient detection time can be avoided.

[0143] Specifically, when the first enable signal Clear is valid, the periodic anti-interference detection module 60 performs edge detection on m cycles of the first comparison signal VA and the second comparison signal VB respectively, to obtain the first characteristic signal VERA indicating whether each cycle of the first comparison signal VA has a rising edge / falling edge within m cycles, and the second characteristic signal VERB indicating whether each cycle of the second comparison signal VB has a rising edge / falling edge within m cycles, and determines whether the power grid is overvoltage or undervoltage by using the first characteristic signal VERA and the second characteristic signal VERB.

[0144] Specifically, the periodic anti-interference detection module 60 is connected to the counter module 50, the first comparator Comp1, the second comparator Comp2, and the power-on self-check module 40, and is used to receive the first enable signal Clear, the first comparison signal VA, the second comparison signal VB, and the second enable signal POST respectively. When the second enable signal POST is at a high level (valid), the periodic anti-interference detection module 60 starts to work, and performs edge detection on m cycles of the first comparison signal VA and the second comparison signal VB in each cycle of the first enable signal Clear, to obtain the first characteristic signal VERA indicating whether each cycle of the first comparison signal VA has a rising edge / falling edge within m cycles, and the second characteristic signal VERB indicating whether each cycle of the second comparison signal VB has a rising edge / falling edge within m cycles.

[0145] After obtaining the first characteristic signal VERA and the second characteristic signal VERB, the periodic anti-interference detection module 60 immediately latches the valid levels of the first characteristic signal VERA and the second characteristic signal VERB until the end of the detection time of each cycle of the first enable signal Clear, and clears (or can be understood as resets) the valid levels of the first characteristic signal VERA and the second characteristic signal VERB at the clearing time of each cycle of the first enable signal Clear, so that the first characteristic signal VERA and the second characteristic signal VERB detected in the previous cycle do not affect the detection of the next cycle.

[0146] It should be understood that since the periodic anti-interference detection module 60 performs edge detection on m cycles of the first comparison signal VA and the second comparison signal VB, at this time, the classification signal Ocheck generated according to the first characteristic signal VERA and the second characteristic signal VERB can accurately determine whether the power grid is overvoltage or undervoltage. Since m cycles of the first comparison signal VA and the second comparison signal VB are detected, it can resist non-continuous-time interference, prevent misoperation caused by interference, ensure non-tripping during instantaneous overvoltage and instantaneous undervoltage fluctuations of the power grid, and improve the detection accuracy and anti-interference ability.

[0147] In this embodiment, a falling-edge detection is performed on m cycles of the first comparison signal VA and the second comparison signal VB within each cycle of the first enable signal Clear. When the first comparison signal VA has a falling edge in each of the m cycles, the first characteristic signal VERA is at a high level; conversely, when the first comparison signal VA does not have a falling edge in any one of the m cycles, the first characteristic signal VERA is at a low level. Similarly, when the second comparison signal VB has a falling edge in each of the m cycles, the second characteristic signal VERB is at a high level; conversely, when the second comparison signal VB does not have a falling edge in any one of the m cycles, the second characteristic signal VERB is at a low level, but this should not be taken as a limitation.

[0148] It should be understood that increasing the number of cycles (i.e., m) for each edge detection of the first comparison signal VA and the second comparison signal VB can improve the detection accuracy. In this embodiment, m = 4.

[0149] Furthermore, the edge detection module 70 is used to perform edge detection on the first characteristic signal VERA and the second characteristic signal VERB respectively, so as to obtain a first classification signal indicating whether the first characteristic signal VERA has a rising edge / falling edge and a second classification signal indicating whether the second characteristic signal VERB has a rising edge / falling edge.

[0150] Furthermore, the edge detection module 70 is used to perform edge detection on the first characteristic signal VERA and the second characteristic signal VERB respectively, so as to obtain a first classification signal QA indicating whether the first characteristic signal VERA has a rising edge / falling edge and a second classification signal QB indicating whether the second characteristic signal VERB has a rising edge / falling edge.

[0151] Specifically, the edge detection module 70 is connected to the periodic anti-interference detection module 60, and is configured to receive the first characteristic signal VERA and the second characteristic signal VERB, and perform edge detection on the first characteristic signal VERA and the second characteristic signal VERB to obtain a first classification signal QA indicating whether the first characteristic signal VERA has a rising edge / falling edge and a second classification signal QB indicating whether the second characteristic signal VERB has a rising edge / falling edge. The first classification signal QA can follow the level characteristic of the first characteristic signal VERA, and the second classification signal QB can follow the characteristic of the second characteristic signal VERB. When the first characteristic signal VERA and the second characteristic signal VERB are cleared, the first classification signal QA and the second classification signal QB can be maintained.

[0152] In this embodiment, the edge detection module 70 is configured to perform rising edge detection on the first characteristic signal VERA and the second characteristic signal VERB. When the first characteristic signal VERA jumps to a high level, the edge detection module 70 detects the rising edge of the first characteristic signal VERA. At this time, the first classification signal QA jumps to a high level; conversely, when the edge detection module 70 does not detect the rising edge of the first characteristic signal VERA, at this time, the first classification signal QA is at a low level. Similarly, when the second characteristic signal VERB jumps to a high level, the edge detection module 70 detects the rising edge of the second characteristic signal VERB. At this time, the second classification signal QB jumps to a high level; conversely, when the edge detection module 70 does not detect the rising edge of the second characteristic signal VERB, at this time, the second classification signal QB is at a low level.

[0153] The classification module 80 is configured to perform a logical operation on the first classification signal QA and the second classification signal QB to obtain the classification signal Ocheck.

[0154] Specifically, the classification module 80 is respectively connected to the edge detection module 70, and is configured to perform a logical operation on the first classification signal QA and the second classification signal QB to obtain a classification signal Ocheck indicating whether the power grid is overvoltage or undervoltage, and use the classification signal Ocheck to determine whether the power grid is overvoltage or undervoltage. In this embodiment, when the classification signal Ocheck is at a high level, it indicates that the power grid has overvoltage or undervoltage. When the classification signal Ocheck is at a low level, it indicates that the power grid is normal.

[0155] In this embodiment, when the edge detection module 70 does not detect the rising edges of the first feature signal VERA and the second feature signal VERB, the first classification signal QA and the second classification signal QB are at a low level. When the edge detection module 70 detects the rising edges of the first feature signal VERA and the second feature signal VERB, the first classification signal QA and the second classification signal QB jump to a high level. However, there may be a time difference in the jump times of the first classification signal QA and the second classification signal QB, resulting in an error in the result of the logical operation on the first classification signal QA and the second classification signal QB (for example, one of the first classification signal QA and the second classification signal QB jumps to a high level while the other is still at a low level, and the result of the logical operation will be incorrect), leading to abnormal function of over- and under-voltage detection. Moreover, since the first classification signal QA and the second classification signal QB are at a low level when the edge detection module 70 does not detect the rising edges of the first feature signal VERA and the second feature signal VERB, or when over- and under-voltage detection has not started yet, performing a logical operation on two low levels may also cause the classification signal Ocheck to be at a high level, resulting in abnormal function of over- and under-voltage detection.

[0156] Based on this, in order to ensure the correct output of the classification signal Ocheck, it is necessary to delay the output of the classification signal Ocheck for a period of time. In this embodiment, the third enable signal Validation is used to control the output of the classification signal Ocheck. Specifically, the classification module 80 is also connected to the counter module 50. After the classification module 80 performs a logical operation on the first classification signal QA and the second classification signal QB, it also performs a logical operation on the result of the logical operation and the third enable signal Validation to obtain the classification signal Ocheck.

[0157] In this embodiment, the classification module 80 includes an exclusive-NOR gate and an AND gate. The exclusive-NOR gate is connected to the edge detection module 70 and is used to perform an exclusive-NOR operation on the first classification signal QA and the second classification signal QB. The AND gate is connected to the counter module 50 and the exclusive-NOR gate and is used to receive the third enable signal Validation and the operation result of the exclusive-NOR gate, and perform an AND operation on the operation result and the third enable signal Validation to obtain the classification signal Ocheck. In this way, the output time of the classification signal Ocheck can follow the jump time of the third enable signal Validation.

[0158] Further, in order to ensure the delayed output of the classification signal Ocheck, the periodic anti-interference detection module 60 has r flip-flops, where 1 < r ≤ n - 1, and m and r satisfy the following relationship:

[0159] m = 2 (r-1) 。

[0160] At this time, it can be ensured that the starting time of the third enable signal Validation is later than the starting times of the first classification signal QA and the second classification signal QB.

[0161] Next, the circuit timing of the over-voltage and under-voltage detection circuit in this embodiment will be described in detail in conjunction with Table 1 and Figures 3a to 3c Among them, Table 1 shows the characteristics of the key signals of the over-voltage and under-voltage detection circuit when the power grid is at normal voltage, over-voltage, and under-voltage, Figures 3a to 3c which are the circuit timing diagrams of the over-voltage and under-voltage detection circuit when the power grid is at normal voltage, over-voltage, and under-voltage, respectively.

[0162] Table 1: Characteristics of Key Signals of Over-Voltage and Under-Voltage Detection Circuit when Power Grid is at Normal Voltage, Over-Voltage, and Under-Voltage

[0163]

[0164] Combined with Figure 2a 、 Figure 2b and Figure 3a As shown, when the over-voltage and under-voltage detection circuit is powered on, the power-on reset unit 21 outputs a power-on reset signal POR. The power-on self-check module 40 is powered on and reset under the control of the power-on reset signal POR, and starts to perform edge detection on the power frequency signal Phase. At time T0, it is detected that each cycle within q cycles of the power frequency signal Phase has a rising edge / falling edge. At this time, the second enable signal POST jumps to a high level. At the same time, the first voltage comparison module 30 starts to work. As Figure 3a and Table 1 show, when the power grid is at normal voltage, the sampled voltage signal Vsamp is greater than the under-voltage threshold voltage Vunder and less than the over-voltage threshold voltage Vover. The first comparison signal VA will periodically appear high and low levels (after half-wave rectification, only half a cycle of the AC signal of the power grid is retained in the sampled voltage signal Vsamp), which is a rectangular wave signal. The second comparison signal VB is at a low level.

[0165] When the second enable signal POST jumps to a high level, under the control of the second enable signal POST, the counter module 50 outputs the first enable signal Clear and the third enable signal Validation. T1 to T5 are the detection times for one period of the first enable signal Clear. At time T1, the periodic anti-interference detection module 60 starts to perform edge detection on 4 periods of the first comparison signal VA and the second comparison signal VB. Since the first comparison signal VA is a periodic high and low level with continuous rising edges, at time T2a, the first characteristic signal VERA jumps to a high level; the second comparison signal VB does not have continuous rising edges, and the second characteristic signal VERB always remains at a low level.

[0166] The edge detection module 70 performs edge detection on the first characteristic signal VERA and the second characteristic signal VERB to obtain the first classification signal QA and the second classification signal QB. Since the first characteristic signal VERA is at a high level after time T2a and has a rising edge, at time T2a, the first classification signal QA jumps to a high level; since the second characteristic signal VERB always remains at a low level and has no rising edge, the second classification signal QB remains at a low level.

[0167] The classification module 80 performs an exclusive-NOR operation on the first classification signal QA and the second classification signal QB, and then performs an AND operation on the operation result and the third enable signal Validation, and outputs the classification signal Ocheck at times T4 to T5. At this time, the classification signal Ocheck is at a low level, indicating that the power grid is in a normal state.

[0168] At time T5, the detection time for one period of the first enable signal Clear ends. After time T5, it enters the clearing time to clear the first characteristic signal VERA and the second characteristic signal VERB, and waits to start detection again in the next period, while the first classification signal QA and the second classification signal QB can be retained.

[0169] Combined with Table 1 and Figure 3b As shown, when the power grid is overvoltage, the sampled voltage signal Vsamp is greater than the undervoltage threshold voltage Vunder and the overvoltage threshold voltage Vover, and both the first comparison signal VA and the second comparison signal VB will periodically appear as high and low levels (after half-wave rectification, the sampled voltage signal Vsamp only retains half of the AC signal of the power grid).

[0170] T1 to T5 are the detection times for one period of the first enable signal Clear. At time T1, the periodic anti-interference detection module 60 starts to perform edge detection on 4 periods of the first comparison signal VA and the second comparison signal VB. Since both the first comparison signal VA and the second comparison signal VB have periodic high and low levels and continuous rising edges, at time T2a, the first characteristic signal VERA jumps to a high level, and at time T2b (usually there is a small time difference between T2a and T2b), the second characteristic signal VERB jumps to a high level.

[0171] The edge detection module 70 performs edge detection on the first characteristic signal VERA and the second characteristic signal VERB to obtain the first classification signal QA and the second classification signal QB. Since the first characteristic signal VERA and the second characteristic signal VERB are both high levels after time T2a and T2b respectively and both have rising edges, at time T2a, the first classification signal QA jumps to a high level, and at time T2b, the second classification signal QB jumps to a high level.

[0172] The classification module 80 performs an exclusive-NOR operation on the first classification signal QA and the second classification signal QB, and then performs an AND operation on the operation result and the third enable signal Validation, and outputs the classification signal Ocheck at times T4 to T5. At this time, the classification signal Ocheck is at a high level, indicating that the power grid is in an overvoltage or undervoltage state.

[0173] Combined with Table 1 and Figure 3c As shown, when the power grid is in an undervoltage state, the sampled voltage signal Vsamp is less than the undervoltage threshold voltage Vunder and the overvoltage threshold voltage Vover, and the first comparison signal VA and the second comparison signal VB always remain at a low level.

[0174] T1 to T5 are the detection times for one period of the first enable signal Clear. At time T1, the periodic anti-interference detection module 60 starts to perform edge detection on 4 periods of the first comparison signal VA and the second comparison signal VB. Since both the first comparison signal VA and the second comparison signal VB are at a low level and there are no continuous rising edges, the first characteristic signal VERA and the second comparison signal VB also always remain at a low level.

[0175] The edge detection module 70 performs edge detection on the first feature signal VERA and the second feature signal VERB to obtain the first classification signal QA and the second classification signal QB. Since the first feature signal VERA and the second feature signal VERB always maintain a low level and there are no rising edges, the first classification signal QA and the second classification signal QB also maintain a low level.

[0176] The classification module 80 performs an exclusive NOR operation on the first classification signal QA and the second classification signal QB, and then performs an AND operation on the operation result and the third enable signal Validation to output the classification signal Ocheck at times T4 to T5. At this time, the classification signal Ocheck is at a high level, indicating that the power grid is in an overvoltage or undervoltage state.

[0177] It can be seen that the over- and under-voltage detection circuit in this embodiment can determine whether the power grid is overvoltage or undervoltage.

[0178] Further, the power grid protection circuit further includes a leakage protection circuit. Among them, the over- and under-voltage detection circuit is connected to the live wire L of the power grid to sample the AC voltage of the power grid, and the leakage protection circuit receives the leakage voltage Input of the power grid.

[0179] The power grid protection circuit integrates the over- and under-voltage detection circuit and the leakage protection circuit together, so that the power grid protection circuit has both the functions of leakage protection and over- and under-voltage detection, and is simple to apply, has high precision, and strong anti-interference ability.

[0180] In this embodiment, the leakage protection circuit and the basic signal generation module 20, the first voltage comparison module 30 and the control circuit of the over- and under-voltage protection circuit are integrated in the same chip, and the over- and under-voltage detection and under-voltage detection share the pin for receiving the sampling voltage signal Vsamp. As an alternative embodiment, the leakage protection circuit and the over- and under-voltage detection circuit can also be integrated in the same chip using a high-voltage process, which reduces the complexity of the system, is more user-friendly to application technicians, and is convenient for system testing and operation and maintenance.

[0181] Please continue to refer to Figure 2a , the leakage protection circuit includes a signal amplification module 90, a second voltage comparison module, a logic processing module, a delay module 100 and a drive module 110. The power-on reset unit 21 also provides the power-on reset signal POR for the signal amplification module 90, the delay module 100 and the drive module 110 at the same time.

[0182] Specifically, the signal amplification module 90 is configured to receive the leakage voltage Input of the power grid and amplify the leakage voltage to obtain a voltage amplified signal AmpOut. The second voltage comparison module includes a fourth comparator Comp4. The positive input terminal of the fourth comparator Comp4 is connected to the signal amplification module 90 for receiving the voltage amplified signal AmpOut, and the positive input terminal of the fourth comparator Comp4 is connected to the reference voltage generation unit 22 for receiving the reference voltage Vref. The fourth comparator Comp4 compares the voltage amplified signal AmpOut with the reference voltage Vref, and then outputs a third comparison signal representing the magnitude relationship between the voltage amplified signal AmpOut and the reference voltage Vref.

[0183] The third comparison signal can also be used to represent whether the leakage voltage Input meets the control requirements. The reference voltage Vref is designed as the maximum leakage voltage that the system can tolerate. When the voltage amplified signal AmpOut is greater than the reference voltage Vref, it indicates that the power grid is leaking electricity; otherwise, it indicates that the power grid is normal.

[0184] Further, the detection results of the leakage protection circuit and the over / under voltage detection circuit are used together to control the on / off of the power grid. The logic processing module is connected to the over / under voltage detection circuit and the second voltage comparison module, and is configured to receive the third comparison signal and the classification signal Ocheck, and then perform a logic operation on the third comparison signal and the classification signal Ocheck output by the over / under voltage detection circuit to obtain a control signal Ctrl for controlling the on / off of the power grid.

[0185] In this embodiment, the logic processing module is an OR gate, and the third comparison signal and the classification signal Ocheck are subjected to an OR operation to obtain the control signal Ctrl, but this should not be taken as a limitation.

[0186] Further, the delay module 100 is connected to the logic processing module and the reference voltage Vref generation module, and is configured to receive the control signal Ctrl and the reference voltage Vref, and delay the output of the control signal Ctrl to prevent the leakage protection from malfunctioning due to interference. The drive module 110 is connected to the delay module 100, and is configured to receive the delayed control signal Ctrl and enhance the driving ability of the control signal Ctrl, and finally output the drive signal Output.

[0187] Optionally, the drive module 110 is connected to the trip module of the power grid, and controls the trip module through the drive signal Output, thereby controlling the on / off of the power grid.

[0188] Figure 4 The application diagram of the power grid protection circuit provided for this embodiment. As Figure 4 shown, the signal acquisition module 10 is connected to the live wire L of the power grid to acquire the sampled voltage signal Vsamp. An induction module 130 is connected between the live wire L and the neutral wire N of the power grid to obtain the leakage voltage Input of the power grid. After integrating the basic signal generation module 20, the first voltage comparison module 30, and the control circuit of the leakage protection circuit and the over- and under-voltage protection circuit on the same chip, the signal input end of the chip is connected to the output end of the signal acquisition module 10 and the output end of the induction module 130; a tripping module 140 is connected between the live wire L and the neutral wire N of the power grid, and the output end of the chip is connected to the tripping module 140 to control the on / off of the power grid by controlling the tripping module 140. At the same time, the power grid powers the chip through the power supply module 120.

[0189] Embodiment 2

[0190] The difference from Embodiment 1 is that in this embodiment, when rectifying the AC voltage of the power grid to obtain the rectified signal, full-wave rectification is performed on the AC voltage of the power grid.

[0191] Figures 5a to 5c They are respectively the circuit timing diagrams of the over- and under-voltage detection circuit when the power grid is at normal voltage, overvoltage, and undervoltage. By comparing Figure 3a and Figure 5a , comparing Figure 3b and Figure 5b as well as comparing Figure 3c and Figure 5c it can be obtained that when performing full-wave rectification on the AC voltage of the power grid, the sampled voltage signal Vsamp can reflect the entire cycle of the AC voltage of the power grid, but the timing of the over- and under-voltage detection circuit will not change. Therefore, the rectifying unit can be a full-wave rectifying unit for performing full-wave rectification on the AC voltage of the power grid.

[0192] In summary, in the power grid protection circuit and method provided by the present invention, the over- and under-voltage detection circuit can implement the functions of over-voltage detection and under-voltage detection. The over-voltage detection and under-voltage detection share pins, and the entire circuit only requires one input port, reducing the scale and complexity of the circuit and facilitating maintenance. Further, when the first enable signal is valid, the m cycles of the first comparison signal and the second comparison signal are respectively detected. At this time, the obtained first characteristic signal and the second characteristic signal can be used to generate a classification signal indicating whether the power grid is over-voltage or under-voltage, realizing over- and under-voltage detection. And because the m cycles of the first comparison signal and the second comparison signal are detected, it can resist non-continuous time interference, prevent misoperation caused by interference, ensure non-tripping during instantaneous over-voltage and instantaneous under-voltage fluctuations of the power grid, and improve the detection accuracy and anti-interference ability. Further, the valid levels of the first characteristic signal and the second characteristic signal are latched until the end of the detection time of each cycle of the first enable signal, and the valid levels of the first characteristic signal and the second characteristic signal are cleared at the clearing time of each cycle of the first enable signal, without affecting the detection of the next cycle. Further, the over- and under-voltage detection circuit is integrated with the leakage protection circuit, so that the power grid protection circuit has both the functions of leakage protection and over- and under-voltage detection, and is simple to apply, has high precision, and strong anti-interference ability. And the leakage protection circuit and the over- and under-voltage detection circuit can be integrated on the same chip, reducing the complexity of the system, being more user-friendly to application technicians, and facilitating system testing and operation and maintenance.

[0193] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art within the technical field, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content of the technical solution of the present invention and are still within the protection scope of the present invention.

Claims

1. A power grid protection circuit, characterized in that, it includes: an over- and under-voltage detection circuit, and the over- and under-voltage detection circuit includes: a signal acquisition module for sampling the AC voltage of the power grid to obtain a sampled voltage signal; a basic signal generation module for generating an under-voltage threshold voltage and an over-voltage threshold voltage; a first voltage comparison module connected to the signal acquisition module and the basic signal generation module for comparing the sampled voltage signal with the under-voltage threshold voltage and the over-voltage threshold voltage respectively to obtain a first comparison signal and a second comparison signal; and, a control circuit connected to the first voltage comparison module for detecting m cycles of the first comparison signal and the second comparison signal respectively when a first enable signal is valid to obtain a first characteristic signal and a second characteristic signal, and generating a classification signal indicating whether the power grid is over-voltage or under-voltage according to the first characteristic signal and the second characteristic signal, where m≥1; wherein, the first voltage comparison module includes a first comparator, a second comparator and a third comparator; the negative input terminal of the first comparator is used to receive the under-voltage threshold voltage, the positive input terminal of the first comparator is used to receive the sampled voltage signal, the first comparator compares the under-voltage threshold voltage with the sampled voltage signal and outputs a first comparison signal indicating the magnitude relationship between the under-voltage threshold voltage and the sampled voltage signal; the negative input terminal of the second comparator is used to receive the over-voltage threshold voltage, the positive input terminal of the second comparator is used to receive the sampled voltage signal, the second comparator compares the over-voltage threshold voltage with the sampled voltage signal and outputs a second comparison signal indicating the magnitude relationship between the over-voltage threshold voltage and the sampled voltage signal; the negative input terminal of the third comparator is used to receive the power frequency threshold voltage, the positive input terminal of the third comparator is used to receive the sampled voltage signal, the third comparator compares the power frequency threshold voltage with the sampled voltage signal and outputs a power frequency signal indicating the magnitude relationship between the power frequency threshold voltage and the sampled voltage signal.

2. The power grid protection circuit according to claim 1, characterized in that, the first enable signal is a periodic signal, each period of the first enable signal includes a detection time and a clearing time, the first enable signal is valid during the detection time and invalid during the clearing time, and the detection time is greater than m cycles of the first comparison signal and m cycles of the second comparison signal.

3. The power grid protection circuit according to claim 2, characterized in that, latch the valid levels of the first characteristic signal and the second characteristic signal until the end of the detection time of each period of the first enable signal, and clear the valid levels of the first characteristic signal and the second characteristic signal during the clearing time of each period of the first enable signal.

4. The power grid protection circuit according to any one of claims 1 to 3, characterized in that, the control circuit includes: A periodic anti-interference detection module, connected to the first voltage comparison module, is configured to detect m periods of the first comparison signal and the second comparison signal respectively when the first enable signal is valid, so as to obtain a first characteristic signal and a second characteristic signal; An edge detection module, connected to the periodic anti-interference detection module, is configured to perform edge detection on the first characteristic signal and the second characteristic signal respectively, so as to obtain a first classification signal indicating whether the first characteristic signal has a rising edge / falling edge and a second classification signal indicating whether the second characteristic signal has a rising edge / falling edge; and, A classification module, connected to the edge detection module, is configured to perform a logical operation on the first classification signal and the second classification signal to obtain the classification signal.

5. The power grid protection circuit according to claim 4, wherein, when the first enable signal is valid, the periodic anti-interference detection module performs edge detection on m periods of the first comparison signal and the second comparison signal respectively, so as to obtain the first characteristic signal for indicating whether each period of the first comparison signal has a rising edge / falling edge within m periods and obtain the second characteristic signal for indicating whether each period of the second comparison signal has a rising edge / falling edge within m periods.

6. The power grid protection circuit according to claim 4, wherein, the control circuit further includes: A counter module, connected to the periodic anti-interference detection module and the first voltage comparison module, is configured to generate the first enable signal according to the power frequency signal.

7. The power grid protection circuit according to claim 6, wherein, the counter module includes: A frequency division unit, connected to the first voltage comparison module, is configured to perform p-frequency division on the power frequency signal n times to obtain n-level frequency division signals, where n, p≥2; and, A logic operation unit, connected to the frequency division unit, is configured to perform a logical operation on the second-level frequency division signal to the n-level frequency division signal to obtain the first enable signal.

8. The power grid protection circuit according to claim 7, wherein, the pulse width of the first enable signal is equal to the sum of the pulse widths of the second-level frequency division signal to the n-level frequency division signal.

9. The power grid protection circuit according to claim 7, wherein, the control circuit further includes: A power-on self-check module, connected to the first voltage comparison module, the counter module and the periodic anti-interference detection module, is configured to perform edge detection on q periods of the power frequency signal according to the power-on reset signal, and generate a valid second enable signal to control the counter module and the periodic anti-interference detection module to start working when each period within q periods of the power frequency signal has a rising edge / falling edge, where q≥1.

10. The power grid protection circuit according to claim 9, wherein, the rising edge of the second enable signal is spaced from the rising edge of the n-level frequency division signal by g periods of the power frequency signal, where g and n satisfy the following relationship: g＝2 (n-1) 。 11. The power grid protection circuit according to claim 9, wherein, The power-on self-check module has s flip-flops, where s≥1, and q and s satisfy the following relationship: q＝2 (s-1) 。 12. The power grid protection circuit according to claim 7, characterized in that The classification module is further connected to the counter module, receives the nth-stage frequency division signal, and after performing a logical operation on the first classification signal and the second classification signal, performs a logical operation on the result of the logical operation and the nth-stage frequency division signal to obtain the classification signal.

13. The power grid protection circuit according to claim 12, characterized in that The classification module includes: An exclusive-NOR gate, connected to the edge detection module, for performing an exclusive-NOR operation on the first classification signal and the second classification signal; and An AND gate, connected to the counter module and the exclusive-NOR gate, for performing an AND operation on the result of the exclusive-NOR operation and the nth-stage frequency division signal to obtain the classification signal.

14. The power grid protection circuit according to claim 7, characterized in that The periodic anti-interference detection module has r flip-flops, where 1<r≤n - 1, and m and r satisfy the following relationship: m＝2 (r-1) 。 15. The power grid protection circuit according to claim 1, characterized in that The signal acquisition module includes: A rectification unit, for rectifying the AC voltage of the power grid to obtain a rectified signal; and A voltage division unit, connected to the rectification unit, for dividing the rectified signal to obtain the sampled voltage signal.

16. The power grid protection circuit according to claim 1, characterized in that The basic signal generation module includes: A reference voltage generation unit, for generating a reference voltage; and A voltage stabilization unit, connected to the reference voltage generation unit, for generating the under-voltage threshold voltage, the over-voltage threshold voltage, and the power frequency threshold voltage according to the reference voltage; A regulated power supply, connected to the reference voltage generation unit, for generating a constant power supply voltage according to the reference voltage.

17. The power grid protection circuit according to claim 9, characterized in that The basic signal generation module further includes: A power-on reset unit, for generating the power-on reset signal.

18. The power grid protection circuit according to claim 1, characterized in that The power grid protection circuit further includes a leakage protection circuit, and the leakage protection circuit is used to detect whether the power grid is leaking, and jointly control the on / off of the power grid according to the leakage detection result and the classification signal.

19. The power grid protection circuit according to claim 18, characterized in that The leakage protection circuit includes: A signal amplification module, connected to the power grid, for amplifying the leakage voltage of the power grid to obtain a voltage amplification signal; A second voltage comparison module, connected to the signal amplification module, for comparing the voltage amplification signal with a reference voltage to obtain a third comparison signal; and A logic processing module, connected to the over- and under-voltage detection circuit and the second voltage comparison module, for performing a logical operation on the third comparison signal and the classification signal to obtain a control signal for controlling the on / off of the power grid.

20. The power grid protection circuit according to claim 19, characterized in that The leakage protection circuit further includes: a delay module, connected to the logic processing module, for delaying and outputting the control signal; and, a driving module, connected to the delay module, for enhancing the driving ability of the delayed control signal and then outputting it.

21. The power grid protection circuit according to any one of claims 18 to 20, characterized in that the leakage protection circuit, the basic signal generation module, the first voltage comparison module and the control circuit are integrated in the same chip.

22. The power grid protection circuit according to any one of claims 18 to 20, characterized in that the leakage protection circuit and the over-voltage and under-voltage detection circuit are integrated in the same chip.

23. A power grid protection method, characterized in that it includes: sampling the AC voltage of the power grid to obtain a sampled voltage signal; comparing the sampled voltage signal with an under-voltage threshold voltage and an over-voltage threshold voltage respectively to obtain a first comparison signal and a second comparison signal; and, when a first enable signal is valid, detecting m cycles of the first comparison signal and the second comparison signal respectively to obtain a first characteristic signal and a second characteristic signal, and generating a classification signal indicating whether the power grid is over-voltage or under-voltage according to the first characteristic signal and the second characteristic signal, where m≥1; wherein, the steps of obtaining the first comparison signal and the second comparison signal include: receiving the under-voltage threshold voltage and the sampled voltage signal, comparing the under-voltage threshold voltage with the sampled voltage signal, and outputting a first comparison signal representing the magnitude relationship between the under-voltage threshold voltage and the sampled voltage signal; receiving the over-voltage threshold voltage and the sampled voltage signal, comparing the over-voltage threshold voltage with the sampled voltage signal, and outputting a second comparison signal representing the magnitude relationship between the over-voltage threshold voltage and the sampled voltage signal; when comparing the sampled voltage signal with the under-voltage threshold voltage and the over-voltage threshold voltage respectively, also comparing the sampled voltage signal with a power frequency threshold voltage to obtain a power frequency signal representing the magnitude relationship between the sampled voltage signal and the power frequency threshold voltage.

24. The power grid protection method according to claim 23, characterized in that the first enable signal is a periodic signal, each period of the first enable signal includes a detection time and a clearing time, the first enable signal is valid during the detection time and invalid during the clearing time, and the detection time is greater than m cycles of the first comparison signal and m cycles of the second comparison signal.

25. The power grid protection method according to claim 24, characterized in that latching the valid levels of the first characteristic signal and the second characteristic signal until the end of the detection time of each period of the first enable signal, and clearing the valid levels of the first characteristic signal and the second characteristic signal during the clearing time of each period of the first enable signal.

26. The power grid protection method according to any one of claims 23 to 25, characterized in that The steps of generating the classification signal according to the first characteristic signal and the second characteristic signal include: Performing edge detection on the first characteristic signal and the second characteristic signal to obtain a first classification signal indicating whether the first characteristic signal has a rising edge / falling edge and a second classification signal indicating whether the second characteristic signal has a rising edge / falling edge; and, Performing a logical operation on the first classification signal and the second classification signal to obtain the classification signal.

27. The power grid protection method according to claim 26, wherein, When the first enable signal is valid, edge detection is respectively performed on m periods of the first comparison signal and the second comparison signal to obtain the first characteristic signal for indicating whether each period of the first comparison signal has a rising edge / falling edge within m periods and the second characteristic signal for indicating whether each period of the second comparison signal has a rising edge / falling edge within m periods.

28. The power grid protection method according to claim 26, wherein, The first enable signal is generated according to the power frequency signal.

29. The power grid protection method according to claim 28, wherein, The steps of generating the first enable signal according to the power frequency signal include: Performing p-frequency division on the power frequency signal n times to obtain n-level frequency division signals, where n, p≥2; and, Performing a logical operation on the second-level frequency division signal to the n-level frequency division signal to obtain the first enable signal.

30. The power grid protection method according to claim 29, wherein, The pulse width of the first enable signal is equal to the sum of the pulse widths of the second-level frequency division signal to the n-level frequency division signal.

31. The power grid protection method according to claim 29, wherein, Before respectively detecting m periods of the first comparison signal and the second comparison signal when the first enable signal is valid, it further includes: Performing edge detection on q periods of the power frequency signal according to the power-on reset signal, and generating a valid second enable signal when each period of the q periods of the power frequency signal has a rising edge / falling edge, and generating the first enable signal according to the second enable signal and the power frequency signal, where q≥1.

32. The power grid protection method according to claim 31, wherein, The rising edge of the second enable signal and the n-level frequency division signal are separated by g periods of the power frequency signal, where g and n satisfy the following relationship: g＝2 (n-1) 。 33. The power grid protection method according to claim 29, wherein, After performing a logical operation on the first classification signal and the second classification signal, performing a logical operation on the result of the logical operation and the n-level frequency division signal to obtain the classification signal.

34. The power grid protection method according to claim 33, wherein, The steps of performing a logical operation on the first classification signal and the second classification signal include: Performing an exclusive NOR operation on the first classification signal and the second classification signal; and, Perform an AND operation on the result of the exclusive-NOR operation and the nth-stage frequency-divided signal to obtain the classification signal.

35. The power grid protection method according to claim 23, characterized in that it further includes: detect whether the power grid is leaking electricity, and jointly control the on / off of the power grid according to the electricity leakage detection result and the classification signal.

36. The power grid protection method according to claim 35, characterized in that the step of jointly controlling the on / off of the power grid according to the electricity leakage detection result and the classification signal includes: amplify the electricity leakage voltage of the power grid to obtain a voltage amplification signal; compare the voltage amplification signal with a reference voltage to obtain a third comparison signal representing the magnitude relationship between the voltage amplification signal and the reference voltage; and perform a logical operation on the third comparison signal and the classification signal to obtain a control signal for controlling the on / off of the power grid.

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