A CMOS ultra-wideband low noise amplifier

Abstract

The present invention discloses a CMOS ultra-wideband low-noise amplifier, including an input-stage complementary common-source circuit, an intermediate-stage common-source negative feedback circuit, and an output-stage common-source buffer circuit. The present invention innovatively introduces resistance feedback, inductance peaking technology, source degeneration inductance technology, and pseudo-resistance structure on the basis of the complementary common-source stage, and combines the common-source negative feedback circuit, the common-source buffer circuit, and the current multiplexing technology, so that the overall circuit has a wide bandwidth while achieving good gain, noise figure, power consumption and other indicators. The present invention can operate in the 0.15-11GHz frequency band, covering the 5G low- and medium-frequency bands (450MHz-6GHz) and the IMT service in the 6GHz candidate frequency band (5925-7125MHz), and is also compatible with the UWB standard frequency band (3.1-10.6GHz).

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit design, and in particular to a CMOS ultra-wideband low-noise amplifier. Background Art

[0002] With the rapid development of wireless technology, mobile communication technology is moving towards higher frequencies and wider bandwidths, and the use of various wireless standards (such as Bluetooth, Zigbee, WLAN, WiFi, UWB, GPS, and 2G / 3G / 4G / 5G cellular phones) has been increasing. However, spectrum resources are limited. In order to meet people's demand for higher speed and larger capacity communications, ultra-wideband communication technology that is compatible with multiple communication standards has gradually become an important research direction.

[0003] The ultra-wideband low-noise amplifier circuit is the core circuit module of the ultra-wideband receiver. As the first-stage amplifier circuit of the ultra-wideband receiving link, according to the noise cascade formula, the noise of the ultra-wideband low-noise amplifier basically determines the overall noise of the receiving link; in addition, the ultra-wideband low-noise amplifier also has gain, matching, power consumption, bandwidth and linearity requirements, and these indicators are in a mutually compromised relationship. The low-noise amplifier circuit design needs to plan the corresponding indicators according to the application requirements.

[0004] Commonly used broadband low-noise amplifier structures include distributed structure, resistor parallel feedback structure, common-gate amplifier structure and source inductor degeneration structure. The distributed amplifier structure adopts a multi-stage amplification structure and uses a delayed transmission line to achieve broadband, and requires large power consumption, which is not suitable for integrated and low-power applications. In the resistor parallel feedback structure, the parallel feedback resistor is connected to the gate and drain of the transistor to reduce the Q value of the input impedance and achieve broadband input matching, but the introduction of the feedback resistor will deteriorate the noise performance of this structure. In the common-gate amplifier structure, the input impedance is approximately 1 / gm. Since the input impedance of the common-gate structure is a constant, it has unparalleled broadband matching performance compared to other structures, and there is no feedback capacitor. It has good isolation, stability, high linearity and low power consumption, but the noise coefficient of this structure is high, and other ways need to be taken to reduce noise. In the source-level inductor degeneration structure, noise and input matching are achieved by adjusting the source inductance and the gate-source capacitance Cgs, but this method can only meet a certain frequency range. In order to expand the excellent noise and matching characteristics of the structure within the frequency band, additional inductor and capacitor elements are often added to form a bandpass filter to achieve broadband matching. This method can achieve good input matching and noise performance within a very wide frequency band. However, the use of too many inductors and capacitors results in a larger area. Summary of the invention

[0005] The present invention solves the problems existing in the background technology in terms of ultra-wideband, low noise, low power consumption, etc., and provides a CMOS ultra-wideband low-noise amplifier.

[0006] To solve the above problems, the present invention is implemented through the following technical solutions:

[0007] A CMOS ultra-wideband low-noise amplifier comprises an input-stage complementary common-source circuit, an intermediate-stage common-source negative feedback circuit and an output-stage common-source buffer circuit.

[0008] The input stage complementary common source circuit includes a PMOS transistor M1, an NMOS transistor M2, a coupling capacitor C1, a feedback resistor R1, a peaking inductor L1, a source degeneration inductor L2, a peaking inductor L3 and a pseudo resistor R pseudo ; The source and substrate of the PMOS transistor M1 are connected to the power supply VDD; the gate of the PMOS transistor M1 is connected to the input terminal Vin through the coupling capacitor C1, connected to the drain of the PMOS transistor M1 through the feedback resistor R1, and connected to the gate of the NMOS transistor M2 through the peaking inductor L1; the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2; the source of the NMOS transistor M2 is grounded through the source degeneration inductor L2; the substrate of the NMOS transistor M2 is grounded through the pseudo resistor R pseudo Ground.

[0009] The intermediate common source negative feedback circuit includes NMOS transistors M3-M4, a parallel peaking inductor L4, a negative feedback resistor R2, a load resistor R3 and a capacitor C2; the drain of the NMOS transistor M3 is connected to the power supply VDD through the series load resistor R3 and the parallel peaking inductor L4; the gate of the NMOS transistor M3 is connected to the drain of the PMOS transistor M1 through the peaking inductor L3; the source of the NMOS transistor M3 is grounded through the parallel negative feedback resistor R2 and the capacitor C2; the substrate of the NMOS tube M3 is grounded; the gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M3; the source and substrate of the NMOS transistor M4 are grounded.

[0010] The output stage common source buffer circuit includes an NMOS transistor M5, a coupling capacitor C3 and an inductor L5; the drain of the NMOS transistor M5 is connected to the power supply VDD; the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M3; the source of the NMOS transistor M5 is connected to the output terminal Vout through the coupling capacitor C3, and is connected to the drain of the NMOS transistor M4 through the inductor L5; the substrate of the NMOS transistor M5 is grounded.

[0011] In the above scheme, the pseudo resistor R pseudoIt is composed of two PMOS transistors M6 and PMOS transistor M7 of the same type; the source of the PMOS transistor M6 is connected to the substrate of the NMOS transistor M2; the substrate and source of the PMOS transistor M6 are connected and connected to the substrate of the NMOS transistor M2; the gate and drain of the PMOS transistor M6 are connected to the substrate and source of the PMOS transistor M7; the gate and drain of the PMOS transistor M7 are connected and grounded.

[0012] Compared with the prior art, the present invention has the following characteristics:

[0013] 1. The present invention innovatively introduces resistor feedback, inductor peaking technology, source degeneration inductor technology and pseudo-resistance structure on the basis of complementary common source stage, and combines common source negative feedback circuit, common source buffer circuit and current multiplexing technology, so that the overall circuit has wide bandwidth and achieves good gain, noise figure and power consumption and other indicators.

[0014] 2. The pseudo-resistance structure introduced into the ultra-wideband low-noise amplifier of the present invention can effectively reduce the noise coefficient of the circuit.

[0015] 3. The present invention can operate in the frequency band of 0.15 to 11 GHz, covering the low and medium frequency bands of 5G (450 MHz to 6 GHz) and the 6 GHz candidate frequency band (5925 to 7125 MHz) of IMT services, and is also compatible with the UWB standard frequency band (3.1 to 10.6 GHz). BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit diagram of a CMOS ultra-wideband low noise amplifier;

[0017] Figure 2 A pseudo-resistance circuit diagram used in a CMOS ultra-wideband low-noise amplifier;

[0018] Figure 3 This is the S-parameter simulation result of a CMOS ultra-wideband low-noise amplifier;

[0019] Figure 4 This is the noise simulation result of a CMOS ultra-wideband low noise amplifier;

[0020] Figure 5 This is the stability simulation result of a CMOS ultra-wideband low-noise amplifier. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the implementation modes and the accompanying drawings.

[0022] A CMOS ultra-wideband low noise amplifier, such as Figure 1 As shown, a single-ended input and output structure is adopted, and it is composed of an input-stage complementary common source circuit, an intermediate-stage common source negative feedback circuit, and an output-stage common source buffer circuit. The input-stage complementary common source circuit is connected to the intermediate-stage common source negative feedback circuit, and the output end of the intermediate-stage common source negative feedback circuit is connected to the output-stage common source buffer circuit.

[0023] The input stage complementary common source circuit includes a PMOS transistor M1, an NMOS transistor M2, an input coupling capacitor C1, a feedback resistor R1, a peaking inductor L1, a source degeneration inductor L2, a peaking inductor L3 and a pseudo resistor R pseudo The source and substrate of the PMOS transistor M1 are connected to the power supply VDD. The gate of the PMOS transistor M1 is connected to the input terminal Vin through the input coupling capacitor C1, connected to the drain of the PMOS transistor M1 through the feedback resistor R1, and connected to the gate of the NMOS transistor M2 through the peaking inductor L1. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2. The source of the NMOS transistor M2 is grounded through the source degeneration inductor L2. The substrate of the NMOS transistor M2 is connected to the ground through the pseudo resistor R pseudo Ground. Pseudo resistor R pseudo It is composed of two PMOS transistors M6 and PMOS transistors M7 of the same type, such as Figure 2 As shown. The source of the PMOS transistor M6 is connected to the substrate of the NMOS transistor M2. The substrate and source of the PMOS transistor M6 are connected and connected to the substrate of the NMOS transistor M2. The gate and drain of the PMOS transistor M6 are connected to the substrate and source of the PMOS transistor M7. The gate and drain of the PMOS transistor M7 are connected and grounded. The input stage adopts a complementary common source stage structure (M1 and M2) to double the current efficiency. The introduction of the feedback resistor R1 not only achieves broadband input matching but also provides bias for the circuit of the present invention. The input stage gain AV1≈-(gm1+gm2)×Zout1, so larger M1 and M2 can be selected to reduce noise and increase the gain of the input stage, while the large-sized transistor increases the output parasitic capacitance, making the frequency band of the input stage output narrower. Figure 1 The L1 and L2 introduced in the circuit can reduce the parasitic capacitance to enhance the bandwidth of the circuit and improve the input matching. The substrate of M2 is connected through the pseudo resistor R pseudo Connecting to the ground forms an open circuit, thereby isolating the RF transistor from the ground, avoiding signal leakage and noise coupling, and improving the noise and gain of the circuit. The input coupling capacitor C1 plays the role of isolating the DC component.

[0024] The intermediate stage common source negative feedback circuit includes NMOS transistors M3-M4, a parallel peaking inductor L4, a negative feedback resistor R2, a load resistor R3 and a capacitor C2. The drain of the NMOS transistor M3 is connected to the power supply VDD through the series load resistor R3 and the parallel peaking inductor L4. The gate of the NMOS transistor M3 is connected to the drain of the PMOS transistor M1 through the peaking inductor L3. The source of the NMOS transistor M3 is grounded through the parallel negative feedback resistor R2 and the capacitor C2. The substrate of the NMOS tube M3 is grounded. The gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M3. The source and substrate of the NMOS transistor M4 are grounded. The signal in the intermediate stage passes through two paths, including the upper path M3 and M5 and the lower path M4. The output parasitic capacitance of the first stage and the input parasitic capacitance of the second stage and the introduced inductor L3 form a π-type matching network, which can achieve inter-stage matching. Inductor L4 and resistor R3 form a parallel peaking structure to expand the bandwidth of the circuit. The source negative feedback structure consists of resistor R2 and capacitor C2 to expand the bandwidth of the circuit and stabilize the circuit. M4 is an auxiliary amplifier stage to increase the gain of the intermediate stage.

[0025] The output stage common source buffer circuit includes an NMOS transistor M5, an output coupling capacitor C3 and an inductor L5. The drain of the NMOS transistor M5 is connected to the power supply VDD. The gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M3. The source of the NMOS transistor M5 is connected to the output terminal Vout through the output coupling capacitor C3, and is connected to the drain of the NMOS transistor M4 through the inductor L5. The substrate of the NMOS transistor M5 is grounded. The output coupling capacitor C3 plays a role in isolating the DC component. The output stage common source buffer circuit is used to achieve broadband output matching.

[0026] This embodiment uses TSMC 0.18um RF CMOS process to implement a CMOS ultra-wideband low noise amplifier. Figure 3 The S parameter simulation results of this embodiment are given. It can be seen from the figure that the 3dB bandwidth of this CMOS ultra-wideband low noise amplifier reaches 11.9GHz. The gain is 13.8-14.5dB in the 0.15-11GHz frequency band, the gain flatness in the band is good, S11 and S22 are both less than -10dB, achieving a good input-output matching effect, and S12 is less than -25dB to achieve a good reverse isolation effect. Figure 4 The noise simulation results of this embodiment are given. It can be seen from the figure that the noise coefficient of the CMOS ultra-wideband low-noise amplifier in the frequency range of 0.15 to 11 GHz is ≤3dB. The noise comparison before and after the introduction of the pseudo-resistance is given. It can be seen from the figure that the noise coefficient of the circuit is significantly optimized after the introduction of the pseudo-resistance. After calculation, the average noise of the circuit is optimized by 0.37dB, and the optimization effect reaches 13%. Figure 5 The stability simulation results of this embodiment are given. It can be seen from the figure that the stability coefficient of this CMOS ultra-wideband low noise amplifier is greater than 1 in the frequency range of 0.15 to 11 GHz. When the power supply voltage is 1.5V, the overall power consumption of the circuit is 6.4mW. In summary, under the TSMC 0.18um RF CMOS process, the present invention can achieve an operating bandwidth of 0.15 to 11GHz, S11 and S22 are both less than -10dB, the gain is 13.8 to 14.5dB, the noise figure is 2.7 to 3dB, and the power consumption is 6.4mW. These simulation results illustrate the effectiveness of the present invention.

[0027] The CMOS ultra-wideband low-noise amplifier proposed in the present invention adopts a current multiplexing structure. The input stage introduces resistor feedback, inductor peaking technology, source degeneration inductor technology and pseudo-resistance structure based on the complementary common source stage, which can expand the circuit bandwidth, improve the circuit gain and reduce the circuit noise. The intermediate stage introduces a gain auxiliary stage and parallel inductor peaking technology based on the common source stage with source negative feedback, which can expand the circuit bandwidth and increase the circuit gain. The output stage adopts a common source buffer circuit to achieve broadband output matching.

[0028] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A CMOS ultra-wideband low noise amplifier, characterized in that: It includes an input-stage complementary common-source circuit, an intermediate-stage common-source negative feedback circuit and an output-stage common-source buffer circuit; The input stage complementary common source circuit includes a PMOS transistor M1, an NMOS transistor M2, a coupling capacitor C1, a feedback resistor R1, a peaking inductor L1, a source degeneration inductor L2, a peaking inductor L3 and a pseudo resistor R pseudo ; The source and substrate of the PMOS transistor M1 are connected to the power supply VDD; the gate of the PMOS transistor M1 is connected to the input terminal Vin through the coupling capacitor C1, connected to the drain of the PMOS transistor M1 through the feedback resistor R1, and connected to the gate of the NMOS transistor M2 through the peaking inductor L1; the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2; the source of the NMOS transistor M2 is grounded through the source degeneration inductor L2; the substrate of the NMOS transistor M2 is grounded through the pseudo resistor R pseudo Grounding; The intermediate common source negative feedback circuit includes NMOS transistors M3-M4, a parallel peaking inductor L4, a negative feedback resistor R2, a load resistor R3 and a capacitor C2; the drain of the NMOS transistor M3 is connected to the power supply VDD through the series load resistor R3 and the parallel peaking inductor L4; the gate of the NMOS transistor M3 is connected to the drain of the PMOS transistor M1 through the peaking inductor L3; the source of the NMOS transistor M3 is grounded through the parallel negative feedback resistor R2 and the capacitor C2; the substrate of the NMOS tube M3 is grounded; the gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M3; the source and substrate of the NMOS transistor M4 are grounded; The output stage common source buffer circuit includes an NMOS transistor M5, a coupling capacitor C3 and an inductor L5; the drain of the NMOS transistor M5 is connected to the power supply VDD; the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M3; the source of the NMOS transistor M5 is connected to the output terminal Vout through the coupling capacitor C3, and is connected to the drain of the NMOS transistor M4 through the inductor L5; the substrate of the NMOS transistor M5 is grounded.

2. A CMOS ultra-wideband low noise amplifier according to claim 1, characterized in that: Pseudo resistor R pseudo It is composed of two PMOS transistors M6 and PMOS transistor M7 of the same type; the source of the PMOS transistor M6 is connected to the substrate of the NMOS transistor M2; The substrate and source of the PMOS transistor M6 are connected and connected to the substrate of the NMOS transistor M2; the gate and drain of the PMOS transistor M6 are connected to the substrate and source of the PMOS transistor M7; the gate and drain of the PMOS transistor M7 are connected and grounded.

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