Display device

Abstract

A display device includes pixels, a scan driver, an emission driver, and a data driver. A pixel on the i-th horizontal line includes: a light-emitting element; a first transistor including a first electrode connected to a first node; a second transistor including a gate electrode connected to an (i+x)-th emission control line and connected to one of the data lines; a third transistor including a gate electrode connected to an (i+y)-th emission control line and connected between the second transistor and the first node; a fourth transistor connected between a third node connected to the second electrode of the first transistor and the second node, and turned on by a scan signal supplied to the i-th scan line; and a fifth transistor connected between a first power supply and the first node, and turned off by an emission control signal supplied to the i-th emission control line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0006121, filed on January 16, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some exemplary embodiments of this disclosure relate to display devices. Background Technology

[0004] A display device is used to display images on a display panel using control signals applied from an external source.

[0005] Display devices typically include multiple pixels. Each pixel may include multiple transistors, as well as a light-emitting element and a capacitor electrically connected to the transistors. The transistors are turned on in response to a signal provided through a line to generate a drive current, and the light-emitting element emits light in response to the drive current.

[0006] Display devices corresponding to various driving frequencies can be used for high-resolution driving, low-power driving, stereoscopic image driving, etc. For example, a pixel structure that includes and combines polysilicon semiconductor transistors and oxide semiconductor transistors in a single pixel can be utilized.

[0007] The information disclosed in this background section is only intended to enhance the understanding of the background, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0008] Aspects of some exemplary embodiments of this disclosure relate to display devices, and, for example, to pixels and display devices including such pixels.

[0009] Aspects of some example embodiments may include pixels that write data signals in response to a transmit control signal.

[0010] Aspects of some example embodiments may include a display device that includes the pixel.

[0011] However, the embodiments according to this disclosure are not limited to the features described above, and various extensions may be made within the scope without departing from the spirit and scope of the embodiments according to this disclosure.

[0012] A display device according to some example embodiments of the present disclosure may include: a pixel connected to a scan line, an emission control line, and a data line; a scan driver configured to supply a scan signal to the scan line; an emission driver configured to supply an emission control signal to the emission control line; and a data driver configured to supply a data signal to the data line in response to the scan signal. A pixel located in the i-th (where i is a natural number) horizontal line may include: a light-emitting element; a first transistor including a first electrode connected to a first node and controlling a drive current based on the voltage of a second node, the first node being electrically connected to a first power supply; a second transistor including a gate electrode connected to the i+x (where x is an integer) emitter control line and connected to one of the data lines; a third transistor including a gate electrode connected to the i+y (where y is a non-zero integer different from x) emitter control line and connected between the second transistor and the first node; a fourth transistor connected between the third node connected to the second electrode of the first transistor and the second node, and turned on by a scan signal supplied to the i-th scan line; and a fifth transistor connected between the first power supply and the first node, and turned off by an emitter control signal supplied to the i-th emitter control line.

[0013] According to some example embodiments, the second transistor and the third transistor can be of different types.

[0014] According to some example embodiments, the second transistor may be an N-type transistor including an oxide semiconductor layer, and the third transistor may be a P-type transistor including a polycrystalline silicon semiconductor layer.

[0015] According to some example embodiments, the second transistor can be turned on by a transmit control signal supplied to the i+x transmit control line, and the third transistor can be turned off by a transmit control signal supplied to the i+y transmit control line.

[0016] According to some example embodiments, the transmit driver can supply the transmit control signal to the (i+x)th transmit control line after supplying the transmit control signal to the (i+x)th transmit control line, and can supply the transmit control signal to the (i+y)th transmit control line after supplying the transmit control signal to the (i+x)th transmit control line.

[0017] According to some example embodiments, the transmit driver can supply the transmit control signal to the (i+y)th transmit control line after supplying the transmit control signal to the (i+y)th transmit control line, and can supply the transmit control signal to the (i+x)th transmit control line after supplying the transmit control signal to the (i)th transmit control line.

[0018] According to some example embodiments, the transmit driver can simultaneously supply transmit control signals to the i-th transmit control line and the i+x-th transmit control line, and can supply transmit control signals to the i+y-th transmit control line after supplying transmit control signals to the i+x-th transmit control line.

[0019] According to some example embodiments, a pixel located in the i-th horizontal line may further include: a sixth transistor connected between the third node and the first electrode of the light-emitting element, and turned off by an emission control signal supplied to the i-th emission control line; and a seventh transistor connected between the second node and the first initialization power supply, and turned on by a scan signal supplied to the (i-1)-th scan line.

[0020] According to some example embodiments, a pixel located in the i-th horizontal line may further include: an eighth transistor coupled between a second initialization power supply and a first electrode of a light-emitting element, and turned on by an emission control signal supplied to the i-th emission control line.

[0021] According to some example embodiments, the fourth, seventh, and eighth transistors may be N-type transistors including an oxide semiconductor layer, and the fifth and sixth transistors may be P-type transistors including a polycrystalline silicon semiconductor layer.

[0022] According to some example embodiments, the second transistor may be a P-type transistor including a polycrystalline silicon semiconductor layer, and the third transistor may be an N-type transistor including an oxide semiconductor layer.

[0023] A pixel according to some example embodiments of the present disclosure may include: a light-emitting element; a first transistor including a first electrode connected to a first node and controlling a drive current based on the voltage of a second node, the first node being electrically connected to a first power supply; a second transistor including a gate electrode connected to a first emission control line and connected to a data line; a third transistor including a gate electrode connected to a second emission control line and connected between the second transistor and the first node; a fourth transistor connected between a third node connected to the second electrode of the first transistor and the second node, and turned on by a scan signal supplied to a first scan line; a fifth transistor connected between the first power supply and the first node, and turned off by an emission control signal supplied to a third emission control line; a sixth transistor connected between the third node and the first electrode of the light-emitting element, and turned off by an emission control signal supplied to the third emission control line; and a storage capacitor connected between the first power supply and the second node.

[0024] According to some example embodiments, the second transistor and the third transistor can be of different types.

[0025] According to some example embodiments, the second transistor may be an N-type transistor including an oxide semiconductor layer, and the third transistor may be a P-type transistor including a polycrystalline silicon semiconductor layer.

[0026] According to some example embodiments, the second transistor can be turned on by an emit control signal supplied to the first emit control line, and the third transistor can be turned off by an emit control signal supplied to the second emit control line.

[0027] According to some example embodiments, when the second transistor, the third transistor, and the fourth transistor are simultaneously turned on, a data signal can be supplied to the first transistor through a data line.

[0028] According to some example embodiments, the pixel may further include: a seventh transistor connected between the second node and the first initialization power supply, and turned on by a scan signal supplied to the second scan line.

[0029] According to some example embodiments, the pixel may further include: an eighth transistor coupled between the second initialization power supply and the first electrode of the light-emitting element, and turned on by an emission control signal supplied to a third emission control line, wherein the eighth transistor may be an N-type transistor including an oxide semiconductor layer, and the fifth and sixth transistors may be P-type transistors including a polysilicon semiconductor layer.

[0030] According to some example embodiments, the fourth and seventh transistors may be N-type transistors.

[0031] According to some example embodiments, the pixel may further include: an eighth transistor coupled between a second initialization power supply and a first electrode of a light-emitting element, and turned on by a scan signal supplied to a first scan line or a second scan line.

[0032] A pixel including an N-type transistor and a P-type transistor, and a display device including such a pixel, according to some example embodiments of this disclosure, can use a transmit control signal to control a second transistor and a third transistor for writing data signals. Therefore, a scan driver configuration for driving the P-type transistor can be eliminated. Consequently, the dead zone and power consumption of the display device can be significantly reduced compared to alternative configurations or structures.

[0033] However, the features of the embodiments according to this disclosure are not limited to those described above, and various extensions may be made within the scope without departing from the spirit and scope of the embodiments according to this disclosure. Attached Figure Description

[0034] The above and other features of embodiments of the present disclosure will become more apparent from the further detailed description of aspects of some exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0035] Figure 1 The figure shows a block diagram of a display device according to some example embodiments of the present disclosure;

[0036] Figure 2A The diagram illustrates the driver. Figure 1 Timing diagram of an example method for a display device;

[0037] Figure 2B The diagram illustrates the driver. Figure 1 Timing diagram of another example of a method for displaying a device;

[0038] Figure 3 The figure shows a circuit diagram of a pixel according to some example embodiments of the present disclosure;

[0039] Figure 4 The diagram illustrates the driver. Figure 3 A timing diagram of examples of pixels;

[0040] Figure 5 The diagram illustrates the driver. Figure 3 A timing diagram showing further details of the pixel examples;

[0041] Figure 6 The diagram illustrates the driver. Figure 3 A timing diagram showing further details of the pixel examples;

[0042] Figure 7 The diagram shows Figure 3 A circuit diagram of an example pixel;

[0043] Figure 8 and Figure 9 This is a circuit diagram illustrating further details of pixels according to some example embodiments; and

[0044] Figure 10 and Figure 11 This is a circuit diagram illustrating further details of pixels according to some example embodiments. Detailed Implementation

[0045] In the following, further details of some exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same parts, and some repeated descriptions of the same parts may be omitted.

[0046] Figure 1 This is a block diagram illustrating a display device according to some example embodiments of the present disclosure.

[0047] Reference Figure 1The display device 1000 may include a pixel unit 100, a scan driver 200, a transmit driver 300, a data driver 400, and a timing controller 500.

[0048] The display device 1000 can display images at various drive frequencies (or image refresh rates or screen refresh rates) depending on the driving conditions. The drive frequency is the frequency at which data signals are essentially written to the drive transistors of the pixels (PX). For example, the drive frequency is also referred to as the refresh rate and screen refresh rate, and indicates the frequency at which the displayed screen is reproduced within one second.

[0049] According to some example embodiments, the display device 1000 can adjust the output frequency of the scan driver 200 and the output frequency of the data driver 400 corresponding to the scan driver 200 according to driving conditions. For example, the display device 1000 can display images corresponding to various driving frequencies from 1Hz to 120Hz.

[0050] Pixel unit 100 may include multiple scan lines S1 to Sn, multiple emission control lines E1 to En, and multiple data lines D1 to Dm, and includes multiple pixels PX (where m and n are integers greater than 1) respectively connected to scan lines S1 to Sn, emission control lines E1 to En, and data lines D1 to Dm. Each of the pixels PX may include a driving transistor and multiple switching transistors.

[0051] The timing controller 500 can generate a scan drive control signal SCS, a transmit drive control signal ECS, and a data drive control signal DCS in response to a synchronization signal supplied from an external source. The scan drive control signal SCS can be supplied to the scan driver 200, the transmit drive control signal ECS can be supplied to the transmit driver 300, and the data drive control signal DCS can be supplied to the data driver 400. Additionally, the timing controller 500 can rearrange the externally supplied image data RGB and supply the rearranged image data RGB to the data driver 400.

[0052] The scan drive control signal SCS can include a scan start pulse and a clock signal. The scan start pulse controls the initial timing of the scan signals. The clock signal can be used to start the shift scan.

[0053] The transmit drive control signal (ECS) can include a transmit control start pulse and a clock signal. The transmit control start pulse controls the initial timing of the transmit control signals. The clock signal can be used to shift the transmit control start pulse.

[0054] The data-driven control signal (DCS) can include a source start pulse and a clock signal. The source start pulse controls the start time of data sampling. The clock signal is used to control the sampling operation.

[0055] The scan driver 200 can receive a scan drive control signal SCS from the timing controller 500 and supply scan signals to scan lines S1 to Sn based on the scan drive control signal SCS. For example, the scan driver 200 can sequentially supply scan signals to scan lines S1 to Sn. The scan signal can be set to a gate turn-on voltage (e.g., a high voltage). When the scan signal is supplied, the transistor included in the pixel PX and receiving the scan signal can be turned on. In the following, the case where the scan signal has a high voltage (the case where a high-level pulse of the scan signal is applied) will be described as the case where the scan signal is supplied.

[0056] Meanwhile, the scan driver 200 can control the scan signals supplied to scan lines S1 to Sn according to the drive frequency.

[0057] The transmit driver 300 can receive the transmit drive control signal ECS from the timing controller 500, and supply transmit control signals to the transmit control lines E1 to En based on the transmit drive control signal ECS. For example, the transmit driver 300 can sequentially supply the transmit control signals to the transmit control lines E1 to En.

[0058] The transmit control signal can be set to a gate cutoff voltage (e.g., a high voltage). In the following text, the case where the transmit control signal has a high voltage (the case where a high-level pulse of the transmit control signal is applied) will be described as the case where the transmit control signal is supplied.

[0059] The emission control signal can be used to control the emission time of pixel PX. For this purpose, the emission control signal can be set to a width wider than the width of the scan signal. For example, the scan driver 200 can supply the scan signal to the (i-1)th scan line Si-1 and the i-th scan line Si to overlap with the emission control signal supplied to the i-th emission control line Ei (i is a natural number equal to or less than n).

[0060] According to some example embodiments, pixels PX can be selected in units of horizontal lines (or in units of pixel rows) in response to the supply of a transmit control signal.

[0061] According to some example embodiments, the transmit driver 300 can supply transmit control signals to transmit control lines E1 to En corresponding to the maximum drive frequency of the display device 1000. For example, the output frequency of the transmit driver 300 outputting the transmit control signals can be constant and independent of changes in the drive frequency (or image frame rate).

[0062] Each of the scan driver 200 and the emitter driver 300 can be mounted on a substrate using a thin-film process. Additionally, the scan driver 200 can be located on either side of the pixel unit 100. Similarly, the emitter driver 300 can also be located on either side of the pixel unit 100.

[0063] In addition, Figure 1 In this embodiment, scan driver 200 and transmit driver 300 supply scan signals and transmit control signals, respectively; however, embodiments according to this disclosure are not limited thereto. For example, scan signals and transmit control signals may be supplied by a single driver.

[0064] The data driver 400 can receive a data drive control signal DCS and image data RGB from the timing controller 500. The data driver 400 can supply data signals to data lines D1 to Dm in response to the data drive control signal DCS. The data signals supplied to data lines D1 to Dm can be supplied to the pixel PX selected by the transmit control signal. Therefore, the data driver 400 can supply data signals to data lines D1 to Dm synchronously with the scan signal.

[0065] At the same time, Figure 1 The diagram shows n scan lines S1 to Sn and n emission control lines E1 to En, but embodiments of this disclosure are not limited thereto. For example, corresponding to the circuit structure of pixel PX, a pixel PX located in the current horizontal line (or current pixel row) can be additionally connected to scan lines located in a previous horizontal line (or previous pixel row) and / or scan lines located in a subsequent horizontal line (or subsequent pixel row). For this purpose, dummy scan lines and / or dummy emission control lines (not shown) can be additionally formed in pixel unit 100.

[0066] Figure 2A The diagram illustrates the driver. Figure 1 A timing diagram illustrating an example of a method for displaying a device.

[0067] Figure 2A The diagram illustrates when driving at the first driving frequency. Figure 1 An example of a driving method for a display device 1000. For example, the first driving frequency can be set to 60Hz or 120Hz. The first driving frequency is the driving frequency (or image refresh rate) applied by the display device 1000 to display a normal image.

[0068] Reference Figure 1 and Figure 2A When the display device 1000 is driven at the first driving frequency, the scanning signal is sequentially supplied to the scan lines S1 to Sn during a frame time period 1F.

[0069] When the display device 1000 is driven at the first driving frequency, transmission control signals are sequentially supplied to transmission control lines E1 to En during a frame time period 1F. Here, the transmission control signal supplied to the i-th transmission control line Ei overlaps with the scan signals supplied to the (i-1)-th scan line Si-1 and the i-th scan line Si. The data signal DS is supplied to the data line D to synchronize with the scan signals. However, this is only an example, and the transmission control signals may have a length of 7 horizontal time periods or longer, and may overlap with the scan signals supplied to the (i-3)-th scan line Si-3 to the (i+3)-th scan line Si+3.

[0070] Pixel PX emits light in response to data signal DS, and the image can be displayed in pixel unit 100.

[0071] Figure 2B The diagram illustrates the driver. Figure 1 A timing diagram of another example of a method for displaying a device.

[0072] Figure 2B The diagram illustrates when driving at the second driving frequency. Figure 1 An example of a driving method for the display device 1000. For example, the second driving frequency can be set to a low frequency of less than 60Hz. The second driving frequency is the driving frequency applied to display an image in the standby mode (e.g., always-on display (AOD) mode) of the display device 1000.

[0073] Reference Figure 1 and Figure 2B The frame time period 1F during which image data is refreshed (or data signals are supplied to pixels) when the display device 1000 is driven at the second driving frequency is divided into a first driving time period T1 and a second driving time period T2. Here, the second driving time period T2 may be longer than or equal to the first driving time period T1.

[0074] For example, when the second driving frequency is 30Hz and the frequency of the transmit control signal is 60Hz, the length of the first driving period T1 and the length of the second driving period T2 can be substantially the same. Alternatively, when the second driving frequency is 1Hz and the frequency of the transmit control signal is 60Hz, the length of the second driving period T2 can be approximately 59 times the length of the first driving period T1. That is, the length of the second driving period T2 can be equal to the time it takes for the first driving period T1 to repeat 59 times.

[0075] The scan signal supplied to the i-th scan line Si and the corresponding data signal DS can be supplied for a period of time that is substantially the same as the second drive frequency.

[0076] During the first driving period T1, scan signals are sequentially supplied to scan lines S1 to Sn. Additionally, during the first driving period T1, transmit control signals are sequentially supplied to transmit control lines E1 to En. Here, the transmit control signal supplied to the i-th transmit control line Ei overlaps with the scan signals supplied to the (i-1)-th scan line Si-1 and the i-th scan line Si.

[0077] The data signal DS is supplied to the data line D to synchronize with the scan signal. The data signal DS supplied to the i-th horizontal line can be supplied for a period of time that is substantially the same as the second drive frequency.

[0078] During the second driving period T2, the scan signal is not supplied to scan lines S1 to Sn. However, during the second driving period T2, the transmit control signal is supplied to transmit control lines E1 to En multiple times. For example, when the second driving frequency is 1 Hz, the transmit control signal is supplied to the i-th transmit control line Ei once during the first driving period T1, and the transmit control signal can be supplied to the i-th transmit control line Ei 59 times during the second driving period T2.

[0079] Simultaneously, the voltage of the reference power supply Vref is supplied to the data line D during the second driving period T2. For example, the voltage of the reference power supply Vref may have a voltage level capable of applying a conduction bias to the driving transistor of pixel PX. However, this is only an example, and the amplitude of the voltage supplied to the data line D during the second driving period T2 can be determined according to the characteristics of the display device 1000 and can vary according to the frame or time.

[0080] In the case of low-frequency drive with a second drive frequency (e.g., 1Hz drive frequency), the image corresponding to the data signal DS can be displayed for a relatively long time after the data signal DS is applied once. In addition, since the scan signal is not supplied to scan lines S1 to Sn during the second drive period T2 (i.e., because the number of triggers of the scan signal at the second drive frequency is reduced), the power consumption in low-frequency drive can be reduced.

[0081] Figure 3 The figure shows a circuit diagram of a pixel according to some example embodiments of the present disclosure.

[0082] exist Figure 3 In the figure, for ease of description, pixel 10 located on the i-th horizontal line and connected to the j-th data line Dj is shown.

[0083] Reference Figure 3 Pixel 10 may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0084] The first electrode (anode or cathode) of the light-emitting element LD is connected to the fourth node N4, and the second electrode (cathode or anode) is connected to the second power supply VSS. The light-emitting element LD generates light of a certain brightness (e.g., a set or predetermined brightness) corresponding to the amount of current supplied from the first transistor M1.

[0085] According to some example embodiments, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer. According to some example embodiments, the light-emitting element LD can be an inorganic light-emitting element formed of inorganic materials. Alternatively, the light-emitting element LD can be in the form in which a plurality of inorganic light-emitting elements are connected in parallel and / or in series between the second power supply VSS and the fourth node N4.

[0086] The first electrode of the first transistor M1 (or driving transistor) can be connected to the first node N1, and the second electrode can be connected to the third node N3. The gate electrode of the first transistor M1 can be connected to the second node N2. The first transistor M1 can control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light-emitting element LD in response to the voltage of the second node N2. For this purpose, the first power supply VDD can be set to a voltage higher than the voltage of the second power supply VSS.

[0087] The second transistor M2 can be connected between the data line Dj and the third transistor M3. The gate electrode of the second transistor M2 can be connected to the (i+x)th (where x is an integer) emitter control line Ei+x (or the first emitter control line EL1). When the emitter control signal is supplied to the (i+x)th emitter control line Ei+x (i.e., when a high voltage of the emitter control signal is supplied), the second transistor M2 can be turned on.

[0088] According to some example embodiments, the second transistor M2 can be formed of an oxide semiconductor transistor. The second transistor M2 may include an oxide semiconductor layer as an active layer (channel). Additionally, the second transistor M2 can be an N-type oxide semiconductor transistor, and therefore the gate turn-on voltage for turning on the second transistor M2 can be a high voltage (logic high level).

[0089] The third transistor M3 is connected between the second transistor M2 and the first node N1. The gate electrode of the third transistor M3 can be connected to the (i+y)th emitter control line Ei+y (or the second emitter control line EL2) (where y is a non-zero integer different from x). When the emitter control signal is supplied to the (i+y)th emitter control line Ei+y, the third transistor M3 can be turned off. In other words, when the emitter control signal is not supplied (i.e., when a low voltage of the emitter control signal is supplied), the third transistor M3 can be turned on.

[0090] According to some example embodiments, the third transistor M3 can be formed of a polysilicon transistor. The second transistor M2 may include a polysilicon semiconductor layer as an active layer (channel). For example, the active layer of the second transistor M2 can be formed by a low-temperature polysilicon process (e.g., a low-temperature polysilicon process).

[0091] In addition, the third transistor M3 can be a P-type polysilicon semiconductor transistor, and therefore the gate turn-on voltage for turning on the third transistor M3 can be a low voltage (logic low level).

[0092] As described above, the second transistor M2 and the third transistor M3 can be connected in series between the data line Dj and the first node N1. Furthermore, the second transistor M2 and the third transistor M3 can be of different types. Therefore, the second transistor M2 and the third transistor M3 are turned on by different voltage levels.

[0093] like Figure 3 As shown, the transmit control signal can be supplied to the gate electrodes of the corresponding second transistor M2 and third transistor M3 at different times. Therefore, the period during which the transmit control signal is supplied to the first transmit control line EL1 can overlap with the period during which the transmit control signal is not supplied to the second transmit control line EL2. Therefore, the periods during which the second transistor M2 and the third transistor M3 are turned on simultaneously (or in parallel) can be determined.

[0094] During the period when the second transistor M2 and the third transistor M3 are turned on simultaneously (or in parallel), the data signal supplied to the data line Dj can be transmitted to the first node N1.

[0095] The fourth transistor M4 can be connected between the second electrode (i.e., the third node N3) and the second node N2 of the first transistor M1. The gate electrode of the fourth transistor M4 can be connected to the i-th scan line Si (or the first scan line SL1). When a scan signal is supplied to the i-th scan line Si, the fourth transistor M4 is turned on to electrically connect the second electrode of the first transistor M1 and the second node N2 to each other. Therefore, when the fourth transistor M4 is turned on, the first transistor M1 is connected in the form of a diode.

[0096] The fifth transistor M5 can be connected between the first power supply VDD and the first node N1. The gate electrode of the fifth transistor M5 can be connected to the emitter control line Ei (or the third emitter control line EL3). When the emitter control signal is supplied to the emitter control line Ei, the fifth transistor M5 is turned off, and under other conditions, the fifth transistor M5 is turned on.

[0097] The sixth transistor M6 can be connected between the second electrode (i.e., the third node N3) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor M6 can be connected to the emitter control line Ei. When the emitter control signal is supplied to the emitter control line Ei, the sixth transistor M6 is turned off, and under other conditions, the sixth transistor M6 is turned on.

[0098] According to some example embodiments, the fifth transistor M5 and the sixth transistor M6 may be P-type polycrystalline silicon semiconductor transistors.

[0099] Furthermore, the first transmit control line EL1 to the third transmit control line EL3 described above can mean supplying the same transmit control signal through different transmit control lines at different timings. Similarly, the first scan line SL1 and the second scan line SL2 can mean supplying the same scan signal through different scan lines at different timings.

[0100] The seventh transistor M7 can be connected between the second node N2 and the initialization power supply Vint. The gate electrode of the seventh transistor M7 can be connected to the (i-1)th scan line Si-1 (or the second scan line SL2). When the scan signal is supplied to the (i-1)th scan line Si-1, the seventh transistor M7 is turned on to supply the voltage of the initialization power supply Vint to the second node N2.

[0101] According to some example embodiments, the voltage of the initialization power supply Vint is set to be lower than the voltage of the data signal supplied to the data line Dj. Therefore, the gate voltage of the first transistor M1 can be initialized to the voltage of the initialization power supply Vint by turning on the seventh transistor M7, and the first transistor M1 can have a conduction bias state (i.e., the first transistor M1 can be initialized to a conduction bias state).

[0102] The eighth transistor M8 can be connected between the initialization power supply Vint and the fourth node N4. According to some example embodiments, the gate electrode of the eighth transistor M8 can be connected to the i-th emitter control line Ei.

[0103] According to some example embodiments, the eighth transistor M8 can be an N-type transistor. For example, the eighth transistor M8 can be an N-type oxide semiconductor transistor.

[0104] The eighth transistor M8 can be turned on when the transmit control signal is supplied to the transmit control line Ei, and turned off under other conditions. That is, as an N-type transistor, the eighth transistor M8 can be turned on or off in the opposite way to the fifth transistor M5 and the sixth transistor M6.

[0105] When the transmit control signal is supplied (i.e., during non-transmit periods), the eighth transistor M8 is turned on to supply the voltage of the initialization power supply Vint to the first electrode of the light-emitting element LD.

[0106] When the voltage of the initialization power supply Vint is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. As the residual voltage charged in the parasitic capacitor is discharged (removed), accidental micro-emissions can be prevented or reduced. Therefore, the black level performance of pixel 10 can be improved.

[0107] According to some example embodiments, the fourth transistor M4 and the seventh transistor M7 can be N-type oxide semiconductor transistors. Therefore, the gate turn-on voltage for turning on the fourth transistor M4 and the seventh transistor M7 can be a high voltage (logic high level).

[0108] Compared to polysilicon transistors, oxide semiconductor transistors (OSTs) can be processed at low temperatures and have lower charge mobility. That is, OSTs are superior in terms of cutoff current characteristics. Therefore, when the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are formed using OSTs, the leakage current from the second node N2 and the fourth node N4 can be minimized, thus improving display quality.

[0109] At the same time, since different types of transistors are located in pixel 10, a scan driver is needed to output scan signals to control the transistors. For example, a conventional display device includes a scan driver for controlling P-type transistors, a scan driver for controlling N-type transistors, and a transmit driver for supplying transmit control signals. That is, because a conventional display device uses at least three drivers (scan driver and transmit driver) to control the pixel, the dead zone and power consumption for driver arrangement and operation may increase.

[0110] However, according to some example embodiments of this disclosure, the display device 1000 including pixel 10 can control the second transistor M2 and the third transistor M3 for writing data signals and the eighth transistor M8 for initializing the light-emitting element LD using a transmission control signal, and can be controlled by using a transmission control signal from... Figure 1 A scan signal output by a scan driver 200 is used to control the fourth transistor M4 and the seventh transistor M7.

[0111] Therefore, the scan driver configuration for driving P-type transistors can be omitted, and the dead zone and power consumption of the display device 1000 can be greatly reduced.

[0112] Figure 4 The diagram illustrates the driver. Figure 3 A timing diagram of an example of pixels.

[0113] Reference Figure 3 and Figure 4 Pixel 10 can be operated by dividing it into emission period (EP) and non-emission period (NEP).

[0114] when Figure 1 When the display device 1000 is driven at the first driving frequency, the pixel 10 can receive scanning signals and transmit control signals at the first driving frequency.

[0115] Meanwhile, when the display device 1000 is driven at a second driving frequency lower than the first driving frequency, the pixel 10 can receive the scanning signal at the second driving frequency.

[0116] The period during which the transmission control signal is supplied to the i-th transmission control line Ei (i.e., the period during which the high voltage of the transmission control signal is supplied) is the non-transmission period NEP of pixel 10. The period during which the transmission control signal is not supplied to the i-th transmission control line Ei (i.e., the period during which the low voltage of the transmission control signal is supplied) is the transmission period EP of pixel 10.

[0117] During the non-emission period (NEP), the fifth transistor M5 and the sixth transistor M6 are turned off by the emission control signal, and therefore pixel 10 does not emit light.

[0118] Additionally, during the non-emitting period (NEP), the eighth transistor M8 can be turned on in response to the emit control signal to supply the voltage of the initialization power supply Vint to the fourth node N4. Therefore, the parasitic capacitor of the light-emitting element (LD) can be discharged.

[0119] Meanwhile, the non-transmission period NEP can include a first period P1 and a second period P2.

[0120] According to some example embodiments, the transmit control signal can be supplied to the (i+x)th transmit control line Ei+x after being supplied to the i-th transmit control line Ei. Alternatively, the transmit control signal can be supplied to the (i+y)th transmit control line Ei+y after being supplied to the (i+x)-th transmit control line Ei+x. For example, x can be 4 (i.e., the (i+4)-th transmit control line Ei+4), and y can be 5 (i.e., the (i+5)-th transmit control line Ei+5). The transmit control signal supplied to the (i+4)-th transmit control line Ei+4 can be a signal obtained by shifting the transmit control signal supplied to the i-th transmit control line Ei by four horizontal time intervals. However, this is only an example, and the transmit control lines connected to the second transistor M2 and the third transistor M3 are not limited thereto.

[0121] During the first time period P1, a scan signal can be supplied to the (i-1)th scan line Si-1. During the second time period P2, a scan signal can be supplied to the ith scan line Si. Here, the scan signal, as a signal used to control the N-type transistor, has a high voltage.

[0122] The seventh transistor M7 can be turned on in response to the scan signal supplied to the (i-1)th scan line Si-1 during the first time period P1. When the seventh transistor M7 is turned on, the voltage of the initialization power supply Vint can be supplied to the second node N2. Therefore, the gate voltage of the first transistor M1 can be initialized and the first transistor M1 can be turned on and biased. Therefore, the first time period P1 can be the initialization period.

[0123] According to some example embodiments, during the first time period P1, no transmit control signal is supplied to the (i+x)th transmit control line Ei+x and the (i+y)th transmit control line Ei+y. Therefore, during the first time period P1, the second transistor M2 can be turned off and the third transistor M3 can be turned on. Consequently, the data line Dj and the first node N1 are not electrically connected to each other.

[0124] The fourth transistor M4 can be turned on in response to the scan signal supplied to the i-th scan line Si during the second time period P2. Additionally, during the second time period P2, the transmit control signal is supplied to the (i+x)-th transmit control line Ei+x, but not to the (i+y)-th transmit control line Ei+y. Therefore, both the second transistor M2 and the third transistor M3 can be turned on during the second time period P2.

[0125] Because all transistors from the second transistor M2 to the fourth transistor M4 are turned on during the second time period P2, the first transistor M1 can be connected as a diode. When the second transistor M2 and the third transistor M3 are turned on, the data line Dj and the first node N1 can be electrically connected to each other, and the data signal DSi can be supplied from the data line Dj to the first node N1. When the fourth transistor M4 is turned on, the second node N2 and the third node N3 can be electrically connected to each other, and therefore the threshold voltage of the first transistor M1 can be compensated. That is, the second time period P2 can be the data writing and threshold voltage compensation period.

[0126] Subsequently, the transmit control signal can be supplied to the (i+y)th transmit control line Ei+y, and thus the third transistor M3 can be turned off. Therefore, the storage capacitor Cst can maintain the state in which the data signal DSi supplied in the second time period P2 is stored.

[0127] Subsequently, the supply of the transmit control signal to the transmit control line Ei is stopped. When the supply of the transmit control signal to the transmit control line Ei is stopped, the fifth transistor M5 and the sixth transistor M6 are turned on. Meanwhile, the eighth transistor M8 is turned off. At this time, the first transistor M1 controls the drive current flowing to the light-emitting element LD according to the voltage of the second node N2. Then, the light-emitting element LD can generate light with a brightness corresponding to the amount of current and emit light during the emission period EP.

[0128] During the transmission period EP, the supply of transmission control signals to the (i+x)th transmission control line Ei+x and the (i+y)th transmission control line Ei+y can be sequentially stopped. However, because at least one of the second transistor M2 and the third transistor M3 is turned off during the transmission period EP, the data line Dj and the first node N1 are not electrically connected to each other during the transmission period EP.

[0129] As described above, since the second transistor M2 and the third transistor M3, which transmit the data signal DSi to the first node N1 of pixel 10, are controlled by the transmit control signal, the configuration of the scan driver used to control the P-type transistors can be eliminated. Therefore, the number of... Figure 1 The dead zone and power consumption of the display device 1000.

[0130] At the same time, Figure 2B During the second driving period T2, only control signals are transmitted for reference. Figure 2B The described second driving frequency is periodically supplied to pixel 10. Therefore, the second transistor M2 and the third transistor M3 can... Figure 2B During the second driving period T2, the transistors M2 and M3 are periodically turned on simultaneously (or in parallel). When the second transistor M2 and the third transistor M3 are turned on simultaneously (or in parallel), the voltage of the reference power supply Vref can be supplied to the first node N1.

[0131] According to some example embodiments, the voltage of the reference power supply Vref can have a voltage level that can apply a conduction bias to the driving transistor of pixel 10. By periodically conducting bias on the first transistor M1 during the second driving period T2, the hysteresis characteristics of the first transistor M1 can be improved. Therefore, image flicker that may occur during low-frequency driving can be improved.

[0132] Figure 5 The diagram illustrates the driver. Figure 3 Another example of a timing diagram of pixels.

[0133] In addition to the timing of the transmission control signals supplied to the i+x and i+y transmission control lines connected to pixel 10, Figure 5 The driving force of the pixels and Figure 4The driving methods are essentially the same, and therefore, some repetitive descriptions can be omitted.

[0134] Reference Figure 3 and Figure 5 The transmit control signal can be supplied to the (i+y)th transmit control line Ei+y after being supplied to the (i+y)th transmit control line Ei+x. Alternatively, the transmit control signal can be supplied to the (i+x)th transmit control line Ei+x after being supplied to the (i)th transmit control line Ei.

[0135] For example, x can be -4 (i.e., the (i-4)th emitter control line Ei-4), and y can be -5 (i.e., the (i-5)th emitter control line Ei-5). However, this is just an example, and the emitter control lines connected to the second transistor M2 and the third transistor M3 are not limited to this.

[0136] The second transistor M2 and the third transistor M3 can be turned on simultaneously (or in parallel) during the second time period P2. That is, the time period in which the transmit control signal is supplied to the (i+x)th transmit control line Ei+x but not to the (i+y)th transmit control line Ei+y can overlap with the second time period P2.

[0137] During periods other than the second time period P2, because the second transistor M2 and the third transistor M3 are not simultaneously (or in parallel) turned on, it is possible to perform operations related to... Figure 4 The driver operates essentially the same way.

[0138] Figure 6 The diagram illustrates the driver. Figure 3 Another example of a timing diagram for pixels.

[0139] In addition to the timing of the transmission control signals supplied to the i+x and i+y transmission control lines connected to pixel 10, Figure 6 The driving force of the pixels and Figure 4 The driving methods are essentially the same, and therefore, some repetitive descriptions can be omitted.

[0140] Reference Figure 3 and Figure 6 The transmit control signal can be supplied to the (i+x)th transmit control line Ei+x after being supplied to the (i+x)th transmit control line Ei+x.

[0141] According to some example embodiments, the gate electrode of the second transistor M2 can be connected to the i-th emitter control line Ei. That is, x can be zero. In this case, the i+y-th emitter control line Ei+y can be the emitter control line that supplies the emitter control signal to it after the second time period P2. For example, y can be greater than zero and less than five. However, this is only an example, and the emitter control lines connected to the second transistor M2 and the third transistor M3 are not limited to this.

[0142] The second transistor M2 and the third transistor M3 can be turned on simultaneously during the second time period P2. That is, the time period in which the transmit control signal is supplied to the (i+x)th transmit control line Ei+x but not to the (i+y)th transmit control line Ei+y can overlap with the second time period P2. In addition, even in the time period before the second time period P2 within the non-transmit time period NEP, there may be a time period in which the second transistor M2 and the third transistor M3 are turned on simultaneously (or in parallel).

[0143] However, after the second time period P2, the second transistor M2 and the third transistor M3 do not conduct simultaneously (or in parallel). For example, when the second time period P2 has passed, the transmit control signal can be supplied to the (i+y)th transmit control line Ei+y. Therefore, it is possible to execute... Figure 4 The driver operates essentially the same way.

[0144] As described above, when the transmit control line is connected to... Figures 4 to 6 When corresponding to the operating conditions shown, the emitter control lines connected to the gate electrodes of the respective second transistor M2 and third transistor M3 can be freely selected. For example, during the second time period P2, it is necessary to supply the emitter control signal to the (i+x)th emitter control line Ei+x (i.e., supply a high-voltage emitter control signal), and it is not necessary to supply the emitter control signal to the (i+y)th emitter control line Ei+y (i.e., supply a low-voltage emitter control signal). Furthermore, at least one of the second transistor M2 and the third transistor M3 can be turned off after the second time period P2.

[0145] Figure 7 The diagram shows Figure 3 A circuit diagram of an example pixel.

[0146] In description Figure 7 When assigning the same reference numerals to the same reference numerals... Figure 3 The parts are the same or similar to the parts, and some repeated descriptions can be omitted.

[0147] Reference Figure 7 Pixel 10' may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0148] The seventh transistor M7 is connected between the second node N2 and the first initialization power supply Vint1. The gate electrode of the seventh transistor M7 is connected to the (i-1)th scan line Si-1. When the scan signal is supplied to the (i-1)th scan line Si-1, the seventh transistor M7 is turned on to supply the voltage of the first initialization power supply Vint1 to the second node N2.

[0149] The eighth transistor M8 can be connected between the second initialization power supply Vint2 and the fourth node N4. According to some example embodiments, the gate electrode of the eighth transistor M8 can be connected to the i-th emitter control line Ei.

[0150] The first initialization power supply Vint1 and the second initialization power supply Vint2 can generate different voltages. That is, the voltage used to initialize the second node N2 and the voltage used to initialize the fourth node N4 can be set differently.

[0151] In low-frequency driving where the image refresh rate varies over time, when the voltage of the first initialization power supply Vint1 supplied to the second node N2 is too low, the hysteresis of the first transistor M1 increases during the corresponding frame period. This hysteresis can cause flickering in low-frequency driving. Therefore, in low-frequency driving display devices, a voltage of the first initialization power supply Vint1 higher than the voltage of the second power supply VSS may be required.

[0152] However, when the voltage of the second initialization power supply Vint2 supplied to the fourth node N4 becomes higher than a reference (e.g., a set or predetermined reference), the voltage of the parasitic capacitor of the light-emitting element LD can be charged instead of discharged. Therefore, the voltage of the second initialization power supply Vint2 needs to be lower than the reference (e.g., a set or predetermined reference). For example, the voltage of the second initialization power supply Vint2 can have a voltage similar to the voltage of the second power supply VSS. However, this is only an example, and depending on the driving conditions of the display device, the voltage of the second initialization power supply Vint2 can be higher or lower than the voltage of the second power supply VSS.

[0153] That is, in order to improve the driving performance of pixel 10', the voltage supplied to the second node N2 through the seventh transistor M7 and the voltage supplied to the fourth node N4 through the eighth transistor M8 can be set differently. Therefore, flickering and incorrect emission can be improved.

[0154] Figure 8 and Figure 9 This is a circuit diagram illustrating other examples of pixels.

[0155] In description Figure 8 and Figure 9 When assigning the same reference numerals to the same reference numerals... Figure 3 and Figure 7 The parts are the same or similar to the parts, and some repeated descriptions can be omitted.

[0156] Reference Figure 8 and Figure 9 Pixels 11 and 11' may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0157] The second transistor M2 and the third transistor M3 can be connected in series between the data line Dj and the first node N1. The second transistor M2 and the third transistor M3 can be of different types.

[0158] According to some example embodiments, the second transistor M2 may be a P-type polysilicon semiconductor transistor, and the third transistor M3 may be an N-type oxide semiconductor transistor.

[0159] The gate electrode of the second transistor M2 can be connected to Figures 4 to 6 One of the i+y emitter control lines Ei+y shown. The gate electrode of the third transistor M3 can be connected to Figures 4 to 6 This is one of the (i+x)th emission control lines Ei+x shown. Therefore, pixels 11 and 11' can perform [the operation] with [other functions]. Figure 3 The operation for pixel 10 is basically the same.

[0160] Because, apart from the configuration of the second transistor M2 and the third transistor M3, Figure 8 Pixel 11 and Figure 3 Since the 10 pixels are the same, some redundant descriptions can be omitted. Additionally, because besides the configuration of the second transistor M2 and the third transistor M3, Figure 9 Pixel 11' and Figure 7 Since the 10' pixels are the same, some of the repeated descriptions can be omitted.

[0161] Figure 10 and Figure 11 This is a circuit diagram illustrating yet another example of a pixel.

[0162] In description Figure 10 and Figure 11 When assigning the same reference numerals to the same reference numerals... Figure 3 and Figure 7 The parts are the same or similar to the parts, and some repeated descriptions can be omitted.

[0163] Reference Figure 10 and Figure 11 Pixels 12 and 13 may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0164] The eighth transistor M8 can be connected between the second initialization power supply Vint2 and the fourth node N4. According to some example embodiments, the gate electrode of the eighth transistor M8 can be connected to one of the (i-1)th scan line Si-1, the ith scan line Si, and the (i+1)th scan line Si+1. Therefore, the eighth transistor M8 can be turned on in response to a scan signal.

[0165] Because, apart from the configuration of the eighth transistor M8, Figure 10 Pixel 12 and Figure 7 Since the 10' pixels are the same, some redundant descriptions can be omitted. Additionally, because besides the configuration of the eighth transistor M8, Figure 11 Pixel 13 and Figure 9 Since the pixel 11' is the same, some of its redundant descriptions can be omitted.

[0166] As described above, a pixel including N-type and P-type transistors, and a display device including such a pixel, according to some example embodiments of this disclosure, can control a second transistor M2 and a third transistor M3 for writing data signals using a transmit control signal. Therefore, a scan driver configuration for driving the P-type transistors can be eliminated. Consequently, the dead zone and power consumption of the display device can be significantly reduced.

[0167] Although this disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes may be made to this disclosure without departing from the spirit and scope of the embodiments of this disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: Pixels are connected to scan lines, emission control lines, and data lines; A scan driver is configured to supply scan signals to the scan line; A transmit driver is configured to supply transmit control signals to the transmit control line; as well as A data driver is configured to supply a data signal to the data line in response to the scan signal. The pixels in the i-th horizontal line among the pixels include: Light-emitting elements; A first transistor includes a first electrode connected to a first node and is configured to control a drive current based on a voltage at a second node, the first node being electrically connected to a first power source. The second transistor includes a gate electrode connected to the i+xth emitter control line and connected to one of the data lines; The third transistor includes a gate electrode connected to the i+y emitter control line and is connected between the second transistor and the first node; A fourth transistor, connected between a third node connected to the second electrode of the first transistor and the second node, is configured to be turned on by a scan signal supplied to the i-th scan line; and The fifth transistor is connected between the first power supply and the first node, and is configured to be turned off by a transmit control signal supplied to the i-th transmit control line. Where i is an integer greater than 0, x is an integer, and y is a non-zero integer different from x. The transmit control signal supplied to the (i+x)th transmit control line and the transmit control signal supplied to the (i+y)th transmit control line are signals offset from the transmit control signal supplied to the (i)th transmit control line. During the data writing and threshold voltage compensation period, the second transistor is configured to be turned on by the transmit control signal supplied to the i+x transmit control line, and the third transistor is configured to be turned on by not supplying the transmit control signal to the i+y transmit control line.

2. The display device according to claim 1, wherein, The second transistor and the third transistor are of different types.

3. The display device according to claim 2, wherein, The second transistor is an N-type transistor including an oxide semiconductor layer, and the third transistor is a P-type transistor including a polycrystalline silicon semiconductor layer.

4. The display device according to claim 3, wherein, The third transistor is configured to be turned off by the transmit control signal supplied to the i+y transmit control line.

5. The display device according to claim 4, wherein, The transmit driver is configured to supply the transmit control signal to the (i+x)th transmit control line after supplying the transmit control signal to the (i+x)th transmit control line, and to supply the transmit control signal to the (i+y)th transmit control line after supplying the transmit control signal to the (i+x)th transmit control line.

6. The display device according to claim 4, wherein, The transmit driver is configured to supply the transmit control signal to the (i+y)th transmit control line after supplying the transmit control signal to the (i+y)th transmit control line, and to supply the transmit control signal to the (i+x)th transmit control line after supplying the transmit control signal to the (i+x)th transmit control line.

7. The display device according to claim 4, wherein, The transmit driver is configured to simultaneously supply the transmit control signal to the i-th transmit control line and the (i+x)-th transmit control line, and to supply the transmit control signal to the (i+y)-th transmit control line after supplying the transmit control signal to the (i+x)-th transmit control line.

8. The display device according to claim 2, wherein, The pixel located in the i-th horizontal line further includes: A sixth transistor, connected between the third node and the first electrode of the light-emitting element, is configured to be turned off by the emission control signal supplied to the i-th emission control line; and The seventh transistor is connected between the second node and the first initialization power supply and is configured to be turned on by a scan signal supplied to the (i-1)th scan line.

9. The display device according to claim 8, wherein, The pixel located in the i-th horizontal line further includes: The eighth transistor, coupled between the second initialization power supply and the first electrode of the light-emitting element, is configured to be turned on by the emission control signal supplied to the i-th emission control line, and Wherein, the fourth transistor, the seventh transistor, and the eighth transistor are N-type transistors including an oxide semiconductor layer, and The fifth and sixth transistors are P-type transistors that include a polycrystalline silicon semiconductor layer.

10. The display device according to claim 2, wherein, The second transistor is a P-type transistor including a polycrystalline silicon semiconductor layer, and the third transistor is an N-type transistor including an oxide semiconductor layer.

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