A communication chip for single-line power supply communication

Abstract

The present application discloses a communication chip for single-line power supply communication, the communication chip is connected to other communication chips via a power supply communication line, the communication chip includes a transmission circuit, the transmission circuit is connected to the power supply communication line to generate a transmission signal on the power supply communication line, wherein the transmission circuit generates a full-modulation transmission signal in a first modulation working mode and generates a non-full-modulation transmission signal in a second modulation working mode; wherein the modulation speed of the non-full-modulation transmission signal is faster than the modulation speed of the full-modulation transmission signal. In the above manner, the present application can improve the communication speed while realizing single-line power supply.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a communication chip for single-line power supply communication. Background Art

[0002] The current single-bus communication uses a single signal line for communication, which can save input / output communication resources, has a simple structure, low cost, and is easy to expand and maintain the bus, etc., and is widely used; the single-bus communication solutions include the Maxim chip single-bus solution and the Infineon chip single-bus solution. The Maxim chip single-bus solution uses a single bus for power supply and communication. Due to the need to take into account single-line communication and power supply, the chip communication rate is slow; in the Infineon chip single-bus solution, the single-bus communication rate is configurable and supports fast communication, but it requires a separate power supply, which affects its use in some scenarios. Summary of the invention

[0003] The present application provides a communication chip for single-line power supply communication, which can improve the communication speed while realizing single-line power supply.

[0004] In order to solve the above technical problems, the technical solution adopted in the present application is: to provide a communication chip for single-line power supply communication, the communication chip is connected to other communication chips via a power supply communication line, the communication chip includes a transmitting circuit, the transmitting circuit is connected to the power supply communication line to generate a transmitting signal on the power supply communication line, wherein the transmitting circuit generates a fully modulated transmitting signal in a first modulation working mode and generates a non-fully modulated transmitting signal in a second modulation working mode; wherein the modulation speed of the non-fully modulated transmitting signal is faster than the modulation speed of the fully modulated transmitting signal.

[0005] Through the above scheme, the beneficial effect of the present application is: the communication chip in the present application includes a transmitting circuit, which can operate in two modes: a first modulation operating mode and a second modulation operating mode, generating a full-modulation transmission signal and a non-full-modulation transmission signal. Since the voltage amplitude corresponding to the full-modulation transmission signal is higher than that of the non-full-modulation transmission signal, the modulation speed of the non-full-modulation transmission signal is faster than the modulation speed of the full-modulation transmission signal. Therefore, when the transmitting circuit operates in the second modulation operating mode, it can speed up the communication speed and reduce the transmission time of the communication signal while realizing single-line power supply, and can be compatible with high-speed single-line communication and ordinary single-line communication to meet the needs of different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0007] Figure 1 It is a structural schematic diagram of an embodiment of a communication chip for single-line power supply communication provided by the present application;

[0008] Figure 2 It is a structural schematic diagram of another embodiment of a communication chip for single-line power supply communication provided by the present application;

[0009] Figure 3 yes Figure 2 A schematic diagram of the structure of a sending circuit in the embodiment shown;

[0010] Figure 4 yes Figure 2 Another structural schematic diagram of the sending circuit in the embodiment shown;

[0011] Figure 5 yes Figure 3 A schematic diagram of the structure of a sending circuit in the embodiment shown;

[0012] Figure 6 yes Figure 5 The signal timing diagram of the embodiment shown;

[0013] Figure 7 yes Figure 2 A schematic diagram of the structure of the adjustment module in the embodiment shown;

[0014] Figure 8 yes Figure 3 Another structural schematic diagram of the sending circuit in the embodiment shown;

[0015] Fig. 9 yes Figure 4 A schematic diagram of the structure of a sending circuit in the embodiment shown;

[0016] Fig.10 yes Fig. 9 The signal timing diagram of the embodiment shown;

[0017] Fig.11 yes Figure 2 A schematic diagram of the structure of a receiving circuit in the embodiment shown;

[0018] Fig.12 yes Fig.11 A schematic diagram of the structure of a receiving circuit in the embodiment shown;

[0019] Fig.13 yes Fig.12 The signal timing diagram of the embodiment shown;

[0020] Fig.14 yes Figure 2 A schematic diagram of the structure of the communication chip and other communication chips in the embodiment shown. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] See also Figure 1 , Figure 1 It is a structural schematic diagram of an embodiment of a communication chip for single-line power supply communication provided by the present application. The communication chip is connected to other communication chips via a power supply communication line, and the communication chip includes a sending circuit 10.

[0023] The power supply communication line can transmit power supply signals and communication signals. The sending circuit 10 is connected to the power supply communication line to generate a sending signal on the power supply communication line, that is, the sending circuit 10 can generate a sending signal and send the sending signal to other communication chips through the power supply communication line. The sending signal includes a full-modulation sending signal or a non-full-modulation sending signal.

[0024] The transmitting circuit 10 can operate in a first modulation working mode or a second modulation working mode. In the first modulation working mode, a fully modulated transmitting signal is generated, and the fully modulated transmitting signal can be an amplitude modulation signal, and the amplitude modulation index is 100%; in the second modulation working mode, a non-fully modulated transmitting signal is generated, and the amplitude modulation index corresponding to the non-fully modulated transmitting signal is less than 100%, such as 10% or 20%. The corresponding working mode can be selected according to specific needs.

[0025] The non-full-modulation transmission signal does not transmit the signal during the time corresponding to the low level, so the modulation speed of the non-full-modulation transmission signal is faster than the modulation speed of the full-modulation transmission signal. When the transmitting circuit 10 works in the second modulation working mode, it can improve the communication speed and reduce the signal transmission time while realizing single-line power supply, and can be compatible with high-speed single-line communication and ordinary single-line communication, providing a variety of working modes for users to choose from, meeting the needs of different application scenarios.

[0026] See also Figure 2 , Figure 2 It is a structural schematic diagram of another embodiment of a communication chip for single-line power supply communication provided by the present application. The sending circuit 10 includes: a sending control unit 11, a first sending processing unit 12 and a second sending processing unit 13.

[0027] The transmission control unit 11 may obtain the data signal tx_data to be transmitted, and generate a corresponding control signal according to the data signal tx_data to be transmitted, so as to control the first transmission processing unit 12 or the second transmission processing unit 13 .

[0028] The first sending processing unit 12 is connected to the sending control unit 11, and it works in the first modulation working mode, and processes the control signal in the first modulation working mode to generate a fully modulated sending signal; the second sending processing unit 13 is connected to the sending control unit 11, and it works in the second modulation working mode, and processes the control signal in the second modulation working mode to generate a non-fully modulated sending signal.

[0029] In a specific embodiment, Figure 3 As shown, the transmission control unit 11 can receive a data signal to be transmitted tx_data and a modulation mode signal tx_mode, and process the data signal to be transmitted tx_data according to the modulation mode signal tx_mode to selectively generate a first control signal ctrl_a or a second control signal ctrl_b.

[0030] The first transmission processing unit 12 is used to receive the first control signal ctrl_a, to operate in the first modulation working mode after receiving the first control signal ctrl_a, and to process the first control signal ctrl_a to generate a fully modulated transmission signal.

[0031] Furthermore, the first sending processing unit 12 includes: a first switch 121, the first switch 121 includes a control end, a first path end and a second path end, the control end of the first switch 121 is connected to the sending control unit 11 and receives the first control signal ctrl_a, the first path end of the first switch 121 is connected to the single-wire interface 20 connecting the communication chip and the power supply communication line, and the second path end of the first switch 121 is connected to the ground signal to pull the voltage at the single-wire interface 20 down to the ground signal during the period when the first control signal ctrl_a is enabled, thereby generating a fully modulated sending signal, which can be a SWI signal (Single Wire Interface).

[0032] The second transmission processing unit 13 is used to receive the second control signal ctrl_b, to operate in the second modulation working mode after receiving the second control signal ctrl_b, and to process the second control signal ctrl_b to generate a non-full modulation transmission signal.

[0033] Further, the second sending processing unit 13 includes: an adjustment module 131 and a second switch 132; the adjustment module 131 includes a first end and a second end, and the first end of the adjustment module 131 is connected to the single-line interface 20; the second switch 132 includes a control end, a first path end and a second path end, the control end of the second switch 132 is connected to the sending control unit 11 and receives the second control signal ctrl_b, the first path end of the second switch 132 is connected to the second end of the adjustment module 131, and the second path end of the second switch 132 is connected to the ground signal to pull the voltage at the single-line interface 20 down to a preset voltage matching the adjustment module 131 when the second control signal ctrl_b is enabled, thereby generating a non-full-modulation sending signal, which can be a SWI signal.

[0034] In another specific embodiment, Figure 4 As shown, the sending circuit 10 further includes: a first switch 121 , an adjustment module 131 and a second switch 132 , the first switch 121 and the second switch 132 constitute a first sending processing unit 12 , and the adjustment module 131 and the second switch 132 constitute a second sending processing unit 13 .

[0035] The first switch 121 includes a control end, a first path end and a second path end. The control end of the first switch 121 receives the modulation mode signal tx_mode, and the first path end of the first switch 121 is connected to the single-wire interface 20; the adjustment module 131 includes a first end and a second end. The first end of the adjustment module 131 is connected to the single-wire interface 20.

[0036] The second switch 132 includes a control end, a first path end, and a second path end. The control end of the second switch 132 is connected to the sending control unit 11 to receive the second control signal ctrl_b. The first path end of the second switch 132 is connected to the second path end of the first switch 121 and the second end of the adjustment module 131. The second path end of the second switch 132 is connected to the ground signal.

[0037] In a specific embodiment, the adjustment module 131 includes a plurality of diodes connected in series (not shown in the figure), the anodes of the plurality of diodes connected in series serve as the first end of the adjustment module 131, and the cathodes of the plurality of diodes connected in series serve as the second end of the adjustment module 131; specifically, in conjunction with reference to Figure 3 and Figure 5, the sending control unit 11 receives the data signal tx_data to be sent and the modulation mode signal tx_mode, the first switch 121 and the second switch 132 are NMOS tubes (Negative channel Metal Oxide Semiconductor, N-type metal oxide semiconductor), the control end, the first channel end and the second channel end are the source, the drain and the gate respectively, the modulation mode signal tx_mode is the control signal of the working mode, and its value is "0" or "1". When the modulation mode signal tx_mode is "1", it works in the first modulation working mode; when the modulation mode signal tx_mode is "0", it works in the second modulation working mode; using the NMOS tube T1, ordinary communication with 100% modulation can be realized. When the NMOS tube T1 is turned on, the NMOS tube T2 is in a closed state, and the voltage of the SWI signal is pulled down to the ground voltage; using the NMOS tube T2, high-speed communication with non-100% modulation can be realized. When the NMOS tube T2 is turned on, the NMOS tube T1 is in a closed state, and the voltage of the SWI signal is pulled down to a preset voltage, which is n*V dioe , where n is the number of diodes D in the adjustment module 131, V dioe For the conduction voltage of each diode D, the corresponding signal timing diagram can be shown as Figure 6 As shown, Figure 6 (a) is the signal timing diagram corresponding to when the modulation mode signal tx_mode is "1". Figure 6 (b) is the signal timing diagram corresponding to when the modulation mode signal tx_mode is "0", from which it can be seen that the lowest voltage of the SWI signal in the second modulation working mode is greater than the lowest voltage of the SWI signal in the first modulation working mode.

[0038] In another specific embodiment, Figure 7 As shown, the adjustment module 131 includes: a first resistor R1, an adjustment resistor R and a third switch 1311 with an adjustable conduction degree, the third switch 1311 includes a control end, a first path end and a second path end, one end of the first resistor R1 and one end of the adjustment resistor R are connected together as a connection node A, the control end of the third switch 1311 is connected to the connection node A, the first path end of the third switch 1311 is connected to the other end of the first resistor R1 and is connected to the single-line interface 20 as the first end of the adjustment module 131, and the second path end of the third switch 1311 is connected to the other end of the adjustment resistor R and is connected to the first path end of the second switch 132 as the second end of the adjustment module 131. Specifically, in conjunction with reference to Figure 3 , Figure 7 and Figure 8, the first switch 121 and the second switch 132 are NMOS tubes, the third switch 1311 is a PMOS tube (Positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor), the sending control unit 11 receives the data signal tx_data to be sent and the modulation mode signal tx_mode, after the NMOS tube T2 and the PMOS tube T3 are turned on, the voltage of the SWI signal is pulled down to a preset voltage, which is k*V thpmos , where k is the proportionality coefficient, and k=1+(resistance value of the first resistor R1) / (resistance value of the adjustment resistor R), V thpmos is the threshold voltage of the PMOS tube T3, the resistance value of the adjustment resistor R can be changed under the control of the third control signal ctrl_c to achieve proportional adjustment, and the corresponding signal timing diagram is Figure 6 Similar; or see Figure 3 , Figure 7 and Fig. 9 , the sending control unit 11 receives the data signal to be sent tx_data, and the control end of the second switch 132 receives the modulation mode signal tx_mode. The corresponding signal timing diagram can be shown as follows Fig.10 shown.

[0039] Continue reading Figure 2 and Figure 7 The communication chip also includes a control logic unit 30 and a receiving circuit 40, and the control logic unit 30 is connected to the sending circuit 10 and the receiving circuit 40; specifically, the control logic unit 30 is connected to the adjustment module 131 to output a third control signal ctrl_c to the control end of the adjustment resistor R, thereby adjusting the resistance value of the adjustment resistor R.

[0040] The receiving circuit 40 is connected to the power supply communication line to receive the data signal to be received transmitted through the power supply communication line, and demodulates the data signal to be received. In the first demodulation working mode, the receiving circuit 40 fully demodulates the data signal to be received to generate a fully demodulated received data signal. The first demodulation working mode corresponds to the first modulation working mode; in the second demodulation working mode, the receiving data signal is not fully demodulated to generate a not fully demodulated received data signal. The second demodulation working mode corresponds to the second modulation working mode.

[0041] In a specific embodiment, Fig.11 As shown, the receiving circuit 40 includes: a receiving control unit 41 , a first receiving processing unit 42 and a second receiving processing unit 43 .

[0042] The receiving control unit 41 is used to obtain a demodulation mode signal rx_mode, and selectively generate a first enable signal EN1 or a second enable signal EN2 according to the demodulation mode signal rx_mode. The demodulation mode signal rx_mode may be the same as the modulation mode signal tx_mode.

[0043] The first receiving processing unit 42 is connected to the receiving control unit 41 and operates in the first demodulation working mode to fully demodulate the receiving data signal rx_SWI in the first demodulation working mode to generate a fully demodulated receiving data signal rx_data1.

[0044] Furthermore, the first receiving processing unit 42 includes: a first demodulation unit 421, which is connected to the single-line interface 20 and the receiving control unit 41 to receive the first enable signal EN1, and demodulate the received data signal rx_SWI when the first enable signal EN1 is enabled, generate a fully demodulated received data signal rx_data1 and send it to the receiving control unit 41.

[0045] The second receiving processing unit 43 is connected to the receiving control unit 41 , and operates in the second demodulation working mode. In the second demodulation working mode, the second receiving processing unit 43 performs non-complete demodulation on the receiving data signal rx_SWI to generate a non-complete demodulated receiving data signal rx_data2 .

[0046] Furthermore, the second receiving processing unit 43 includes: a delay unit 431 and a second demodulation unit 432; the delay unit 431 is connected to the single-wire interface 20, and is used to receive the data signal rx_SWI to be received, and delay the data signal rx_SWI to be received; the second demodulation unit 432 is connected to the single-wire interface 20 and the receiving control unit 41, and is used to receive the second enable signal EN2, and compare the data signal rx_SWI to be received with the delayed data signal to be received when the second enable signal EN2 is enabled, generate a non-fully demodulated receiving data signal rx_data2 and send it to the receiving control unit 41.

[0047] The receiving control unit 41 is also used to output a data signal rx_data after receiving the fully demodulated received data signal rx_data1 or the non-fully demodulated received data signal rx_data2, and the data signal rx_data may be the same as the fully demodulated received data signal rx_data1 or the non-fully demodulated received data signal rx_data2; or the receiving control unit 41 may process the fully demodulated received data signal rx_data1 or the non-fully demodulated received data signal rx_data2 to generate the data signal rx_data.

[0048] In a specific embodiment, Fig.12As shown, the delay unit 431 includes a second resistor R2 and a capacitor C, one end of the second resistor R2 is connected to the single-wire interface 20, the other end of the second resistor R2 is connected to one end of the capacitor C and the second demodulation unit 432, and the other end of the capacitor C is connected to the ground signal.

[0049] The first demodulation unit 421 is a Schmitt trigger, which includes an input terminal and an enable control terminal. The input terminal of the Schmitt trigger 421 is connected to the single-wire interface 20 , and the enable control terminal of the Schmitt trigger 421 is connected to the receiving control unit 41 to receive the first enable signal EN1 .

[0050] The Schmitt trigger 421 can be used to demodulate ordinary communication signals, and a 100% modulated signal can be demodulated and output to the receiving control unit 41.

[0051] The second demodulation unit 432 is a comparator, which includes a first input terminal, a second input terminal, an output terminal and an enable control terminal. The first input terminal of the comparator 432 is connected to the single-wire interface 20, the second input terminal of the comparator 432 is connected to one end of the capacitor C, the output terminal of the comparator 432 is connected to the receiving control unit 41, and the enable control terminal of the comparator 432 is connected to the receiving control unit 41 to receive the second enable signal EN2, wherein the first input terminal and the second input terminal are respectively a non-inverting input terminal and an inverting input terminal.

[0052] The received data signal rx_SWI may be a SWI signal. The comparator 432 may be used to implement high-speed demodulation of the communication signal. The second resistor R2 and the capacitor C in the circuit may delay the SWI signal. The comparator 432 compares the SWI signal with the delayed signal, extracts the envelope signal on the SWI signal, and outputs the non-fully demodulated received data signal rx_data2 to the receiving control unit 41. The corresponding signal timing diagram is shown in FIG. Fig.13 As shown, V0 is the signal of the SWI signal after being delayed by the second resistor R2 and the capacitor C. By comparing the V0 signal and the SWI signal, the SWI signal can be demodulated. Through flexible mode configuration, high-speed and ordinary single-line communication can be achieved.

[0053] The communication chip can communicate with other communication chips through the power supply communication line. Specifically, Fig.14As shown, other communication chips serve as host chips, and the communication chip in this embodiment serves as a slave chip. The host chip includes an MCU (MicroControl Unit) and a power supply VCC, a resistor R0, at least one diode D0 and an NPN transistor Q. The MCU includes two GPIO interfaces (General Purpose Input Output). The MCU controls the NPN transistor Q and the diode D0 through GPIO2 to achieve non-100% modulated communication during high-speed communication. It can meet the requirement that the power supply of the chip is not greatly affected while achieving high-speed communication. When receiving a non-100% modulated signal, the MCU can adopt a solution similar to that adopted by the communication chip or adopt an ADC (Analog to Digital Converter) to achieve it.

[0054] In addition to the transmitting circuit 10, the single-line interface 20, the control logic unit 30 and the receiving circuit 40 in the above-mentioned embodiment, the slave chip also includes a diode D1, a capacitor C1 and a power supply VDD. The diode D1 and the capacitor C1 can play a role of buffering and filtering. The signal of the power supply VDD comes from the power supply VCC in the host chip. By designing the transmitting circuit 10 and the receiving circuit 40, compatibility between high-speed communication and ordinary communication can be achieved.

[0055] This embodiment provides a solution for power supply and communication using a single bus, improves the compatibility issue between power supply and high-speed communication of the single bus, adds a communication circuit structure with amplitude modulation that is not 100% modulation, and further speeds up the communication rate and shortens the communication time while ensuring the power supply of the communication chip.

[0056] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A communication chip for single-line power supply communication, which is connected to other communication chips via a power supply communication line, characterized in that: The communication chip comprises: a transmitting circuit connected to the power supply communication line to generate a transmitting signal on the power supply communication line, wherein the transmitting circuit generates a full-modulation transmitting signal in a first modulation working mode and generates a non-full-modulation transmitting signal with a modulation speed faster than the full-modulation transmitting signal in a second modulation working mode; The transmitting circuit includes: a transmitting control unit, which obtains a data signal to be transmitted and generates a corresponding control signal according to the data signal to be transmitted; a second transmitting processing unit, which is connected to the transmitting control unit and receives and processes a second control signal to generate the non-full modulation transmitting signal; The second sending processing unit includes an adjustment module and a second switch, the adjustment module includes a first end and a second end, wherein the first end of the adjustment module is connected to the single-line interface; wherein the control end of the second switch is connected to the sending control unit and receives the second control signal, the first path end of the second switch is connected to the second end of the adjustment module, and the second path end of the second switch is connected to the ground signal; The adjustment module includes: a first resistor, an adjustment resistor and a third switch with adjustable conduction degree, wherein one end of the first resistor and one end of the adjustment resistor are connected together as a connection node, the control end of the third switch is connected to the connection node, the first path end of the third switch is connected to the other end of the first resistor and is connected to the single-wire interface connecting the communication chip and the power supply communication line as the first end of the adjustment module, and the second path end of the third switch is connected to the other end of the adjustment resistor and is connected to the second switch as the second end of the adjustment module.

2. The communication chip according to claim 1, characterized in that: The transmitting circuit comprises: The first transmission processing unit is connected to the transmission control unit and operates in the first modulation working mode to process the control signal in the first modulation working mode to generate the fully modulated transmission signal.

3. The communication chip according to claim 2, characterized in that: The transmission control unit receives the data signal to be transmitted and the modulation mode signal, and processes the data signal to be transmitted according to the modulation mode signal to selectively generate a first control signal or a second control signal; The first transmission processing unit receives the first control signal, operates in the first modulation operation mode after receiving the first control signal, and processes the first control signal to generate the fully modulated transmission signal.

4. The communication chip according to claim 3, characterized in that: The first sending processing unit includes: A first switch, comprising a control end, a first path end, and a second path end, wherein the control end of the first switch is connected to the transmission control unit and receives the first control signal, the first path end of the first switch is connected to a single-wire interface connecting the communication chip and the power supply communication line, and the second path end of the first switch is connected to a ground signal, so as to pull the voltage at the single-wire interface down to the ground signal during the period when the first control signal is enabled, thereby generating the fully modulated transmission signal; The second transmission processing unit is used to pull down the voltage at the single-wire interface to a preset voltage matching the adjustment module when the second control signal is enabled, thereby generating the non-full-modulation transmission signal.

5. The communication chip according to claim 2, characterized in that: The transmitting circuit further comprises: A first switch, comprising a control end, a first path end and a second path end, wherein the control end of the first switch receives a modulation mode signal, and the first path end of the first switch is connected to a single-line interface connecting the communication chip and the power supply communication line; The first switch and the second switch constitute the first sending processing unit, and the first path end of the second switch is connected to the second path end of the first switch.

6. The communication chip according to claim 4 or 5, characterized in that: The communication chip further includes a control logic unit, which is connected to the adjustment module to output a third control signal to the control end of the adjustment resistor, thereby adjusting the resistance value of the adjustment resistor.

7. The communication chip according to claim 1, characterized in that: The communication chip further comprises: A receiving circuit is connected to the power supply communication line to receive a data signal to be received transmitted via the power supply communication line, and demodulates the data signal to be received, wherein the receiving circuit fully demodulates the data signal to be received in a first demodulation working mode to generate a fully demodulated received data signal, and in a second demodulation working mode, the receiving circuit partially demodulates the data signal to be received to generate a partially demodulated received data signal.

8. The communication chip according to claim 7, characterized in that: The receiving circuit comprises: A receiving control unit acquires a demodulation mode signal and selectively generates a first enable signal or a second enable signal according to the demodulation mode signal; a first receiving processing unit, connected to the receiving control unit and operating in the first demodulation working mode, to fully demodulate the to-be-received data signal in the first demodulation working mode to generate the fully demodulated received data signal; The second receiving processing unit is connected to the receiving control unit and operates in the second demodulation working mode to perform incomplete demodulation on the to-be-received data signal in the second demodulation working mode to generate the incompletely demodulated received data signal.

9. The communication chip according to claim 8, characterized in that: The first receiving processing unit includes: a first demodulation unit, connected to the single-wire interface connecting the communication chip and the power supply communication line, to receive the first enable signal, and demodulate the to-be-received data signal during the period when the first enable signal is enabled, to generate the fully demodulated received data signal and send it to the receiving control unit; The second receiving processing unit includes: A delay unit, connected to the single-wire interface, to receive the to-be-received data signal and delay the to-be-received data signal; A second demodulation unit is connected to the single-wire interface and the receiving control unit to receive the second enable signal, and compares the to-be-received data signal with the delayed to-be-received data signal while the second enable signal is enabled, generates the non-fully-demodulated received data signal and sends it to the receiving control unit.

10. The communication chip according to claim 9, characterized in that: The delay unit includes a second resistor and a capacitor, one end of the second resistor is connected to the single-wire interface, the other end of the second resistor is connected to one end of the capacitor and the second demodulation unit, and the other end of the capacitor is connected to a ground signal.

11. The communication chip according to claim 10, characterized in that: The first demodulation unit is a Schmitt trigger, the Schmitt trigger includes an input terminal and an enable control terminal, the input terminal of the Schmitt trigger is connected to the single-wire interface, and the enable control terminal of the Schmitt trigger is connected to the receiving control unit to receive the first enable signal; The second demodulation unit is a comparator, which includes a first input terminal, a second input terminal, an output terminal and an enable control terminal. The first input terminal of the comparator is connected to the single-wire interface, the second input terminal of the comparator is connected to one end of the capacitor, the output terminal of the comparator is connected to the receiving control unit, and the enable control terminal of the comparator is connected to the receiving control unit to receive the second enable signal.

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