Thin film transistor, method for manufacturing the same, and display device

Abstract

The present disclosure relates to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The plurality of metal films are spaced apart from the gate, and the plurality of metal films are insulated from the gate and the active layer.

Description

Technical Field

[0001] The present disclosure relates to display technology, and more particularly to a thin film transistor and a manufacturing method thereof, and a display device. Background Art

[0002] At present, active matrix organic light emitting diode (AMOLED) products are developing towards high definition, large size and high refresh rate. This puts high demands on the thin film transistors (TFT) used in the AMOLED driving circuit. The TFTs currently used in the AMOLED driving circuit mainly include an etch stop layer structure (ESL), a top gate structure (top gate) or a back channel etching structure (BCE). Among them, the top gate structure can effectively reduce the parasitic capacitance, and has a better refresh rate, a shorter channel and a smaller size, which can meet the needs of AMOLED development. Therefore, the top gate structure shows great prospects for future AMOLED products. Summary of the invention

[0003] An embodiment of the present disclosure provides a thin film transistor. The thin film transistor includes an active layer; a gate insulating layer on the active layer; a gate and a plurality of metal films, the gate and the plurality of metal films on the gate insulating layer. The plurality of metal films are spaced apart from the gate, and the plurality of metal films are insulated from the gate and the active layer. Since the plurality of metal films can effectively reflect light emitted by an OLED and external light during operation, the effective channel length uniformity and threshold voltage uniformity of the TFT are significantly improved.

[0004] Another embodiment of the present disclosure provides a method for manufacturing a thin film transistor. The method may include sequentially forming an active layer, a gate insulating layer, and a first metal layer on a substrate; and patterning the first metal layer to form a gate and a plurality of metal films located on at least one side of the gate. The gate may be insulated from the plurality of metal films, and the plurality of metal films may be insulated from the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The subject matter regarded as the present disclosure is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features and advantages of the present disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0006] FIG. 1A shows a schematic cross-sectional view of a top-gate oxide thin film transistor in the related art;

[0007] Figure 1B The effect of carrier diffusion to the channel active region of the active layer in the related art is shown;

[0008] Figure 2AA schematic cross-sectional view of a thin film transistor according to an embodiment of the present disclosure is shown;

[0009] Figure 2B A schematic top view of a thin film transistor according to an embodiment of the present disclosure is shown;

[0010] Figures 3A to 3G A schematic diagram showing a method for manufacturing a thin film transistor according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0011] The present disclosure will be further described in detail with reference to the accompanying drawings and embodiments so that those skilled in the art can better understand the technical solution of the present disclosure. Figure 3G When referring to the drawings, like structures and elements shown throughout are denoted by like reference numerals.

[0012] In the description of the specification, references to the terms "one embodiment", "some embodiments" and "exemplary embodiments", "examples" and "specific examples" or "some examples" and the like are intended to indicate specific features and structures, materials or characteristics described in conjunction with the embodiments or examples and included in at least some embodiments or examples of the present disclosure. Schematic expressions of terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0013] For the purpose of the following surface description, such as the orientation alignment in the accompanying drawings, the terms "above", "below", "left", "right", "vertical", "horizontal", "top", "bottom" and their derivatives may be referred to in this disclosure. The terms "covering", "on", "positioned on" or "positioned on top of" mean, for example, that a first element of a first structure is on a second element of a second structure, wherein there may be an intermediate element, such as an intermediate structure, between the first element and the second element. The term "contacting" means, for example, that a first element of a first structure and a second element of a second structure are directly or indirectly connected, and other elements may or may not be present at the interface between the two elements.

[0014] In addition, the terms "first" and "second" are for illustrative purposes only and should not be interpreted as indicating or implying relative importance or implying the number of technical features indicated by reference. Therefore, the features defined by the terms "first" and "second" may explicitly or implicitly include one or more features. In the description of the present disclosure, unless otherwise specifically defined, the meaning of "plurality" is two or more.

[0015] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is directed. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having the same meaning as in the context of the relevant technology. Unless clearly defined herein, these terms should not be interpreted as idealized or having extreme meanings. As used herein, a statement that two or more components are "connected" or "coupled" together refers to the components being joined together directly or through one or more intermediate components.

[0016] As used herein, a numerical range modified by "about" means that the upper and lower limits of the numerical range may vary by 10%.

[0017] FIG1A shows a schematic cross-sectional view of a top-gate oxide thin film transistor (TFT) in the related art. As shown in FIG1 , the oxide TFT includes a buffer layer 2, an active layer 4, a gate insulating layer 5, a gate 6, an interlayer dielectric (ILD) layer 8, a source electrode 9-1, and a drain electrode 9-2 on a substrate 1. The active layer 4 includes a channel active region 4-1 and a conductive active region 4-2 on both sides of the channel active region 4-1. As shown in FIG1A , the backplane of the top-gate oxide TFT is inevitably irradiated by the light emitted by the OLED and the external light in the actual operating environment. After irradiation, the active layer in the TFT backplane can generate a plurality of photogenerated carriers, which include, for example, electron-hole pairs and ionized oxygen vacancies, such as Vo. + 、Vo 2+ Etc. These electron-hole pairs and ionized oxygen vacancies may drift to the interface between the active layer and the insulating layer under the action of the electric field, resulting in capture or injection. Therefore, the threshold voltage drift phenomenon may occur.

[0018] Figure 1B The effect of carrier diffusion into the channel active region of the active layer in the related art is shown. Since the channel of the top gate structure is short, the uniformity of the TFT threshold voltage is easily affected by the short channel effect. Especially in the conductorization process of the active layer such as the indium gallium zinc oxide (IGZO) layer, the effect of carrier diffusion on the channel active region of the active layer is very obvious, thereby affecting the uniformity of the effective channel length (Effective Ch.length). Since the channel length (Ch.length) and the effective channel length have the following relationship: Ch.Length = EffectiveCh.Length + 2△L, as Figure 1B2ΔL is the length of the carrier diffusion to the channel active region during the conductorization of the active layer. Therefore, in order to ensure the uniformity of the effective channel length and to further improve the uniformity of the TFT threshold voltage, it is necessary to reduce the influence of the carrier diffusion on the channel active region of the active layer during the conductorization of the active layer.

[0019] Figure 2A FIG. 1 is a schematic cross-sectional view of a thin film transistor (TFT) according to an embodiment of the present disclosure. Figure 2A As shown, the TFT may include a substrate 1, a buffer layer 2 on the substrate 1, an active layer 4 on the buffer layer 2, a gate insulating layer 5 on the active layer 4; and a gate 6 and a plurality of metal films 7 on the gate insulating layer 5. The plurality of metal films 7 may be spaced apart from the gate 6 and distributed on one side or both sides of the gate 6. The plurality of metal films 7 may be insulated from the gate 6 and the active layer 4.

[0020] In one embodiment, Figure 2A As shown, the active layer 4 includes a channel active region 4-1 and two conductive active regions 4-2 respectively located on both sides of the channel active region 4-1. The gate 6 is formed above the channel active region 4-1 of the active layer 4, and a plurality of metal films 7 are formed above the conductive active region 4-2 of the active layer 4. In one embodiment, the orthographic projection of the gate 6 on the active layer 4 is substantially the same as the channel active region 4-1 of the active layer 4. "Substantially" here means that the difference between the orthographic projection of the gate 6 on the active layer 4 and the channel active region 4-1 of the active layer 4 is less than 10% of the channel active region 4-1 of the active layer 4. The orthographic projections of the plurality of metal films 7 on the active layer 4 are located in the conductive active region 4-2 of the active layer 4. The gate 6 and the plurality of metal films 7 can be formed directly on the gate insulating layer 5. The gate 6 and the plurality of metal films 7 can be made of the same material. For example, similar to the gate 6, each of the plurality of metal films 7 can include at least one of metal copper, aluminum or molybdenum. The thickness of each of the plurality of metal thin films 7 in a direction perpendicular to the substrate 1 may be in a range of about 300 nm to about 1000 nm, preferably in a range of about 450 nm to 800 nm.

[0021] Figure 2B FIG. 1 shows a schematic top view of a thin film transistor according to an embodiment of the present disclosure. Figure 2BAs shown, the plurality of metal films 7 may include two columns of metal films respectively on both sides of the gate 6. The shape of each of the plurality of metal films 7 is substantially rectangular. For example, the shape of each of the plurality of metal films 7 is substantially rectangular, and the length of the rectangle is in the range of about 4 μm to about 12 μm, for example, about 8 μm, and the width is in the range of about 2 μm to about 10 μm, for example, about 6 μm. The spacing distance between two adjacent metal films in the column direction may be in the range of about 1 μm to about 10 μm, preferably in the range of about 3 μm to about 8 μm, for example, about 5 μm. The surface area of ​​each of the plurality of metal films 7 may be about 8 μm. 2 To about 120μm 2 The range is preferably about 20 μm. 2 To about 100 μm 2 In the range of about 50 μm 2 .

[0022] In one embodiment, the TFT may further include an interlayer dielectric layer 8 covering the gate 6, the plurality of metal films 7, the active layer 4 and the buffer layer 2, and a source electrode 9-1 and a drain electrode 9-2 on the interlayer dielectric layer 8. The source electrode 9-1 and the drain electrode 9-2 are electrically connected to the active layer 4 through a through hole in the interlayer dielectric layer 8. In one embodiment, the orthographic projection of the plurality of metal films 7 on the active layer 4 is located between the orthographic projection of the source electrode 9-1 on the active layer 4 and the orthographic projection of the drain electrode 9-2 on the active layer 4. The plurality of metal films 7 are insulated from the source electrode 9-1 and the drain electrode 9-2.

[0023] According to some embodiments of the present disclosure, since the multiple metal films 7 on at least one side of the gate 6 are usually reflective, the multiple metal films 7 can effectively reflect the light emitted by the OLED and the external light, thereby effectively reducing the irradiation to the TFT backplane. Thereby, the stability of the TFT backplane in operation can be significantly improved. In addition, the multiple metal films can effectively reduce the number of carriers generated by irradiation in the conductive active area of ​​the active layer. In this way, during the conductorization process of the active layer, the diffusion of carriers into the channel active area of ​​the active layer can be significantly reduced. Therefore, the influence of the diffusion of carriers on the channel active area of ​​the active layer during the conductorization process of the active layer is significantly reduced. Therefore, the uniformity of the effective channel length is ensured, and the uniformity of the TFT threshold voltage is significantly improved.

[0024] Figure 3A-3G is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. The method for manufacturing a thin film transistor may include forming a buffer layer 2 on a substrate 1, such as Figure 3AAs shown. The substrate may be a glass substrate. The buffer layer 2 may be formed by a plasma enhanced chemical vapor deposition (PECVD) method to deposit a first insulating film on the substrate. The first insulating film may be made of silicon oxide or silicon nitride. During PECVD deposition, the ratio of N2O to SiH4 may be in the range of about 40:1 to about 80:1, and the thickness of the buffer layer may be in the range of about 200 nm to about 400 nm.

[0025] In one embodiment, the method for manufacturing a thin film transistor may further include forming an active layer 4 on a surface of the buffer layer 2 away from the substrate 1, such as Figure 3B As shown. Forming the active layer 4 may include depositing an oxide semiconductor film on the buffer layer 2 and patterning the oxide semiconductor film to obtain the active layer 4. The oxide semiconductor film may be made of indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), etc. The thickness of the active layer 4 may be in the range of about 30 nm to about 80 nm.

[0026] In one embodiment, the method for manufacturing a thin film transistor may further include forming a gate insulating (GI) layer 5 on a surface of the active layer 4 away from the substrate 1. Figure 3C As shown. The GI layer 5 may be formed by depositing a second insulating film on the surface of the active layer 4 away from the substrate 1 by a PECVD method. The second insulating film may be made of silicon oxide or silicon nitride, etc. During PECVD deposition, the ratio of N2O to SiH4 may be in the range of about 50:1 to about 70:1. The thickness of the GI layer 5 may be in the range of about 80nm to about 300nm.

[0027] In one embodiment, the method for manufacturing a thin film transistor may further include forming a gate 6 and a plurality of metal films 7 on the gate insulating layer 5. The plurality of metal films 7 are spaced apart from each other and distributed on at least one side of the gate 6. In one embodiment, forming the gate 6 and the plurality of metal films 7 may include forming a first metal layer 7' on the gate insulating layer 5, such as Figure 3D As shown. The first metal layer 7' can be formed, for example, by magnetron sputtering technology. Then, as Figure 3E As shown, the first metal layer 7' and the GI layer 5 are patterned to form a gate 6 and a plurality of metal films 7 on the GI layer 5. In one embodiment, patterning the first metal layer 7' to form the gate 6 and the plurality of metal films 7 on at least one side of the gate 6 may include placing a mask on the first metal layer 7', the mask having patterns of the gate and the plurality of metal films; removing the first metal layer and the gate insulating layer exposed by the mask by etching to form the gate 6 and the plurality of metal films 7 on at least one side of the gate. The removal of the first metal layer and the gate insulating layer exposed by the mask may be performed by a dry etching method or a wet etching method.

[0028] Then, in one embodiment, the active layer 4 is subjected to a conductorization process using the gate 6 and the plurality of metal films 7 as masks. Therefore, the portion of the active layer 4 not covered by the gate 6 is conductorized to form a conductive active region 4-2 of the active layer 4. The portion of the active layer 4 covered by the gate 6 is not conductorized under the mask formed by the gate, thereby forming a channel active region 4-1 of the active layer 4. Since the area of ​​each of the plurality of metal films 7 is small, the active layer below the plurality of metal films 7 can also be conductorized. Therefore, the orthographic projections of the plurality of metal films 7 on the active layer are located within the conductive active region 4-2 of the active layer 4. The orthographic projection of the gate 6 on the active layer is substantially the same as the channel active region 4-1 of the active layer. The thickness of the gate 6 can be in the range of about 350 nm to about 800 nm. The thickness of each of the plurality of metal films 7 can also be in the range of about 350 nm to about 800 nm. The plurality of metal films 7 may be insulated from the gate 6 and from the active layer 4 through the GI layer 5. In one embodiment, performing a conductorization process on the active layer includes plasma-treating the active layer 4 using the gate 6 and the plurality of metal films 7 as masks, thereby forming a channel active region 4-1 under the gate 6, and forming conductive active regions 4-2 on both sides of the channel active region 4-1.

[0029] In one embodiment, the method for manufacturing a thin film transistor may further include forming an interlayer dielectric (ILD) layer 8, such as Figure 3F As shown. The ILD layer 8 may cover the gate 6 and the plurality of metal films 7. The ILD layer 8 may be formed by depositing a third insulating film 8' covering the gate 6 and the plurality of metal films 7 by a PECVD method, and patterning the third insulating film 8'. The third insulating film 8' may be made of silicon oxide, silicon nitride, or the like. During PECVD deposition, the ratio of N2O to SiH4 is in the range of about 40:1 to about 80:1. The thickness of the ILD layer 8 is in the range of about 400nm to about 800nm.

[0030] In one embodiment, the method for manufacturing a thin film transistor may further include forming a source electrode 9-1 and a drain electrode 9-2 on the ILD layer 8. Figure 3G As shown. In one embodiment, a second metal film is deposited on the ILD layer 8 by magnetron sputtering technology. Then, the second metal film is patterned to form a source 9-1 and a drain 9-2. The second metal film can be made of metal copper or aluminum, etc. The thickness of the source and the drain can be in the range of about 400nm to about 800nm. In one embodiment, the orthographic projection of the plurality of metal films 7 on the active layer 4 is located between the orthographic projection of the source 9-1 on the active layer 4 and the orthographic projection of the drain 9-2 on the active layer 4. The plurality of metal films 7 are insulated from the source 9-1 and the drain 9-2.

[0031] In one embodiment, before depositing the second metal film, the method for forming a thin film transistor may further include forming at least two through holes in the third insulating film 8' above the conductive active region of the active layer. The source and the drain are connected to the conductive active region of the active layer through the through holes in the ILD layer 8.

[0032] An embodiment of the present disclosure provides a display device. The display device may include a thin film transistor according to an embodiment of the present disclosure. The display device may be a top emission WOLED device.

[0033] The principles and embodiments of the present disclosure are described in the specification. The description of the embodiments of the present disclosure is only used to help understand the method of the present disclosure and its core ideas. At the same time, for those of ordinary skill in the art, the scope of the present disclosure to which the present disclosure relates and the technical embodiments are not limited to the specific combination of these technical features, and other technical embodiments composed of a combination of these technical features or their equivalent features should also be covered without departing from the concept of the present invention. For example, a technical embodiment can be obtained by replacing the above-mentioned features disclosed in the present disclosure with similar features (but not limited to).

Claims

1. A thin film transistor, comprising: Active layer; a gate insulating layer on the active layer; as well as A gate and a plurality of metal films, wherein the gate and the plurality of metal films are on the gate insulating layer; wherein the plurality of metal films are spaced apart from the gate, and the plurality of metal films are insulated from the gate and the active layer; It also includes: a source and a drain, the orthographic projections of the multiple metal films on the active layer are located between the orthographic projections of the source on the active layer and the orthographic projections of the drain on the active layer, and the multiple metal films are insulated from the source and the drain.

2. The thin film transistor according to claim 1, wherein: The plurality of metal films are spaced apart from each other, the gate is above the channel active region of the active layer, and the plurality of metal films are above the conductive active region of the active layer.

3. The thin film transistor according to claim 2, wherein: An orthographic projection of the gate on the active layer is substantially the same as the channel active region of the active layer.

4. The thin film transistor according to claim 2, wherein: The orthographic projections of the plurality of metal thin films on the active layer are located within the conductive active region of the active layer.

5. The thin film transistor according to claim 1, wherein: The gate electrode and the plurality of metal thin films are made of the same material.

6. The thin film transistor according to claim 1, wherein: The gate and the plurality of metal thin films are formed by a same patterning process.

7. The thin film transistor according to claim 1, wherein: Each of the plurality of metal films is substantially rectangular in shape, and the plurality of metal films include two columns of metal films respectively located at two sides of the gate.

8. The thin film transistor according to claim 1, wherein: Each of the plurality of metal films includes at least one of copper, aluminum or molybdenum.

9. The thin film transistor according to claim 1, wherein: A thickness of each of the plurality of metal thin films is in a range of 300 nm to 1000 nm.

10. The thin film transistor according to claim 1, wherein: The surface area of ​​each of the plurality of metal thin films is 8 μm 2 Up to 120μm 2 within the range.

11. A method for manufacturing a thin film transistor, comprising: An active layer, a gate insulating layer and a first metal layer are sequentially formed on a substrate; as well as patterning the first metal layer to form a gate and a plurality of metal films located on at least one side of the gate, wherein the plurality of metal films are insulated from the gate and the active layer; Also includes: forming an interlayer dielectric layer covering the active layer, the gate and the plurality of metal films; and forming a source electrode and a drain electrode on the interlayer dielectric layer, The orthographic projections of the plurality of metal thin films on the active layer are located between the orthographic projections of the source electrode on the active layer and the orthographic projections of the drain electrode on the active layer, and The plurality of metal films are insulated from the source and the drain.

12. The method for manufacturing a thin film transistor according to claim 11, wherein: The first metal layer is formed on the gate insulating layer by magnetron sputtering technology.

13. The method for manufacturing a thin film transistor according to claim 11, wherein: The patterning of the first metal layer to form a gate and a plurality of metal films located on at least one side of the gate comprises: placing a mask on the first metal layer, the mask having a pattern of a gate and a plurality of metal films; and The first metal layer and the gate insulating layer exposed by the mask are removed by etching to form the gate and a plurality of metal films located on at least one side of the gate.

14. The method for manufacturing a thin film transistor according to claim 13, wherein: Removal of the first metal layer and the gate insulating layer exposed by the mask is performed by a dry etching method or a wet etching method.

15. The method for manufacturing a thin film transistor according to claim 11, further comprising: The active layer is subjected to a conductorization process using the gate electrode and the plurality of metal thin films as masks.

16. The method for manufacturing a thin film transistor according to claim 15, wherein: The conductorization process includes performing plasma treatment on the active layer using the gate and the plurality of metal films as masks, thereby forming a channel active region of the active layer below the gate and forming conductive active regions on both sides of the channel active region.

17. The method for manufacturing a thin film transistor according to claim 11, before forming the source electrode and the drain electrode on the interlayer dielectric layer, further comprising forming two through holes in the interlayer dielectric layer, The source electrode and the drain electrode are electrically connected to the active layer through the two through holes respectively.

18. A display device comprising the thin film transistor according to any one of claims 1 to 10.

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