A chip verification method and device

Abstract

The present application provides a chip verification method and device to solve the problems in the prior art that when verifying whether a chip has a bug, human participation is required, the operation is cumbersome, and the verification efficiency is low. Method 1: Select the corresponding instruction sequence based on a determined random value, and then repeat the steps that meet the conditions; Method 2: After determining a control parameter, select an instruction sequence based on an unused random value and generate an actual instruction use case based on the determined control parameter, and then repeat the steps that meet the conditions. Therefore, in the chip verification process, no human participation is required, the operation is simple, and the verification efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a method and apparatus for chip verification. Background Art

[0002] With the development of large-scale integrated circuits and multi-threaded multi-core processors, the need to verify whether there are problems in chips is increasing. For example, verifying the cache coherence between the central processing unit (CPU) on a system on chip (SOC) and the caches of other devices in the SOC is one aspect of verifying whether there are problems in a chip.

[0003] In the prior art, generally, the "constraint-based random test template" method is used to verify whether there are problems in a chip. This method first defines a test template, which includes an instruction set and instruction constraints. Then, instruction combinations are randomly generated from the instruction set according to the instruction constraints to form an instruction sequence. Instruction test cases are generated based on the instruction sequence and default control parameters. The control parameters are used to control the parameters used by different instructions in the instruction sequence during operation. Thus, after the chip to be verified runs the instruction test cases, different function values of the function points of the chip to be verified are output. The test coverage rate is obtained based on the ratio of the number of output function values to the number of expected function values to be obtained. The verification personnel analyze the test coverage rate. If the test coverage rate does not meet the expectation, the instruction set in the test template is modified according to the analysis result. For example, instructions for testing the functions corresponding to the function values without output in the instruction set are added, thereby increasing the test coverage rate. By running the instruction test cases on the chip to be verified again and again, until the test coverage rate meets the expectation and no defects (bugs) occur during the process of running the instruction test cases, it is proved that the chip to be verified has no problems. If a bug occurs during the process of running the instruction test cases and the test coverage rate meets the expectation, the verification stops, and the technical personnel repair the defects of the chip to be verified according to the bug that appears.

[0004] When using the "constraint-based random test template" verification method to verify whether there are problems in a chip, since verification personnel are required to participate, the operation is relatively cumbersome and the verification efficiency is low. Summary of the Invention

[0005] Embodiments of this application provide a method and apparatus for chip verification, which are used to solve the problem that in the prior art, when verifying whether there are problems in a chip, verification personnel are required to participate, the operation is relatively cumbersome, and the verification efficiency is low.

[0006] In a first aspect, the present application provides a chip verification method, including determining a random value; selecting a corresponding instruction sequence in a test template based on the random value, where the test template includes multiple instructions; repeatedly executing the following steps based on the instruction sequence:

[0007] Traverse an un-traversed control parameter in a preset control parameter set, and generate an actual test instruction case according to the selected instruction sequence and the traversed control parameter;

[0008] When the test coverage rate obtained when the first chip runs the actual test instruction case is greater than a preset value, control the first chip to run the actual test instruction case multiple times. If a defect (bug) appears, end. Otherwise, execute again the step of traversing an un-traversed control parameter in the preset control parameter set.

[0009] In the above method, after a verification device or component for verifying a chip determines a random value, an instruction series is generated based on the random value, and the instruction sequence and different traversed control parameters are respectively combined into different actual test instruction cases. Furthermore, different actual test instruction cases generated based on different control parameters and the same instruction sequence can be used to verify the chip to be verified (i.e., the first chip). And when the test coverage rate obtained when the first chip runs an actual test instruction case is greater than a preset value, the first chip can be controlled to continue running the actual test instruction case multiple times until a bug in the chip to be verified is detected. Therefore, the verification efficiency of the chip can be improved, and no human participation is required throughout the process, and both the verification efficiency and accuracy can be enhanced.

[0010] In a possible design, when determining a random value, a random value can be randomly generated first; based on the random value, a corresponding instruction sequence is selected in the test template, and a simulated test instruction case is generated according to the selected instruction sequence and a default control parameter; when the test coverage rate obtained when the first chip runs the simulated test instruction case is greater than a preset value, the generated random value is used as the random value determined above.

[0011] Since the test coverage rate obtained after the first chip runs the instruction case composed of the instruction sequence and the default control parameter obtained based on the random value is greater than the preset value, it can be determined that the random value is a better random value. Using the better random value as the random number for generating actual test instruction cases subsequently can further improve the test accuracy.

[0012] In a possible design, selecting corresponding instructions in the test template based on the random value to obtain an instruction sequence includes: calculating multiple instruction index values based on the random value, and selecting a corresponding instruction sequence in the test template based on the calculated multiple instruction index values.

[0013] In the above method, a way to obtain an instruction sequence based on a random value is given. Since the instruction sequence is selected based on the instruction index values calculated from the random value, the method of selecting instructions is simpler and easier to operate.

[0014] In a possible design, if an un-traversed control parameter cannot be found in the control parameter set, it is possible to return to execute the step of determining other random values, then continue to determine the instruction sequence based on the determined other random values, and combine the instruction sequences determined based on the other random values with different control parameters to generate different actual test instruction cases, and continue to test the first chip until a bug is detected.

[0015] In the above method, during the process of chip verification, if no control parameter can be traversed, the step of determining other random values is returned to execute, so as to enter the next new test loop, enabling the verification process to automatically run in a loop.

[0016] In a possible design, it is also possible to continue to control the first chip to run the simulation test instruction case M times after the test coverage rate obtained when the first chip runs the simulation test instruction case is greater than the preset value, and obtain M test coverage rates respectively; when it is determined that at least N test coverage rates among the M test coverage rates are greater than the preset value, then determine the generated random value as a determined random value, where both M and N are positive integers, and M >= N.

[0017] This can ensure that the determined random value is more optimized, providing a good basis for generating actual test instruction cases with better test effects subsequently.

[0018] In a possible design, if a bug occurs in the first chip during the test process, it is also possible to store the determined random value in a random number set, and the random number set can be used to provide random values when verifying the second chip.

[0019] Since a bug occurs in the verification chip, it proves that the selected random value is relatively optimized. Therefore, storing the selected random value in the random number set can enable continuous learning and accumulation of relatively excellent random values in the random number set, so that when verifying other chips (such as the second chip), excellent random values can be preferentially provided to reduce the time for finding and determining random values when verifying the second chip, and further improve the verification efficiency.

[0020] In a possible design, the default control parameter may be one of the preset control parameter sets. Of course, it may also not be one of the preset control parameter sets, and the default control parameter can be selected according to needs.

[0021] In a possible design, the test coverage rate can be determined by at least one of the following methods, but is not limited thereto:

[0022] Use the MRS (Move to Register from System register) instruction to read the Performance Monitoring Unit (PMU) register from the system status register to obtain the test coverage rate, which is used as the test coverage rate of the first chip when running the actual test instruction case; or

[0023] Use the MRS instruction to read the special register to obtain the test coverage rate, which is used as the test coverage rate of the first chip when running the actual test instruction case; or

[0024] Use the load instruction to read the memory of the first chip to obtain the test coverage rate, which is used as the test coverage rate of the first chip when running the actual test instruction case.

[0025] In a second aspect, the present application provides another chip verification method, including determining a control parameter; selecting a corresponding instruction sequence in a test template based on an unused random value, where the test template includes multiple instructions; generating an actual test instruction case according to the selected instruction sequence and the control parameter; when the test coverage rate obtained when the first chip runs the actual test instruction case is greater than a preset value, controlling the first chip to run the actual test instruction case multiple times. If a defect (bug) occurs, end the process. Otherwise, execute again the step of selecting a corresponding instruction sequence based on other unused random values.

[0026] In the above method, after a verification device or component for verifying a chip determines a control parameter, different actual test instruction cases are obtained respectively based on instruction series combinations generated by the control parameter and different random values. Furthermore, different actual test instruction cases generated based on the same control parameter and different random values can be used to verify the chip to be verified (i.e., the first chip). And when the test coverage rate obtained when the first chip runs an actual test instruction case is greater than the preset value, the first chip can be continuously controlled to run the actual test instruction case multiple times until a bug in the chip to be verified is detected. Therefore, cyclic verification can be performed during chip verification without human participation, thereby improving verification efficiency and verification accuracy.

[0027] In a possible design, when determining a control parameter, a control parameter can be randomly selected first; a corresponding instruction sequence is selected in the test template using the corresponding random value, and a simulated test instruction case is generated based on the instruction sequence and the control parameter; when the test coverage rate obtained when the first chip runs the simulated test instruction case is greater than a preset value, the selected control parameter is used as a determined control parameter.

[0028] Since the test coverage rate obtained after the first chip runs the instruction case generated based on the instruction sequence and the control parameter obtained from the corresponding random value is greater than the preset value, it can be determined that the control parameter is a better control parameter. Using the better random value as the control parameter for generating the actual test instruction case subsequently can further improve the test accuracy.

[0029] In a possible design, the selecting the corresponding instruction sequence in the test template based on an unused random value includes: calculating a plurality of instruction index values based on an unused random value, and selecting the corresponding instruction sequence in the test template based on the calculated plurality of instruction index values.

[0030] In the above method, it is given how to obtain the instruction sequence based on the random value. Since the corresponding instruction sequence is selected based on the instruction index value calculated from the random value, the method of selecting instructions is simpler and easier to operate.

[0031] In a possible design, after the test coverage rate obtained when the first chip runs the simulated test instruction case is greater than the preset value, the first chip can be further controlled to run the simulated test instruction case M times, and M test coverage rates are obtained respectively; when it is determined that at least N test coverage rates among the M test coverage rates are greater than the preset value, it is further determined that the selected control parameter is a determined control parameter, where both M and N are positive integers and M >= N.

[0032] This can ensure that the determined control parameter is more excellent and provide a good basis for generating actual test instruction cases with better test effects subsequently.

[0033] In a possible design, if a bug occurs in the first chip during the test, the determined control parameter can also be stored in a control parameter set, and the control parameter set can be used to provide a control parameter when verifying the second chip.

[0034] In this way, since a bug appears in the verification chip, it proves that the selected control parameters are relatively optimized. Therefore, storing the determined control parameters into the control parameter set can enable continuous learning and accumulation of relatively excellent control parameters in the control parameter set, so that when verifying other chips (such as the second chip), relatively excellent control parameters can be provided preferentially, thereby reducing the time for finding and determining the control parameters when verifying the second chip and further improving the verification efficiency.

[0035] In one possible design, the test coverage rate can be determined by at least one of the following methods, but is not limited thereto:

[0036] Using the MRS (Move to Register from System register) instruction to read the Performance Monitoring Unit (PMU) register from the system status register to obtain the test coverage rate, which is used as the test coverage rate of the first chip when running the actual test instruction case; or

[0037] Using the MRS instruction to read a special register to obtain the test coverage rate, which is used as the test coverage rate of the first chip when running the actual test instruction case; or

[0038] Using the load instruction to read the memory of the first chip to obtain the test coverage rate, which is used as the test coverage rate of the first chip when running the actual test instruction case.

[0039] In a third aspect, the present application further provides a device, which has the functions involved in the above first aspect or second aspect. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0040] In a possible design, the structure of the device may include a processing unit and a storage unit, and may also include a communication unit, etc. These units can execute the corresponding parts in the examples of the above first aspect or second aspect. For example, the structure of the device may include a processor and a memory, the processor and the memory are coupled, and the memory stores necessary program instructions and data. The memory is used to store computer programs; the processor is configured to execute the computer programs stored in the memory to complete the corresponding functions in the above first aspect or second aspect.

[0041] In a fourth aspect, the present application further provides a computer storage medium, in which computer executable instructions are stored. When the computer executable instructions are called by the computer, they are used to make the computer execute the methods mentioned in any possible design in the above first aspect, or execute the methods mentioned in any possible design in the above second aspect.

[0042] Fifth aspect, the present application further provides a computer program product containing instructions, which, when running on a device, causes the device to execute the method mentioned in any possible design of the first aspect above, or causes the device to execute the method mentioned in any possible design of the second aspect above.

[0043] Sixth aspect, the present application further provides a device, which may be a chip. The chip is connected to a memory and is used to read and execute program instructions stored in the memory to implement the method mentioned in any possible design of the first aspect above, or to implement the method mentioned in any possible design of the second aspect above. Description of the Drawings

[0044] Figure 1 Schematic diagram of an existing verification framework for verifying a chip;

[0045] Figure 2 Schematic diagram of a verification framework for verifying a chip provided by an embodiment of the present application;

[0046] Figure 3 Specific flowchart of a method for verifying a chip provided by an embodiment of the present application;

[0047] Figure 4 Schematic diagram of a process for selecting a corresponding instruction sequence according to a random value provided by an embodiment of the present application;

[0048] Figure 5 Complete flowchart of a method for chip verification provided by an embodiment of the present application;

[0049] Figure 6 Specific flowchart of another method for verifying a chip provided by an embodiment of the present application;

[0050] Figure 7 Complete flowchart of another method for chip verification provided by an embodiment of the present application;

[0051] Figure 8 Schematic diagram of the first device structure provided by an embodiment of the present application;

[0052] Figure 9 Schematic diagram of the second device structure provided by an embodiment of the present application. Detailed Description of the Embodiment

[0053] Next, the embodiments of the present application will be further described in detail in conjunction with the drawings.

[0054] The embodiments of the present application provide a method and a device for chip verification, which are used to solve the problems in the prior art that when verifying whether there are bugs in a chip, personnel are required to participate, the operation is cumbersome, and the verification efficiency is low. Among them, the method and the device are based on the same inventive concept. Since the principles of the method and the device for solving problems are similar, the implementation of the device and the method can be referred to each other, and the repeated parts will not be described again.

[0055] When developing a new chip, R & D personnel need to verify each function of the chip. Only after successful verification can the chip be put on the market. When verifying the functions of the chip, one of the most critical issues is to verify whether there are bugs in the chip. If there are bugs, the verification personnel need to analyze the bugs, find out the reasons for the bugs, and continue to verify the chip after solving the reasons for the bugs. The verification of the chip can be used to verify whether there are bugs in aspects such as "memory consistency", CPU interrupts, exceptions, page tables and virtualization, branch prediction, instruction fetching, decoding, micro-operation decomposition, distribution, emission, write-back, instruction submission, and rollback of the chip, or it can also be used to verify all SOC systems including the CPU.

[0056] Before introducing the embodiments of the present application, several key concepts related to the embodiments of the present application are first defined and described to facilitate a better understanding of the implementation process of the embodiments of the present application.

[0057] 1) Random value: A value randomly generated by using some random algorithms, which can be a 64-bit hexadecimal number. Based on this hexadecimal number, a set of digital sequences can be calculated using a preset algorithm, and this digital sequence can be used as an instruction index value sequence; the random algorithm refers to using a random function, and the return value of the random function directly or indirectly affects the execution process or execution result of the algorithm.

[0058] 2) Test template: It refers to a test instruction library pre-generated by testers based on experience, which is used to store an instruction set and instruction constraints. The instruction set contains at least one instruction, including various different instructions pre-written by testers for different chips. Different instructions can form an instruction sequence, and an instruction sequence can form a test instruction case with different control parameters for testing the chip to be verified; the instruction constraints include the constraints for selecting instructions, that is, the function for calculating the instruction index value.

[0059] 3) Control parameter: It is used to control the parameters used by different instructions in the instruction sequence during operation. In order to be able to test different test points of different chips to be verified, different test parameters can be set for the chip to be verified to achieve the purpose of testing all different test points.

[0060] 4) Test instruction cases are executable programs generated that can directly act on the chip to be verified. Usually, when the chip to be verified runs this executable program, if there are problems, bugs are usually triggered. A test instruction case consists of an instruction sequence and control parameters. The process of the chip to be verified running the test instruction case is to access the corresponding address in the chip to be verified with the instructions in the instruction case to obtain the corresponding data in the chip, and this address is indicated by the control parameters in the instruction sequence.

[0061] 5) Test coverage refers to the ratio of the number of different function values tested after the chip to be verified runs the test instruction cases to the number of function values expected to be obtained.

[0062] 6) Instruction index value is an index value calculated using a preset algorithm based on a random value. Based on different instruction index values, corresponding instructions can be indexed in the test template.

[0063] 7) "Multiple" means two or more.

[0064] 8) In the description of this application, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0065] Currently, for the verification of chips, it is usually based on Figure 1 the shown verification framework diagram for verification processing, as Figure 1As shown in the figure, the schematic diagram of the existing verification framework includes a random instruction generator, which in turn includes a random number generator, a test template, and an instruction generation module. Among them, the test template includes an instruction set and instruction constraints. The instruction set is predefined and contains multiple instructions. The instruction constraints store some constraint conditions for generating instruction index values. The instruction generation module is used to index instructions from the instruction set according to the instruction index values generated by the instruction constraints, and finally obtain an instruction sequence. When verifying whether a chip to be verified has problems, the random number generator is used to randomly generate a random number, which can also be called a "seed" here. The "seed" can be a 64-bit hexadecimal value. The random number generator will generate multiple instruction index values according to the "seed" and the constraint conditions in the instruction constraints. Then, the instruction generation module selects corresponding multiple instructions from the instruction set according to the multiple instruction index values to form an instruction sequence, combines the instruction sequence with the default control parameters into an instruction test case, and outputs it to the target chip (i.e., the chip to be verified). The chip to be verified runs the instruction test case, and then uses functions such as "assertion" or "test coverage" of the EDA (Electronic Design Automation) tool to collect the test coverage when the target chip runs the instruction test case. Then, the "coverage analysis tool" stores the collected test coverage and other information in a folder. Subsequently, the verification personnel can modify or improve the instruction set in the test template according to the test coverage and other information stored in this file. During the process of verifying and running the instruction test case on the target chip, if there is a bug, the verification stops, and the verification personnel can analyze the bug.

[0066] It should be noted that an assertion refers to the inspection of unexpected situations during the execution of an instruction test case. When an unexpected situation occurs, an assertion will appear, that is, an error will be reported and the verification will stop.

[0067] To facilitate the understanding of the method for chip verification in the prior art, the following is an example for illustration.

[0068] For example, there are 10 instructions in the instruction set of the test template, namely Instruction A, Instruction B, Instruction C, Instruction D, Instruction E, Instruction F, Instruction G, Instruction H, Instruction I, and Instruction J. The random number generator randomly selects a "seed" of 123. According to the instruction constraint conditions in the instruction constraint and the "seed" 123, the randomly selected instruction sequence in the test template is Instruction A, Instruction E, and Instruction F. Then, Instruction A, Instruction E, and Instruction F are combined with the default control parameters to form a test instruction case and output to the target chip. After the target chip runs this test instruction sequence, with the help of an eda tool, collect the test coverage rate obtained by the target chip running this test instruction case. If the collected test coverage rate information is 70%, if the target chip needs to verify 10 functions, then 3 functions are not verified. At this time, the verification personnel can modify or improve the test template according to the 3 unverified functions.

[0069] To improve the efficiency of chip verification, in the solution of this embodiment, the Figure 1 framework can be modified to avoid excessive reliance on the manual modification and improvement of verification personnel, thereby aiming to improve verification efficiency and verification accuracy.

[0070] The verification framework diagram implemented in the embodiments of this application can be as Figure 2 shown, including an adaptive instruction generator, which includes an adaptive expert system controller, a random number generator, an instruction generation module, and a performance monitoring unit counter. Among them, the adaptive expert system controller includes a test template and a control parameter template. The test template includes an instruction set and instruction constraints. The control parameter template includes a control parameter set. The control parameters in the control parameter set are used to control the parameters used by different instructions in the instruction sequence during operation. The specific implementation can be to generate the addresses that the instructions need to access on the chip to be verified according to the control parameters; the random number generator can randomly generate a "seed", and the instruction constraint conditions in the instruction constraint and the "seed" can generate multiple instruction index values. The instruction generation module indexes multiple instructions in the instruction set according to the multiple instruction index values to generate an instruction sequence; the performance monitoring unit counter can automatically count whether the test coverage rate reaches a preset value when the chip to be verified runs the instruction sequence. If it can reach the preset value, trigger the performance monitoring unit counter to increment by 1.

[0071] Based on Figure 2 the verification framework shown, the embodiments of this application provide a method for chip verification, which is applicable to Figure 2 the adaptive instruction generator shown. Referring to Figure 3 shown, the specific process of a method for verifying a chip provided by the embodiments of this application includes:

[0072] Step 300, determine a random number.

[0073] In an alternative embodiment, a random number generator in the adaptive instruction generator randomly generates a random number. Based on this random number, a corresponding instruction sequence is selected from the test templates in the adaptive instruction generator. After generating a simulated test instruction case according to this instruction sequence and the default control parameters, the chip to be verified runs this simulated test instruction case. When the chip to be verified finishes running this simulated test instruction case, it is determined whether the test coverage obtained when the chip to be verified runs this simulated test instruction case is greater than a preset value. If it is greater than the preset value, this random number is used as the random number determined in step 300.

[0074] Exemplarily, the default control parameter can be a control parameter in a preset control parameter set. Specifically, the adaptive expert system controller can read the default control parameter in the chip to be verified according to the storage address of the default control parameter.

[0075] The test coverage after the chip to be verified runs this simulated test instruction case can be obtained by at least one of the following three methods:

[0076] Method 1: Use the MRS (move to general purpose register from system register) instruction in the adaptive expert system controller to read the PMU (performance monitors unit) register to obtain the test coverage;

[0077] Method 2: Use the MRS instruction in the adaptive expert system controller to read a special register to obtain the test coverage;

[0078] Method 3: Use the load instruction in the adaptive expert system controller to read the memory of the chip to be verified to obtain the test coverage.

[0079] It should be noted that when obtaining the test coverage by using the MRS instruction to read the PMU register, the test coverage information obtained by the chip under verification running the simulation test instruction case will be stored in the PMU register; when obtaining the test coverage by using the MRS instruction to read the special register, the test coverage information obtained by the chip under verification running the simulation test instruction case will be stored in the special register. Since each special register has a clear function, the test coverage can be obtained by using the MRS to read the special register with the function of storing the test coverage; when obtaining the test coverage by using the load instruction to read the memory of the chip under verification, the test coverage information obtained by the chip under verification running the simulation test instruction case will be stored in the memory of the chip under verification. When using this method to obtain the test coverage, there is no need to add new PMU registers and special registers, which can save resources.

[0080] In an alternative embodiment, to select the corresponding instruction sequence from the test template based on a random value, multiple instruction index values can be calculated first based on the random value, and then the corresponding instruction sequence can be selected from the test template of the adaptive instruction generator based on the calculated multiple instruction index values.

[0081] To facilitate the understanding of selecting the corresponding instruction sequence according to the random value, an example is given below.

[0082] As Figure 4 shown, it is a schematic diagram of the process of selecting the corresponding instruction sequence according to the random value provided by the embodiment of the present application. Figure 4 In it, X is the selected random value, and X can be a 64-bit hexadecimal number. Based on the preset first function Y = f1(X), a series of digital sequences (Y1, Y2, Y3... Yn) are calculated respectively. When calculating Y1 based on X, X is used as the initial input value of the function Y = f1(X). In the subsequent calculations of Y2, Y3... Yn, the previous calculation result value is used as the input value of the function Y = f1(X) each time. Then, the digital sequence (Y1, Y2, Y3... Yn) is used as the instruction index value sequence, and based on the preset second function Z = f2(Y), the instruction Z that each instruction index value Y can index in the test template is calculated respectively. Therefore, the instruction sequence (Z1, Z2, Z3... Zn) can be indexed in the test template according to the instruction index value sequence (Y1, Y2, Y3... Yn).

[0083] It should be noted here that a set of digital sequences is calculated based on the random number using a preset algorithm. The preset algorithm Y = f1(X) here can be obtained according to the instruction constraints.

[0084] In an alternative embodiment, after the performance monitoring unit counter obtains that the test coverage rate obtained when the chip under verification runs the simulation test instruction case is greater than a preset value, the adaptive instruction generator can control the chip under verification to continue running the simulation test instruction case M times. After determining that N out of the M obtained test coverage rates are all greater than the preset value, finally, the generated random value is used as the random value determined in step 300 above, where M is greater than or equal to N. In this way, it can be ensured that the selected random value is more excellent and can be defined as an excellent random value or an excellent "seed".

[0085] For example, the preset value is 80%, M is 5, and N is 3. After obtaining that the test coverage rate obtained when the chip under verification runs a simulation test instruction case is 90%, the chip under verification can be controlled to continue running the simulation test instruction case 5 times. The 5 obtained test coverage rates are 85%, 88%, 90%, 91%, and 79%. Since 4 out of the 5 obtained test coverage rates are greater than the preset value of 80%, the random value of the instruction sequence that generates the simulation test instruction case can be used as an excellent random value, that is, an excellent "seed". The excellent "seed" can then be used as the real "seed" when generating the actual test instruction case.

[0086] Step 301: The adaptive expert system controller selects the corresponding instruction sequence in the test template based on the random value. The test template includes multiple instructions.

[0087] After determining the random value, the corresponding instruction sequence is selected in the test template based on the random value. Here, the process of selecting the corresponding instruction sequence in the test template based on the random value is the same as the process of selecting the corresponding instruction sequence from the test template based on the random value when determining a random value, and will not be repeated here.

[0088] Step 302: The adaptive expert system controller repeatedly executes the following steps based on the selected instruction sequence:

[0089] Traverse an un-traversed control parameter in the preset control parameter set, and generate an actual test instruction case according to the selected instruction sequence and the traversed control parameter; when the test coverage rate obtained when the chip under verification runs the actual test instruction case is greater than the preset value, control the chip under verification to run the instruction case multiple times. If a bug appears, end; otherwise, execute the step of traversing an un-traversed control parameter in the preset control parameter set again.

[0090] The different control parameters in the preset control parameter set can be preset according to the different functions of the chip to be verified. For example, for the chip A to be verified, some control parameters of the chip A to be verified can be preset. When verifying the chip A to be verified, some control parameters preset for the chip A to be verified are stored in the preset control parameter set; for the chip B to be verified, some control parameters of the chip B to be verified are preset. When verifying the chip B to be verified, some control parameters preset for the chip B to be verified are stored in the preset control parameter set.

[0091] Traverse an un-traversed control parameter in the preset control parameter set, that is, when generating an actual test instruction case according to the selected instruction sequence and control parameter each time, the control parameter is an unused control parameter in the preset control parameter set before generating the actual test instruction case this time. This is to prevent the chip to be verified from repeatedly running some identical instruction cases and avoid wasting time.

[0092] After generating an actual test instruction case, let the chip to be verified run the actual test instruction case, and obtain the test coverage rate obtained after the chip to be verified runs the actual test instruction case. Here, obtaining the test coverage rate obtained after the chip to be verified runs the instruction case is the same as the method of obtaining the test coverage rate after the chip to be verified runs the simulation test instruction case above, and will not be repeated here.

[0093] In a possible implementation manner, when the chip to be verified runs the actual test instruction case, if a bug occurs, the random value of the instruction sequence that generates the actual test instruction case can be stored in a random number set. The random numbers in the random number set can be used to provide excellent random values when verifying other target chips, which can better save time for verifying other target chips.

[0094] In an alternative implementation manner, if no un-traversed control parameter can be traversed in the preset control parameter set, the step of determining other random values can be returned and executed, and then steps 301 and 302 are repeatedly executed until a bug occurs in the chip to be verified.

[0095] The method for verifying a chip provided above first determines a random value, then selects a corresponding instruction sequence based on the random value, and then traverses the control parameters. An actual test instruction case is generated according to the instruction series and the traversed control parameters. When the test coverage rate obtained by the chip to be verified running the actual test instruction case is greater than the preset value, the chip to be verified is controlled to run the actual test instruction case multiple times. If a bug appears, the verification stops. If no bug appears, the control parameters are continuously traversed, and the chip to be verified is loop-verified through some preset conditions, so that no personnel participation is required, the operation is simple, and the verification efficiency can be improved.

[0096] Based on the above Figure 3 shown embodiment, the embodiment of the present application also provides a complete method flow chart for chip verification. Refer to Figure 5 shown, the flow chart of this example may specifically include:

[0097] Step 500, the random number generator randomly selects a random number X, and uses a preset algorithm to calculate a set of digital sequences based on the random number X. This set of digital sequences can be used as an instruction index value sequence, and then the corresponding instructions are sequentially selected from the test template using this instruction index value sequence to form an instruction sequence;

[0098] Step 501, the adaptive expert system controller combines the obtained instruction sequence (Z1, Z2, Z3... Zn) with the default control parameters to generate a simulated test instruction case. Specifically, the default control parameters can be read according to the storage address of the default control parameters, and then the default control parameters and the obtained instruction sequence (Z1, Z2, Z3... Zn) are combined to generate this simulated test instruction case, and then the target chip is made to run this simulated test instruction case;

[0099] Step 502, the performance monitoring unit counter obtains the test coverage rate output after the target chip runs this simulated test instruction case;

[0100] Step 503, the performance monitoring unit counter determines whether the test coverage rate output after the target chip runs this simulated test instruction case is greater than the preset value. If so, execute Step 504. Otherwise, return to Step 500, and the adaptive expert system controller triggers the random instruction generator to randomly select other X values and then continue to execute Steps 500 to 502; it should be noted here that the random number X selected when returning to Step 500 again is an X that has not been selected before. For example, after the first execution of Steps 500 to 502 based on the selected X1, if returning to Step 500 again, X2 will be selected, and Steps 500 to 502 will be executed again based on X2.

[0101] To determine whether a simulation test instruction case is a good one for target chip verification, one of the criteria is whether the test coverage obtained when the target chip runs this simulation test instruction case reaches a preset value. If it can reach the preset value, it can be shown that this simulation test instruction case is a relatively good one. For example, if the test coverage obtained after the target chip runs a simulation test instruction case is 10%, that is to say, this simulation test instruction case only verifies 10% of the functions that need to be verified when verifying the target chip. If an instruction sequence is generated using the random values in the simulation test instruction case with a test coverage of 10%, and then this instruction sequence and the actual test instruction case generated by the traversed control parameters are used to verify whether there are bugs in the chip, the verification efficiency is low. Therefore, it is necessary to first determine that this simulation test instruction case is a relatively good one.

[0102] Step 504, the adaptive expert system controller continues to control the target chip to run this simulation test instruction case M times, and the performance monitoring unit counter obtains M test coverage results respectively output by the M runs.

[0103] Step 505, if there are N test coverage results among the M test coverage results that are all greater than the preset value, then execute Step 506; otherwise, return to Step 500, and the adaptive expert system controller triggers the random instruction generator to randomly select other X values and then continue to execute Steps 500 to 502; it should be noted here that the random number X selected when returning to Step 500 again is an X that has not been selected before. For example, after executing Steps 500 to 502 based on the selected X1 for the first time, if returning to Step 500 again, then X2 will be selected, and Steps 500 to 502 will be executed again based on X2.

[0104] Among them, M >= N. For example, M can be 5 and N can be 3.

[0105] It should be noted here that in Step 503, the adaptive expert system controller determines whether this simulation test instruction case is a relatively good one according to the status of the performance monitoring unit counter. If the performance monitoring unit counter increments by 1, it can be determined that this simulation test instruction case is a relatively good one. Since the target chip has only run this simulation test instruction case once, in order to further determine that this simulation test instruction case is indeed a relatively good one, the target chip is continued to be controlled to run this simulation test instruction case M times. If there are N results among the M test coverage results obtained that are greater than the preset value, then it is determined that this simulation test instruction case is a good one.

[0106] Step 506, the adaptive expert system controller triggers the random instruction generator to re - execute the operations in Step 500 according to the random number X, indexes the instruction sequence (Z1, Z2, Z3…Zn) in the test template, and determines whether an un - traversed control parameter can be traversed in the control parameter set. Specifically, it can be to determine whether an un - traversed storage address can be traversed in the address set corresponding to each control parameter. If so, execute Step 507; otherwise, return to Step 500, where the adaptive expert system controller triggers the random instruction generator to randomly select other X values and then continue to execute Steps 500 to 502. It should be noted here that the random number X selected when returning to Step 500 again is an X that has not been selected before. For example, after the first execution of Steps 500 to 502 based on the selected X1, if returning to Step 500 again, X2 will be selected, and Steps 500 to 502 will be executed again based on X2.

[0107] Step 507, the adaptive expert system controller generates an actual test instruction case based on the instruction sequence (Z1, Z2, Z3…Zn) and the traversed control parameter.

[0108] Step 508, after the adaptive expert system controller controls the target chip to run this actual test instruction case, the performance monitoring unit counter obtains the test coverage rate output by the target chip when running this actual test instruction case.

[0109] Step 509, the performance monitoring unit counter determines whether the test coverage rate output by the target chip when running this actual test instruction case is greater than the preset value. If so, execute Step 510; otherwise, return and continue to execute Step 506.

[0110] Step 510, the adaptive expert system controller continues to control the target chip to run this actual test instruction case K times.

[0111] Step 511, the adaptive expert system controller determines whether a bug occurs during the process of the target chip running this actual test instruction case K times. If so, the test ends; otherwise, return and continue to execute Step 506.

[0112] After the above - mentioned Step 504 is executed, if among the M test coverage rate results, N test coverage rate results are all greater than the preset value, then the selected random value X can be stored, or the storage address corresponding to the selected random value X can be stored. In this way, when testing other chips subsequently, these excellent random values stored can be preferentially selected, or excellent random values can be obtained according to the storage addresses of the preferential random values stored, thereby reducing the time spent in finding excellent random values and improving the efficiency of finding excellent random values.

[0113] Based onFigure 2 For the verification framework shown, an embodiment of the present application further provides a method for chip verification, which is applicable to Figure 2 the adaptive instruction generator shown. Refer to Figure 6 shown, the specific process of another method for verifying a chip provided by an embodiment of the present application includes:

[0114] Step 600: Determine a control parameter.

[0115] In an alternative embodiment, first, the adaptive expert system controller randomly selects a control parameter, uses the corresponding random value to select a corresponding instruction sequence in the test template, and generates a simulated test instruction case based on the instruction sequence and the control parameter; when the test coverage rate obtained when the performance monitoring unit counter obtains the chip to be verified running the simulated test instruction case is greater than the preset value, the selected control parameter is used as the control parameter determined in step 600.

[0116] Exemplarily, a randomly selected control parameter can be selected from a pre-set set of control parameters. For different chips to be verified, the control parameters in the pre-set set of control parameters may be different.

[0117] In an alternative embodiment, to select a corresponding instruction sequence from the test template using the corresponding random value, multiple instruction index values can be calculated based on an unused random value, and then the corresponding instruction sequence is selected in the test template of the adaptive instruction generator based on the calculated multiple instruction index values.

[0118] The corresponding random value here can be a randomly generated random value that has not been used before.

[0119] The method for obtaining the test coverage rate after the chip to be verified runs the simulated test instruction case here is the same as the method for obtaining the test coverage rate after the chip to be verified runs the simulated test instruction case in Figure 3 , and will not be repeated here.

[0120] In an alternative embodiment, after the performance monitoring unit counter obtains that the test coverage rate obtained when the chip to be verified runs the simulated test instruction case is greater than the preset value, the adaptive instruction generator can control the chip to be verified to run the simulated test instruction case M times. After determining that there are N test coverage rates greater than the preset value among the obtained M test coverage rates, finally, the control parameter in the simulated test instruction case is used as the control parameter determined in step 600 above, where M is greater than or equal to N. In this way, it can be ensured that the selected control parameter is more excellent and can be defined as an excellent control parameter.

[0121] Step 601: Select a corresponding instruction sequence in the test template based on an unused random value, where the test template includes multiple instructions.

[0122] In an alternative embodiment, calculate multiple instruction index values based on an unused random value, and select a corresponding instruction sequence in the test template based on the calculated multiple instruction index values.

[0123] Step 602: Generate an actual test instruction case according to the selected instruction sequence and the control parameter.

[0124] The purpose of generating the actual test instruction case here is to let the target chip run the actual test instruction case to obtain the test coverage rate. Similarly, the method of obtaining the test coverage rate is the same as that in Figure 3 the method of obtaining the test coverage rate after the chip under verification runs the simulated test instruction case, and will not be repeated here.

[0125] Step 603: When the test coverage rate obtained by the performance monitoring unit counter when the target chip runs the actual test instruction case is greater than the preset value, the adaptive expert system controller controls the target chip to run the actual test instruction case multiple times. If a bug occurs, it ends; otherwise, it repeats the step of selecting a corresponding instruction sequence based on other unused random values.

[0126] In a possible embodiment, when a bug occurs when the chip under verification runs the actual test instruction case, the control parameter for generating the actual test instruction case can be marked in the preset control parameter set. The control parameters marked in the preset control parameter set can be used to provide excellent control parameters when verifying other target chips, which can save time better for verifying other target chips.

[0127] Another method for verifying a chip provided above first determines a control parameter, then generates an actual test instruction case based on an unused random value and the control parameter, and after obtaining that the test coverage rate obtained by the chip under verification running the actual test instruction case is greater than the preset value, controls the chip under verification to run the actual test instruction case multiple times. If a bug occurs, the verification stops; if no bug occurs, it continues with the step of selecting a corresponding instruction sequence using other unused random values, and verifies the chip under verification through some preset conditions in a loop, thus eliminating the need for human participation, being easy to operate, and being able to improve the verification efficiency.

[0128] Based on the above Figure 6 shown embodiments, the embodiments of the present application also provide another complete method flowchart for chip verification. Referring to Figure 7 shown, the flowchart of this example may specifically include:

[0129] Step 700: The adaptive expert system controller randomly selects a control parameter P from a preset set of control parameters; specifically, it can randomly select a storage address from the set of storage addresses corresponding to each control parameter, and obtain the control parameter P according to the selected storage address;

[0130] Step 701: The random number generator randomly selects a random number X, and uses a preset algorithm to calculate a set of digital sequences based on the random number X. This set of digital sequences can be used as an instruction index value sequence. Then, the instruction generation module uses this instruction index value sequence to sequentially select corresponding instructions from the test template to form an instruction sequence;

[0131] Step 702: The adaptive expert system controller combines the obtained instruction sequence (Z1, Z2, Z3... Zn) with the control parameter P to generate a simulated test instruction case, and then controls the target chip to run this simulated test instruction case;

[0132] Step 703: The performance monitoring unit counter obtains the test coverage rate output after the target chip runs this simulated test instruction case;

[0133] Step 704: The performance monitoring unit counter determines whether the test coverage rate output after the target chip runs this simulated test instruction case is greater than a preset value. If so, execute Step 705; otherwise, execute Steps 710 - 711 - 702, and use the random number X generated in Step 700 and other randomly selected control parameters P to generate simulated test instruction cases; it should be noted here that the randomly selected control parameter P in Step 711 is a P that has not been selected before. For example, if P1 is selected in Step 701, then P2 will be selected when Step 710 is executed.

[0134] Step 705: The adaptive expert system controller continues to let the target chip run this simulated test instruction case M times, and the performance monitoring unit counter obtains M test coverage rate results respectively output by the M runs.

[0135] Step 706: If N test coverage rate results among the M test coverage rate results are all greater than the preset value, determine the previously randomly selected control parameter P as a good control parameter, fix this control parameter P, and then execute Step 707; otherwise, execute Steps 710 - 711 - 702, and use the random number X generated in Step 700 and other randomly selected control parameters P to generate simulated test instruction cases; it should be noted here that the randomly selected control parameter P in Step 711 is a P that has not been selected before. For example, if P1 is selected in Step 701, then P2 will be selected when Step 710 is executed.

[0136] Among them, M >= N. For example, M can be 5 and N can be 3.

[0137] Step 707: The random number generator re - executes the operation in Step 700, that is, randomly selects other numbers X that have not been selected before. Here, it should be noted that the randomly selected number X when re - executing Step 700 is an X that has not been selected before. For example, if X1 is selected when executing Step 700 for the first time, if Step 700 is executed again, X2 will be selected. Based on X2, a new instruction sequence (Z1, Z2, Z3…Zn)' is re - indexed in the test template, and the re - indexed new instruction sequence is combined with the determined good control parameter P to generate an actual test instruction case. After controlling the target chip to run this actual test instruction case, the test coverage rate is obtained, and it is judged whether the test coverage rate is greater than the preset value. If so, Step 708 is executed; otherwise, return to Step 701, randomly select other random values X and then continue to execute Steps 702 - 706. Here, it should be noted that the other random value X selected when returning to Step 701 again is an X that has not been selected before. For example, if X1 is selected for the first time, if returning to Step 701 again, X2 will be selected.

[0138] Step 708: The adaptive expert system controller continues to control the target chip to run this actual test instruction case K times.

[0139] Step 709: The adaptive expert system controller determines whether a bug occurs during the process of the target chip running this actual test instruction case K times. If so, the test ends; otherwise, return and continue to execute Step 700.

[0140] Step 710: The instruction generation module generates an instruction case using the random number X in Step 701.

[0141] Step 711: The adaptive expert system controller randomly generates an unused control parameter P.

[0142] After the above Step 706 is executed, if there are N test coverage rate results among the M test coverage rate results that are all greater than the preset value, the control parameter P can be marked in the preset control parameter set, or the storage address corresponding to the control parameter P in the address set corresponding to the parameter set can be marked. In this way, when verifying other chips subsequently, the control parameter with the said mark in the preset control parameter set can be preferentially selected, or the storage address with the mark in the address set corresponding to the preset parameter set can be preferentially selected, and the excellent control parameter can be obtained according to the selected storage address, thereby reducing the time spent in finding excellent control parameters and improving the efficiency of finding excellent control parameters.

[0143] The embodiments of the present application provide two methods for verifying a chip. Both methods require setting some preset conditions to verify the chip in a loop, so that no personnel are involved and the verification efficiency is improved.

[0144] Based on the above embodiments, the embodiments of the present application further provide a device for implementing the method for verifying a chip as shown in Figure 3 or Figure 5 . Referring to Figure 8 , the device 800 includes: a processing unit 801 and a storage unit 802. The storage unit 802 is used to store program codes. When the program codes are executed by the processing unit 801, the processing unit 801 can execute the steps 300 to 302 shown in Figure 3 , or execute the steps 500 to 511 shown in Figure 5 , or enable the processing unit 801 to execute the steps 600 to 603 shown in Figure 6 , or execute the steps 700 to 711 shown in Figure 7 .

[0145] Using the device provided by the embodiments of the present application, a random value is determined, and then a corresponding instruction sequence is selected based on the random value. The following steps are repeatedly executed based on the instruction sequence: First, traverse an untraversed control parameter, and then generate an actual test instruction case according to the selected instruction sequence and the traversed control parameter. When the test coverage rate obtained when the chip runs the actual test instruction case is greater than the preset value, the chip is made to run the actual test instruction case multiple times. If a defect bug appears, the process ends; otherwise, the step of traversing an untraversed control parameter in the preset control parameter set is executed again. In this way, when verifying the chip, it can be verified in a loop according to the preset conditions, without the need for personnel to participate, and the operation is simple, thereby improving the verification efficiency.

[0146] Alternatively, using the device provided by the embodiments of the present application, a control parameter is determined, and then corresponding instruction sequences are selected based on different random values. The following steps are repeatedly executed based on each selected instruction sequence: Generate an actual test instruction case with the determined control parameter. When the test coverage rate obtained when the chip runs the actual test instruction case is greater than the preset value, the chip is made to run the actual test instruction case multiple times. If a defect bug appears, the process ends; otherwise, the step of generating an actual test instruction case by combining the instruction sequence determined by using other random values and the control parameter is executed again. In this way, when verifying the chip, it can be verified in a loop according to the preset conditions, without the need for personnel to participate, and the operation is simple, thereby improving the verification efficiency.

[0147] It should be noted that the division of units in the embodiments of this application is illustrative. It is only a logical function division, and there may be other division methods in actual implementation. In the embodiments of this application, each functional unit may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0148] If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0149] Based on the above embodiments, the embodiments of this application also provide a device. Refer to Figure 9 As shown, the device 900 includes: a processor 901. Optionally, it further includes a memory 902. The processor 901 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 901 may further include a hardware chip. The above hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0150] The processor 901 and the memory 902 are interconnected. Optionally, the processor 901 and the memory 902 are interconnected via a bus 903; the bus 903 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity of representation, Figure 9 only a thick line is used to represent it in Figure 9 , but it does not mean that there is only one bus or one type of bus.

[0151] Figure 9 The device shown can be Figure 2 the adaptive instruction generator in Figure 2 , or can also be Figure 2 a control component or a control unit in the adaptive instruction generator in Figure 2 . The above-mentioned Figure 8 The processing unit 801 in Figure 8 can be implemented based on the processor 901 here, and the storage unit 802 can be implemented based on the memory 902 here. For the specific functions and execution principles of the processor 901 and the memory 902, please refer to the detailed description in the above method embodiments, and will not be repeated here.

[0152] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0153] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0154] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to work in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the functions specified in one or more of the processes Figure 1 one or more processes and / or blocks Figure 1 specified in one or more of the blocks.

[0155] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one or more of the processes Figure 1 one or more processes and / or blocks Figure 1 specified in one or more of the blocks.

[0156] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to cover these modifications and variations.

Claims

1. A chip verification method, It is characterized in that include: Determine a random value; Selecting a corresponding instruction sequence in a test template based on the random value, the test template comprising a plurality of instructions; The following steps are repeatedly performed based on the instruction sequence: Traversing a control parameter in a preset control parameter set that has not been traversed, and generating an actual test instruction case according to the selected instruction sequence and the traversed control parameter; When the test coverage obtained when the first chip runs the actual test instruction case is greater than a preset value, the first chip is controlled to run the actual test instruction case multiple times. If a defect bug occurs in the first chip, the test is terminated. Otherwise, the step of traversing a control parameter in the preset control parameter set that has not been traversed is executed again.

2. The method according to claim 1, It is characterized in that Determining a random value includes: Randomly generate a random value; Selecting a corresponding instruction sequence in the test template based on the random value, and generating a simulation test instruction case according to the selected instruction sequence and default control parameters; When the test coverage rate obtained when the first chip runs the simulation test instruction case is greater than a preset value, the generated random value is used as a determined random value.

3. The method according to claim 1 or 2, It is characterized in that The selecting a corresponding instruction sequence in the test template based on the random value includes: A plurality of instruction index values ​​are calculated based on the random value, and a corresponding instruction sequence is selected in the test template based on the plurality of instruction index values ​​obtained by calculation.

4. The method according to claim 1, It is characterized in that After the step of traversing a control parameter in the preset control parameter set that has not been traversed is performed again, the method further includes: If no untraversed control parameter is found in the control parameter set, the process returns to the step of determining other random value.

5. The method according to claim 2, It is characterized in that Before using the generated random value as a determined random value, the following steps are also included: When the test coverage rate obtained when the first chip runs the simulation test instruction case is greater than a preset value, the first chip is controlled to run the simulation test instruction case M times to obtain M test coverage rates respectively; Determine that among the M test coverages, at least N test coverages are greater than a preset value; both M and N are positive integers, and M>=N.

6. The method according to claim 1 or 2, It is characterized in that Also includes: If a bug occurs in the first chip, the determined random value is stored in a random number set, and the random number set is used to provide a random value when verifying the second chip.

7. The method according to claim 2, It is characterized in that The default control parameter is a control parameter in the preset control parameter set.

8. The method according to claim 1, It is characterized in that The test coverage is determined by at least one of the following methods: Use the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage rate as the test coverage rate of the first chip running the actual test instruction case; Use the MRS instruction to read the special register to obtain the test coverage rate as the test coverage rate of the first chip running the actual test instruction case, and the special register has a function of storing the test coverage rate; and The memory of the first chip is read using a load instruction to obtain the test coverage, which is used as the test coverage of the first chip running the actual test instruction case.

9. A chip verification method, It is characterized in that include: Determine a control parameter; Selecting a corresponding instruction sequence in a test template based on an unused random value, the test template comprising a plurality of instructions; Generate an actual test instruction case according to the selected instruction sequence and control parameters; When the test coverage obtained when the first chip runs the actual test instruction case is greater than a preset value, the first chip is controlled to run the actual test instruction case multiple times. If a defect bug occurs in the first chip, the test is terminated. Otherwise, the step of selecting a corresponding instruction sequence in the test template based on an unused random value is executed again.

10. The method according to claim 9, It is characterized in that The determining of a control parameter comprises: Randomly select a control parameter; Select a corresponding instruction sequence in the test template using a corresponding random value, and generate a simulation test instruction case based on the instruction sequence and the control parameter; When the test coverage rate obtained when the first chip runs the simulation test instruction case is greater than a preset value, the selected control parameter is used as a determined control parameter.

11. The method according to claim 9 or 10, It is characterized in that The selecting a corresponding instruction sequence in the test template based on an unused random value includes: A plurality of instruction index values ​​are calculated based on an unused random value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.

12. The method according to claim 10, It is characterized in that Before taking the selected control parameter as a determined control parameter, the method further includes: When the test coverage rate obtained when the first chip runs the simulation test instruction case is greater than a preset value, the first chip is controlled to run the simulation test instruction case M times to obtain M test coverage rates respectively; Determine that among the M test coverages, at least N test coverages are greater than a preset value; both M and N are positive integers, and M>=N.

13. The method according to claim 9 or 10, It is characterized in that Also includes: If a bug occurs in the first chip, the determined control parameters are stored in a control parameter set, and the control parameter set is used to provide control parameters when verifying the second chip.

14. The method of claim 9, It is characterized in that The test coverage is determined by at least one of the following methods: Use the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage rate as the test coverage rate of the first chip running the actual test instruction case; Use the MRS instruction to read the special register to obtain the test coverage rate as the test coverage rate of the first chip running the actual test instruction case, and the special register has a function of storing the test coverage rate; and The memory of the first chip is read using a load instruction to obtain the test coverage, which is used as the test coverage of the first chip running the actual test instruction case.

15. A chip verification device, It is characterized in that include: a processor and a memory, the processor being coupled to the memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory so that the device performs to determine a random value; select a corresponding instruction sequence in a test template based on the random value, wherein the test template includes a plurality of instructions; and repeatedly perform the following steps based on the instruction sequence: traverse a control parameter that has not been traversed in a preset control parameter set, and generate an actual test instruction case according to the selected instruction sequence and the traversed control parameter; When the test coverage obtained when the first chip runs the actual test instruction case is greater than a preset value, the first chip is controlled to run the actual test instruction case multiple times. If a defect bug occurs in the first chip, the test is terminated. Otherwise, the step of traversing a control parameter in the preset control parameter set that has not been traversed is executed again.

16. The device according to claim 15, It is characterized in that When the processor determines a random value, it is specifically used to: Randomly generate a random value; Selecting a corresponding instruction sequence in the test template based on the random value, and generating a simulation test instruction case according to the selected instruction sequence and default control parameters; When the test coverage rate obtained when the first chip runs the simulation test instruction case is greater than a preset value, the generated random value is used as a determined random value.

17. The device according to claim 15 or 16, It is characterized in that When the processor selects a corresponding instruction sequence in a test template based on the random value, it is specifically used to: A plurality of instruction index values ​​are calculated based on the random value, and a corresponding instruction sequence is selected in the test template based on the plurality of instruction index values ​​obtained by calculation.

18. The device according to claim 15, It is characterized in that The processor is further configured to: If no untraversed control parameter is found in the control parameter set, the process returns to the step of determining other random value.

19. The device according to claim 16, It is characterized in that The processor is further configured to: Before using the generated random value as a determined random value, after obtaining a test coverage rate obtained when the first chip runs the simulation test instruction case and the test coverage rate is greater than a preset value, controlling the first chip to run the simulation test instruction case M times to obtain M test coverage rates respectively; Determine that among the M test coverages, at least N test coverages are greater than a preset value; both M and N are positive integers, and M>=N.

20. The device according to claim 15 or 16, It is characterized in that The processor is further configured to: If a bug occurs in the first chip, the determined random value is stored in a random number set, and the random number set is used to provide a random value when verifying the second chip.

21. The device according to claim 15, It is characterized in that The test coverage is determined by at least one of the following methods: The processor uses the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage rate as the test coverage rate of the first chip running the actual test instruction case; The processor uses the MRS instruction to read the special register to obtain the test coverage as the test coverage of the first chip running the actual test instruction case, and the special register has a function of storing the test coverage; and The processor uses the load instruction to read the memory of the first chip to obtain the test coverage as the test coverage of the first chip running the actual test instruction case.

22. A chip verification device, It is characterized in that include: a processor and a memory, the processor being coupled to the memory; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory so as to cause the device to determine a control parameter; Selecting a corresponding instruction sequence in a test template based on an unused random value, the test template comprising a plurality of instructions; generating an actual test instruction case according to the selected instruction sequence and the control parameter; When the test coverage obtained when the first chip runs the actual test instruction case is greater than a preset value, the first chip is controlled to run the actual test instruction case multiple times. If a defect bug occurs in the first chip, the test is terminated. Otherwise, the step of selecting a corresponding instruction sequence in the test template based on an unused random value is executed again.

23. The device according to claim 22, It is characterized in that When the processor determines a control parameter, it is specifically used to: Randomly select a control parameter; Use the corresponding random value to select the corresponding instruction sequence in the test template, and generate a simulation test instruction case based on the instruction sequence and the control parameter; when the test coverage obtained when the first chip runs the simulation test instruction case is greater than the preset value, the selected control parameter is used as a determined control parameter.

24. The device according to claim 22 or 23, It is characterized in that When the processor selects a corresponding instruction sequence in a test template based on an unused random value, it is specifically used to: A plurality of instruction index values ​​are calculated based on an unused random value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.

25. The device according to claim 23, It is characterized in that The processor is further configured to: Before using the selected control parameter as a determined control parameter, after obtaining a test coverage rate obtained when the first chip runs the simulation test instruction case and the test coverage rate is greater than a preset value, controlling the first chip to run the simulation test instruction case M times and obtaining M test coverage rates respectively; Determine that among the M test coverages, at least N test coverages are greater than a preset value; both M and N are positive integers, and M>=N.

26. The device of claim 24, It is characterized in that The processor is further configured to: If a bug occurs in the first chip, the determined control parameters are stored in a control parameter set, and the control parameter set is used to provide control parameters when verifying the second chip.

27. The device of claim 22, It is characterized in that The test coverage is determined by at least one of the following methods: The processor uses the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage rate as the test coverage rate of the first chip running the actual test instruction case; The processor uses the MRS instruction to read the special register to obtain the test coverage as the test coverage of the first chip running the actual test instruction case, and the special register has a function of storing the test coverage; and The processor uses the load instruction to read the memory of the first chip to obtain the test coverage as the test coverage of the first chip running the actual test instruction case.

28. A computer readable storage medium, It is characterized in that The method comprises a program or an instruction. When the program or the instruction is run on a computer, the method according to any one of claims 1 to 14 is executed.

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