Noise and calibration adaptive compilation of quantum programs

Abstract

A method includes performing a calibration operation on a set of qubits in a first iteration to produce a set of parameters, a first subset of the set of parameters corresponding to a first qubit of the set of qubits and a second subset of the set of parameters corresponding to a second qubit of the set of qubits. The method further includes selecting the first qubit in response to the parameters of the first subset meeting an acceptability criterion. The method further includes forming a quantum gate using the first qubit and a third qubit in response to a second parameter of the second subset failing to meet a second acceptability criterion.

Description

Technical Field

[0001] This invention generally relates to methods for quantum computing. More specifically, this invention relates to a method for noise and calibration adaptive compilation of quantum programs. Background Technology

[0002] In the following text, unless explicitly distinguished in use, the “Q” prefix in the word of a phrase indicates that the word or phrase is being used in the context of quantum computing.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, the branch of physics that explores how the physical world works at its most fundamental level. At this level, particles behave in strange ways, simultaneously existing in more than one state and interacting with other particles very far away. Quantum computing utilizes these quantum phenomena to process information.

[0004] The computers we use today are called classic computers (also referred to here as "traditional" computers or traditional nodes, or "CN"). Traditional computers use traditional processors, which are manufactured using semiconductor materials and technologies, semiconductor memory, and magnetic or solid-state storage devices, a process known as the von Neumann architecture. In particular, the processors in traditional computers are binary processors, meaning they operate on binary data represented by 1s and 0s.

[0005] Quantum processors (Q processors) utilize the odd-numbered property of entangled qubit devices (referred to as "qubits" or multiple "qubits" in this paper) to perform computational tasks. In specific domains of quantum mechanics, matter particles can exist in multiple states, such as "on," "off," and simultaneously "on" and "off." Where binary computation using semiconductor processors is limited to using only on and off states (equivalent to 1 and 0 in binary code), quantum processors leverage these quantum states of matter to output signals that can be used for data computation.

[0006] Traditional computers encode information using bits. Each bit can take the value 1 or 0, and these 1s and 0s serve as switches to ultimately drive the computer's functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can simultaneously represent 1 and 0. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one (whether it's 1, 0, or both) can depend on the state of the other, and more information can be determined when two qubits are entangled than when they are processed individually.

[0007] Using these two principles, qubits function as more complex information processors, enabling quantum computers to solve problems that are difficult to solve using conventional computers. IBM has successfully built and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines Corporation in the United States and other countries).

[0008] One type of superconducting qubit includes a Josephson junction. A Josephson junction is formed by separating two thin-film superconducting metal layers using a non-superconducting material. When the metal in the superconducting layer becomes superconducting, for example by lowering the temperature of the metal to a specific cryogenic temperature, electron pairs can tunnel from one superconducting layer through a non-superconducting layer to the other. In a qubit, the Josephson junction—which functions as a dispersive nonlinear inductor—is electrically coupled in parallel to one or more capacitive devices forming a nonlinear microwave oscillator. The oscillator has a resonant / transition frequency determined by the values ​​of the inductance and capacitance in the qubit circuit. Any reference to the term "qubit" is a reference to a superconducting qubit circuit employing a Josephson junction unless explicitly distinguished in use.

[0009] Information processed by qubits is carried or transmitted as microwave signals / photons in the microwave frequency range. These microwave signals are captured, processed, and analyzed to decipher the quantum information encoded within them. A readout circuit is a circuit coupled to the qubit to capture, read, and measure its quantum state. The output of the readout circuit is information that can be used by a Q-processor to perform calculations.

[0010] Superconducting qubits possess two quantum states – |0> and |1>. These two states can be the two energy states of an atom, for example, the ground state (|g>) and the first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of the nucleus or electron spin, the two locations of crystal defects, and the two states of a quantum dot. Due to the quantum properties of the system, any combination of the two states is allowed and valid.

[0011] For quantum computing using qubits to be reliable, quantum circuits, such as the qubit itself, the readout circuitry associated with the qubit, and other parts of the quantum processor, must not alter the energy state of the qubit, for example, by injecting or dissipating energy, in any meaningful way or affecting the relative phase between the |0> and |1> states of the qubit. This operational constraint on any circuit operating with quantum information needs to be carefully considered when fabricating semiconductor and superconducting structures for such circuits.

[0012] The illustrative embodiments recognize that quantum processors exhibit varying physical properties over time. The illustrative embodiments also recognize that the calibration of a quantum processor determines the error rates of its associated qubits and quantum gates. The illustrative embodiments further recognize that quantum processors are typically calibrated only once or twice per day. Summary of the Invention

[0013] Illustrative embodiments provide a method for noise and calibration adaptive compilation of quantum programs. According to one aspect of the invention, a method is provided comprising: performing a calibration operation on a set of qubits in a first iteration to generate a set of parameters, a first subset of the parameter set corresponding to a first qubit of the set of qubits, and a second subset of the parameter set corresponding to a second qubit of the set of qubits.

[0014] The method further includes selecting the first qubit in response to the parameters of the first subset satisfying an acceptability criterion. The method further includes forming a quantum gate using the first qubit and the third qubit in response to the second parameters of the second subset failing to satisfy a second acceptability criterion.

[0015] In one embodiment, the method includes performing the calibration operation on the set of qubits in a second iteration to generate a new set of parameters, a new subset of which corresponds to a first qubit of the set of qubits. In another embodiment, the method includes deselecting the first qubit in response to a new parameter in the new subset failing to meet the acceptability criterion. In yet another embodiment, the method includes forming the quantum gate using a fourth and a fifth qubit.

[0016] In one embodiment, performing the calibration operation includes performing a predetermined operation on the first qubit. In another embodiment, performing the calibration operation includes comparing the output of the predetermined operation with a desired output.

[0017] In one embodiment, selecting the first qubit includes converting a quantum algorithm into a set of quantum gates, each quantum gate in the set being formed by a subset of the qubit set. In another embodiment, selecting the first qubit includes determining that the first quantum gate is formed by at least the first qubit. In yet another embodiment, selecting the first qubit includes comparing parameters of the first subset with the acceptability criterion.

[0018] In this embodiment, the acceptability criterion is a measurement error of up to four percent. In this embodiment, the acceptability criterion is a coherence time of at least 50 microseconds.

[0019] The embodiments include a computer-usable program product. The computer-usable program product includes a computer-readable storage device and program instructions stored on the storage device.

[0020] In one embodiment, computer-usable code is stored in a computer-readable storage device within a data processing system, and the computer-usable code is transmitted over a network from a remote data processing system. In another embodiment, computer-usable code is stored in a computer-readable storage device within a server data processing system, and the computer-usable code is downloaded over a network to a remote data processing system for use in a computer-readable storage device associated with the remote data processing system.

[0021] The embodiments include a computer system. The computer system includes a processor, a computer-readable storage device, a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory. Attached Figure Description

[0022] The appended claims set forth novel features that are considered characteristic of the invention. However, the invention itself, its preferred modes of use, further objects and advantages will be best understood by referring to the following detailed description of illustrative embodiments taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 A block diagram of a network that can implement the illustrative embodiments of the data processing system is depicted;

[0024] Figure 2 A block diagram of a data processing system that can implement illustrative embodiments is depicted;

[0025] Figure 3 An example configuration for noise and calibration adaptive compilation of a quantum program according to an illustrative embodiment is depicted;

[0026] Figure 4 An exemplary configuration for calibrating a quantum processor, according to an illustrative embodiment, is depicted;

[0027] Figure 5 An example configuration of a quantum circuit construction according to an illustrative embodiment is depicted;

[0028] Figure 6 An example configuration of a connectivity diagram of a quantum processor according to an illustrative embodiment is depicted.

[0029] Figure 7 An example configuration of a connectivity diagram of a quantum processor according to an illustrative embodiment is depicted.

[0030] Figure 8 An example configuration of a circuit diagram according to an illustrative embodiment is depicted;

[0031] Figure 9A flowchart depicts an example method for noise and calibration adaptive compilation of quantum programs according to an illustrative embodiment;

[0032] Figure 10 A flowchart depicts an example method for performing a calibration operation on a qubit set according to an illustrative embodiment; and

[0033] Figure 11 A flowchart depicts an example method for selecting qubits according to an illustrative embodiment. Detailed Implementation

[0034] These illustrative embodiments used to describe the invention generally relate to and address the aforementioned need to reduce error rates on qubits and quantum gates in quantum processors. The illustrative embodiments provide a method for noise and calibration adaptive compilation of quantum programs.

[0035] Operations described herein as occurring at one or more frequencies should be interpreted as signal occurrences at one or more frequencies. Unless explicitly distinguished in use, all references to "signal" are references to microwave signals.

[0036] For clarity of description and without implying any limitation thereof, some example configurations are used to describe illustrative embodiments. Based on this disclosure, those skilled in the art will be able to conceive of many variations, adaptations, and modifications to the construction for achieving the described objectives, and these are all considered to be within the scope of the exemplary embodiments.

[0037] Furthermore, simplified diagrams of example resistors, inductors, capacitors, and other circuit components are used in the accompanying drawings and illustrative embodiments. In actual manufacture or circuitry, additional structures or components not shown or described herein, or structures or components that differ from those shown but have similar functions to those described herein, may be present without departing from the scope of the illustrative embodiments.

[0038] These illustrative embodiments are described by way of example only, relating to certain types of materials, electrical properties, steps, quantities, frequencies, circuits, components, and applications. Any particular manifestation of these and other similar human-made elements is not intended to limit the invention. Any suitable manifestation of these and other similar products may be chosen within the scope of the exemplary embodiments.

[0039] The examples in this disclosure are for illustrative purposes only and are not intended to limit the scope of the illustrative embodiments. Any advantages listed herein are merely examples and are not intended to limit the illustrative embodiments. Additional or different advantages may be achieved through specific illustrative embodiments. Furthermore, specific illustrative embodiments may have some, all, or none of the advantages listed above.

[0040] Refer to the attached diagram, and specifically refer to... Figure 1 and 2 These figures are example diagrams of a data processing environment in which illustrative embodiments can be implemented. Figure 1 and 2 This is merely an example and is not intended to assert or imply any limitation regarding the environment in which different embodiments may be implemented. Specific implementations may make many modifications to the depicted environment based on the following description.

[0041] Figure 1 A block diagram of a network in which an illustrative embodiment of a data processing system may be implemented is described. Data processing environment 100 is a computer network in which the illustrative embodiment may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between various devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0042] The client or server are merely example roles of certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles of these data processing systems. Servers 104 and 106 are coupled to network 102 along with storage unit 108. Software applications can execute on any computer in data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as server 104 or 106 or clients 110, 112, or 114 can contain data and can have software applications or software tools executing on them.

[0043] This is merely an example and does not imply any limitations on such an architecture. Figure 1 Certain components that may be used in example implementations of the embodiments are depicted. For example, servers 104 and 106 and clients 110, 112, and 114 are depicted as servers and clients only as examples and not to imply limitations on the client-server architecture. As another example, one embodiment may be distributed across several data processing systems and data networks as shown, while another embodiment may be implemented on a single data processing system within the scope of the illustrative embodiments. Data processing systems 104, 106, 110, 112, and 114 also represent example nodes in clusters, partitions, and other configurations suitable for implementing the embodiments.

[0044] Device 132 is an example of the device described herein. For example, device 132 may take the form of a smartphone, tablet computer, laptop computer, client 110 in fixed or portable form, wearable computing device, or any other suitable device. Figure 1Any software application executing in another data processing system within the device 132 can be configured to execute in a similar manner. Figure 1 Any data or information stored or generated in another data processing system can be configured to be stored or generated in device 132 in a similar manner.

[0045] Servers 104 and 106, storage unit 108, clients 110, 112 and 114, and device 132 can be coupled to network 102 using wired connections, wireless communication protocols, or other suitable data connections. Clients 110, 112, and 114 can be, for example, personal computers or network computers.

[0046] In the described example, server 104 may provide data, such as boot files, operating system images, and applications, to clients 110, 112, and 114. In this example, clients 110, 112, and 114 may be clients of server 104. Clients 110, 112, 114, or some combination thereof, may include their own data, boot files, operating system images, and applications. Data processing environment 100 may include additional servers, clients, and other devices not shown. Server 104 includes application 105, which may be configured to implement one or more functions described herein for design optimization of quantum circuits according to one or more embodiments. Storage device 108 includes one or more databases 109 configured to store quantum circuit design information, such as a set of acceptability criteria.

[0047] In the described example, data processing environment 100 can be the Internet. Network 102 can represent a collection of networks and gateways that communicate with each other using Transmission Control Protocol / Internet Protocol (TCP / IP) and other protocols. At the core of the Internet is the backbone of data communication links between master nodes or host computers, including thousands of commercial, government, educational, and other computer systems that route data and messages. Of course, data processing environment 100 can also be implemented as many different types of networks, such as intranets, local area networks (LANs), or wide area networks (WANs). Figure 1 This is intended as an example, not as an architectural limitation on different illustrative embodiments.

[0048] Among other uses, the data processing environment 100 can be used to implement a client-server environment in which exemplary embodiments can be implemented. A client-server environment enables software applications and data to be distributed across a network so that applications function by using interoperability between client data processing systems and server data processing systems. The data processing environment 100 can also employ a service-oriented architecture, where interoperable software components distributed across the network can be packaged together as a consistent business application. The data processing environment 100 can also take the form of a cloud and employ a service-delivered cloud computing model to enable convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), which can be rapidly provisioned and released with minimal management effort or interaction with service providers.

[0049] refer to Figure 2 This figure illustrates a block diagram of a data processing system that can implement illustrative embodiments. Data processing system 200 is an example of a computer, such as... Figure 1 Servers 104 and 106, or clients 110, 112 and 114, or another type of device, wherein computer-usable program code or instructions for implementing the processing can be set up for exemplary embodiments.

[0050] Data processing system 200 also represents a data processing system or a configuration thereof, such as Figure 1 The data processing system 132 includes computer-usable program code or instructions that can be configured to implement the processing of exemplary embodiments. The data processing system 200 is described as a computer by way of example only and is not limited thereto. Without departing from the general description of the operation and function of the data processing system 200 described herein, terms such as... Figure 1 The implementation of device 132 in the form of other devices may be modified by adding a touch interface to the data processing system 200, and even by removing certain depicted components from the data processing system 200.

[0051] In the described example, the data processing system 200 employs a hub architecture, including a Northbridge and Memory Controller Hub (NB / MCH) 202 and a Southbridge and Input / Output (I / O) Controller Hub (SB / ICH) 204. A processing unit 206, main memory 208, and a graphics processor 210 are coupled to the Northbridge and Memory Controller Hub (NB / MCH) 202. The processing unit 206 may contain one or more processors and can be implemented using one or more heterogeneous processor systems. The processing unit 206 may be a multi-core processor. In some implementations, the graphics processor 210 may be coupled to the NB / MCH 202 via an Accelerated Graphics Port (AGP).

[0052] In the described example, a local area network (LAN) adapter 212 is coupled to the Southbridge and I / O controller hub (SB / ICH) 204. An audio adapter 216, a keyboard and mouse adapter 220, a modem 222, a read-only memory (ROM) 224, a universal serial bus (USB) and other ports 232, and a PCI / PCIe device 234 are coupled to the Southbridge and I / O controller hub 204 via bus 238. A hard disk drive (HDD) or solid-state drive (SSD) 226 and a CD-ROM 230 are coupled to the Southbridge and I / O controller hub 204 via bus 240. The PCI / PCIe device 234 may include, for example, an Ethernet adapter, an add-in card, and a PC card for a notebook computer. PCI uses a card bus controller, while PCIe does not. The ROM 224 may be, for example, a flash binary input / output system (BIOS). Hard disk drive 226 and CD-ROM 230 may use, for example, integrated drive electronics (IDE), Serial Advanced Technology Attachment (SATA) interface, or variants such as external SATA (eSATA) and micro SATA (mSATA). Super I / O (SIO) device 236 may be coupled to the southbridge and I / O controller hub (SB / ICH) 204 via bus 238.

[0053] Memory, such as main memory 208, ROM 224, or flash memory (not shown), is some example of computer-usable storage devices. Hard disk drives or solid-state drives 226, CD-ROMs 230, and other similar available devices are some examples of computer-usable storage devices that include computer-usable storage media.

[0054] The operating system runs on the processing unit 206. The operating system coordinates and provides services to... Figure 2 The data processing system 200 controls various components within it. The operating system can be a commercially available operating system for any type of computing platform, including but not limited to server systems, personal computers, and mobile devices. Object-oriented or other types of programming systems can operate alongside the operating system and provide calls to the operating system from programs or applications executing on the data processing system 200.

[0055] Used in operating systems, object-oriented programming systems, and such Figure 1The instructions for an application or program, such as application 105, reside on a storage device, such as in the form of code 226A on hard disk drive 226, and may be loaded into at least one of one or more memories, such as main memory 208, for execution by processing unit 206. The processes of the illustrative embodiment may be executed by processing unit 206 using computer-implemented instructions, which may reside in memory, such as main memory 208, read-only memory 224, or in one or more peripheral devices.

[0056] Furthermore, in one scenario, code 226A can be downloaded from remote system 201B via network 201A, where similar code 201C is stored on storage device 201D. In another scenario, code 226A can be downloaded to remote system 201B via network 201A, where the downloaded code 201C is stored on storage device 201D.

[0057] Figure 1-2 The hardware can vary depending on the implementation. Besides... Figure 1-2 In addition to the hardware described herein, or as an alternative, other internal hardware or peripheral devices such as flash memory, equivalent non-volatile memory, or optical disc drives may be used.

[0058] In some illustrative examples, the data processing system 200 may be a personal digital assistant (PDA), which is typically configured with flash memory to provide non-volatile memory for storing operating system files and / or user-generated data. The bus system may include one or more buses, such as a system bus, I / O bus, and PCI bus. Of course, the bus system can be implemented using any type of communication architecture or structure that provides data transfer between different components or devices attached to that architecture or structure.

[0059] The communication unit may include one or more devices for sending and receiving data, such as a modem or network adapter. The memory may be, for example, main memory 208 or a cache, such as the cache found in the Northbridge and memory controller hub 202. The processing unit may include one or more processors or CPUs.

[0060] Figure 1-2 The examples described herein and those above are not intended to imply architectural limitations. For example, the data processing system 200 could take the form of a tablet computer, laptop computer, or telephone device, in addition to being a mobile or wearable device.

[0061] When a computer or data processing system is described as a virtual machine, virtual device, or virtual component, the virtual machine, virtual device, or virtual component operates in a manner similar to that of the data processing system 200 using virtualized representations of some or all of the components depicted in the data processing system 200. For example, in a virtual machine, virtual device, or virtual component, processing unit 206 is represented as a virtualized instance of all or some of the hardware processing units 206 available in the host data processing system, main memory 208 is represented as a virtualized instance of all or some portions of the main memory 208 available in the host data processing system, and disk 226 is represented as a virtualized instance of all or some portions of the disk 226 available in the host data processing system. In this case, the host data processing system is represented by data processing system 200.

[0062] refer to Figure 3 The figure depicts an example configuration for noise and calibration adaptive compilation of a quantum program according to an illustrative embodiment. The example embodiment includes application 302. In a particular embodiment, application 302 is... Figure 1 Example of application 105, application 302 includes a calibration component 304 and a quantum circuit building component 306. The calibration component 304 calibrates the input quantum processor 308 according to the exemplary methods described herein. The quantum circuit building component 306 compiles the output quantum circuit design 310 according to the exemplary methods described herein.

[0063] refer to Figure 4 The figure depicts an example configuration for calibrating a quantum processor according to an illustrative embodiment. The example embodiment includes application 402. In a particular embodiment, application 402 is... Figure 1 Example of application 105.

[0064] Application 402 includes calibration component 404. In one specific embodiment, component 404 is Figure 3 Example of component 304, component 404 includes calibration operator component 406, qubit parameter analysis component 408, and quantum gate parameter analysis component 410. Application 402 receives calibration operation 412.

[0065] Calibration operator 406 performs calibration operation 412. In an embodiment, calibration operation 412 performs a set of operations on a plurality of qubits Q1, Q2, Q3, ..., Qn of quantum processor 414. In an embodiment, calibration operation 412 performs a method of randomized benchmarking. For example, calibration operation 412 may perform a predetermined set of operations on a plurality of qubits of quantum processor 414. The predetermined set of operations generates a set of values ​​for each qubit in response to the execution of the predetermined set of operations. In an embodiment, calibration operator 412 compares the set of values ​​for each qubit with the expected answer of at least one of the predetermined set of operations.

[0066] In an embodiment, calibration operation 412 returns a set 416 of qubit parameter values ​​for a plurality of qubits of quantum processor 414. For example, qubit coherence time, qubit relaxation time, measurement error, and other qubit parameter values ​​can be determined by the calibration operation. Each qubit of quantum processor 414 may include a subset of this set of parameter values. For example, qubit Q1 may include associated parameter values ​​P1, P2, ..., Pn, etc. These examples of qubit parameter values ​​are not limiting. Based on this disclosure, those skilled in the art will be able to envision many other qubit parameter values ​​suitable for calibrating the set of qubits, and these are considered within the scope of these illustrative embodiments.

[0067] In this embodiment, calibration operation 412 returns a set of quantum gate parameters. For example, calibration operation 412 may return parameters corresponding to the error rate of each quantum gate in quantum processor 414. In this embodiment, calibration operation 412 returns parameters corresponding to the error rates of each and every two qubit gates (primitive gates) in quantum processor 414.

[0068] Component 408 analyzes the set of qubit parameter values ​​416. In an embodiment, component 408 analyzes the set of qubit parameter values ​​416 according to at least one of the qubit acceptability criteria set 418. For example, component 408 may compare the parameter values ​​of the qubits with the qubit acceptability criteria. For example, component 408 may determine that the coherence time of a qubit fails to meet a threshold coherence time for performing a set of operations. As another example, component 408 may determine that the coherence time of another qubit meets a threshold coherence time for performing the set of operations.

[0069] Component 410 analyzes the set of quantum gate parameters. In an embodiment, the quantum gate parameters correspond to the set of qubits forming the quantum gate and the layout of the qubits on the quantum processor. In an embodiment, calibration operation 412 returns a set of quantum gate parameter values ​​for a plurality of quantum gates for quantum processor 414. For example, gate error rate, gate velocity, gate crosstalk matrix, and other quantum gate parameter values ​​can be determined by the calibration operation. Each quantum gate of quantum processor 414 may include a subset of the set of quantum gate parameter values. Examples of these quantum gate parameters are not limiting. Based on this disclosure, those skilled in the art will be able to envision many other quantum gate parameter values ​​suitable for calibrating the set of quantum gates, and such parameter values ​​can be envisioned within the scope of the exemplary embodiments.

[0070] Component 410 analyzes the set of quantum gate parameter values. In an embodiment, component 410 analyzes the set of quantum gate parameter values ​​according to at least one of the quantum gate acceptability criteria set 420. For example, component 410 may compare the parameter values ​​of the quantum gate with the quantum gate acceptability criteria. For example, component 410 may determine that the gate error rate of the quantum gate fails to meet a threshold error rate for the quantum gate to be executed.

[0071] In one embodiment, component 410 generates the composite gate error rate of a composite gate from a set of primitive gate error rates, the composite gate being formed from a set of primitive gate error rates corresponding to the primitive gate error rates. In another embodiment, component 410 uses a formula... The three qubits forming a composite gate generate a composite gate error rate, where Axy and Bxy It is the elementary gate error rate of the quantum gate formed by qubits x and y during the first calibration operation and the second calibration operation, respectively.

[0072] refer to Figure 5 The figure depicts an example configuration of a quantum circuit construction according to an illustrative embodiment. This example embodiment includes application 502. In a particular embodiment, application 502 is... Figure 1 Example of application 105.

[0073] Application 502 includes quantum circuit construction component 504. In a particular embodiment, component 504 is... Figure 3 Example of component 306. Component 504 includes quantum circuit compiler component 506. Component 506 is configured to transform input quantum algorithm 514 into an optimized quantum circuit design 516. Component 516 includes algorithm transformation component 508, circuit parameter calculation component 510, and quantum circuit reconfiguration component 512.

[0074] Component 508 translates the quantum algorithm code into a first quantum circuit design corresponding to the operations performed by the quantum algorithm. In an embodiment, component 510 analyzes the first quantum circuit to determine the qubits and quantum gates used in the first quantum circuit. For example, component 510 determines that the first qubit and the second qubit form the first quantum gate. In an embodiment, component 510 determines that the first qubit performs a set of operations.

[0075] Component 512 reconfigures the quantum circuit according to at least one of a set of qubit acceptability criteria and a set of quantum gate acceptability criteria. In an embodiment, component 512 determines that the first qubit meets the qubit acceptability criteria. For example, component 512 may determine that the first qubit includes a measurement error of 3 percent, which is less than a threshold measurement error of 4 percent. As another example, component 512 may determine that the first qubit includes a coherence time of 60 microseconds, which is greater than a threshold coherence time of 50 microseconds.

[0076] In one embodiment, component 512 determines that the second qubit fails to meet the qubit acceptability criterion. In response to determining that the qubit fails to meet the acceptability criterion, component 512 selects a different qubit to form a quantum gate. Component 512 outputs an optimized quantum circuit design 516.

[0077] refer to Figure 6 The figure depicts an example configuration of a connection diagram for a quantum processor according to an illustrative embodiment. Configuration 600 includes a connection diagram 602 of a quantum processor comprising a set of qubits.

[0078] One embodiment configures quantum gates between qubits 604 and 606 in response to transforming a quantum algorithm into a first quantum circuit, the first quantum circuit including quantum gates. For example, application 105 may configure controlled NOT gates between qubits 604 and 606. In an embodiment, application 105 measures the qubits after executing the quantum gate. In an embodiment, qubits 604 and 606 are not adjacent qubits. In an embodiment, application 105 moves at least one of qubits 604 and 606 adjacent to another qubit to execute the quantum gate. In an embodiment, application 105 places a swap gate on path 608 to connect qubits 604 and 606 and form a quantum gate. The swap gate allows adjacent qubits to switch their corresponding states. For example, swap gates may be placed to allow qubit 604 to exchange states with adjacent qubits of qubit 606 through a series of swap gates, and vice versa. As another example, swap gates may be placed to allow qubit 604 to exchange states and allow qubit 606 to exchange states.

[0079] In one embodiment, application 105 analyzes the set of parameters of the qubit set of the connectivity graph 602 generated during the first iteration of the calibration operation. In one embodiment, application 105 selects a path connecting qubits 604 and 606. In one embodiment, the first iteration of the calibration operation selects path 608 in response to determining that path 608 minimizes the error rate of the quantum gates between qubits 604 and 606. In one embodiment, application 105 selects path 608 in response to determining that path 608 minimizes the cumulative error along the selected path between qubits 604 and 606. In one embodiment, application 105 selects path 608 in response to determining that path 608 avoids qubits in connectivity graph 602 having the shortest coherence time.

[0080] In one embodiment, application 105 selects qubits on path 608 with the highest measurement fidelity to execute a quantum gate. For example, application 105 may select qubits 16 and 17 to execute a quantum gate. Application 105 may place a swap gate between qubit 0 and qubit 16, and between qubit 17 and qubit 19. In one embodiment, application 105 selects path 608 in response to determining that another operation is in progress while a quantum gate is being formed. For example, application 105 may determine that a controlled NOT (CNOT) gate is being formed between qubits 8 and 9. In one embodiment, application 105 selects path 608 to minimize crosstalk between the quantum gate formed between qubits 8 and 9 and the quantum gate formed between qubits 0 and 19.

[0081] refer to Figure 7 The figure depicts an example configuration of a connection diagram for a quantum processor according to an illustrative embodiment. Configuration 700 includes a connection diagram 702 of a quantum processor comprising a set of qubits.

[0082] One embodiment configures quantum gates between qubits 704 and 706 in response to converting a quantum algorithm into a first quantum circuit, the first quantum circuit including quantum gates. In one embodiment, application 105 moves at least one of qubits 704 and 706 adjacent to another qubit to execute the quantum gate. In another embodiment, application 105 places a swap gate on path 708 to connect qubits 704 and 706 and form a quantum gate. The swap gate allows adjacent qubits to switch their corresponding states. For example, the swap gate can be positioned to allow qubit 704 to exchange states with adjacent qubits of qubit 706 through a series of swap gates, and vice versa. As another example, the swap gate can be positioned to allow qubit 704 to exchange states and qubit 706 to exchange states.

[0083] In one embodiment, application 105 analyzes the set of parameters of the qubit set of the connectivity graph 702 generated during the second iteration of the calibration operation. In one embodiment, application 105 selects a path to connect qubits 704 and 706. In one embodiment, the second iteration of the calibration operation selects path 708 in response to determining path 708 that minimizes the error rate of the quantum gates between qubits 704 and 706. In one embodiment, application 105 selects path 708 in response to determining path 708 that minimizes the cumulative error along the selected path between qubits 604 and 606. In one embodiment, application 105 selects path 708 in response to determining path 708 to avoid qubits in connectivity graph 702 having the shortest coherence time.

[0084] In one embodiment, application 105 selects the qubits with the highest measurement fidelity on path 708 to execute a quantum gate. For example, application 105 may select qubits 5 and 11 to execute a quantum gate. Application 105 may place a swap gate between qubits 0 and 5 and between qubits 11 and 19. In one embodiment, application 105 selects path 708 in response to determining that another operation is in progress while a quantum gate is being formed. For example, application 105 may determine that a controlled NOT gate is being formed between qubits 2 and 7. In one embodiment, application 105 selects path 708 to minimize crosstalk between the quantum gate formed between qubits 2 and 7 and the quantum gate formed between qubits 0 and 19.

[0085] refer to Figure 8 The figure depicts an example configuration of a circuit diagram according to an illustrative embodiment. Configuration 800 includes a first circuit diagram 802 and a second circuit diagram 804. In an embodiment, application 105 translates a quantum algorithm into circuit diagrams 802 and 804. In an embodiment, application 105 generates the first circuit diagram 802 in response to a first iteration of a calibration operation. In an embodiment, application 105 generates the second circuit diagram 804 in response to a second iteration of a calibration operation. In an embodiment, application 105 selects different qubits to form the same quantum gate in response to the second iteration of a calibration operation.

[0086] refer to Figure 9 The figure depicts a flowchart of an example method for noise and calibration adaptive compilation of a quantum program according to an illustrative embodiment. In the embodiment, method 900 is performed by application 105.

[0087] In one embodiment, application 105 calibrates the quantum processor in the first iteration. In block 902, application 105 performs a calibration operation on the set of qubits in the first iteration. In one embodiment, the calibration operation produces a set of parameters, a first subset of which corresponds to a first qubit in the set of qubits, and a second subset of which corresponds to a second qubit in the set of qubits. In one embodiment, application 105 performs a predetermined operation on the first qubit. In one embodiment, application 105 compares the output of the predetermined operation with an expected output.

[0088] In block 906, application 105 selects a first qubit in response to determining that the first qubit meets an acceptability criterion. In an embodiment, application 105 transforms the quantum algorithm into a set of quantum gates, each quantum gate in the set being formed by a subset of the qubit set. In an embodiment, application 105 determines that the first quantum gate is formed by at least the first qubit. In an embodiment, application 105 compares the parameters of the first subset with the acceptability criterion.

[0089] In block 908, application 105 forms a quantum gate. In an embodiment, application 105 uses the first and third qubits to form the quantum gate in response to the second parameter of the second subset failing to meet the second acceptability criterion. Thereafter, application 105 terminates process 900.

[0090] In one embodiment, application 105 performs subsequent iterations of method 900. In another embodiment, application 105 performs a calibration operation on the qubit set in a second iteration to generate a new set of parameters, a new subset of which corresponds to the first qubit in the qubit set. In yet another embodiment, in response to the new parameters of the new subset failing to meet the acceptability criterion, application 105 deselects the first qubit. In yet another embodiment, application 105 uses the fourth and fifth qubits to form a quantum gate.

[0091] refer to Figure 10 , Figure 10 A flowchart depicts an example method for performing a calibration operation on a set of qubits according to an illustrative embodiment. In the embodiment, application 105 performs method 1000 at block 902. In block 1002, application 105 performs a predetermined operation on a first qubit to produce an output. In the embodiment, the expected output of the predetermined operation is stored in a database (e.g., ...). Figure 1 In database 109).

[0092] In box 1004, application 105 compares the output generated from the first qubit with the expected output stored in a database to determine the parameter values ​​of the first qubit. For example, application 105 can determine the difference between the generated output and the expected output to calculate the error rate of the first qubit.

[0093] In box 1006, application 105 analyzes the parameter set of the qubit set. For example, application 105 can compare a subset of the parameter set with a qubit acceptability criterion. In box 1008, application 105 analyzes the second parameter set of the quantum gate set. For example, application 105 can compare a subset of the second parameter set with a quantum gate acceptability criterion. Afterward, application 105 ends processing 1000.

[0094] refer to Figure 11The figure depicts a flowchart of an example method for selecting qubits according to an illustrative embodiment. In the embodiment, application 105 performs method 1100 at block 904. In block 1102, application 105 translates a quantum algorithm into a quantum circuit that performs the operation of the quantum algorithm, the quantum circuit comprising a set of quantum gates. In block 1104, application 105 determines that a first quantum gate in the set of quantum gates is formed by at least a first qubit in the set of qubits. In block 1106, application 105 compares the parameters of the first qubit determined in the calibration operation with an acceptability criterion. For example, application 105 may compare the coherence time of the first qubit with a threshold time to perform quantum gate operation. Application 105 then terminates process 1100.

[0095] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of the invention. While various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are illustrated in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, provided that the described functionality is maintained even if the orientation changes. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, reference in this description to forming layer "A" on layer "B" includes the case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," provided that the relevant characteristics and functionality of layers "A" and layer "B" are substantially not altered by the intermediate layers.

[0096] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprising,” “including,” “containing,” “having,” “containing,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0097] Additionally, the term "illustrative" is used herein to mean "serving as an example, illustration, or description." Any embodiment or design described herein as "illustrative" should not necessarily be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" may include both indirect "connection" and direct "connection."

[0098] References to "an embodiment," "embodiment," "example embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic; however, each embodiment may or may not include a particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments, whether explicitly described or not, to affect such a feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0099] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include a degree of error associated with measuring a particular quantity based on equipment available at the time of filing of this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value. Various embodiments of the invention have been described for illustrative purposes, but these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to commercially available technologies, or to enable others skilled in the art to understand the embodiments described herein.

[0100] Various embodiments of the invention have been described for illustrative purposes, but these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to commercially available technologies, or to enable others skilled in the art to understand the embodiments described herein.

[0101] Therefore, the illustrative embodiments provide a computer-implemented method, system, or apparatus, and a computer program product for managing participation in online communities and other related features, functions, or operations. Where embodiments or portions thereof are described with respect to a type of device, the computer-implemented method, system, or apparatus, computer program product, or portions thereof are adapted or configured for use with appropriate and comparable manifestations of that type of device.

[0102] Where embodiments are described as being implemented within an application, the delivery of the application in a Software as a Service (SaaS) model is considered within the scope of the illustrative embodiments. In a SaaS model, the ability to implement the application of an embodiment is provided to the user by executing the application within a cloud infrastructure. Users can access the application using various client devices through thin-client interfaces such as web browsers (e.g., web-based email) or other lightweight client applications. Users do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage of the cloud infrastructure. In some cases, users may not even manage or control the capabilities of the SaaS application. In some other cases, the SaaS implementation of the application may allow limited, user-specific exceptions to application configuration settings.

[0103] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0104] Computer-readable storage media can be tangible devices that can hold and store instructions used by instruction execution devices. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in recesses on which instructions are recorded), and any suitable combination of the foregoing. As used herein, computer-readable storage media is not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0105] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0106] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention by utilizing the status information of the computer-readable program instructions.

[0107] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0108] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium having the instructions stored therein includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0109] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A computer-implemented method, comprising: In the first iteration, a calibration operation is performed on the qubit set to generate a parameter set, a first subset of which corresponds to a first qubit circuit of the qubit set, and a second subset of which corresponds to a second qubit circuit of the qubit set; as well as The first qubit circuit is selected in response to the parameters of the first subset meeting the acceptability criteria; as well as In response to the second parameter of the second subset failing to meet the second acceptability criterion, a quantum gate is formed using the first qubit circuit and the third qubit circuit.

2. The method of claim 1, further comprising: In the second iteration, the calibration operation is performed on the set of qubits to generate a new set of parameters, a new subset of which corresponds to the first qubit circuit of the set of qubits; The first qubit circuit is deselected in response to the new parameters of the new subset failing to meet the acceptability criteria; and The quantum gate is formed using a fourth qubit circuit and a fifth qubit circuit.

3. The method of claim 1, wherein performing the calibration operation further comprises: Perform a predetermined operation on the first qubit circuit.

4. The method of claim 3, wherein performing the calibration operation further comprises: The output of the predetermined operation is compared with the expected output.

5. The method of claim 1, wherein selecting the first qubit circuit further comprises: The quantum algorithm is converted into a set of quantum gates, where each quantum gate is formed by a subset of the set of qubits.

6. The method of claim 5, wherein selecting the first qubit circuit further comprises: It is determined that the first quantum gate is formed by at least the first quantum bit circuit; as well as The parameters of the first subset are compared with the acceptability criteria.

7. The method of claim 1, wherein the acceptability criterion is at most four percent of measurement error.

8. The method of claim 1, wherein the acceptability criterion is a coherence time of at least 50 microseconds.

9. A computer-usable program product, comprising a computer-readable storage device and program instructions stored on the storage device, the stored program instructions comprising: Program instructions for performing a calibration operation on a set of qubits in a first iteration to generate a set of parameters, a first subset of which corresponds to a first qubit circuit of the set of qubits, and a second subset of which corresponds to a second qubit circuit of the set of qubits; as well as Program instructions for selecting the first qubit circuit in response to the parameters of the first subset meeting the acceptability criteria; as well as Program instructions for forming a quantum gate using the first and third qubit circuits in response to the second parameter of the second subset failing to meet the second acceptability criterion.

10. The computer-usable program product of claim 9, wherein the computer-usable code is stored in a computer-readable storage device in a data processing system, and wherein the computer-usable code is transmitted from a remote data processing system via a network.

11. The computer-usable program product of claim 9, wherein the computer-usable code is stored in a computer-readable storage device in a server data processing system, and wherein the computer-usable code is downloaded via a network to a remote data processing system for use in a computer-readable storage device associated with the remote data processing system.

12. The computer-usable program product of claim 9, wherein the stored program instructions further include: Program instructions for performing the calibration operation on the set of qubits in the second iteration to generate a new set of parameters, a new subset of the new set of parameters corresponding to the first qubit circuit of the set of qubits; Program instructions for deselecting the first qubit circuit in response to the failure of new parameters of the new subset to meet the acceptability criteria; as well as Program instructions for forming the quantum gate using a fourth qubit circuit and a fifth qubit circuit.

13. The computer-usable program product of claim 9, wherein the program instructions for performing the calibration operation further include: Program instructions for performing a predetermined operation on the first qubit circuit.

14. The computer-usable program product of claim 13, wherein the program instructions for performing the calibration operation further include: Program instructions for comparing the output of the predetermined operation with the expected output.

15. The computer-usable program product of claim 9, wherein the program instructions for selecting the first qubit circuit further include: Program instructions for converting a quantum algorithm into a set of quantum gates, where each quantum gate is formed by a subset of the set of qubits.

16. The computer-usable program product of claim 15, wherein the program instructions for selecting the first qubit circuit further include: Program instructions used to determine that the first quantum gate is formed by at least the first quantum bit circuit; as well as Program instructions for comparing the parameters of the first subset with the acceptability criteria.

17. The computer-usable program product of claim 9, wherein the acceptability criterion is at most four percent of measurement error.

18. The computer-usable program product of claim 9, wherein the acceptability criterion is a coherence time of at least 50 microseconds.

19. A computer system comprising a processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory, the stored program instructions comprising: Program instructions for performing a calibration operation on a set of qubits in a first iteration to generate a set of parameters, a first subset of which corresponds to a first qubit circuit of the set of qubits, and a second subset of which corresponds to a second qubit circuit of the set of qubits; as well as Program instructions for selecting the first qubit circuit in response to the parameters of the first subset meeting the acceptability criteria; as well as Program instructions for forming a quantum gate using the first and third qubit circuits in response to the second parameter of the second subset failing to meet the second acceptability criterion.

20. The computer system of claim 19, wherein the stored program instructions further include: Program instructions for performing the calibration operation on the set of qubits in the second iteration to generate a new set of parameters, a new subset of the new set of parameters corresponding to the first qubit circuit of the set of qubits; Program instructions for deselecting the first qubit circuit in response to the failure of new parameters of the new subset to meet the acceptability criteria; as well as Program instructions for forming the quantum gate using a fourth qubit circuit and a fifth qubit circuit.

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