Performing on-demand refresh operations of a memory subsystem

Abstract

A time attribute of user data stored in a memory component is identified. It is determined that the identified time attribute satisfies a time condition. An indication is provided of whether a refresh operation of the user data improves performance of the memory component. User input is received indicating to perform the refresh operation of the memory component. The refresh operation of the memory component is performed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more specifically, to on-demand refresh operations of memory subsystems. BACKGROUND

[0002] A memory subsystem can be a storage system, such as a solid state drive (SSD) or a hard disk drive (HDD). A memory subsystem can be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). A memory subsystem can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize a memory subsystem to store data at and retrieve data from the memory components. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which:

[0004] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0005] Figure 2 A flowchart of an example method of performing a refresh operation of a memory subsystem based on a time attribute of user data according to some embodiments of the present disclosure.

[0006] Figure 3 A flowchart of an example method of performing a refresh operation of a memory subsystem based on a time difference between a refresh operation and a previously performed refresh operation according to some embodiments of the present disclosure.

[0007] Figure 4 A flowchart of an example method of performing a refresh operation using a modified translation mapping according to some embodiments of the present disclosure.

[0008] Figure 5 An example of modifying a translation mapping according to some embodiments of the present disclosure is described.

[0009] Figure 6 A flowchart of an example method of performing a refresh operation of a memory subsystem based on a set optimization type according to some embodiments of the present disclosure.

[0010] Figure 7 A block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to performing refresh operations of a memory sub-system. The memory sub-system is also referred to as a "memory device" hereinafter. An example of a memory sub-system is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of a storage device include a solid state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, and a hard disk drive (HDD). Another example of a memory sub-system is a memory module coupled to a CPU via a memory bus. Examples of a memory module include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), a non-volatile dual in-line memory module (NVDIMM), and the like. In some embodiments, the memory sub-system can be a hybrid memory / storage sub-system. Generally, a host system can utilize a memory sub-system that includes one or more memory components. The host system can provide data to store at the memory sub-system and can request data to retrieve from the memory sub-system.

[0012] A memory sub-system can include a plurality of memory components that can store data from a host system. A memory component can include memory cells for storing data. Each memory cell can store a data value as a threshold voltage of that particular memory cell. Each different threshold voltage range represents a predetermined value of data stored at the memory cell. A conventional memory sub-system can store multiple data bits in a single memory cell by mapping a sequence of data bits to different threshold voltage ranges of the memory cell. Data can be stored into a memory cell by using a program operation that applies a series of program pulses to the memory cell. The series of program pulses can be applied to the memory cell until a voltage level within a corresponding threshold voltage range is reached at the memory cell. After the memory cell has been programmed, data can be read from the memory cell by applying a read threshold voltage to the memory cell at the corresponding threshold voltage range and converting the voltage level observed at the memory cell to a sequence of one or more binary values.

[0013] In a conventional memory sub-system, once data has been programmed (e.g., written) to a cell, the age of the data begins to increase. The longer the time elapses, the higher the probability that some conditions (e.g., charge loss, etc.) can cause a difference between the threshold voltage applied to program the data and the threshold voltage applied to read the data. Changes in the threshold voltage can make it difficult, or sometimes impossible, to correctly read the data. As recovery of the data to be becomes difficult, the memory sub-system can attempt to recover the data using error handling procedures.

[0014] When in an error handling flow, a conventional memory sub-system can implement error detection and correction (i.e., error control) operations for data stored at and / or retrieved from memory components of the memory sub-system. Errors can be detected and corrected based on error correction / handling operations. Error correction / handling operations can include one or more read retries using different parameters (e.g., variations in voltage thresholds) as an initial read operation performed on a memory cell. Error correction / handling operations can also use hard information corresponding to a bit value (e.g., 0 or 1) read from a memory cell, as well as soft information corresponding to a probability that the hard information read from the memory cell is accurate to correct the bit value stored at the memory cell.

[0015] Error handling operations can be time consuming and impact the performance of the memory sub-system. Error handling operations can cause read times to increase and / or cause performance to degrade as observed by a host system. The more frequently error handling operations are triggered, the slower the performance of the memory system as fewer read and write operations can be performed. Also, the specific location of the memory sub-system that is prevented from entering the error handling flow from the host to fetch other commands, thereby reducing the availability of the memory sub-system. Users or host systems can sometimes noticeably observe a significant decrease in read performance of data that was previously written due to the increase in error handling operations or prevented as the degree of aging of data stored at the memory cell increases.

[0016] In conventional memory sub-systems, background scans can be periodically performed to allow the memory sub-system to perform background refreshes of the memory sub-system. In a background refresh, data can be reprogrammed on the memory sub-system in order to improve the performance of the memory sub-system. For example, data stored at one or more memory cells can be reprogrammed to another one or more memory cells. However, users cannot flexibly control background refreshes. Users cannot customize the background refreshes according to user needs, control any settings of the refresh operations, or control the timing of the background refreshes (e.g., when to perform refresh operations). Furthermore, during a background refresh, the memory sub-system still attempts to maintain good performance (e.g., certain read and / or write latencies) while performing the background refresh. Thus, limited types of algorithms can be used in background refreshes to avoid introducing additional performance degradation while the background refresh is being performed. In some conventional memory sub-systems, a backup technique can request a host system to send user data to be overwritten to the memory components. However, requiring the host system to send data is cumbersome, inconvenient, disruptive, and infeasible.

[0017] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem capable of providing refresh operations on-demand driven by a host system or a user of the host system. In some implementations, a time attribute (e.g., age) of user data stored in a memory component can be identified. The memory subsystem can determine that the time attribute satisfies a time condition (e.g., the age of the user data is above a threshold age). An indication can be provided indicating whether the refresh operation of the user data improves performance of the memory component. Based on the indication, a user can select to provide a user input indicating to perform a refresh operation of the memory component. Upon receiving the user input, the refresh operation can be performed.

[0018] In some implementations, a mechanism can be employed to prevent the host system from initiating refreshes too frequently. For example, the memory subsystem can determine that a time between the refresh operation and a previously performed refresh operation does not exceed a threshold time. In this scenario, the memory subsystem can determine not to perform the refresh operation.

[0019] In some implementations, once a user has provided a user input to perform a refresh operation, the memory subsystem can optimize the user data for the refresh operation by employing various techniques. In on-demand refresh operations, more optimal algorithms or data alignment is possible. In background refresh operations, due to constraints, such as limited available memory for reorganizing data, a small subset of the data can be reorganized. Using the present disclosure, the memory subsystem can send an initial translation map (e.g., logical to physical block address translation map) to the host system. The host system can use its memory and computing resources to store and indicate an optimal pattern of block addresses to be used during the on-demand refresh operation. Thus, the memory subsystem can receive a modified translation map (e.g., reorganized logical to physical block address translation map) from the host system and use the modified translation map to perform the refresh operation.

[0020] In some implementations, the memory subsystem can identify a setting optimization type for performing the refresh operation. For example, the setting optimization type can include a performance optimization, a data retention optimization, a durability optimization, a read-intensive optimization, a write-intensive optimization, etc. The memory subsystem can then determine refresh operation parameters, such as a particular setting (e.g., voltage, current level, intensity, duration, number of pulses to be applied, etc.) to be used, based on the determined setting optimization type. The memory subsystem can perform the refresh operation using the particular setting.

[0021] The present disclosure provides a mechanism for system administrators and other users to initiate refresh operations for on-demand refresh of a memory sub-system to bring the memory sub-system to its original or improved performance level. Advantages of the present disclosure include, but are not limited to, improved performance of the memory sub-system when performing error correction operations due to the operations being performed more efficiently and optimally, thereby minimizing latency without wasting computing resources. As a result, error rates in the memory sub-system can be reduced or eliminated. The on-demand refresh mechanism provided herein allows for optimization of refresh operations and customization of optimization attributes. As a result, the overall performance of the memory sub-system can be improved and address the needs of the host system.

[0022] Figure 1 An example computing environment 100 including a memory sub-system 110 according to some embodiments of the present disclosure is described. The memory sub-system 110 can include media, such as memory components 112A to 112N. The memory components 112A to 112N can be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory sub-system is a storage system. An example of a storage system is an SSD. In some embodiments, the memory sub-system 110 is a hybrid memory / storage sub-system. In general, the computing environment 100 can include a host system 120 that uses the memory sub-system 110. For example, the host system 120 can write data to the memory sub-system 110 and read data from the memory sub-system 110.

[0023] The host system 120 can be a computing device such as a desktop computer, a notebook computer, a network server, a mobile device, or such computing device that includes a memory and a processing device. The host system 120 can include or be coupled to the memory sub-system 110, such that the host system 120 can read data from or write data to the memory sub-system 110. The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120.

[0024] The memory components 112A-112N can include any combination of different types of non-volatile and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of the memory components 112A-112N can include one or more arrays of memory cells, such as single-level cells (SLCs) or multi-level cells (MLCs) (e.g., triple-level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include both SLC and MLC portions of memory cells. Each of the memory cells can store one or more bits of data (e.g., a block of data) used by the host system 120. While non-volatile memory components such as NAND-type flash memory are described, the memory components 112A-112N can be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A-112N can be, but are not limited to, random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-volatile (NOR) flash memory, electrically erasable programmable read only memory (EEPROM), and cross point arrays of non-volatile memory cells. Cross point arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Additionally, in contrast to many flash-based memories, cross point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. Furthermore, the memory cells of the memory components 112A-112N can be grouped into memory pages or blocks, which can refer to units of the memory components used to store data.

[0025] The memory system controller 115 (hereinafter referred to as “controller”) can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N, among other such operations. The controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 has been illustrated as including the controller 115, in another embodiment of the present disclosure, the memory sub-system 110 can not include the controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system). Figure 1

[0026] In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address associated with the memory components 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory components 112A to 112N, as well as convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0027] ​The memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory components 112A-N.

[0028] The memory sub-system 110 includes a memory refresh component 113 that can be used to perform refresh operations of the memory sub-system on-demand. In some embodiments, the controller 115 includes at least a portion of the memory refresh component 113. For example, the controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the memory refresh component 113 is part of the host system 120, an application, or an operating system.

[0029] The memory refresh component 113 can identify a temporal attribute of user data stored in a memory component. The memory refresh component 113 can determine that the temporal attribute satisfies a temporal condition. The memory refresh component 113 can provide an indication of whether a refresh operation of the user data improves performance of the memory component. The memory refresh component 113 can receive a user input indicating to perform a refresh operation of the memory component. The memory refresh component 113 can perform the refresh operation of the memory component.

[0030] Figure 2 A flow diagram of an example method 200 of performing refresh operations of a memory sub-system based on a temporal attribute of user data in accordance with some embodiments of the present disclosure. The method 200 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by the memory refresh component 113 of the Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that steps can be performed in a different order, and / or concurrently with each other. Additionally, one or more steps can be omitted in various embodiments. Thus, not all steps are necessarily required for every embodiment. Other processes can also be included.

[0031] At operation 202, the processing device identifies a time attribute of user data stored in the memory component. In an example, the time attribute can be an age of the user data. In some embodiments, the age of the user data can be an amount of time that has elapsed since the user data was last written to the memory component. In some embodiments, the time attribute can be an amount of time that the memory subsystem has been powered on (i.e., power-on hours) or a durability characteristic, such as an average number of program-erase cycles that have been performed by the memory subsystem or have been performed for the memory component. The time attribute can be stored as metadata with the user data and obtained by the processing device.

[0032] At operation 204, the processing device determines that the identified time attribute satisfies a time condition. As the age of the user data increases, the host system can observe a significant degradation in read performance of the user data written to memory cells of the memory component. The performance can be seen to degrade significantly after a certain amount of time has elapsed after the data was written to the memory cells. A time condition can be specified to assess whether the performance of read operations has degraded significantly. The processing device can determine whether the time attribute satisfies the specified time condition. In some examples, the memory subsystem can set a threshold for the time attribute in order to assess whether the time condition is satisfied. In some examples, the processing device can determine that the identified time attribute is above a threshold time attribute. The threshold time attribute can be set (e.g., predefined) based on previous experiments, types of memory components used, etc. The threshold time attribute can be a point at which degradation in data read performance is typically noticeable.

[0033] At operation 206, the processing device provides an indication of whether the refresh operation of the user data improved performance of the memory component. In some examples, the indication can be based on a time attribute meeting a time condition. For example, the processing device can determine a benefit of the on-demand refresh operation using an algorithm that utilizes an aging of the user data. The algorithm can be based on a plurality of read operations of the user data. For example, the memory sub-system can perform a plurality of read operations on a block of data of the user data. Each of the read operations can be based on a different read threshold voltage applied to the block of data of the user data. For example, each of the read threshold voltages can be incremented from a previous read threshold voltage. A read threshold voltage that results in a minimum number of errors in the user data can be considered an optimal read threshold voltage. Further, a difference between the original read threshold voltage and the optimal read threshold voltage can indicate an amount of aging of the user data. In some embodiments, if the difference between the original read threshold voltage and the optimal read threshold voltage exceeds a threshold voltage, the memory sub-system can determine that the refresh operation can improve performance of the memory component. The processing device can provide at least one of an indication that identifies that the refresh operation of the user data improved performance of the memory component, or an indication that identifies that the refresh operation of the user data did not improve performance of the memory component. In some examples, the processing device provides a probability that the refresh operation of the user data was successful in improving performance of the memory component. In some examples, the processing device provides the indication of whether the refresh operation of the user data improved performance of the memory component to a host device coupled to the memory component. In some implementations, the indication can be actively provided by the processing device without a user asking for a benefit of the on-demand refresh operation. In some implementations, a user can initiate a command to receive the indication of whether the refresh operation of the user data improved performance of the memory component. The processing device can provide the indication based on receiving the user command to indicate.

[0034] At operation 208, the processing device receives a user input indicating to perform a refresh operation of the memory component. In some examples, the user input can be received from a human user, such as a system administrator or a host system user. In some examples, the user input can be received from a system user. Examples of a system user include, but are not limited to, an automatic process of a host system, a continuous value stream system, a continuous integration system, or a continuous deployment system that is performed at a recurring occurrence time. In some embodiments, the system user can be a process initiated by a health monitoring system that monitors the memory subsystem. In some examples, the user input can be a command that is executable by the user. In some examples, the user input can include parameters and parameter values specified by the user. For example, the user can indicate to use a read-intensive or a write-intensive refresh operation. In a read-intensive refresh operation, the user data is written in a manner such that the user data can be less frequently and / or slowly written and more frequently and / or quickly read. In a write-intensive refresh operation, the user data is written in a manner such that the user data can be more frequently and / or quickly written and less frequently and / or slowly read. In other examples, the user can indicate to perform the refresh operation optimized for performance, data retention, and / or endurance. Performance is a measure of the speed of reading data. For example, when optimized for performance, the performance of a read operation is improved, that is, the read operation can be performed faster and / or more frequently. Data retention is a measure of the time that data can be retained in the memory subsystem. For example, when optimized for data retention, the user data can be retained in the memory subsystem for a longer period of time. Endurance is a measure of the duration of the memory subsystem before the memory subsystem is worn out. For example, when optimized for endurance, the memory subsystem can last for a longer time before the memory subsystem is worn out. In some examples, the user can be provided with an indication of whether on-demand refresh operations are currently supported and / or whether the refresh operation is allowed. In some examples, the user can initiate a command to receive an indication of whether on-demand refresh is currently supported or allowed.

[0035] In some implementations, the processing device determines whether a time between the refresh operation and a previously performed refresh operation exceeds a threshold time. Determining the time between the current refresh operation and the previous refresh operation can be used to prevent performing on-demand refresh operations too frequently and prematurely degrading the memory sub-system. If the processing device determines that the time exceeds the threshold time, the processing device performs the refresh operation. If the processing device determines that the time does not exceed the threshold time, the processing device determines not to perform the refresh operation. The processing device can provide an indication that it is too early to perform another refresh operation since the previous refresh operation. The processing device can provide a wait time before another refresh operation can be performed. In some examples, the processing device can provide an indication including a length of time since a previous refresh operation was performed or attempted. In some examples, a user can initiate a command to receive an indication including a length of time since a previous refresh operation was performed or attempted.

[0036] At operation 210, the processing device performs a refresh operation of the memory component. To perform the refresh operation of the memory component, the processing device can erase user data from a first location of the memory component and perform a write operation on a second location of the memory component using the user data. In some examples, the first location and the second location are different locations. In some examples, the first location and the second location are the same.

[0037] In addition, the processing device can provide additional information associated with the refresh operation. The additional information can include one or a combination of: a number of total refresh operations attempted by the memory sub-system, a number of successful refresh operations attempted by the memory sub-system, a number of unsuccessful refresh operations attempted by the memory sub-system, an average time to complete a refresh operation attempted by the memory sub-system, a standard deviation of times to complete a refresh operation attempted by the memory sub-system, a first status of the refresh operation, or a second status of a previous refresh operation attempted by the memory sub-system. In some examples, the status of the previous refresh operation can include one or more of: the previous refresh operation is still in progress, completed successfully, failed to complete, etc. If the previous refresh operation is still in progress, the indication can include a running time of the previous refresh operation, a percentage of completion, etc. If the previous refresh operation has completed, the indication can include whether the previous refresh operation was successful or failed. If the previous operation failed, the indication can include details of the failure, including a reason for the failure, a particular block that failed, etc.

[0038] In some examples, the processing device can provide an indication of whether a refresh operation has started. One or more of the following indications can be provided: a refresh operation has started, a refresh operation is in progress, a time since a refresh operation has been in progress, a time remaining to complete a refresh operation, a percentage of completion, a refresh successfully completed, a refresh operation has been aborted, a refresh operation was not successful, a refresh operation is not allowed at this time, etc. In the case of a failure, a description of the cause of the failure can be provided. The description can include information such as the device is busy, a command that does not support a refresh operation, a command that does not support a refresh operation at this time, it is too soon since a previous refresh operation was performed, etc.

[0039] In some examples, the performance of the memory sub-system can temporarily degrade when a refresh operation is being performed. The temporary performance degradation can allow for longer term improvements in performance, such as flexibility in rearranging data, optimizing the type of optimization using preferred settings, more flexibility in the algorithms used during a refresh operation, etc. Thus, the temporary performance degradation can be acceptable when a user intentionally initiates a refresh operation at a convenient time in anticipation of the temporary degradation occurring. When a user can anticipate a refresh operation that will cause a temporary performance degradation, the user can avoid initiating other tasks using the memory sub-system. Thus, one advantage of the refresh operation is that the user can control the timing of the refresh operation and accordingly control the scheduling.

[0040] Figure 3 A flowchart of an example method 300 for performing a refresh operation of a memory sub-system based on a time difference between the refresh operation and a previously performed refresh operation in accordance with some embodiments of the present disclosure. The method 300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by the memory refresh component 113 of FIG. 1. Figure 1 The order of the processes can be modified unless otherwise specifically stated. It is understood, therefore, that the illustrated embodiments are only examples, and that a particular sequence of the processes can be performed in a different order, and that some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

[0041] At operation 302, the processing device identifies a time attribute of user data stored in the memory component. In an example, the time attribute can be an age of the user data, a number of power-on hours, or a durability characteristic. The time attribute can be stored as metadata with the user data and obtained by the processing device. Operation 302 is comparable to operation 202. At operation 304, the processing device determines that the identified time attribute satisfies a time condition. Operation 304 is comparable to operation 204. At operation 306, the processing device provides an indication of whether a refresh operation of the user data improves performance of the memory component. Operation 306 is comparable to operation 206. At operation 308, the processing device receives a user input indicating to perform a refresh operation of the memory component. Operation 308 is comparable to operation 208.

[0042] At operation 310, the processing device determines that a time between the refresh operation and a previously performed refresh operation does not exceed a threshold time. Determining the time between the current refresh and the previous refresh can be used to prevent performing on-demand refresh operations too frequently and prematurely degrading the memory subsystem. As such, the threshold time can be set such that exceeding the threshold time can indicate that the refresh operation is not being performed too frequently. If it is determined that the time does not exceed the threshold time, the processing device determines that the refresh operation is being performed too frequently. The processing device can provide an indication that another refresh operation is being performed prematurely since the previous refresh operation. The processing device can provide a wait time before another refresh operation can be performed. In some examples, the processing device can provide an indication including a length of time since the previous refresh operation was performed or attempted. In some examples, a user can initiate a command to receive an indication including a length of time since the previous refresh operation was performed or attempted.

[0043] At operation 312, the processing device determines not to perform a refresh operation of the memory component. The determination not to perform the refresh operation can be based on the time between the refresh operation and a previously performed refresh operation not exceeding a threshold time. In this scenario, the processing device does not perform the refresh operation even though the user input indicates to perform the refresh operation.

[0044] Figure 4 A flowchart of an example method 400 for performing a refresh operation using a modified translation mapping in accordance with some embodiments of the present disclosure. The method 400 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by a processing device, such as the processing device 102 of FIG. 1. Figure 1The memory refresh component 113 of the memory system 100 performs. Although shown in a particular order or sequence, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the illustrated embodiments are only examples, and that the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

[0045] At operation 402, the processing device receives a user input from a user to perform a refresh operation of a memory component. In some examples, the user input can be received from a human user, such as a system administrator or a host system user. In some examples, the user input can be received from a system user. In some examples, the user input can be a command that is executable by the user. In some examples, the user input can include parameters and parameter values specified by the user. For example, the user input can indicate to reorganize user data to optimize the user data for sequential access of the user data.

[0046] At operation 404, the processing device sends an initial translation map to a host system coupled to the memory component. In some examples, the initial translation map is configured to map a number of logical block addresses (LBAs) to a number of physical block addresses using a first order. In some examples, the first order of mapping LBAs to physical block addresses in the initial translation map can be in a non-sequential order. For example, the LBAs can be mapped to non-sequential physical block addresses. The initial translation map is sent to the host system because the host system can have more memory capacity to handle the reorganization of the translation map. In a background refresh operation, reorganization cannot be performed for a majority of the translation map, for example, due to memory capacity constraints of the memory subsystem. The memory subsystem can typically reorganize a small portion of data during a background refresh operation, which does not significantly improve performance of user data read using the translation map. The host system, which has access to a larger amount of cache memory, can receive a majority, or even the entire, initial translation map. The host system can reorganize the entire initial translation map according to a sequential logical block order. Reorganizing the translation map so that data can be written back to the memory component in a sequential logical block order can significantly improve performance in cases where user data is accessed sequentially faster than randomly. After the host system reorganizes the initial translation map, the host system can send the reorganized translation map back to the memory subsystem.

[0047] At operation 406, the processing device receives a modified translation map from the host system. In some examples, the modified translation map is configured to map the number of LBAs to the number of physical block addresses using a second order that is different than the first order. In some examples, the modified translation map is a reorganized initial translation map that is reorganized by the host system. In some examples, the host system can suggest a new, more optimal pattern of blocks to be used based on global or superblock optimization. For example, the optimal pattern of blocks can be based on word line groups, plane selection, availability of different types of memory cells (e.g., single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC)). The modified translation map can be in sequential logical block order.

[0048] At operation 408, the processing device performs a refresh operation of the memory component using the modified translation map. In some examples, the processing device performs the refresh operation of the memory component using the physical block addresses in the second order. In some examples, to perform the refresh operation, the processing device erases user data from a first location of the memory component and performs a write operation using the user data on a second location of the memory component. In some examples, the first location and the second location are the same location, while in other examples, the first location and the second location are different locations. The write operation can be performed using the second order indicated by the modified translation map.

[0049] In some examples, to perform the write operation on the second location, the processing device provides the user data to the host system for storage of the user data. For example, the memory sub-system can have limited cache capacity, preventing the entire superblock of user data to be written in the second order from being received. The host system can be used to temporarily store the contents of the superblock. During the process of temporary storage, the contents of the superblock are not valid until the refresh operation of the entire superblock is completed. The processing device performs the write operation on the second location of the memory component incrementally in a number of stages. A portion of the user data is written to the second location in each of the number of stages. After completing the write operation using the number of stages, the processing device indicates to the host system to erase the user data from the host system.

[0050] Figure 5 An example of modifying a translation map is illustrated in accordance with some embodiments of the disclosure. Figure 5 An initial translation map 510 is shown that maps a number of LBAs 512 to a number of physical block addresses 514. The initial translation map uses a first order 516 of the physical block addresses. The LBAs 512 include logical block addresses that are presented in sequential order. The corresponding physical block addresses 514 in the first order 516 are depicted in non-sequential order.

[0051] Figure 5 A modified translation map 520 for use in a background refresh operation is also depicted. The modified translation map 520 maps the number of LBAs 512 to the number of physical block addresses 514 using a second order 546 that is different than the first order 516 used in the initial translation map 510. A small subset of the translation map 520 is reorganized individually during the background refresh operation. As shown, within the subset 525 of the translation map, the physical block addresses 514 are depicted as reorganized in a sequential order 526. That is, for the subset 525, the LBAs having values 1, 2, 3, and 4 had corresponding physical block address values 11, 12, 3, and 4, respectively, in the initial translation map 510. Since the background refresh operation can use a small subset to reorganize the data, for the subset 525, the LBAs having values 1, 2, 3, and 4 are mapped to corresponding physical block address values 3, 4, 11, and 12, respectively, in the modified translation map 520 in the sequential order 526 within the subset 525. For the physical block addresses, the subset 527 has a sequential order 528 and the subset 529 has a sequential order 530. However, the entire modified translation map does not have a sequential order for the physical block addresses 514. Thus, the user data is not fully optimized for sequential reads and the performance improvement is not significant.

[0052] Figure 5 A modified translation map 540 using an on-demand refresh operation is depicted. The entire initial translation map 510 is sent to the host system for reorganization. The physical block addresses 514 of the entire modified translation map have been re-mapped to the LBAs 512 using a second order 546 that encompasses all of the physical block addresses. The second order 546 is different than the first order 516. The entire second order 546 is a sequential order of the physical block addresses. The modified translation map 540 can be sent to the memory sub-system for use in overwriting the data for the refresh operation using the sequential order of the modified translation map 540. Since the entire translation map is sequentially ordered, the data is fully optimized for sequential reads and the performance improvement is maximized.

[0053] Figure 6 A flowchart of an example method 600 for performing a refresh operation of a memory sub-system based on a set optimization type in accordance with some embodiments of the present disclosure. The method 600 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1The memory refresh component 113 performs. Although shown in a particular order or sequence, unless otherwise specified, the order or sequence can be modified. Thus, the illustrated embodiments should be understood only as examples, and that the illustrated procedures can be performed in a different order, and that some procedures can be performed in parallel. Additionally, one or more procedures can be omitted in various embodiments. Thus, not all procedures are required in every embodiment. Other procedural flows are also possible.

[0054] At operation 602, the processing device determines a setting optimization type for performing a refresh operation of a memory component. The setting optimization type can include one or a combination of: a performance optimization, a data retention optimization, a durability optimization, a read-intensive optimization, or a write-intensive optimization.

[0055] In some implementations, the processing device identifies a workload performed by the memory component and determines the setting optimization type based on the identified workload. In some examples, the identified workload indicates a workload pattern. The workload pattern can be identified as a write-intensive workload pattern, or a read-intensive workload pattern. For example, the processing device can identify that the memory subsystem has performed a read-intensive workload for a period of time that has elapsed. Accordingly, the processing device can determine to switch to a write-intensive workload for a next refresh operation. In some implementations, the processing device receives a user input indicating the setting optimization type. The processing device then determines the setting optimization type based on the user input.

[0056] For example, if a user anticipates initiating refresh operations at frequent intervals (e.g., every two weeks), the user can deprioritize the data retention aspect of the optimization because the data does not need to be retained for a long period of time. As such, the user can prioritize the performance of the data and indicate that the write of the data is optimized for performance of the data read during the refresh operation. The user can provide a user input indicating the setting optimization type as a performance optimization. In another example, a user of a database system can anticipate a workload of the database system to be read-intensive. The user can provide a user input indicating the setting optimization type as a read-intensive optimization.

[0057] At operation 604, the processing device determines refresh operation parameters to be used based on the determined setting optimization type. In some examples, the refresh operation parameters can be a particular setting. The particular setting can be a "TRIM" setting of the memory sub-system. The TRIM setting is a value for a register in the memory sub-system that causes the memory sub-system to behave differently. For example, the TRIM setting can include a default amount of word line current to be used in a standard write operation. In another example, a default threshold voltage for a read operation is specified in the TRIM setting. In some examples, the particular setting can include one or a combination of: a threshold voltage to be used for a refresh operation, a specified current level to be used for a refresh operation, a specified intensity level (e.g., a particular voltage level) to be used for a refresh operation, a duration to be used for a refresh operation, or a number of pulses of a write operation for a refresh operation. The memory sub-system can modify the value of the particular setting that can implement the determined setting optimization type. Based on the particular setting used, the memory sub-system behaves differently (e.g., faster write, slower write, etc.).

[0058] In other examples, the particular setting can also identify where data is written. In general, writing data to a cell with fewer bits is faster. A cell with fewer bits has more margin for reading back the data and thus implements better data retention. If there are more bits per cell, the write performance is generally slower because it can take a longer amount of time to write the data and the probability of successfully reading back the data is reduced as the data ages. Thus, for example, in a performance only optimization, frequently accessed data can be written to a location configured for a cell with fewer bits per cell, while less frequently accessed data can be written to a location with higher bits per cell. In a retention only optimization, some cells can be reconfigured to reduce the number of bits per cell for some blocks and allow more margin when reading the cell while still maintaining the capacity of the device.

[0059] As previously discussed, over time, the threshold voltage applied to read data can naturally shift based on various factors such as the particular type of memory component, whether a charge loss condition has occurred, etc. The TRIM value can set the read threshold voltage to use during a read operation. In an example, if the setting optimization type is determined to be a performance optimization, the read threshold voltage can be set to be within a first specified range so that successful read operations can be implemented and error handling procedures can be avoided. In another example, if the setting optimization type is determined to be a durability optimization, the read threshold voltage can be set to be within a second specified range to implement a desired durability.

[0060] For example, if the set optimization type is determined to be write-intensive optimization, then the specified current level or threshold voltage to be used for write operations, for refresh operations can be selected to be at a higher level than the threshold voltage that would be used for read-intensive optimization. A higher current level or threshold voltage can make the write operation faster.

[0061] In another example, if the set optimization type is determined to be read-intensive optimization, then the write operation can be performed using slower writes such that the probability of a first successful read of the data is increased and thus the overall read speed is increased. Typically, when a write operation is performed, multiple passes are used to complete the write operation. In doing so, a quality of the write operation is balanced against a performance of the write operation. Quality indicates an accuracy of the data, and performance indicates a speed of performing the operation. There is typically a tradeoff between quality and performance such that if the quality is increased, the performance can be decreased. Under normal operating conditions, fast operations are needed while maintaining a minimum amount of charge to provide good data quality. In an on-demand refresh scenario, the performance (e.g., speed) can be allowed to decrease because a temporary performance degradation can be acceptable. The write operation can be performed more accurately and in a slow manner such that a necessary amount of charge can enter each memory cell. Thus, the read performance is improved due to the accuracy achieved during the write operation. Better write accuracy can also be achieved by allowing more passes to complete the write operation. In addition, less current can be used, which can increase the time to perform the write operation.

[0062] At operation 606, the processing device performs a refresh operation of the memory component using the refresh operation parameters (e.g., the particular settings). In some examples, the processing device can erase user data from a first location of the memory component and perform a write operation on the memory component at a second location using the user data. In some examples, the first location and the second location are different locations from each other. In some examples, the first location is the same as the second location.

[0063] Figure 7 An example machine of a computer system 700 is illustrated in which an instruction set can be executed for causing the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 700 can correspond to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to Figure 1 Figure 1 Figure 1 ​​the operation of the memory refresh component 113 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0064] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0065] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0066] Processing device 702 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 702 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over the network 720.

[0067] The data storage system 718 can include a machine-readable storage medium 724 (also known as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and / or main memory 704 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0068] In one embodiment, the instructions 726 include instructions to implement functionality corresponding to a memory refresh component (e.g., memory refresh component 113 of FIG. 1). While the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. Figure 1

[0069] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In this context, and for purposes of

[0070] It is also important to note that while the present disclosure can have been described in the context of individual embodiments, the assistance of these can also include a combination of embodiments. Accordingly, the present disclosure can include all combinations of individual embodiments, as well as other

[0071] ​​The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0072] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0073] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium can include any mechanism for storing information in a form accessible by a machine (e.g., computer, etc.). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., readonly memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.).

[0074] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A system, comprising: a memory component; and a processing device, operatively coupled with the memory component, to: identify a temporal attribute of user data stored in the memory component; determine that the identified temporal attribute satisfies a temporal condition; upon determining that the identified temporal attribute satisfies the temporal condition, provide an indication of whether a refresh operation of the user data improves performance of the memory component; in response to the indication, receive a user input from a user indicating to perform the refresh operation of the memory component; in response to receiving the user input from the user indicating to perform the refresh operation of the memory component, send an initial translation map to a host system coupled to the memory component; receive a modified translation map from the host system; and using the modified translation map, perform the refresh operation of the memory component.

2. The system of claim 1, wherein the temporal attribute represents an amount of time that has elapsed since the user data was stored in the memory component, wherein to determine that the identified temporal attribute satisfies a first temporal condition, the processing device is to: determine that the amount of time that has elapsed exceeds a threshold amount of time.

3. The system of claim 1, wherein to provide the indication of whether the refresh operation of the user data improves performance of the memory component, the processing device is to provide at least one of: an indication that the refresh operation of the user data improves performance of the memory component; or an indication that the refresh operation of the user data does not improve performance of the memory component.

4. The system of claim 1, wherein to provide the indication of whether the refresh operation of the user data improves performance of the memory component, the processing device is to provide a probability that the refresh operation of the user data is successful to improve performance of the memory component.

5. The system of claim 1, wherein to provide the indication of whether the refresh operation of the user data improves performance of the memory component, the processing device is to: provide the indication identifying whether the refresh operation of the user data improves performance of the memory component to a host system coupled to the memory component.

6. The system of claim 1, wherein to perform the refresh operation of the memory component, the processing device is to: erase the user data from a first location of the memory component; and perform a write operation using the user data on a second location of the memory component.

7. The system of claim 6, wherein the first location is the same as the second location.

8. The system of claim 1, wherein the processing device is further to: provide one or more information associated with the refresh operation, the one or more information comprising one or more of: ​ a number of all refresh operations attempted in association with the memory component; a number of successful refresh operations attempted in association with the memory component; a number of unsuccessful refresh operations attempted in association with the memory component; an average time to complete a refresh operation attempted in association with the memory component; a standard deviation of time to complete a refresh operation attempted in association with the memory component; a first status of the refresh operation; or a second status of a previous refresh operation attempted in association with the memory component.

9. The system of claim 1, wherein prior to performing the refresh operation of the memory component, the processing device is to: determine that a time between the refresh operation and a previously performed refresh operation exceeds a threshold time.

10. A method comprising: receiving, from a user, a user input to perform a refresh operation of a memory component in response to an indication indicating whether the refresh operation of user data improved performance of the memory component; after receiving the user input from the user to perform the refresh operation of the memory component, sending an initial translation map to a host system coupled to the memory component; receiving a modified translation map from the host system; and performing, by a processing device, the refresh operation of the memory component using the modified translation map.

11. The method of claim 10, wherein the initial translation map is configured to map a plurality of logical block addresses (LBAs) to a plurality of physical block addresses using a first order, and wherein the modified translation map is configured to map the plurality of LBAs to the plurality of physical block addresses using a second order different than the first order.

12. The method of claim 11, wherein performing the refresh operation of the memory component using the modified translation map comprises: performing the refresh operation of the memory component using the physical block addresses in the second order.

13. The method of claim 10, wherein performing the refresh operation of the memory component comprises: erasing user data from a first location of the memory component; and performing a write operation on a second location of the memory component using the user data.

14. The method of claim 13, wherein performing the write operation on the second location of the memory component comprises: providing the user data to the host system for storage of the user data; performing the write operation on the second location of the memory component progressively in a plurality of stages, wherein a portion of the user data is written to the second location in each stage of the plurality of stages; and after completing performing the write operation using the plurality of stages, indicating to the host system to erase the user data from the host system.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: determine a setting optimization type for performing a refresh operation of a memory component; ​ ​ ​ determining refresh operation parameters to be used based on the determined setting optimization type; sending an initial translation map to a host system coupled to the memory component in response to receiving a user input from a user to perform the refresh operation of the memory component; receiving a modified translation map from the host system; and performing the refresh operation of the memory component using the refresh operation parameters and the modified translation map.

16. The non-transitory computer-readable storage medium of claim 15, wherein to determine the setting optimization type, the processing device is to: identify a workload associated with the memory component being executed; and determine the setting optimization type based on the identified workload.

17. The non-transitory computer-readable storage medium of claim 16, wherein the identified workload indicates a workload pattern corresponding to one of: a write-intensive workload pattern, or a read-intensive workload pattern.

18. The non-transitory computer-readable storage medium of claim 15, wherein to determine the setting optimization type, the processing device is to: receive a user input indicating the setting optimization type; and determine the setting optimization type based on the user input.

19. The non-transitory computer-readable storage medium of claim 15, wherein the setting optimization type corresponds to one or more of: a performance optimization; a data retention optimization; a durability optimization; a read-intensive optimization; or a write-intensive optimization.

20. The non-transitory computer-readable storage medium of claim 15, wherein the refresh operation parameters include one or more of: a threshold voltage to be used for the refresh operation; a specified current level to be used for the refresh operation; a specified intensity level to be used for the refresh operation; a duration to be used for the refresh operation; or a number of passes to be used for the refresh operation.

21. The non-transitory computer-readable storage medium of claim 15, wherein to perform the refresh operation of the memory component, the processing device is to: erase user data from a first location of the memory component; and based on the user data, perform a write operation on a second location of the memory component using the refresh operation parameters.

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