Display panel and manufacturing method thereof, and display device

Abstract

A display panel (10) and a manufacturing method thereof, and a display device (100). The display panel (10) comprises a display area (101) and a frame area (102) located around the display area (101), the frame area (102) comprising a peripheral circuit area (1020) and a peripheral area, and the peripheral circuit area (1020) is arranged between the display area (101) and the peripheral area; the display panel (10) comprises: a substrate (1), a blocking structure (3), a peripheral circuit (2), a packaging substrate (15), and a packaging adhesive (13). At least part of the blocking structure (3) is located in a peripheral circuit area (1020) on a base substrate (1) and comprises: an organic blocking layer (31) and an inorganic blocking layer (32); the organic blocking layer (31) comprises an opening (3101) penetrating the organic blocking layer (31); the extension direction of the opening (3101) is substantially the same as the extension direction of an edge of the display panel (10) near the opening (3101) in the display panel (10); the inorganic blocking layer (32) covers the organic blocking layer (31) and fills the opening (3101); the peripheral circuit (2) is located on the base substrate (1) and in the peripheral circuit area (1020); the packaging substrate (15) is arranged on a side of the blocking structure (3) away from the base substrate (1); and the packaging glue (13) is filled between the base substrate (1) and the packaging substrate (15) and covers the display area (101) and the peripheral circuit area (1020).

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] The performance and life of OLED devices are easily affected by water vapor and oxygen. It is very important to use effective sealing technology to prevent water vapor and oxygen from contacting OLED devices. At the same time, narrow borders are the development trend of OLED displays. For example, the narrow border requirements can usually be achieved by reducing the distance from the display area packaging border to the light-emitting area (AA area). Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display panel, which has a display area and a frame area located around the display area, the frame area includes a peripheral circuit area and a peripheral area, and the peripheral circuit area is arranged between the display area and the peripheral area; the display panel includes: a substrate, a blocking structure, a peripheral circuit, a packaging substrate and a packaging glue. At least part of the blocking structure is located in the peripheral circuit area on the substrate and includes: an organic barrier layer and an inorganic barrier layer, the organic barrier layer includes an opening penetrating the organic barrier layer, and the extension direction of the opening is substantially the same as the extension direction of the edge of the display panel near the opening in the display panel; the inorganic barrier layer covers the organic barrier layer and fills the opening; the peripheral circuit is located on the substrate and in the peripheral circuit area; the packaging substrate is arranged on the side of the blocking structure away from the substrate; the packaging glue is filled between the substrate and the packaging substrate, covering the display area and the peripheral circuit area.

[0004] For example, the display panel provided in one embodiment of the present disclosure further includes: a frame sealant located in the peripheral area and connected to the base substrate and the packaging substrate respectively, and the packaging sealant fills the area enclosed by the frame sealant, the base substrate and the packaging substrate.

[0005] For example, in a display panel provided by an embodiment of the present disclosure, the organic barrier layer is located on a side of the frame sealant close to the display area, and the inorganic barrier layer includes a portion located between the organic barrier layer and the frame sealant.

[0006] For example, in a display panel provided by an embodiment of the present disclosure, there is a gap between the inorganic barrier layer and the frame sealing glue.

[0007] For example, in a display panel provided by an embodiment of the present disclosure, the direction from the display area to the border area is a first direction, and the peripheral circuit includes a first signal line and a functional element; the first signal line extends along a second direction intersecting with the first direction; the orthographic projection of the first signal line on the base substrate is located within the orthographic projection of the organic barrier layer on the base substrate, and the orthographic projection of the opening on the base substrate does not overlap with the orthographic projection of the first signal line on the base substrate.

[0008] For example, in a display panel provided by an embodiment of the present disclosure, the peripheral circuit includes a plurality of first signal lines, wherein the plurality of first signal lines are arranged in the same layer, and there is a gap between two adjacent ones of the plurality of first signal lines, and the orthographic projection of the opening on the base substrate is located within the gap between two adjacent ones of the plurality of first signal lines on the base substrate.

[0009] For example, the display panel provided by an embodiment of the present disclosure further includes: a protection layer covering the first signal line and located between the first signal line and the organic barrier layer.

[0010] For example, in a display panel provided by an embodiment of the present disclosure, the protective layer is located in the frame area and is spaced apart from the display area, and the inorganic barrier layer covers the protective layer.

[0011] For example, in the display panel provided by an embodiment of the present disclosure, the direction from the display area to the border area is a first direction, and the peripheral circuit includes a second signal line extending from the display area to the border area along the first direction; the second signal line includes a first part and a second part connected in series with each other, the first part is exposed by the opening, and the second part is not exposed by the opening; the first part includes at least two lines connected in parallel, and the second part is a single line.

[0012] For example, the display panel provided in one embodiment of the present disclosure further includes: an encapsulation layer covering the display area and the inorganic barrier layer.

[0013] For example, in the display panel provided by one embodiment of the present disclosure, the opening includes a closed annular first opening surrounding the display area; the closed annular first opening separates the organic barrier layer into the inner part close to the display area and the outer part away from the display area, the inner part is a closed annular shape and surrounds the display area, and the outer part is a closed annular shape and surrounds the first opening.

[0014] For example, in a display panel provided by an embodiment of the present disclosure, the organic barrier layer includes a plurality of the openings located in the frame area.

[0015] For example, in a display panel provided by an embodiment of the present disclosure, the opening further includes a non-annular opening spaced apart from the first opening, and the non-annular opening is located in at least one of the outer portion and the inner portion.

[0016] For example, in the display panel provided in an embodiment of the present disclosure, the width of the opening in the direction from the frame area to the display area is 1 μm to 5000 μm.

[0017] For example, the display panel provided by an embodiment of the present disclosure further includes: a planar layer, including a portion located in the display area and a portion located in the frame area, wherein the planar layer serves as the organic barrier layer.

[0018] For example, a display panel provided by an embodiment of the present disclosure further includes: a light emitting device located on a portion of the planar layer located in the display area.

[0019] For example, in a display panel provided by an embodiment of the present disclosure, a direction from the display area to the frame area is a first direction, and a width of the frame area in the first direction is ≥5 mm.

[0020] At least one embodiment of the present disclosure further provides a display device, comprising any display panel provided by the embodiments of the present disclosure.

[0021] At least one embodiment of the present disclosure provides a method for manufacturing a display panel, wherein the display panel has a display area and a frame area located around the display area, and the manufacturing method includes: providing a base substrate; forming a blocking structure on the base substrate, including: forming an organic blocking layer, wherein the organic blocking layer includes an opening penetrating the organic blocking layer, wherein an extension direction of the opening is substantially the same as an extension direction of an edge of the display panel in the display panel close to the opening; and forming an inorganic blocking layer covering the organic blocking layer and filling the opening; the manufacturing method of the display panel also includes: forming a peripheral circuit on the base substrate, wherein the frame area includes a peripheral circuit area, and the peripheral circuit is located in the peripheral circuit area; providing a packaging substrate; forming a packaging glue covering the display area and the peripheral circuit area; and aligning the packaging substrate with the base substrate so that the blocking structure is away from one side of the base substrate, and the packaging glue is filled between the base substrate and the packaging substrate.

[0022] For example, a method for manufacturing a display panel provided in an embodiment of the present disclosure also includes: forming a frame sealant on the base substrate, wherein the frame sealant is located in the border area and surrounds at least a portion of the blocking structure, and the opening of the organic barrier layer is located between the frame sealant and the display area.

[0023] For example, in a method for manufacturing a display panel provided in an embodiment of the present disclosure, the organic barrier layer is located on a side of the frame sealant close to the display area, and the inorganic barrier layer includes a portion located between the organic barrier layer and the frame sealant.

[0024] For example, in a method for manufacturing a display panel provided in an embodiment of the present disclosure, the opening includes a closed annular first opening surrounding the display area; the closed annular first opening separates the organic barrier layer into an inner part close to the display area and an outer part away from the display area, the inner part is a closed annular shape and surrounds the display area, and the outer part is a closed annular shape and surrounds the first opening.

[0025] For example, in a method for manufacturing a display panel provided by an embodiment of the present disclosure, the opening further includes a non-annular opening spaced apart from the first opening.

[0026] For example, a method for manufacturing a display panel provided in an embodiment of the present disclosure includes: forming a flat layer, wherein the flat layer includes a portion located in the display area and a portion located in the border area, and performing a composition process on a material layer used to form the flat layer to form the organic barrier layer.

[0027] For example, a method for manufacturing a display panel provided by an embodiment of the present disclosure further includes: forming a light-emitting device on a portion of the planar layer located in the display area.

[0028] For example, in a method for manufacturing a display panel provided in an embodiment of the present disclosure, a direction from the display area to the border area is a first direction, and forming the peripheral circuit includes: forming a first signal line and a functional element, wherein the first signal line extends along a second direction intersecting with the first direction; an orthographic projection of the first signal line on the base substrate is located within an orthographic projection of the organic barrier layer on the base substrate, and an orthographic projection of the opening on the base substrate does not overlap with an orthographic projection of the first signal line on the base substrate.

[0029] For example, in the manufacturing method of the display panel provided by an embodiment of the present disclosure, the direction from the display area to the border area is a first direction, and forming the peripheral circuit also includes: forming a second signal line extending along the first direction signal line, wherein the second signal line includes a first part and a second part connected in series with each other, the first part is exposed by the opening, and the second part is not exposed by the opening; the first part includes at least two parallel routing lines, and the second part is a single routing line. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0031] Figure 1 A schematic plan view of a display panel provided in one embodiment of the present disclosure;

[0032] Figure 2A For along Figure 1 A schematic cross-sectional view of the I-I' line in FIG.

[0033] Figure 2B For along Figure 1 Another schematic cross-sectional view of the line I-I' in FIG.

[0034] Figure 2C For along Figure 1 Another cross-sectional schematic diagram of the line I-I' in FIG.

[0035] Figure 2D For along Figure 1 Another cross-sectional schematic diagram of the line I-I' in FIG.

[0036] Figure 2E A schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure;

[0037] Figure 3 A schematic plan view of a display panel provided in one embodiment of the present disclosure;

[0038] Figure 4 For along Figure 3 Schematic diagram of the cross section of the G-G' line;

[0039] Figure 5 A schematic diagram of a display device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0042] At least one embodiment of the present disclosure provides a display panel, which has a display area and a frame area located around the display area, and includes a substrate, a peripheral circuit and a blocking structure. The peripheral circuit is located on the substrate and in the frame area; the blocking structure is located on the substrate, and the orthographic projection on the substrate overlaps at least part of the orthographic projection of the peripheral circuit on the substrate; the blocking structure includes: an organic barrier layer and an inorganic barrier layer, the organic barrier layer includes an opening located in the frame area, and the organic barrier layer is disconnected at the opening; the inorganic barrier layer covers the organic barrier layer and fills the opening.

[0043] For example, Figure 1 A schematic plan view of a display panel provided in one embodiment of the present disclosure is shown in FIG. Figure 2A For along Figure 1 A schematic cross-sectional view of the I-I' line in FIG. Figure 1 and Figure 2A The display panel 10 has a display area 101 and a frame area 102 located around the display area 101. It should be noted that the display area 101 refers to a light-emitting area with a display function, for example, a plurality of pixel units distributed in an array are provided. The frame area 102 refers to a non-light-emitting area, for example, the frame area 102 surrounds the entire display area 101.

[0044] The display panel 10 includes a base substrate 1, a peripheral circuit 2, a blocking structure 3, a packaging substrate 15 and a packaging glue 13. The frame area 102 includes a peripheral circuit area 1020, and the peripheral circuit 2 is located on the base substrate 1 and in the peripheral circuit area 1020. The blocking structure 3 is located on the base substrate 1, and the blocking structure 3 includes: an organic barrier layer 31 and an inorganic barrier layer 32, the organic barrier layer 31 includes an opening 3101 penetrating the organic barrier layer 31, and the extension direction of the opening 3101 is substantially the same as the extension direction of the edge of the display panel near the opening 3101 in the display panel. The opening 3101 is located at the opening 3101 in the frame 102 area. The organic barrier layer 31 is disconnected at the opening 3101, that is, the opening 3101 separates the organic barrier layer 31 into a plurality of parts spaced apart from each other; the inorganic barrier layer 32 covers the organic barrier layer 31 and fills the opening 3101. The inorganic barrier layer 32 and the organic barrier layer 31 can prevent external water vapor, oxygen, etc. from entering the display area. The barrier capacity of organic materials to water vapor and oxygen is relatively weak, while that of inorganic materials to water vapor and oxygen is relatively strong. Since the opening 3101 disconnects the inorganic barrier layer 32 in the frame area 102, the organic barrier layer 31 covers the organic barrier layer 31 and fills the opening 3101, thereby forming an alternating inorganic barrier layer and an organic barrier layer in the direction from the frame area 102 to the display area 101, so as to enhance the barrier capacity of the barrier structure 3 to water vapor and oxygen in the direction from the frame area 102 to the display area 101. The encapsulation substrate 15 is arranged on the side of the barrier structure 3 away from the base substrate 1; the encapsulation glue 13 is filled between the base substrate 1 and the encapsulation substrate 15, covering the display area 101 and the peripheral circuit area 1020.

[0045] In addition, the orthographic projection of the blocking structure 3 on the base substrate 1 at least partially overlaps with the orthographic projection of the peripheral circuit area 1020 on the base substrate 1, for example. Figure 1 and Figure 2A As shown, a portion of the orthographic projection of the blocking structure 3 on the base substrate 1 overlaps with the orthographic projection of the peripheral circuit area 1020 on the base substrate 1, and the orthographic projection of the opening 3101 on the base substrate 1 is located within the orthographic projection of the peripheral circuit area 1020 on the base substrate 1, so that the blocking structure 3 at least partially overlaps with the peripheral circuit 2 in a direction perpendicular to the base substrate 1, thereby enhancing the blocking ability of the organic blocking layer 31 and reducing the frame of the display panel 10. For example, the peripheral circuit 2 is a driving circuit (such as a GOA driving circuit) for driving the pixel units distributed in an array in the display area 101 to provide a scanning signal.

[0046] It should be noted that the organic barrier layer 31 is not a sealant (dam glue) for sealing. For example, the display panel also includes a sealant 11, which is located in the peripheral area and surrounds the barrier structure 3, and the opening 3101 of the organic barrier layer 31 is located between the sealant 11 and the display area 101, so as to better block the water vapor and oxygen not absorbed by the sealant 11. The sealant 11 is connected to the base substrate 1 and the packaging substrate 15 respectively, and the packaging glue 13 is filled in the area surrounded by the sealant 11, the base substrate 1 and the packaging substrate 15. For example, the sealant 11 is a mouth-shaped dam glue surrounding the barrier structure 3.

[0047] For example, the organic barrier layer 31 is located on the side of the frame sealant 11 close to the display area 101, and the inorganic barrier layer 32 includes a portion 321 located between the organic barrier layer 31 and the frame sealant 11, so as to achieve a better effect of blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101.

[0048] For example, there is a gap 14 between the inorganic barrier layer 32 and the frame sealing glue 11 to increase the transmission path of water vapor and oxygen from the frame sealing glue 11 to the display area 101. The gap 14 has a buffering effect, thereby achieving a better effect of blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101.

[0049] Figure 2D For along Figure 1 Another cross-sectional schematic diagram of the line II' in FIG. For example, the display panel 10 adopts a face seal or Dam & Fill. For example, Figure 2D As shown, the display panel 10 also includes an encapsulation layer 4, which covers the display area 101 and the inorganic barrier layer 32. The encapsulation layer 4 covers the upper surface of the inorganic barrier layer 32 away from the base substrate 1 and the side facing the frame sealant 11. Thus, the encapsulation layer 4 covers and seals the display area 101 and at least part of the frame area 102. For example, the encapsulation layer 4 includes an inorganic encapsulation layer. For example, in some embodiments, the encapsulation layer 4 may also include an organic layer encapsulation layer stacked with the inorganic encapsulation layer. Those skilled in the art may design the material structure of the encapsulation layer 4 according to conventional techniques, and the embodiments of the present disclosure are not limited to this. In the case of surface encapsulation, the display panel 10 may also include a frame sealant 11 arranged around the encapsulation layer at the edge of the encapsulation layer to perform a sealing effect. The frame sealant 11 may also include a water-absorbing material, an oxygen-absorbing material, etc. to reduce the water vapor and oxygen entering the display area 101 from the outside.

[0050] Figure 2D The other structures and technical effects of the display panel shown are the same as those Figure 2A For the same purpose, please refer to the description of 2A.

[0051] For example, in Figure 2AIn the illustrated embodiment, the inorganic barrier layer 32 can be used as an encapsulation layer to simplify the structure of the display panel 10. For example, the inorganic barrier layer 32 covers the display area 101 and the organic barrier layer 31. For example, the inorganic barrier layer 32 covers the upper surface of the organic barrier layer 31 away from the base substrate 1 and the side surface facing the frame sealant 11, so that the encapsulation layer 4 plays a role in sealing the display area 101 and at least part of the frame area 102.

[0052] For example, Figure 1 As shown, the opening 3101 is a closed ring around the display area 101, that is, the opening includes a closed ring-shaped first opening around the display area, and the first opening is the opening 3101. The closed ring-shaped first opening 3101 separates the organic barrier layer 31 into an inner portion 311 close to the display area 101 and an outer portion 312 away from the display area 101, the inner portion 311 is a closed ring and surrounds the display area 101, and the outer portion 312 is a closed ring and surrounds the first opening 3101. In this way, a tight sealing effect can be achieved, thereby enhancing the effect of the barrier structure at various positions around the display area 101 in blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101.

[0053] For example, the width l of the first opening 3101 in the direction from the frame area to the display area is 1 μm to 5000 μm. Those skilled in the art can design the width of the frame area of ​​the display panel according to actual requirements.

[0054] For example, in Figure 2AIn the illustrated embodiment, the display panel 10 further includes a flat layer 5, the flat layer 5 includes a portion located in the display area 101 and a portion located in the frame area 102, and the portion of the flat layer 5 located in the display area 101 can form a flat surface to facilitate the formation of a light-emitting device on the flat surface. For example, the display panel 10 further includes a light-emitting device 6 located in the display area 101 and located on the portion of the flat layer 5 located in the display area 101. For example, the light-emitting device 6 is an electroluminescent device, such as an OLED light-emitting device, a Micro LED light-emitting device, etc. The light-emitting device 6 includes an anode, a light-emitting layer, and a cathode in a direction perpendicular to the base substrate 1. For example, the cathode is a single layer, and the material of the single layer cathode is aluminum (Al), magnesium / silver (Mg:Ag, i.e., a stacked magnesium film and a silver film) indium tin oxide (IZO), aluminum-doped zinc oxide (AZO), etc. For example, the cathode may also include a plurality of layers stacked in a direction perpendicular to the base substrate 1, for example, the cathode includes a transparent conductive layer and a light-transmitting metal film stacked in a direction perpendicular to the base substrate 1. The material of the transparent conductive layer is, for example, IZO or AZO, and the material of the light-transmitting metal film is, for example, Ag or Mg:Ag, etc. For example, the display panel 10 further includes a pixel driving circuit 9 located in the display area 101 for controlling the light-emitting state of the pixel unit, and those skilled in the art can design it according to conventional techniques.

[0055] For example, the material of the planar layer 5 is a resin material, a photoresist material, etc. The thickness of the planar layer 5 in the direction perpendicular to the substrate 1 is 0.2 μm to 3 μm. Of course, the material and thickness of the planar layer 5 are only exemplary, and the embodiment of the present disclosure does not limit this, and can be selected as needed.

[0056] Of course, the encapsulation layer 4 is not limited to including only one inorganic barrier layer 32, for example, it includes other organic encapsulation layers and inorganic encapsulation layers stacked with the inorganic barrier layer 32 in a direction perpendicular to the base substrate 1, and those skilled in the art can design it according to conventional techniques.

[0057] Figure 2B For along Figure 1 Another cross-sectional diagram of the I-I' line in FIG. Figure 2B In the illustrated embodiment, the planar layer 5 is used as the organic barrier layer 31 , that is, the material layer used to form the planar layer 5 is subjected to a patterning process to form the organic barrier layer 31 having the opening, without the need to form the organic barrier layer 31 separately, thereby optimizing the structure and manufacturing process of the display panel 10 .

[0058] Figure 2B Other features of the illustrated embodiment are Figure 2A For the same Figure 2A Description.

[0059] like Figure 1 and Figure 2A As shown, the direction from the display area 101 to the frame area 102 is the first direction (eg Figure 1 ), the peripheral circuit 2 also includes a first signal line 21 and a functional device (not shown in the figure), and the first signal line 21 extends along a second direction intersecting the first direction. The functional device includes, for example, a thin film transistor, a capacitor, etc. For example, the second direction is perpendicular to the first direction, for example, the first signal line 21 extends along the frame of the display panel 10. The orthographic projection of the first signal line 21 on the base substrate 1 is located within the orthographic projection of the organic barrier layer 31 on the base substrate 1, and the orthographic projection of the opening (for example, the first opening 3101) on the base substrate 1 does not overlap with the orthographic projection of the first signal line 21 on the base substrate 1. In other words, the first signal line 21 does not overlap with the above-mentioned opening in a direction perpendicular to the base substrate 1, and the entire first signal line 21 is not exposed by the first opening 3101. For example, for OLED display panels, especially large-size OLED display panels, masks are required in the evaporation process, construction process, chemical deposition (CVD) process and other processes of the organic light-emitting layer and the metal film layer used to form the circuit wiring or the electrode of the light-emitting device. In the process of film formation using the mask, it is easy to cause the metal wiring (such as the first signal line 21) of the peripheral circuit located in the area between the display area and the frame sealant to be scratched. Therefore, if the first signal line 21 is set at the position corresponding to the above-mentioned opening, the first signal line 21 is easy to be damaged during the production process of the display panel 10, thereby causing display problems such as signal short circuit. In order to reduce or avoid scratches on the metal wiring of the peripheral circuits, such as the first signal line 21, in the embodiment of the present disclosure, since the organic barrier layer 31 covers the first signal line 21 in a direction perpendicular to the base substrate 1, and the orthographic projection of the first opening 3101 on the base substrate 1 does not overlap with the orthographic projection of the first signal line 21 on the base substrate 1, the organic barrier layer 31 can further protect the first signal line 21 and prevent the first signal line 21 from being damaged or broken due to the setting of the first signal line 21 at the opening, thereby avoiding the above-mentioned problem that the first signal line 21 is easily damaged during the manufacturing process of the display panel 10.

[0060] For example, Figure 2A As shown, the peripheral circuit 2 includes a plurality of first signal lines 21, the plurality of first signal lines 21 are arranged in the same layer, and two adjacent ones of the plurality of first signal lines 21 (in Figure 2A The orthographic projection of the above-mentioned opening (for example, the first opening 3101) on the base substrate 1 is located within the orthographic projection of the above-mentioned opening on the base substrate 1. The interval between two adjacent first signal lines 211 and 212 among the plurality of first signal lines 21 is within the orthographic projection of the above-mentioned opening on the base substrate 1, thereby solving the problem that the first signal line 21 is easily damaged during the manufacturing process of the display panel 10 while playing the role of the above-mentioned opening.

[0061] For example, the display panel 10 further includes a protective layer 8, which covers the first signal line 21 and is located between the first signal line 21 and the organic barrier layer 31 to further protect the first signal line 21. The protective layer 8 also blocks water vapor and oxygen. For example, the material of the protective layer 8 is an organic material such as resin.

[0062] For example, the protective layer 8 is located in the frame area 102 and is spaced apart from the display area 101, and the inorganic barrier layer 32 covers the protective layer 8. The protective layer 8 can be provided separately, or it can be provided in the same layer as the insulating layer in the display area 101 (such as the interlayer insulating layer in the pixel circuit of the display area) and made of the same material, that is, the protective layer 8 is formed by using the insulating layer in the display area 101 to simplify the manufacturing process and manufacturing difficulty of the display panel 10.

[0063] For example, Figure 1 and Figure 2A As shown, the peripheral circuit 2 includes a second signal line 22 extending from the display area 101 to the frame area 102 along the first direction; the second signal line 22 includes a first portion 221 and a second portion 222 connected in series with each other, the first portion 221 is exposed by the above-mentioned opening (for example, the first opening 3101), and the second portion 222 is not exposed by the opening, that is, the orthographic projection of the first portion 221 on the substrate substrate 1 overlaps with the orthographic projection of the first opening 3101 on the substrate substrate 1, and the orthographic projection of the second portion 222 on the substrate substrate 1 does not overlap with the orthographic projection of the first opening 3101 on the substrate substrate 1 (there is no overlapping portion). The first portion 221 includes at least two parallel routing lines, and the second portion is a single routing line. For example, in Figure 1 In the embodiment, the first part 221 includes two parallel routing lines 2211 and 2212, and the second part 222 includes a first section 2221 and a second section 2222. At the position corresponding to the inner part 311 of the organic barrier layer 31, the first section 2221 is a single routing line; at the position corresponding to the first opening 3101, the second signal line 22 is divided into two parallel routing lines 2211 and 2212, and the two routing lines 2211 and 2212 are connected in series with the first section 2221; at the position corresponding to the outer part 312 of the organic barrier layer 31, the two routing lines 2211 and 2212 are merged into a single routing line, that is, merged into the second section 2222. Since the second signal line 22 overlapping with the orthographic projection of the first opening 3101 on the base substrate 1 is easily broken or damaged in the manufacturing process of the display panel 10, the first part 221 includes at least two parallel routing lines to avoid the problem that the signal line exposed by the first opening 3101 is easily damaged.

[0064] In other embodiments, the second signal line 22 may also include a portion located in the display area 101, and may be integrally formed with the gate line in the display area 101, and the gate line is a portion of the second signal line 22. For another example, the second signal line 22 is electrically connected to the gate line in the display area 101.

[0065] For example, in Figure 2A In the illustrated embodiment, the first signal line 21 is located on a side of the second signal line 21 away from the substrate 1 . Of course, in other embodiments, the first signal line 21 may also be located on a side of the first signal line 21 close to the substrate 1 .

[0066] The first signal line 21 may be a signal line with any function. For example, the peripheral circuit 2 is a gate driving circuit (GOA driving circuit), and the first signal line 21 is a clock signal line in the GOA driving circuit.

[0067] For example, Figure 2E Schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure. Figure 2E As shown, the gate drive circuit 2 includes a plurality of cascaded shift register units 100, wherein any one or more shift register units 100 may adopt the structure of the shift register unit 100 provided in any embodiment of the present disclosure or a variation thereof. For example, the gate drive circuit 2 may be directly integrated on the array substrate of the display device using the same semiconductor process as the thin film transistor to realize the progressive scanning or interlaced scanning driving function.

[0068] Except for the first-stage shift register unit, the input terminals INT of the remaining shift register units are connected to the output terminals OUT of the upper-stage shift register units; except for the last-stage shift register unit, the reset terminals RST of the remaining shift register units are connected to the output terminals OUT of the lower-stage shift register units.

[0069] like Figure 2E As shown, the gate drive circuit 2 also includes a first clock signal line CLK1 and a second clock signal line CLK2. For example, the first signal line 21 includes the first clock signal line CLK1 and the second clock signal line CLK2. For example, the first clock signal line CLK1 and the second clock signal line CLK2 are respectively connected to the clock signal terminals CLK of a plurality of cascaded shift register units to provide clock signals. For example, the reset control signal includes the clock signal provided by the first clock signal line CLK1 and the second clock signal line CLK2. It should be noted that the gate drive circuit 2 may also include four, six or eight or more clock signal lines, and the number of clock signal lines depends on the specific situation. The embodiments of the present disclosure are not limited here. The first signal line 21 may include the four, six or eight or more clock signal lines.

[0070] For example, Figure 2E As shown, each of the shift register units also includes a clock signal terminal CLK, and is configured to be connected to the first clock signal line CLK1 or the second clock signal line CLK2 to receive the first clock signal or the second clock signal. The first clock signal line CLK1 is connected to the clock signal terminal CLK of the 2n-1 (n is an integer greater than 0) stage shift register unit, and the second clock signal line CLK2 is connected to the clock signal terminal CLK of the 2n-1 stage shift register unit. It should be noted that the embodiments of the present disclosure include but are not limited to the above-mentioned connection methods. For example, it can also be adopted that: the first clock signal line CLK1 is connected to the clock signal terminal CLK of the 2n-1 stage shift register unit, and the second clock signal line CLK2 is connected to the clock signal terminal CLK of the 2n-1 stage shift register unit.

[0071] It should be noted that Figure 2E OUT_m (m is an integer greater than 0) shown in represents the output end of the m-th shift register unit, OUT_m+1 represents the output end of the m+1-th shift register unit, OUT_m+2 represents the output end of the m+2-th shift register unit, ... The reference numerals in the following embodiments are similar to this and are not repeated here.

[0072] For example, the input terminal INT of the first stage shift register unit can be configured to receive the trigger signal STV, and the reset terminal RST of the last stage shift register unit can be configured to receive the reset signal. For simplicity, the trigger signal STV and the reset signal are shown in FIG. Figure 2E Not shown in FIG.

[0073] For example, the gate drive circuit 2 further includes a first voltage line, a second voltage line, a third voltage line and a fourth voltage line (not shown in the figure). For example, the first voltage line is connected to the first voltage terminal VDD and is configured to provide a first voltage; the second voltage line is connected to the second voltage terminal VSS and is configured to provide a second voltage; the third voltage line is connected to the third voltage terminal VGH1 and is configured to provide a third voltage; the fourth voltage line is connected to the fourth voltage terminal VGH2 and is configured to provide a fourth voltage.

[0074] For example, the first signal line may also be the first voltage line or the second voltage line mentioned above.

[0075] For example, Figure 2EAs shown, the gate drive circuit 2 may further include a timing controller 300. For example, the timing controller 300 may be configured to be connected to the first clock signal line CLK1 and the second clock signal line CLK2 to provide a clock signal to each shift register unit; the gate drive circuit 10 may also be configured to be connected to the first voltage line, the second voltage line, the third voltage line and the fourth voltage line to provide the first voltage to the fourth voltage to each shift register unit 100. For example, the timing controller 300 may also be configured to provide a trigger signal STV and a reset signal.

[0076] For example, the pixel circuit of each pixel unit in the display area includes a display signal line (Data line) configured to provide a signal for controlling the display grayscale of the light-emitting device. The peripheral circuit may also include a portion of the display signal line extending to the peripheral circuit area. The first signal line may also be the portion of the display signal line extending to the peripheral circuit area.

[0077] For example, the second signal line 22 is a scanning signal line for providing scanning signals to the pixel units distributed in an array in the display area 101, connected to the gate line in the display area 101, and formed integrally with the gate line. The second signal line 22 has a bent portion in the frame area, and the bent portion is connected to another part 12 of the gate drive circuit, and the other part 12 is, for example, a scanning signal integrated chip. Figure 2E As shown, the second signal line 22 includes an m-th scanning signal line extending from the output end OUT_m (m is an integer greater than 0) of the m-th shift register unit to the display area (AA), an m+1-th scanning signal line extending from the output end OUT_m+1 of the m+1-th shift register unit to the display area, and an m+2-th scanning signal line extending from the output end OUT_m+2 of the m+2-th shift register unit to the display area, ... The embodiment of the present disclosure does not limit the number of scanning signal lines included in the second signal line 22.

[0078] For example, the first signal line 21 and the second signal line 22 are metal wirings.

[0079] For example, in Figure 2A In the embodiment shown, the width d of the frame area 102 in the first direction is less than 5 mm, thereby achieving a narrow frame. In this case, the above-mentioned good water vapor and oxygen blocking effect is achieved simultaneously through the cooperation of the above-mentioned organic barrier layer 31 including the opening and the inorganic barrier layer 32.

[0080] For example, in another embodiment of the present disclosure, the width d of the frame area 102 in the first direction is ≥ 5 mm, and the transmission path of water vapor and oxygen from the frame sealant 11 to the display area 101 is increased by increasing the width of the frame area 102, thereby achieving a better effect of blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101. The width of the frame area 102 in the first direction can be determined according to demand, and the embodiment of the present disclosure is not limited to this.

[0081] For example, in the embodiment of the present disclosure, the material of the organic barrier layer 31 may be an organic material such as resin, including an oxygen absorbing material or a water absorbing material. For example, the material of the inorganic barrier layer 32 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The material of the organic barrier layer 31 and the material of the inorganic barrier layer 32 are not limited to the above-mentioned types, and the embodiment of the present disclosure does not limit this.

[0082] Figure 2C For along Figure 1 Another cross-sectional schematic diagram of the I-I' line in FIG. Figure 2C In the illustrated embodiment, the display panel 10 may also be packaged using a sealant 11, a packaging glue 13, and a packaging substrate 15. The packaging substrate 15 is arranged opposite to the base substrate 1, and the sealant 11 bonds the packaging substrate 15 and the base substrate 1 to each other. The packaging glue 13 is filled between the inorganic barrier layer 4 and the packaging substrate 15, and the packaging glue 13 includes a water-absorbing material, an oxygen-absorbing material, or a heat-insulating material, etc., to prevent the light-emitting device 6 of the display area 101 from being damaged by external water vapor, oxygen, and heat.

[0083] Figure 2C Other features of the illustrated embodiment are Figure 2A For the same Figure 2A Description.

[0084] Figure 3 A schematic plan view of a display panel provided in one embodiment of the present disclosure is shown in FIG. Figure 4 For along Figure 3 Schematic diagram of the cross section of the G-G' line in FIG. Figure 3 and Figure 4 As shown, the display panel 10 and Figure 2AThe display panel shown has the following differences. The organic barrier layer 31 includes a plurality of the openings located in the frame area 102. For example, the openings include the above-mentioned first opening 3101 and a non-annular opening 3102 spaced apart from the first opening 3101. The non-annular opening 3102 is located in the outer portion 312 of the organic barrier layer 31 or in the inner portion 311 of the organic barrier layer 31. For example, in the present embodiment, the non-annular opening 3102 is located in the outer portion 312 of the organic barrier layer 31 as an example. In other embodiments, a non-annular opening may also be provided in the inner portion 311, or a non-annular opening may be provided in both the inner portion 311 and the outer portion 312.

[0085] like Figure 4 As shown, the first portion 221 of the second signal line 22 includes a first interval and a second interval, the first interval and the second interval are exposed by the first opening 3101 and the non-annular opening 3101 respectively, and the second portion 222 of the second signal line 22 includes a first segment 2221, a second segment 2222 and a third segment 2223 that are not exposed by the first opening 3101 and the non-annular opening 3102. That is, the orthographic projection of the first interval on the substrate substrate 1 overlaps with the orthographic projection of the first opening 3101 on the substrate substrate 1, the orthographic projection of the second interval on the substrate substrate 1 overlaps with the orthographic projection of the non-annular opening 3102 on the substrate substrate 1, and the orthographic projections of the first segment 2221, the second segment 2222 and the third segment 2223 on the substrate substrate 1 do not overlap with the orthographic projection of the first opening 3101 on the substrate substrate 1 and the orthographic projection of the non-annular opening 3102 on the substrate substrate 1 (there is no overlapping part). Reference Figure 3 and Figure 4 , the first section and the second section each include at least two parallel routings, and the first section 2221, the second section 2222, and the third section 2223 of the second part 22 are all single routings. The first section of the first part 221 includes two parallel routings 2211 and 2212, and the second section of the first part 221 includes two parallel routings 2213 and 2214. The first section 2221, the two routings 2211 and 2212, the second section 2222, the two routings 2213 and 2214, and the third section 2223 are connected in series with each other. The technical effect of this design refers to the above description.

[0086] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display panels provided in the embodiments of the present disclosure.

[0087] For example, Figure 5 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 5As shown, the display device 100 includes any display panel 10 provided in the embodiment of the present disclosure. The display device 100 is, for example, an OLED display device or a Micro LED display device. For example, the display device 100 is any device with a display function, such as a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, etc. The other structures of the display device 100 except the display panel can be designed by those skilled in the art according to specific needs and conventional techniques in the art.

[0088] At least one embodiment of the present disclosure also provides a method for manufacturing a display panel, which has a display area and a frame area located around the display area, and the manufacturing method includes: providing a base substrate; forming a blocking structure on the base substrate, including: forming an organic blocking layer, wherein the organic blocking layer includes an opening penetrating the organic blocking layer, wherein an extension direction of the opening is substantially the same as an extension direction of an edge of the display panel in the display panel close to the opening; and forming an inorganic blocking layer, covering the organic blocking layer and filling the opening; the manufacturing method of the display panel also includes: forming a peripheral circuit on the base substrate, wherein the frame area includes a peripheral circuit area, and the peripheral circuit is located in the peripheral circuit area; providing a packaging substrate; forming a packaging glue covering the display area and the peripheral circuit area; and aligning the packaging substrate with the base substrate so that the blocking structure is away from one side of the base substrate, and the packaging glue is filled between the base substrate and the packaging substrate.

[0089] The manufacturing method can form alternating inorganic barrier layers and organic barrier layers in the direction from the frame area to the display area, so as to enhance the barrier structure's barrier capability against water vapor and oxygen in the direction from the frame area to the display area.

[0090] For example, in one embodiment, Figure 1 and Figure 2A The manufacturing method of the display panel 10 shown further includes: forming a sealant 11 on the base substrate 1, wherein the sealant 11 is located in the peripheral area of ​​the frame area 102, and the opening 3101 of the organic barrier layer 31 is located between the sealant 11 and the display area 101. For example, the organic barrier layer 31 is located on a side of the sealant 11 close to the display area 101, and the inorganic barrier layer 32 includes a portion 321 located between the organic barrier layer 31 and the sealant 11.

[0091] For example, Figure 1As shown, the formed opening 3101 is a closed ring around the display area 101, that is, the opening includes a closed ring-shaped first opening around the display area, and the first opening is the opening 3101. The closed ring-shaped first opening 3101 separates the organic barrier layer 31 into an inner portion 311 close to the display area 101 and an outer portion 312 away from the display area 101, the inner portion 311 is a closed ring and surrounds the display area 101, and the outer portion 312 is a closed ring and surrounds the first opening 3101. In this way, a tight sealing effect can be achieved, thereby enhancing the effect of the barrier structure at various positions around the display area 101 in blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101.

[0092] For example, Figure 2B The manufacturing method of the display panel 10 shown includes: forming a flat layer 5, the flat layer 5 includes a portion located in the display area 101 and a portion located in the frame area 102, and the portion of the flat layer 5 located in the display area 101 can form a flat surface, so as to facilitate the formation of the light-emitting device 6 on the flat surface. The flat layer 5 is used as an organic barrier layer 31, that is, the material layer used to form the flat layer 5 is subjected to a patterning process to form the organic barrier layer 31 having the opening, and there is no need to form the organic barrier layer 31 separately, thereby simplifying the manufacturing process of the display panel 10.

[0093] For example, the method for manufacturing the display panel further includes forming a light-emitting device 6 on a portion of the flat layer 5 located in the display area 101. For example, the light-emitting device 6 is an electroluminescent device, such as an OLED light-emitting device, a Micro LED light-emitting device, etc. The light-emitting device 6 includes an anode, a light-emitting layer, and a cathode in a direction perpendicular to the substrate 1. For example, the display panel 10 further includes a pixel driving circuit 9 located in the display area 101, which is used to control the light-emitting state of the pixel unit, and those skilled in the art can design it according to conventional techniques.

[0094] The manufacturing method of the display panel also includes providing a packaging substrate 15; forming a packaging glue 13 covering the display area 101 and the peripheral circuit area 102; and aligning the packaging substrate 15 with the base substrate 1 so that the blocking structure 31 is away from one side of the base substrate 1, and the packaging glue 13 is filled between the base substrate 1 and the packaging substrate 15. The frame sealing glue 11 is connected to the base substrate 1 and the packaging substrate 15 respectively, and the packaging glue 13 is filled in the area surrounded by the frame sealing glue 11, the base substrate 1 and the packaging substrate 15.

[0095] like Figure 1 and Figure 2A As shown, the direction from the display area 101 to the frame area 102 is the first direction (eg Figure 1), forming the peripheral circuit 2 includes forming a first signal line 21 and a functional device (not shown in the figure), wherein the first signal line 21 extends along a second direction intersecting the first direction. The functional device includes, for example, a thin film transistor, a capacitor, etc. For example, the second direction is perpendicular to the first direction, for example, the first signal line 21 extends along the frame of the display panel 10. The orthographic projection of the first signal line 21 on the base substrate 1 is located within the orthographic projection of the organic barrier layer 31 on the base substrate 1, and the orthographic projection of the opening (for example, the first opening 3101) on the base substrate 1 does not overlap with the orthographic projection of the first signal line 21 on the base substrate 1. In other words, the first signal line 21 does not overlap with the above-mentioned opening in a direction perpendicular to the base substrate 1, and the first signal line 21 is not exposed by the above-mentioned opening. For example, for OLED display panels, especially large-size OLED display panels, masks are required in the evaporation process, construction process, chemical deposition (CVD) process and other processes of the organic light-emitting layer and the metal film layer used to form the circuit wiring or the electrode of the light-emitting device. In the process of film formation using the mask, the metal wiring (for example, the first signal line 21) of the peripheral circuit located in the area between the display area and the frame sealant is easily scratched. Therefore, if the first signal line 21 is set at the position corresponding to the above-mentioned opening, the first signal line 21 is easily damaged during the manufacturing process of the display panel 10, thereby causing display defects such as signal short circuit. In order to reduce or avoid scratches on the metal wiring of the peripheral circuit, such as the first signal line 21, in the embodiment of the present disclosure, since the organic barrier layer 31 covers the first signal line 21 in a direction perpendicular to the base substrate 1, and the orthographic projection of the above-mentioned opening (such as the first opening 3101) on the base substrate 1 does not overlap with the orthographic projection of the first signal line 21 on the base substrate 1, the organic barrier layer 31 can further protect the first signal line 21 and prevent the first signal line 21 from being damaged or broken due to the setting of the first signal line 21 at the opening, thereby avoiding the above-mentioned problem of the first signal line 21 being easily damaged during the manufacturing process of the display panel 10.

[0096] For example, Figure 2A As shown, forming the peripheral circuit 2 includes forming a plurality of the first signal lines 21, wherein the plurality of the first signal lines 21 are arranged in the same layer, and two adjacent ones of the plurality of the first signal lines 21 (in Figure 2A The orthographic projection of the above-mentioned opening (for example, the first opening 3101) on the base substrate 1 is located within the orthographic projection of the above-mentioned opening on the base substrate 1. The interval between two adjacent first signal lines 211 and 212 among the plurality of first signal lines 21 is within the orthographic projection of the above-mentioned opening on the base substrate 1, thereby solving the problem that the first signal line 21 is easily damaged during the manufacturing process of the display panel 10 while playing the role of the above-mentioned opening.

[0097] For example, Figure 2AAs shown, the manufacturing method of the display panel 10 further includes forming a protective layer 8, wherein the protective layer 8 covers the first signal line 21 and is located between the first signal line 21 and the organic barrier layer 31 to further protect the first signal line 21, and the protective layer 8 plays a role in blocking water vapor and oxygen. For example, the material of the protective layer 8 is an organic material such as resin.

[0098] For example, the protective layer 8 is located in the frame area 102 and is spaced apart from the display area 101, and the inorganic barrier layer 32 covers the protective layer 8. The protective layer 8 can be provided separately, or it can be provided in the same layer as the insulating layer in the display area 101 (such as the interlayer insulating layer in the pixel circuit of the display area) and made of the same material, that is, the protective layer 8 is formed by using the insulating layer in the display area 101 to simplify the manufacturing process and manufacturing difficulty of the display panel 10.

[0099] For example, Figure 1 and Figure 2A As shown, forming the peripheral circuit 2 includes forming a second signal line 22 extending from the display area 101 to the frame area 102 along the first direction, wherein the second signal line 22 includes a first portion 221 and a second portion 222 connected in series, the first portion 221 is exposed by the above-mentioned opening (for example, the first opening 3101), and the second portion 222 is not exposed by the opening, that is, the orthographic projection of the first portion 221 on the substrate substrate 1 overlaps with the orthographic projection of the first opening 3101 on the substrate substrate 1, and the orthographic projection of the second portion 222 on the substrate substrate 1 does not overlap with the orthographic projection of the first opening 3101 on the substrate substrate 1 (there is no overlapping portion). The first portion 221 includes at least two parallel routing lines, and the second portion is a single routing line. For example, in Figure 1 In the embodiment, the first part 221 includes two parallel routing lines 2211 and 2212, and the second part 222 includes a first section 2221 and a second section 2222. At the position corresponding to the inner part 311 of the organic barrier layer 31, the first section 2221 is a single routing line; at the position corresponding to the first opening 3101, the second signal line 22 is divided into two parallel routing lines 2211 and 2212, and the two routing lines 2211 and 2212 are connected in series with the first section 2221; at the position corresponding to the outer part 312 of the organic barrier layer 31, the two routing lines 2211 and 2212 are merged into a single routing line, that is, merged into the second section 2222. Since the second signal line 22 overlapping with the orthographic projection of the first opening 3101 on the base substrate 1 is easily broken or damaged in the manufacturing process of the display panel 10, the first part 221 includes at least two parallel routing lines to avoid the problem that the signal line exposed by the first opening 3101 is easily damaged.

[0100] For example, Figure 3 and Figure 4The manufacturing method of the display panel 10 shown includes: forming a plurality of the openings. For example, forming the first opening 3101 and the non-annular opening 3102 spaced apart from the first opening 3101. The non-annular opening 3102 is located in the outer portion 312 of the organic barrier layer 31 or in the inner portion 311 of the organic barrier layer 31. For example, in this embodiment, the non-annular opening 3102 is located in the outer portion 312 of the organic barrier layer 31. In other embodiments, the non-annular opening may be formed in the inner portion 311, or the non-annular opening may be formed in both the inner portion 311 and the outer portion 312.

[0101] like Figure 3 and Figure 4 As shown, the first portion 221 of the second signal line 22 includes a first interval and a second interval, the first interval and the second interval are exposed by the first opening 3101 and the non-annular opening 3102 respectively, and the second portion 222 of the second signal line 22 includes a first segment 2221, a second segment 2222 and a third segment 2223 that are not exposed by the first opening 3101 and the non-annular opening 3102. That is, the orthographic projection of the first interval on the substrate substrate 1 overlaps with the orthographic projection of the first opening 3101 on the substrate substrate 1, the orthographic projection of the second interval on the substrate substrate 1 overlaps with the orthographic projection of the non-annular opening 3102 on the substrate substrate 1, and the orthographic projections of the first segment 2221, the second segment 2222 and the third segment 2223 on the substrate substrate 1 do not overlap with the orthographic projection of the first opening 3101 on the substrate substrate 1 and the orthographic projection of the non-annular opening 3102 on the substrate substrate 1 (there is no overlapping part). Reference Figure 3 and Figure 4 , the first section and the second section each include at least two parallel routings, and the first section 2221, the second section 2222, and the third section 2223 of the second portion 22 are all single routings. The first section of the first portion 221 includes two parallel routings 2211 and 2212, and the second section of the first portion 221 includes two parallel routings 2213 and 2214. The first section 2221, the two routings 2211 and 2212, the second section 2222, the two routings 2213 and 2214, and the third section 2223 are connected in series with each other.

[0102] For example, the above structures of the display panel can be formed by photolithography and semiconductor processes. For example, the light-emitting layer of the light-emitting device can be formed by inkjet printing (IJP), evaporation, etc.; the cathode of the light-emitting device can be formed by thermal evaporation, sputtering, etc.; the inorganic barrier layer and the inorganic encapsulation layer can be formed by chemical vapor deposition (CVD). Those skilled in the art can make selections based on conventional techniques.

[0103] For example, the method for manufacturing a display panel also includes a packaging process, such as Figure 2AThe thin film packaging shown in FIG. 4 is to use the packaging layer 4 for face sealing (Face Seal), or to use the thin film packaging shown in FIG. Figure 2C The frame sealant 11 , the packaging sealant 13 and the packaging substrate 15 are packaged to further block external water vapor, oxygen, etc. from entering the display area.

[0104] The structures and technical effects not mentioned in the embodiment of the method for manufacturing a display panel are the same as those in the embodiment of the display panel, and please refer to the previous description.

[0105] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined according to the scope defined in the claims.

Claims

1. A display panel comprising a display area and a frame area located around the display area, wherein the frame area comprises a peripheral circuit area and a peripheral area, and the peripheral circuit area is arranged between the display area and the peripheral area; The display panel comprises: substrate substrate; A blocking structure is at least partially located in a peripheral circuit area on the substrate and includes: an organic barrier layer, comprising an opening penetrating the organic barrier layer, wherein an extending direction of the opening is the same as an extending direction of an edge of the display panel close to the opening in the display panel; and an inorganic barrier layer covering the organic barrier layer and filling the opening; and A peripheral circuit is located on the substrate and in the peripheral circuit area; A packaging substrate, disposed on a side of the blocking structure away from the base substrate; Packaging glue, filled between the base substrate and the packaging substrate, covering the display area and the peripheral circuit area; The peripheral circuit includes a plurality of first signal lines, wherein the plurality of first signal lines are arranged in the same layer, and there is a gap between two adjacent ones of the plurality of first signal lines, and the orthographic projection of the opening on the base substrate is located within the gap between two adjacent ones of the plurality of first signal lines on the base substrate.

2. The display panel according to claim 1, further comprising: The frame sealant is located in the peripheral area and is connected to the base substrate and the packaging substrate respectively. The packaging sealant fills the area surrounded by the frame sealant, the base substrate and the packaging substrate.

3. The display panel according to claim 2, wherein: The organic barrier layer is located on a side of the frame-sealing adhesive close to the display area, and the inorganic barrier layer includes a portion located between the organic barrier layer and the frame-sealing adhesive.

4. The display panel according to claim 2, wherein: There is a gap between the inorganic barrier layer and the frame sealing glue.

5. The display panel according to claim 1, wherein: The direction from the display area to the frame area is a first direction, and the peripheral circuit includes a first signal line and a functional element; The plurality of first signal lines extend along a second direction intersecting the first direction; The orthographic projections of the plurality of first signal lines on the base substrate are located within the orthographic projection of the organic barrier layer on the base substrate, and the orthographic projection of the opening on the base substrate does not overlap with the orthographic projections of the plurality of first signal lines on the base substrate.

6. The display panel according to claim 5, further comprising: The protection layer covers the first signal line and is located between the first signal line and the organic barrier layer.

7. The display panel according to claim 6, wherein: The protection layer is located in the frame area and is spaced apart from the display area, and the inorganic barrier layer covers the protection layer.

8. The display panel according to any one of claims 1 to 7, wherein: A direction from the display area to the frame area is a first direction, and the peripheral circuit includes a second signal line extending from the display area along the first direction to the frame area; The second signal line includes a first portion and a second portion connected in series with each other, the first portion is exposed by the opening, and the second portion is not exposed by the opening; The first part includes at least two parallel routing lines, and the second part is a single routing line.

9. The display panel according to any one of claims 1 to 7, further comprising: The encapsulation layer covers the display area and the inorganic barrier layer.

10. The display panel according to any one of claims 1 to 7, wherein: The opening comprises a closed annular first opening surrounding the display area; The closed annular first opening separates the organic barrier layer into an inner portion close to the display area and an outer portion away from the display area, the inner portion is a closed annular shape surrounding the display area, and the outer portion is a closed annular shape surrounding the first opening.

11. The display panel according to any one of claims 1 to 7, wherein: The organic barrier layer includes a plurality of the openings located in the frame area.

12. The display panel according to claim 10, wherein: The opening further includes a non-annular opening spaced apart from the first opening, the non-annular opening being located in at least one of the outer portion and the inner portion.

13. The display panel according to any one of claims 1 to 7, wherein: The width of the opening in the direction from the frame area to the display area is 1 μm to 5000 μm.

14. The display panel according to any one of claims 1 to 7, further comprising: The planar layer includes a portion located in the display area and a portion located in the frame area, wherein the portion of the planar layer located in the frame area serves as the organic barrier layer.

15. The display panel according to claim 14, further comprising: A light emitting device is located on a portion of the planar layer located in the display area.

16. The display panel according to any one of claims 1 to 7, wherein: A direction from the display area to the frame area is a first direction, and a width of the frame area in the first direction is ≥5 mm.

17. A display device, comprising the display panel according to any one of claims 1 to 7.

18. A method for manufacturing a display panel, the display panel comprising a display area and a frame area located around the display area, the manufacturing method comprising: providing a substrate base plate; Forming a blocking structure on the substrate includes: forming an organic barrier layer, wherein the organic barrier layer comprises an opening penetrating the organic barrier layer, wherein an extending direction of the opening is the same as an extending direction of an edge of the display panel close to the opening in the display panel; and forming an inorganic barrier layer covering the organic barrier layer and filling the opening; The method for manufacturing the display panel further includes: forming a peripheral circuit on the base substrate, wherein the frame area includes a peripheral circuit area, and the peripheral circuit is located in the peripheral circuit area; Providing a packaging substrate; forming a packaging glue covering the display area and the peripheral circuit area; and The packaging substrate is aligned with the base substrate so that the blocking structure is away from one side of the base substrate, and the packaging glue is filled between the base substrate and the packaging substrate, wherein the peripheral circuit includes a plurality of first signal lines, wherein the plurality of first signal lines are arranged in the same layer, and there is a gap between two adjacent ones of the plurality of first signal lines, and the orthographic projection of the opening on the base substrate is located within the gap between two adjacent ones of the plurality of first signal lines on the orthographic projection of the opening on the base substrate.

19. The method according to claim 18, further comprising: A frame sealant is formed on the base substrate, wherein the sealant fills a region surrounded by the frame sealant, the base substrate and the packaging substrate.

20. The method according to claim 19, wherein: The organic barrier layer is located on a side of the frame-sealing adhesive close to the display area, and the inorganic barrier layer includes a portion located between the organic barrier layer and the frame-sealing adhesive.

21. The method according to claim 18, wherein: The opening comprises a closed annular first opening surrounding the display area; The closed annular first opening separates the organic barrier layer into an inner portion close to the display area and an outer portion away from the display area, the inner portion is a closed annular shape surrounding the display area, and the outer portion is a closed annular shape surrounding the first opening.

22. The method according to claim 21, wherein: The opening also includes a non-annular opening spaced apart from the first opening.

23. The method according to claim 18, comprising: A planar layer is formed, wherein the planar layer includes a portion located in the display area and a portion located in the frame area, and a material layer used to form the planar layer is patterned to form the organic barrier layer using the portion of the planar layer located in the frame area.

24. The method according to claim 23, further comprising: A light emitting device is formed on a portion of the planar layer located in the display area.

25. The method according to any one of claims 18 to 24, wherein: The direction from the display area to the frame area is a first direction, and forming the peripheral circuit further comprises: forming the plurality of first signal lines and functional elements, wherein the plurality of first signal lines extend along a second direction intersecting the first direction; The orthographic projections of the plurality of first signal lines on the base substrate are located within the orthographic projection of the organic barrier layer on the base substrate, and the orthographic projection of the opening on the base substrate does not overlap with the orthographic projection of the first signal lines on the base substrate.

26. The method according to any one of claims 18 to 24, wherein: The direction from the display area to the frame area is a first direction, and forming the peripheral circuit further comprises: forming a second signal line extending along the first direction signal line, wherein the second signal line comprises a first portion and a second portion connected in series with each other, the first portion is exposed by the opening, and the second portion is not exposed by the opening; The first part includes at least two parallel routing lines, and the second part is a single routing line.

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