Memory management method, device and electronic equipment

Abstract

The present application discloses a memory management method, device and electronic device. The method divides part of the memory area of ​​the central processing unit and allocates it to a chip connected to an electronic device, such as an AI chip. And the area is set so that the central processing unit does not use the area. In this way, the chip can directly use part of the memory area of ​​the central processing unit of the electronic device as memory without having to connect other external data storage devices through the electronic device. In addition, since the chip is connected to the electronic device, the speed of using part of the memory of the central processing unit of the electronic device for data access is also much faster than using other external data storage devices. In this way, the data processing speed and computing efficiency of the chip can be greatly improved.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a memory management method, device and electronic device. Background Art

[0002] With the development of AI chip technology and the expansion of its application areas, the requirements for the computing power and memory capacity of AI chips are becoming increasingly higher.

[0003] In recent practical applications, although the computing power of AI chips continues to increase, due to the limited data storage capacity of the on-chip memory of AI chips, the memory of AI chips has to be expanded through external data storage, which makes the data access speed during memory operation slower, ultimately resulting in no significant improvement in computing efficiency. Summary of the invention

[0004] The inventors of the present applicant creatively provide a memory management method, device and electronic device.

[0005] According to a first aspect of an embodiment of the present application, a memory management method is provided, which is applied to an electronic device, wherein the electronic device includes a first chip and a central processing unit, and the method includes: allocating a portion of an area in the memory of the central processing unit as a first area to the first chip as a memory area of ​​the first chip; and setting the first area so that the central processing unit does not use the first area.

[0006] According to an embodiment of the present application, the method further includes: allocating a partial area of ​​the input and output of the central processing unit to the first chip as a second area for data exchange between the first chip and the central processing unit.

[0007] According to one embodiment of the present application, a partial area in the memory of the central processing unit is allocated as a first area to the first chip as the memory area of ​​the first chip, including: in the process of running the electronic device boot system, enabling the bus interface memory area reserved in the memory of the central processing unit; mapping the bus interface memory area to at least one physical memory area; and allocating the bus interface memory area as the first area to the bus interface connected to the first chip as the memory area of ​​the first chip.

[0008] According to an embodiment of the present application, mapping a bus interface memory area to at least one physical memory area includes: mapping the bus interface memory to at least one physical memory area by specifying a memory address and size.

[0009] According to one embodiment of the present application, the first chip is connected to the bus interface through an embedded controller, and accordingly, the bus interface memory area is allocated as a first area to the bus interface connected to the first chip to serve as the memory area of ​​the first chip, including: allocating the bus interface memory area as a first area to the bus interface connected to the embedded controller to serve as the memory area of ​​the first chip.

[0010] According to one embodiment of the present application, a bus interface memory area is allocated as a first area to a bus interface connected to an embedded controller to serve as a memory area of ​​a first chip, including: mapping the first area as a shadow memory area of ​​the embedded controller; granting the first chip permission to access the shadow memory area so that the shadow memory area serves as the memory area of ​​the first chip.

[0011] According to a second aspect of an embodiment of the present application, a memory management device is provided, which is applied to an electronic device, wherein the electronic device includes a first chip and a central processing unit. The device includes: a memory area allocation module, which is used to allocate a part of the area in the memory of the central processing unit as a first area to the first chip as the memory area of ​​the first chip; and a memory area setting module, which is used to set the first area so that the central processing unit does not use the first area.

[0012] According to a third aspect of an embodiment of the present application, an electronic device is provided for executing any of the above-mentioned memory management methods, the electronic device comprising: a central processing unit; a memory of the central processing unit; an embedded controller connected to the central processing unit via a bus interface; a first chip connected to the embedded controller via a high-speed internal connection bus interface; wherein a partial area in the memory of the central processing unit is allocated as a first area to the first chip as a memory area of ​​the first chip.

[0013] According to an embodiment of the present application, the embedded controller includes an embedded controller connected to a central processing unit via an enhanced serial peripheral interface eSPI.

[0014] According to an embodiment of the present application, the first chip includes a first chip connected to the embedded controller through a high-speed internal connection bus interface QPI.

[0015] An embodiment of the present application provides a memory management method, device and electronic device, which divides part of the memory area of ​​the central processing unit and allocates it to a chip connected to the electronic device, such as an AI chip. And the area is set so that the central processing unit does not use the area. In this way, the chip can directly use a part of the memory area of ​​the central processing unit of the electronic device as memory without having to connect other external data storage devices through the electronic device. In addition, since the chip is connected to the electronic device, the speed of using part of the memory of the central processing unit of the electronic device for data access is also much faster than using other external data storage devices. In this way, the data processing speed and computing efficiency of the chip can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become readily understood. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, wherein:

[0017] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0018] Figure 1 This is a schematic diagram of the implementation process of an embodiment of the memory management method of the present application;

[0019] Figure 2 A schematic diagram of the connection relationship and memory mapping of various hardware in another embodiment of the memory management method of the present application;

[0020] Figure 3 This is a schematic diagram of a specific process of implementing memory management through a BIOS system boot program in another embodiment of the memory management method of the present application;

[0021] Figure 4 A schematic diagram of the composition structure of an embodiment of the memory management device of the present application;

[0022] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, features, and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0024] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0026] Figure 1 The implementation process of memory management in the embodiment of the present application is shown. Figure 1 This embodiment provides a memory management method, which is applied to an electronic device, wherein the electronic device includes a first chip and a central processing unit. The method includes: operation S110, allocating a part of the memory of the central processing unit as a first area to the first chip as the memory area of ​​the first chip; operation S120 setting the first area so that the central processing unit does not use the first area.

[0027] Among them, electronic devices include large servers, personal computers, mobile devices, smart homes and other electronic devices equipped with a central processing unit (CPU), and personal computers can be desktops, tablets or portable laptops, etc.

[0028] The central processing unit refers to the computing and control core of an electronic device, which is used to interpret computer instructions and process data in computer software.

[0029] The memory of the central processing unit refers to the storage space connected to the central processing unit and used to store program instructions and data. It assists the central processing unit in implementing program execution and data processing through addressing operations, including dynamic random access memory (DRAM), resistive random access memory (RRAM) and magnetoresistive random access memory (MRAM).

[0030] The first chip refers to an electronic chip connected to an electronic device, which can be built-in or external, and is mainly used to assist electronic devices in completing specific data processing or computing functions, including field programmable gate array (FPGA) chips, application-specific integrated circuit (ASIC) chips, and general-purpose chips (GPU), etc.

[0031] Some chips used for high-performance computing are equipped with on-chip memory, such as block random access memory (BlockRAM). However, since on-chip memory has high requirements for manufacturing process and space miniaturization, it is expensive and has limited capacity, and often cannot meet the needs of large-scale data computing or data processing.

[0032] To this end, chip developers have used various technical approaches and manufacturing processes to reduce the cost of accessing memory, including the manufacture and use of non-volatile memory that can store analog values. However, if these solutions are applied to existing devices, new memory often needs to be added. If these new memories are built-in, new models need to be developed and the design of existing devices needs to be changed; if these memories are external, it will cause problems such as inconvenience in carrying and unsightly.

[0033] The inventor of this application creatively thought of using the memory of the central processing unit as the memory of the first chip. On the one hand, the memory of the central processing unit itself has the ability to access data at high speed and has a large capacity; on the other hand, the first chip is also connected to the electronic device where the central processing unit is located, and the "physical distance" between the computing unit on the first chip and the memory of the central processing unit is also close, which can achieve high-speed transmission of data between the computing unit and the storage unit (the memory of the central processing unit). Therefore, using the memory of the central processing unit as the memory of the first chip makes it easier to meet the data access requirements of the first chip for big data computing and data processing, and there are no problems with peripheral carrying and aesthetics.

[0034] Based on the above inventive ideas, the embodiments of the present application provide Figure 1 The memory management method shown.

[0035] Since the central processing unit also needs to use memory to process program instructions or input and output data of the electronic device, the entire memory of the central processing unit cannot be used as the memory area of ​​the first chip, and only part of the memory of the central processing unit can be allocated to the first chip as the first area. However, in fact, since electronic devices are usually not limited by physical space, the cost of their memory is relatively low, and they can also be flexibly expanded through pluggable interfaces. Therefore, even if only part of the memory of the central processing unit is used, it can basically meet the data storage needs of the first chip.

[0036] The first area is used as the memory of the first chip, that is, it is realized by mapping the virtual memory on the first chip to a physical memory area in the memory of the central processing unit. Therefore, in operation 110, a part of the area in the memory of the central processing unit is allocated to the first chip as the first area, which mainly refers to the allocation on the physical memory area, and its allocation method is also mainly realized by address allocation in the addressing space of the central processing unit.

[0037] For example, the first chip can be used as a common device. In the Linux kernel, the address space register is configured to perform space mapping of the bus interface memory area (Generic Memory Range) address, and the reserved bus interface memory area is allocated to the first chip for use. The bus interface memory area is often reserved for each bus interface for different models through fixed address allocation.

[0038] Usually, the first chip and the central processor both use the virtual storage area to store data, and no matter which physical storage area the virtual storage area is mapped to, it is transparent to the first chip. Therefore, when the first chip maps the virtual storage area to a physical memory area (i.e., the first area) in the memory of the central processor, the first chip does not know where the actual physical memory is located, but accesses the area like accessing an on-chip storage area.

[0039] The allocation of the first area is often allocated before starting the operating system and is a static allocation. Once allocated, its address, size and purpose are basically fixed and will not change dynamically.

[0040] Since the first chip does not know that the virtual memory maps to the memory area of ​​the CPU, it will not greet the CPU when using the first area. Therefore, this area cannot be shared with the CPU, and it is necessary to perform setting on the electronic device side through operation 120 so that the CPU will not use the first area to avoid data access conflict.

[0041] There are many ways to set the first area, for example, when manufacturing the electronic device, a physical memory area is reserved and set for a special purpose; or, part of the memory area allocated to the electronic device boot system can be used as the first area, and the area is allocated to the bus or controller connected to the first chip. Since the above areas are reserved and have special purposes, once some of these areas are allocated, the central processor will no longer use these areas.

[0042] In this regard, the embodiments of the present application do not limit the specific implementation methods for realizing the above functions, as long as after the first area is allocated to the first chip, the central processing unit does not use the first area.

[0043] It should be noted that Figure 1 The embodiment shown is only the most basic embodiment of the information processing method of the present application, and implementers can further refine and expand it on this basis.

[0044] According to an embodiment of the present application, the method further includes: allocating a partial area of ​​the input and output of the central processing unit to the first chip as a second area for data exchange between the first chip and the central processing unit.

[0045] In some application scenarios, the central processing unit may also need to exchange data with the first chip. In this case, part of the input and output area of ​​the central processing unit can be allocated to the first chip as the second area. Unlike the first area, this area is not used as the memory of the first chip, but as a memory area accessible to both the first chip and the central processing unit. The first chip or the central processing unit can store the data to be exchanged in this area as needed, and notify the other party to read the data put in by the other party through electrical signals or interrupts.

[0046] For example, the first chip can be used as a common device. In the Linux kernel, the address space register is configured to perform space mapping of the bus interface input and output area (Generic IO Range), and some reserved memory areas are allocated to the first chip for use. The central processing unit can read and write the address space allocated to the first chip through these registers, thereby realizing data exchange between the central processing unit and the first chip.

[0047] It should be noted that hardware resources generally include memory area, input / output (IO) area and interrupts, etc. The first area in the memory management method of the present application mainly refers to the memory area, and the second area mainly refers to the IO area specified by the IO port address.

[0048] According to one embodiment of the present application, a partial area in the memory of the central processing unit is allocated as a first area to the first chip as the memory area of ​​the first chip, including: in the process of running the electronic device boot system, enabling the bus interface memory area reserved in the memory of the central processing unit; mapping the bus interface memory area to at least one physical memory area; and allocating the bus interface memory area as the first area to the bus interface connected to the first chip as the memory area of ​​the first chip.

[0049] The electronic device boot system mainly refers to the program used to perform power-on, hardware self-test, electronic device initialization operations and start the operating system. For example, the UEFI system boot program or BIOS system boot program used by personal computers.

[0050] Generally, when an electronic device boots up a system, a reserved bus interface memory area can be enabled; then, the bus interface memory area is mapped to at least one physical memory area through an address space register; then, the bus interface memory area can be allocated to a controller or peripheral connected to a bus for use. The at least one physical memory area can be continuous or discontinuous. In this way, the existing physical memory space can be fully utilized.

[0051] In this embodiment, a bus interface memory area reserved in the memory of the central processing unit is enabled during the operation of the electronic device boot system, and the area is allocated to the bus interface connected to the first chip to achieve allocation of part of the memory of the central processing unit to the first chip.

[0052] The bus interface connected to the first chip may be a low pin count interface (Low Pin Count, LPC) or an enhanced serial peripheral interface (Enhanced Serial Peripheral, eSPI).

[0053] According to an embodiment of the present application, mapping a bus interface memory area to at least one physical memory area includes: mapping the bus interface memory to at least one physical memory area by specifying a memory address and size.

[0054] The mapping can be achieved through the decode operation of the bus interface memory area mapping register, for example, the LPC interface general IO address space mapping register (LPC I / F Generic Decode Range Register) or the eSPI PCI configuration register (eSPIConfiguration Registers). The decode operation here is equivalent to mapping and authorization, that is, mapping the bus interface memory to at least one physical memory area and authorizing the bus interface to use it.

[0055] Usually, the bus interface memory region mapping register has three domain values. The first domain value is the enable bit (enable); the second domain value is the base address; and the next domain value is the mask bit of the mapping size. The bus interface memory can be mapped to at least one physical memory region through the base address and mapping size (i.e., memory address and size).

[0056] Among them, the base address and mapping size can be specified.

[0057] According to one embodiment of the present application, the first chip is connected to the bus interface through an embedded controller, and accordingly, the bus interface memory area is allocated as a first area to the bus interface connected to the first chip to serve as the memory area of ​​the first chip, including: allocating the bus interface memory area as a first area to the bus interface connected to the embedded controller to serve as the memory area of ​​the first chip.

[0058] Among them, the embedded controller (EC) is a chip mounted under the south bridge 202, corresponding to the super input and output (super IO) in the desktop computer. It is mainly responsible for powering on and off the portable notebook computer, managing battery charging and discharging, scanning keyboard keys, processing Touchpad data, obtaining CPU temperature in real time to control fan speed, and controlling some LED lights of the notebook computer.

[0059] When the electronic device is a portable notebook computer, the first chip is usually not directly connected to the notebook computer through a bus, but is usually connected to the portable notebook computer through an embedded controller.

[0060] According to one embodiment of the present application, a bus interface memory area is allocated as a first area to a bus interface connected to an embedded controller to serve as a memory area of ​​a first chip, including: mapping the first area as a shadow memory area of ​​the embedded controller; granting the first chip permission to access the shadow memory area so that the shadow memory area serves as the memory area of ​​the first chip.

[0061] The shadow memory area refers to a physical memory area that does not really exist, but is a virtual memory area mapped to the first area.

[0062] By mapping the first area to the shadow memory area of ​​the embedded controller, for the first chip, only the shadow memory area provided by the embedded controller is visible without having to worry about the physical memory area (ie, the first area) mapped by the shadow memory area, which makes implementation simpler.

[0063] The above embodiments are all for Figure 1 The basic embodiment shown is further expanded and refined. The implementer can also combine the implementation methods of the above-mentioned multiple embodiments to form a new embodiment according to specific implementation conditions.

[0064] Figures 2 to 3 Another embodiment of the memory management method of the present application is shown in FIG. 1 , which combines the implementation methods of the above-mentioned multiple embodiments and achieves a good implementation effect. This embodiment is applied to Figure 2In the portable notebook computer 20 shown in the figure, the first chip 203 is connected to the embedded controller 201 through a high-speed internal connection bus (Quik Path Interconnect, QPI), and is connected to the bus interface (e.g., eSPI) through the embedded controller 201. At this time, the eSPI PCI configuration register (in Figure 2 The decode operation (not shown) maps the bus interface memory 2041 in the addressing space 204 to a memory area in the physical memory 205, for example, the memory block 2051 and the memory block 2052, and allocates the bus interface memory 2041 to the embedded controller 201 for use.

[0065] Specifically, Figure 3 As shown, this embodiment uses the BIOS system boot program to complete the following operations, thereby allocating the bus interface memory area 204 to the embedded controller 201 for use:

[0066] Step S310, configuring the addressing space;

[0067] This step is a routine operation of the BIOS system boot program, which usually allocates the reserved fixed-address physical memory area, input / output ports and interrupts to the corresponding interfaces, controllers or peripherals according to pre-settings.

[0068] Step S320, enabling the bus interface memory area;

[0069] Set the enable bit of the eSPI PCI configuration register to 1 according to user configuration.

[0070] It should be noted that the enable bit of the eSPI PCI configuration register defaults to 0. If the BIOS system boot program is required to set the enable bit of the eSPI PCI configuration register to 1, the BIOS configuration needs to be actively modified to set it to "enable".

[0071] Step S330, decoding the designated access address and size as the memory of the first chip.

[0072] The memory address (usually the base address) and size of the memory block 2051 and the memory block 2052 are specified, and the bus interface memory 2041 in the addressing space 204 is mapped to the memory block 2051 and the memory block 2052 through the decoding operation of the eSPI PCI configuration register on the south bridge 202.

[0073] The above functions can be implemented through BIOS programming, and receive the memory address (usually the base address) and size as parameters to set the physical memory area to be mapped, where the base address needs to be within the memory range reserved for the bus interface memory, and the size cannot exceed the space reserved for the bus interface memory (currently, the maximum space reserved for the X86 system is 4GB).

[0074] Afterwards, the first chip 203 can obtain more physical memory space by mapping the chip memory 2031 to the memory of the embedded controller 201 (ie, the bus interface memory area 204 ), that is, the memory block 2051 and the memory block 2052 are used as the memory area of ​​the first chip 203 .

[0075] It should be noted that Figures 2 to 3 The embodiments shown are only exemplary descriptions of the memory method of the present application, and are not intended to limit the implementation methods and application scenarios. The implementer may adopt any applicable implementation method and apply it to any applicable application scenario according to specific implementation conditions.

[0076] Furthermore, the embodiment of the present application also provides a memory management device, which is applied to an electronic device, wherein the electronic device includes a first chip and a central processing unit, such as Figure 4 As shown, the device 40 includes: a memory area allocation module 401, which is used to allocate a part of the area in the memory of the central processing unit as a first area to the first chip as the memory area of ​​the first chip; a memory area setting module 402, which is used to set the first area so that the central processing unit does not use the first area.

[0077] According to an embodiment of the present application, the device 40 further includes: an input / output region allocation module, configured to allocate a portion of the input / output region of the central processing unit as a second region to the first chip for data exchange between the first chip and the central processing unit.

[0078] According to one embodiment of the present application, the memory area allocation module 401 includes: a bus interface memory area enabling submodule, which is used to enable the bus interface memory area reserved in the memory of the central processing unit during the process of running the electronic device boot system; a physical memory area mapping submodule, which is used to map the bus interface memory area to at least one physical memory area; and a memory area allocation submodule, which is used to allocate the bus interface memory area as a first area to the bus interface connected to the first chip as the memory area of ​​the first chip.

[0079] According to an embodiment of the present application, the physical memory area mapping submodule is specifically used to map the bus interface memory to at least one physical memory area by specifying the memory address and size.

[0080] According to one embodiment of the present application, the first chip is connected to the bus interface through an embedded controller. Accordingly, the memory area allocation module 401 is specifically used to allocate the bus interface memory area as the first area to the bus interface connected to the embedded controller to serve as the memory area of ​​the first chip.

[0081] According to one embodiment of the present application, the memory area allocation module 401 includes: a shadow memory area mapping submodule, used to map the first area as a shadow memory area of ​​the embedded controller; a shadow memory area authorization submodule, used to grant the first chip permission to access the shadow memory area so that the shadow memory area serves as the memory area of ​​the first chip.

[0082] In addition, an embodiment of the present application also provides an electronic device for executing any of the above memory management methods, such as Figure 5 As shown, the electronic device 50 includes: a central processing unit 501; a memory 502 of the central processing unit; an embedded controller 503 connected to the central processing unit via a bus interface; and a first chip 504 connected to the embedded controller via a high-speed internal connection bus interface; wherein a portion of the area in the memory 502 of the central processing unit is allocated as a first area to the first chip 504 as a memory area of ​​the first chip.

[0083] According to an embodiment of the present application, the embedded controller includes an embedded controller connected to a central processing unit via an enhanced serial peripheral interface eSPI.

[0084] It should be noted that, in actual applications, the embedded controller is usually not directly connected to the central processing unit, but is connected to the south bridge and establishes a connection with the central processing unit through the south bridge.

[0085] Among them, eSPI as an enhanced serial peripheral interface has the following advantages: 1) external sideband signals are reduced and converted into in-band signals, with fewer pins; 2) IO is changed to 1.8V, with lower power consumption; 3) it supports multiple clock rates and variable bandwidth.

[0086] According to an embodiment of the present application, the first chip includes a first chip connected to the embedded controller through a high-speed internal connection bus interface QPI.

[0087] The embedded controller is connected to the first chip via a high-speed internal connection bus interface QPI, which can make the data transmission speed between the embedded controller and the first chip faster, thereby speeding up the first chip's access to the physical memory area in the memory mapped by its memory and the central processing unit through the embedded controller.

[0088] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, the storage medium comprising a set of computer-executable instructions, which are used to execute any one of the above-mentioned memory management methods when the instructions are executed.

[0089] It should be pointed out here that the above description of the memory management device embodiment, the above description of the electronic device embodiment, and the above description of the computer-readable storage medium embodiment are similar to the description of the aforementioned method embodiment, and have similar beneficial effects as the aforementioned method embodiment, so they are not described in detail. For the technical details of the description of the memory management device embodiment, the description of the electronic device embodiment, and the description of the computer-readable storage medium embodiment that have not been disclosed in this application, please refer to the description of the aforementioned method embodiment of this application for understanding, and in order to save space, they are not described in detail.

[0090] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0091] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another device, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0092] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0093] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0094] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage medium, read-only memory (ROM), disk or optical disk, etc. Various media that can store program codes.

[0095] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly reflected in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage media, ROM, magnetic disks or optical disks.

[0096] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory management method, applied to an electronic device, wherein the electronic device comprises a first chip and a central processing unit, and the method comprises: In the process of running the electronic device boot system, enabling a bus interface memory area reserved in a memory connected to the central processing unit; Mapping the bus interface memory area to at least one physical memory area; allocating the bus interface memory area as a first area to a bus interface connected to the first chip to serve as a memory area of ​​the first chip; The first area is set so that the central processing unit does not use the first area.

2. The method according to claim 1, further comprising: A partial area of ​​the input and output of the central processing unit is allocated to the first chip as a second area for data exchange between the first chip and the central processing unit.

3. The method according to claim 1, wherein mapping the bus interface memory area to at least one physical memory area comprises: The bus interface memory is mapped to at least one physical memory area by specifying a memory address and a size.

4. The method according to claim 1, wherein the first chip is connected to the bus interface via an embedded controller, Correspondingly, allocating the bus interface memory area as the first area to the bus interface connected to the first chip to serve as the memory area of ​​the first chip includes: The bus interface memory area is allocated as a first area to a bus interface connected to the embedded controller to serve as a memory area of ​​the first chip.

5. The method according to claim 4, wherein allocating the bus interface memory area as a first area to a bus interface connected to the embedded controller to serve as a memory area of ​​the first chip comprises: Mapping the first area as a shadow memory area of ​​the embedded controller; The first chip is granted permission to access the shadow memory area, so that the shadow memory area serves as the memory area of ​​the first chip.

6. A memory management device, applied to an electronic device, the electronic device comprising a first chip and a central processing unit, the device comprising: The memory area allocation module includes: a bus interface memory area enabling submodule, which is used to enable the bus interface memory area reserved in the memory connected to the central processing unit during the operation of the electronic device boot system; a physical memory area mapping submodule, which is used to map the bus interface memory area to at least one physical memory area; and a memory area allocation submodule, which is used to allocate the bus interface memory area as a first area to the bus interface connected to the first chip, so as to serve as the memory area of ​​the first chip. The memory area setting module is used to set the first area so that the central processing unit does not use the first area.

7. An electronic device, configured to execute the method according to claim 1, the electronic device comprising: CPU; a memory connected to the central processing unit; An embedded controller connected to the central processing unit via a bus interface; A first chip connected to the embedded controller via a high-speed internal connection bus interface; Part of the area in the memory connected to the central processing unit is allocated as a first area to the first chip as a memory area of ​​the first chip. 8 . The electronic device according to claim 7 , wherein the embedded controller comprises an embedded controller connected to the central processing unit via an enhanced serial peripheral interface (eSPI). 9 . The electronic device according to claim 7 , wherein the first chip comprises a first chip connected to the embedded controller via a high-speed internal connection bus interface (QPI).

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