Display device

Abstract

The present invention relates to a display device. A display device according to an embodiment includes: a substrate; gate lines located on the substrate; data lines intersecting the gate lines; pixels connected to the gate lines and the data lines; and dummy data lines located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy data lines include openings located in portions adjacent to the overlapping portions with the gate lines, and portions of the dummy data lines on both sides of the openings of the dummy data lines are electrically insulated from each other.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] As a device for displaying a display screen, display devices include liquid crystal display devices (LCD: Liquid Crystal Display), organic light emitting display devices (OLED: Organic Light Emitting Diode), and the like. Such display devices are used in various electronic devices such as mobile phones, navigators, digital cameras, e-books, portable game consoles, or various terminals.

[0003] A display device may include various wirings located in different layers. These wirings may be insulated by an insulating film. The display device may be manufactured through multiple processes such as deposition and etching, and defects may occur during these processes. For example, a defect may occur where wirings designed to be located in different layers and electrically insulated are electrically connected to each other.

[0004] Inspections for detecting such defects are carried out at multiple stages. In cases where a defect is not detected in the initial stage but is detected in the later stage and the product is discarded, there is a problem of increased cost loss. This may be the case where a defect has occurred in the initial stage but is missed because it is not detected during the inspection. Or, it may be the case where no defect has occurred in the initial stage, but a defect occurs after a high voltage stress test or other processes. Summary of the Invention

[0005] An embodiment is for providing a display device capable of preventing a short circuit defect between wirings located in different layers in a part of an area.

[0006] A display device according to an embodiment includes: a substrate; gate lines located on the substrate; data lines intersecting the gate lines; pixels connected to the gate lines and the data lines; and dummy data lines located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy data lines include openings located in portions adjacent to an overlapping portion with the gate lines, and portions of the dummy data lines on both sides of the openings of the dummy data lines are electrically insulated from each other.

[0007] The openings of the dummy data lines may include: an upper opening located above the overlapping portion with the gate lines in a plane; and a lower opening located below the overlapping portion with the gate lines in a plane.

[0008] The number of the openings of the dummy data lines may be more than the number of the gate lines.

[0009] The number of openings of the dummy data lines may be twice the number of the gate lines.

[0010] The display device according to an embodiment may further include: a gate insulating film disposed between the gate line and the data line and between the gate line and the dummy data line, wherein the gate line and the data line overlap each other with the gate insulating film therebetween, and the gate line and the dummy data line overlap each other with the gate insulating film therebetween.

[0011] The gate line may extend in a first direction, the data line extends in a second direction perpendicular to the first direction, and the dummy data line extends in the second direction.

[0012] The display device according to an embodiment may further include: dummy pixels located at an edge portion on the substrate and between the data line and the dummy data line, wherein the dummy pixels are set to a floating state.

[0013] The dummy data line may be set to a floating state.

[0014] The display device may include multiple gate lines, multiple data lines, and multiple pixels. The multiple pixels are arranged in a matrix form. Each gate line is connected to the pixels in the same row among the multiple pixels, and each data line is alternately connected to the pixels on the left side and the pixels on the right side of the data line among the multiple pixels.

[0015] Data voltages with different polarities may be applied to the adjacent data lines among the multiple data lines.

[0016] The display device according to an embodiment may further include: a dummy reference voltage line located at an edge portion on the substrate and intersecting with the gate line, wherein the dummy reference voltage line includes an opening portion located in a part adjacent to the overlapping portion with the gate line, and the parts of the dummy reference voltage line on both sides of the opening portion of the dummy reference voltage line are electrically insulated from each other.

[0017] The data line may include a first data line and a second data line, the dummy data line includes a first dummy data line and a second dummy data line, and the first dummy data line and the second dummy data line respectively include opening portions located in parts adjacent to the overlapping portions with the gate line.

[0018] A display device according to an embodiment may include: a substrate; gate lines located on the substrate; data lines and reference voltage lines intersecting the gate lines; pixels connected to the gate lines, the data lines, and the reference voltage lines; and dummy reference voltage lines located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy reference voltage lines include openings in portions adjacent to the overlapping portions with the gate lines, and portions of the dummy reference voltage lines on both sides of the openings of the dummy reference voltage lines are electrically insulated from each other.

[0019] A display device according to an embodiment may further include: dummy data lines located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy reference voltage lines are located between the dummy data lines and the data lines.

[0020] The dummy data lines may include openings in portions adjacent to the overlapping portions with the gate lines, and portions of the dummy data lines on both sides of the openings of the dummy data lines are electrically insulated from each other.

[0021] A display device according to an embodiment may further include: dummy pixels located at an edge portion on the substrate and between the data lines and the dummy data lines, wherein the dummy pixels are set to a floating state.

[0022] The dummy reference voltage lines and the dummy data lines may be set to a floating state.

[0023] The openings of the dummy reference voltage lines may include: an upper opening located above the overlapping portion with the gate lines in a plane; and a lower opening located below the overlapping portion with the gate lines in a plane.

[0024] A display device according to an embodiment includes: a substrate; gate lines and data lines located on the substrate and intersecting each other; a reference voltage line located on the substrate and applied with a constant voltage; a first transistor and a second transistor connected to the gate lines and the data lines; a third transistor connected to the gate lines, the second transistor, and the reference voltage line; a first sub-pixel electrode connected to the first transistor; a second sub-pixel electrode connected to the second transistor; and dummy data lines located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy data lines include openings in portions adjacent to the overlapping portions with the gate lines, and portions of the dummy data lines on both sides of the openings of the dummy data lines are electrically insulated from each other.

[0025] The display device according to an embodiment may further include: dummy reference voltage lines located at an edge portion of the substrate and intersecting the gate lines, wherein the dummy reference voltage lines include openings located in portions adjacent to the overlapping portions with the gate lines, and portions of the dummy reference voltage lines located on both sides of the openings of the dummy reference voltage lines are electrically insulated from each other.

[0026] According to an embodiment, even if a short circuit occurs between wirings located in different layers in a part of the display device, it is possible to prevent defects resulting therefrom, thereby saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram of a display device according to an embodiment.

[0028] Figure 2 is with Figure 1 The equivalent circuit diagram of a pixel is illustrated together with the structure of the display device shown.

[0029] Figure 3 is a diagram showing the connection relationship between a pixel and signal lines of a display device according to an embodiment.

[0030] Figure 4 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0031] Figure 5 is showing Figure 4 The plan view of a pixel shown and dummy pixels adjacent thereto.

[0032] Figure 6 is along Figure 5 The cross-sectional view shown along the VI-VI line.

[0033] Figure 7 is along Figure 5 The cross-sectional view shown along the VII-VII line.

[0034] Figure 8 is along Figure 5 The cross-sectional view shown along the VIII-VIII line.

[0035] Figure 9 is along Figure 5 The cross-sectional view shown along the IX-IX line.

[0036] Figure 10 is a plan view showing a display device according to an embodiment.

[0037] Figure 11 is a plan view showing a display device according to an embodiment.

[0038] Figure 12It is a plan view showing a display device according to an embodiment.

[0039] Figure 13 It is a plan view showing a display device according to an embodiment.

[0040] Figure 14 It is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0041] Figure 15 It shows Figure 14 A plan view of a pixel shown.

[0042] Figure 16 It is a plan view of a dummy pixel of a display device according to an embodiment.

[0043] Explanation of reference numerals

[0044] 121: Gate line 171: Data line

[0045] 171a: First data line 171b: Second data line

[0046] 171d: Dummy data line 171da: First dummy data line

[0047] 171db: Second dummy data line 172: Reference voltage line

[0048] 172d: Dummy reference voltage line 191: Pixel electrode

[0049] 191a: First sub-pixel electrode 191b: Second sub-pixel electrode

[0050] 191d: Dummy pixel electrode 191da: First dummy sub-pixel electrode

[0051] 191db: Second dummy sub-pixel electrode

[0052] 911: Upper opening of the dummy data line

[0053] 912: Lower opening of the dummy data line

[0054] 921: Upper opening of the first dummy data line

[0055] 922: Lower opening of the first dummy data line

[0056] 951: Upper opening of the dummy reference voltage line

[0057] 952: Lower opening of the dummy reference voltage line

[0058] 961: Upper opening of the second dummy data line

[0059] 962: Lower opening of the second dummy data line Detailed implementation mode

[0060] Hereinafter, multiple embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those with basic knowledge in the technical field to which the present invention belongs can easily implement it. The present invention can be implemented in a variety of different forms and is not limited to the embodiments described herein.

[0061] To clearly illustrate the present invention, parts irrelevant to the description are omitted, and throughout the specification, the same or similar constituent elements are given the same reference numerals.

[0062] Moreover, for ease of explanation, the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown, so the present invention is not necessarily limited to the illustrated content. In the drawings, the thicknesses are enlarged to clearly show multiple layers and regions. Also, in the drawings, the thicknesses of some layers and regions are exaggerated for ease of explanation.

[0063] Moreover, when referring to a part such as a layer, film, region, plate, etc. being "above" or "on" another part, it includes not only the case where it is "immediately above" the other part, but also the case where there are other parts in between. In contrast, when referring to a part being "immediately above" another part, it means there are no other parts in between. And the so-called being "above" or "on" the reference part means being above or below the reference part, and does not necessarily mean being "above" or "on" in the direction opposite to gravity.

[0064] Moreover, throughout the specification, when referring to a part "including" a certain constituent element, without particularly contrary description, it does not mean excluding other constituent elements, but means that other constituent elements may also be included.

[0065] Moreover, throughout the specification, when referring to "on a plane", this means observing the object part from above, and when referring to "in a cross-section", this means observing the cross-section obtained by vertically cutting the object part from the side.

[0066] First, refer to Figure 1 and Figure 2 The description of the display device according to an embodiment is as follows.

[0067] Figure 1 is a block diagram of a display device according to an embodiment, Figure 2 is Figure 1 The equivalent circuit diagram of a pixel is illustrated together with the structure of the display device shown.

[0068] As Figure 1As shown, a display device according to an embodiment includes: a liquid crystal panel assembly 300; and a gate driving unit 400, a data driving unit 500, which are connected to the liquid crystal panel assembly 300; a grayscale voltage generation unit 800, which is connected to the data driving unit 500; and a signal control unit 600, which controls the above components.

[0069] Viewed from the equivalent circuit, the liquid crystal panel assembly 300 includes a plurality of signal lines (not shown) and a plurality of pixels PX connected thereto and arranged in a row-and-column pattern. dummy pixels dPX may also be arranged at both side edge portions of the liquid crystal panel assembly 300. For example, a plurality of dummy pixels dPX may be arranged in the column direction at the left edge portion and the right edge portion of the liquid crystal panel assembly 300.

[0070] From Figure 2 Viewed from the structure shown, the liquid crystal panel assembly 300 includes a thin film transistor display panel 100 and a counter display panel 200 facing each other and a liquid crystal layer 3 disposed therebetween.

[0071] The signal lines include a plurality of gate lines (not shown) for transmitting a gate signal Vg (also referred to as a “scan signal”) and a plurality of data lines (not shown) for transmitting a data voltage Vd. The gate lines extend substantially in the row direction and are substantially parallel to each other, and the data lines extend substantially in the column direction and are substantially parallel to each other.

[0072] Each pixel PX may include a pair of sub-pixels, and each sub-pixel may include liquid crystal capacitors Clca, Clcb. At least one of the two sub-pixels may include a switching element (not shown) connected to the gate line, the data line, and the liquid crystal capacitors Clca, Clcb.

[0073] The liquid crystal capacitors Clca, Clcb use the first sub-pixel electrode PEa and the second sub-pixel electrode PEb of the thin film transistor display panel 100 and the common electrode CE of the counter display panel 200 as two terminals, and the liquid crystal layer 3 between the first sub-pixel electrode PEa and the second sub-pixel electrode PEb and the common electrode CE functions as a dielectric. The first sub-pixel electrode PEa and the second sub-pixel electrode PEb are separated from each other and constitute a pixel electrode PE. The common electrode CE may be formed on the front surface of the counter display panel 200 and may receive a common voltage Vcom. The liquid crystal layer 3 may have negative dielectric anisotropy.

[0074] In addition, in order to achieve color display, each pixel PX can be fixed to display one of the primary colors (spatial division), or each pixel PX can alternately display the primary colors according to time (time division), so as to identify the desired color by using the spatial and temporal sums of these primary colors. The primary colors can be, for example, the three primary colors such as red, green, and blue. Figure 2 As an example of spatial division, it is shown that each pixel PX is equipped with a color filter CF that displays one of the primary colors in the area of the opposing display panel 200. Figure 2 Different from this, the color filter CF can also be formed above or below the first sub-pixel electrode PEa and the second sub-pixel electrode PEb of the thin-film transistor display panel 100.

[0075] At least one polarizing plate (not shown) that polarizes light can be attached to the outer surface of the liquid crystal display panel assembly 300.

[0076] Refer to again Figure 1 , the grayscale voltage generation unit 800 generates an overall grayscale voltage or a limited number of grayscale voltages (referred to as "reference grayscale voltages") related to the transmittance of the pixel PX. Relative to the common voltage Vcom, the (reference) grayscale voltage can include cases with positive values and cases with negative values.

[0077] The gate driving unit 400 is connected to the gate lines of the liquid crystal display panel assembly 300, and thus applies a gate signal Vg composed of a combination of a gate conduction voltage Von and a gate cut-off voltage Voff to the gate lines.

[0078] The data driving unit 500 is connected to the data lines of the liquid crystal display panel assembly 300, selects the grayscale voltage generated by the grayscale voltage generation unit 800, and applies it as a data voltage Vd to the data lines. However, when the grayscale voltage generation unit 800 only provides a predetermined number of reference grayscale voltages instead of providing voltages for all grayscales, the data driving unit 500 divides the reference grayscale voltages to generate grayscale voltages for the entire grayscale, and selects the data voltage Vd therefrom.

[0079] The signal control unit 600 can control the gate driving unit 400, the data driving unit 500, etc.

[0080] These driving devices 400, 500, 600, 800 can be directly mounted on the liquid crystal display panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown) and attached to the liquid crystal display panel assembly 300 in the form of a tape carrier package (TCP), or mounted on a separate printed circuit board (not shown). In contrast, these driving devices 400, 500, 600, 800 can also be integrated with signal lines, switching elements, etc. into the liquid crystal display panel assembly 300. Moreover, the driving devices 400, 500, 600, 800 can be integrated into a single chip. In this case, at least one of them or at least one circuit element constituting it can be located outside the single chip.

[0081] Next, with further reference to Figure 3 , the connection relationship between a plurality of pixels and signal lines and dummy pixels in a display device according to an embodiment will be further described.

[0082] Figure 3 FIG. is a diagram showing the connection relationship between pixels and signal lines in a display device according to an embodiment. Figure 3 FIG. shows a part of the plurality of pixels in a display device according to an embodiment, and particularly shows pixels adjacent to a part of the dummy pixels located at the left edge portion of the display device and the signal lines connected thereto.

[0083] A plurality of gate lines GL include a first gate line G1, a second gate line G2, a third gate line G3, a fourth gate line G4, a fifth gate line G5, etc. that extend substantially in the row direction. A plurality of data lines DL include a first data line D1, a second data line D2, a third data line D3, a fourth data line D4, a fifth data line D5, a sixth data line D6, a seventh data line D7, etc. that intersect the gate lines GL and extend substantially in the column direction. The dummy data line dDL is arranged adjacent to the outermost first data line D1 among the plurality of data lines DL.

[0084] The plurality of pixels PX can be arranged substantially in a matrix form in the row direction and the column direction. Each pixel PX is connected to the gate line GL and the data line DL. The gate lines GL are respectively connected to the pixels PX located in the same row among the plurality of pixels PX. For example, the first gate line G1 is connected to the pixels PX located in the first row, the second gate line G2 is connected to the pixels PX located in the second row, and the third gate line G3 is connected to the pixels PX located in the third row.

[0085] The data line DL is alternately connected to the pixels PX on the left side and the pixels PX on the right side of the data line DL among multiple pixels PX. For the first data line D1, it is connected to the pixels PX located in the second row and the fourth row among the pixels PX in the first column. For the second data line D2, it is connected to the pixels PX located in the first row, the third row, and the fifth row among the pixels PX in the first column, and is also connected to the pixels PX located in the second row and the fourth row among the pixels PX in the second column. For the third data line D3, it is connected to the pixels PX located in the first row, the third row, and the fifth row among the pixels PX in the second column, and is also connected to the pixels PX located in the second row and the fourth row among the pixels PX in the third column.

[0086] The dummy pixel dPX can be arranged adjacent to the pixels PX in the first column. The dummy pixel dPX can be located between the dummy data line dDL and the data line DL. At this time, the dummy pixel dPX can be located between the dummy data line dDL and the first data line D1. The dummy pixel dPX can be arranged in the column direction. The dummy pixel dPX is not connected to the gate line GL, the data line DL, and the dummy data line dDL. The dummy pixel dPX is set to a floating state.

[0087] The gate line GL can be applied with a gate signal, and the data line DL can be applied with a data voltage. The data voltage can be composed of a positive polarity and a negative polarity. The dummy data line dDL is not applied with a signal. The dummy data line dDL is set to a floating state.

[0088] A part of the data lines DL can be applied with a data voltage of positive polarity, and another part of the data lines DL can be applied with a data voltage of negative polarity. At this time, the data lines DL adjacent to each other can be applied with data voltages of different polarities. For example, the first data line D1, the third data line D3, the fifth data line D5, and the seventh data line D7 can be applied with a data voltage of positive polarity, and the second data line D2, the fourth data line D4, and the sixth data line D6 can be applied with a data voltage of negative polarity. And, in the next frame, conversely, the first data line D1, the third data line D3, the fifth data line D5, and the seventh data line D7 can be applied with a data voltage of negative polarity, and the second data line D2, the fourth data line D4, and the sixth data line D6 can be applied with a data voltage of positive polarity. At this time, the data line DL is not only connected to the pixels PX in the same column, but is alternately connected to the pixels PX on the left and right sides, so the pixels PX in the same column can have different polarities. That is, the effect of dot inversion can be achieved through column inversion driving.

[0089] In this structure, when the capacitances of the data lines on both sides of the pixel PX located in the same column are asymmetric, defects caused by changes in RC delay may be recognized. In the display device according to an embodiment, by arranging the dummy data line dDL adjacent to the pixel PX located at the edge portion (for example, the pixel PX located in the first column), the capacitances on the left and right sides can be made symmetric. Also, when performing processes such as exposure, for the outermost pattern, defects such as being formed thinner may occur. In the display device according to an embodiment, by arranging the dummy data line dDL and the dummy pixel dPX at both edge portions, such abnormal defects of the pattern can be prevented.

[0090] Next, further reference will be made to Figure 4 to further describe the display device according to an embodiment.

[0091] Figure 4 is an equivalent circuit diagram of one pixel of the display device according to an embodiment.

[0092] The display device according to an embodiment includes a plurality of signal lines GL, DL, RL and a plurality of pixels PX connected thereto.

[0093] The signal lines GL, DL, RL include a gate line GL for transmitting a gate signal, a data line DL for transmitting a data voltage, and a reference voltage line RL for applying a constant voltage.

[0094] A first switching element T1 and a second switching element T2 connected to the same gate line GL and the same data line DL are formed. Also, a third switching element T3 is formed, which is connected to the first switching element T1 and the second switching element T2 on the same gate line GL and is connected to the second switching element T2 and the reference voltage line RL. The first switching element T1, the second switching element T2, and the third switching element T3 may be formed of a thin film transistor or the like.

[0095] Each pixel PX includes two sub-pixels PXa, PXb. A first liquid crystal capacitor Clca connected to the first switching element T1 is formed in the first sub-pixel PXa, and a second liquid crystal capacitor Clcb connected to the second switching element T2 is formed in the second sub-pixel PXb.

[0096] A first terminal of the first switching element T1 is connected to the gate line GL, a second terminal of the first switching element T1 is connected to the data line DL, and a third terminal of the first switching element T1 is connected to the first liquid crystal capacitor Clca. At this time, the third terminal of the first switching element T1 may be connected to the first sub-pixel electrode PEa constituting the first liquid crystal capacitor Clca.

[0097] The first terminal of the second switching element T2 is connected to the gate line GL, the second terminal of the second switching element T2 is connected to the data line DL, and the third terminal of the second switching element T2 is connected to the second liquid crystal capacitor Clcb. At this time, the third terminal of the second switching element T2 may be connected to the second sub-pixel electrode PEb that constitutes the second liquid crystal capacitor Clcb.

[0098] The first terminal of the third switching element T3 is connected to the gate line GL, the second terminal is connected to the reference voltage line RL, and the third terminal is connected to the third terminal of the second switching element T2.

[0099] Observing the operation of the display device according to an embodiment, if a gate-on voltage is applied to the gate line GL, the first switching element T1, the second switching element T2, and the third switching element T3 connected thereto are turned on, and the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb are charged with the data voltage transmitted through the data line DL.

[0100] At this time, since the third switching element T3 is in the on state, the data voltage transmitted to the second sub-pixel PXb through the data line DL is divided by the third switching element T3 connected in series with the second switching element T2. At this time, the voltage is distributed according to the sizes of the channels of the second switching element T2 and the third switching element T3. Therefore, even if the data voltages transmitted to the first sub-pixel PXa and the second sub-pixel PXb through the data line DL are the same, the voltages charged in the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb are different from each other. That is, the voltage charged in the second liquid crystal capacitor Clcb is lower than the voltage charged in the first liquid crystal capacitor Clca. Therefore, the lateral visibility can be improved by changing the voltages charged in the first sub-pixel PXa and the second sub-pixel PXb within one pixel PX.

[0101] Next, with further reference to Figures 5 to 9 the display device according to an embodiment will be further described.

[0102] Figure 5 is a plan view showing Figure 4 one pixel shown in Figure 5 and the dummy pixel adjacent thereto. Figure 6 The pixel shown in Figure 5 may be a pixel located at the upper left corner of the display device, and the dummy pixel may be located on the left side of the pixel. Figure 7 is a cross-sectional view taken along the VI-VI line of Figure 5 is a cross-sectional view taken along the VII-VII line of Figure 8 is a cross-sectional view taken along the VIII-VIII line of Figure 5 is a cross-sectional view taken along the VIII-VIII line of Figure 9 is a cross-sectional view taken along the Figure 5The cross-sectional view shown by the IX-IX line.

[0103] First, the thin film transistor display panel 100 will be described as follows.

[0104] On the first substrate 110, gate lines 121 extending in the first direction and sustain electrode lines 131 may be arranged.

[0105] The gate lines 121 mainly extend in the row direction and may transmit a gate signal Vg. On the first substrate 110, a first gate electrode 124a and a second gate electrode 124b that are formed integrally with and connected to each other may be arranged. And, on the first substrate 110, a third gate electrode 124c may be formed integrally with the gate line 121 and arranged adjacent to the first gate electrode 124a and the second gate electrode 124b. The first gate electrode 124a, the second gate electrode 124b, and the third gate electrode 124c may be connected to the same gate line 121 and be applied with the same gate signal.

[0106] The sustain electrode lines 131 extend in a direction substantially parallel to the gate lines 121, and a constant sustain voltage may be applied to the sustain electrode lines 131. On the first substrate 110, sustain electrodes 133 protruding from the sustain electrode lines 131 may be arranged. The sustain electrodes 133 may have a shape protruding upward from the sustain electrode lines 131 on a plane. The sustain electrodes 133 may be formed to surround an edge portion of a first sub-pixel electrode 191a, which will be described later, and may overlap with a reference voltage line 172.

[0107] On the first substrate 110, a first dummy gate electrode 124da and a second dummy gate electrode 124db that are formed integrally with and connected to each other may be arranged. And, on the first substrate 110, a third dummy gate electrode 124dc may be formed integrally with the gate line 121 and arranged adjacent to the first dummy gate electrode 124da and the second dummy gate electrode 124db.

[0108] The gate lines 121, the first gate electrode 124a, the second gate electrode 124b, the third gate electrode 124c, the sustain electrode lines 131, the first dummy gate electrode 124da, the second dummy gate electrode 124db, and the third dummy gate electrode 124dc may be formed in the same process and may be located in the same layer, and these will be referred to as a gate conductor. On the gate conductor, a gate insulating film 140 may be arranged. The gate insulating film 140 may be formed of an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO x ). And, the gate insulating film 140 may be formed of a single-layer film or a multi-layer film.

[0109] On the gate insulating film 140, a first semiconductor 154a, a second semiconductor 154b, and a third semiconductor 154c may be disposed. The first semiconductor 154a, the second semiconductor 154b, and the third semiconductor 154c may be formed of amorphous silicon, polysilicon, or an oxide semiconductor material. The first semiconductor 154a may overlap with the first gate electrode 124a, the second semiconductor 154b may overlap with the second gate electrode 124b, and the third semiconductor 154c may overlap with the third gate electrode 124c.

[0110] Moreover, on the gate insulating film 140, a first dummy semiconductor 154da, a second dummy semiconductor 154db, and a third dummy semiconductor 154dc may be disposed. The first dummy semiconductor 154da may overlap with the first dummy gate electrode 124da, the second dummy semiconductor 154db may overlap with the second dummy gate electrode 124db, and the third dummy semiconductor 154dc may overlap with the third dummy gate electrode 124dc.

[0111] On the first semiconductor 154a, the second semiconductor 154b, the third semiconductor 154c, and the gate insulating film 140, a data line 171, a reference voltage line 172, a first source electrode 173a, a first drain electrode 175a, a second source electrode 173b, a second drain electrode 175b, a third source electrode 173c, and a third drain electrode 175c may be disposed.

[0112] The first semiconductor 154a, the second semiconductor 154b, and the third semiconductor 154c may be located not only above the first gate electrode 124a, the second gate electrode 124b, and the third gate electrode 124c but also below the data line 171. Moreover, the second semiconductor 154b and the third semiconductor 154c may be connected to each other. However, this embodiment is not limited thereto, and the first semiconductor 154a, the second semiconductor 154b, and the third semiconductor 154c may be located only above the first gate electrode 124a, the second gate electrode 124b, and the third gate electrode 124c, and the second semiconductor 154b and the third semiconductor 154c may be disposed separately from each other.

[0113] The data line 171 and the reference voltage line 172 extend in a second direction. The second direction is a direction intersecting the first direction and may be, for example, a direction perpendicular to the first direction.

[0114] The data line 171 mainly extends in the column direction, intersects the gate line 121, and may transmit a data voltage Vd.

[0115] The reference voltage line 172 extends in a direction substantially parallel to the data line 171, and a constant reference voltage can be applied to the reference voltage line 172. The reference voltage line 172 can be located between two adjacent data lines 171. The reference voltage line 172 can overlap with the pixel electrode 191, and in particular, can be located at the center of the pixel electrode 191 and extend in the column direction. The reference voltage line 172 can be detoured in such a way as not to overlap with the third switching element T3 located between the first sub-pixel electrode 191a and the second sub-pixel electrode 191b. The reference voltage line 172 can overlap with the sustain electrode 133. The reference voltage applied to the reference voltage line 172 can be substantially the same as the sustain voltage applied to the sustain electrode 133.

[0116] The first source electrode 173a can protrude from the data line 171 and can overlap with the first gate electrode 124a. The first source electrode 173a can have a U-shaped form bent on the first gate electrode 124a.

[0117] The first drain electrode 175a can be arranged on the first gate electrode 124a to be separated from the first source electrode 173a. A channel is formed in the first semiconductor 154a of the portion exposed between the first source electrode 173a and the first drain electrode 175a which are separated from each other.

[0118] The second source electrode 173b can extend from the first source electrode 173a and overlap with the second gate electrode 124b. The second source electrode 173b can have a U-shaped form bent on the second gate electrode 124b.

[0119] The second drain electrode 175b can be arranged on the second gate electrode 124b to be separated from the second source electrode 173b. A channel is formed in the second semiconductor 154b of the portion exposed between the second source electrode 173b and the second drain electrode 175b which are separated from each other.

[0120] The third source electrode 173c can protrude from the reference voltage line 172 and overlap with the third gate electrode 124c.

[0121] The third drain electrode 175c can be connected to the second drain electrode 175b and can overlap with the third gate electrode 124c. The third drain electrode 175c can be arranged on the third gate electrode 124c to be separated from the third source electrode 173c. A channel is formed in the third semiconductor 154c of the portion exposed between the third source electrode 173c and the third drain electrode 175c which are separated from each other.

[0122] The first gate electrode 124a, the first semiconductor 154a, the first source electrode 173a, and the first drain electrode 175a described above constitute the first switching element T1. Further, the second gate electrode 124b, the second semiconductor 154b, the second source electrode 173b, and the second drain electrode 175b constitute the second switching element T2, and the third gate electrode 124c, the third semiconductor 154c, the third source electrode 173c, and the third drain electrode 175c constitute the third switching element T3.

[0123] On the first dummy semiconductor 154da, the second dummy semiconductor 154db, the third dummy semiconductor 154dc, and the gate insulating film 140, a dummy data line 171d, a dummy reference voltage line 172, a first dummy source electrode 173da, a first dummy drain electrode 175da, a second dummy source electrode 173db, a second dummy drain electrode 175db, a third dummy source electrode 173dc, and a third dummy drain electrode 175dc may be arranged.

[0124] The first dummy semiconductor 154da, the second dummy semiconductor 154db, and the third dummy semiconductor 154dc may be located not only above the first dummy gate electrode 124da, the second dummy gate electrode 124db, and the third dummy gate electrode 124dc but also below the dummy data line 171d. Further, the second dummy semiconductor 154db and the third dummy semiconductor 154dc may be connected to each other. However, the present embodiment is not limited thereto, and the first dummy semiconductor 154da, the second dummy semiconductor 154db, and the third dummy semiconductor 154dc may be located only above the first dummy gate electrode 124da, the second dummy gate electrode 124db, and the third dummy gate electrode 124dc, and the second dummy semiconductor 154db and the third dummy semiconductor 154dc may be arranged to be separated from each other.

[0125] The dummy data line 171d and the dummy reference voltage line 172d may extend in a direction substantially parallel to the data line 171 and the reference voltage line 172.

[0126] The dummy data line 171d may be arranged adjacent to the data line 171, mainly extend in the column direction, and cross the gate line 121. The dummy data line 171d is set to a floating state, and no signal is applied to the dummy data line 171d.

[0127] Dummy data line 171d includes openings 911 and 912 that are located in portions adjacent to the overlapping portion with gate line 121. The openings 911 and 912 of dummy data line 171d may include an upper opening 911 that is located on the upper side of the overlapping portion with gate line 121 in a plane and a lower opening 912 that is located on the lower side of the overlapping portion with gate line 121 in a plane. The portions of dummy data line 171d located on both sides with respect to openings 911 and 912 are separated from each other. For example, the portion of dummy data line 171d located above upper opening 911 is separated from the portion of dummy data line 171d located below upper opening 911. Also, the portion of dummy data line 171d located above lower opening 912 is separated from the portion of dummy data line 171d located below lower opening 912. Accordingly, the portions of dummy data line 171d located on both sides of openings 911 and 912 of dummy data line 171d are electrically insulated from each other.

[0128] Thus, since openings 911 and 912 of dummy data line 171d are located on the upper side and the lower side of the overlapping portion with gate line 121, the number of openings 911 and 912 of dummy data line 171d may be more than the number of gate lines 121. For example, the number of openings 911 and 912 of dummy data line 171d may be about twice the number of gate lines 121. However, this is merely an example, and the present embodiment is not limited thereto. Openings 911 and 912 of dummy data line 171d may also be formed to be adjacent to only a part of the overlapping portion with gate line 121, rather than being adjacent to all of the overlapping portions with gate line 121. Accordingly, the number of openings 911 and 912 of dummy data line 171d can be variably changed.

[0129] Dummy reference voltage line 172d may be disposed adjacent to data line 171, mainly extend in the column direction, and cross gate line 121. Dummy reference voltage line 172d may be located between data line 171 and dummy data line 171d. Dummy reference voltage line 172d is set to a floating state, and no signal is applied to dummy reference voltage line 172d. Dummy reference voltage line 172d may overlap with dummy pixel electrode 191d, and in particular, may be located at the center of dummy pixel electrode 191d and extend in the column direction.

[0130] Dummy reference voltage line 172d includes openings 951 and 952 located in and adjacent to the overlapping portion with gate line 121. Openings 951 and 952 of dummy reference voltage line 172d may include an upper opening 951 located on the upper side of the overlapping portion with gate line 121 in a plane and a lower opening 952 located on the lower side of the overlapping portion with gate line 121 in a plane. Portions of dummy reference voltage line 172d located on both sides with respect to openings 951 and 952 are separated from each other. For example, a portion of dummy reference voltage line 172d located above upper opening 951 is separated from a portion of dummy reference voltage line 172d located below upper opening 951. Also, a portion of dummy reference voltage line 172d located above lower opening 952 is separated from a portion of dummy reference voltage line 172d located below lower opening 952. Therefore, portions of dummy reference voltage line 172d located on both sides of openings 951 and 952 of dummy reference voltage line 172d are electrically insulated from each other.

[0131] Thus, since openings 951 and 952 of dummy reference voltage line 172d are located on the upper side and the lower side of the overlapping portion with gate line 121, the number of openings 951 and 952 of dummy reference voltage line 172d may be more than the number of gate lines 121. For example, the number of openings 951 and 952 of dummy reference voltage line 172d may be about twice the number of gate lines 121. However, this is merely an example, and the present embodiment is not limited thereto. Openings 911 and 912 of dummy reference voltage line 172d may also be formed to be adjacent to only a part of the overlapping portion with gate line 121, rather than being formed adjacent to all of the overlapping portions with gate line 121. Accordingly, the number of openings 951 and 952 of dummy reference voltage line 172d can be variously changed.

[0132] The first dummy source electrode 173da may protrude from the dummy data line 171d and overlap with the first dummy gate electrode 124da. The first dummy source electrode 173da may have a U-shaped bend on the first dummy gate electrode 124da.

[0133] The first dummy drain electrode 175da may be arranged on the first dummy gate electrode 124da to be spaced apart from the first dummy source electrode 173da.

[0134] The second dummy source electrode 173db may extend from the first dummy source electrode 173da and overlap with the second dummy gate electrode 124db. The second dummy source electrode 173db may have a U-shaped bend on the second dummy gate electrode 124db.

[0135] The second dummy drain electrode 175db may be disposed on the second dummy gate electrode 124db and spaced apart from the second dummy source electrode 173db.

[0136] The third dummy source electrode 173dc may protrude from the dummy reference voltage line 172d and overlap with the third dummy gate electrode 124dc.

[0137] The third dummy drain electrode 175dc may be connected to the second dummy drain electrode 175db and overlap with the third dummy gate electrode 124dc. The third dummy drain electrode 175dc may be disposed on the third dummy gate electrode 124dc and spaced apart from the third dummy source electrode 173dc.

[0138] The dummy data line 171d, the dummy reference voltage line 172d, the first dummy source electrode 173da, the second dummy source electrode 173db, the third dummy source electrode 173dc, the first dummy drain electrode 175da, the second dummy drain electrode 175db, and the third dummy drain electrode 175dc may have planar shapes similar to those of the data line 171, the reference voltage line 172, the first source electrode 173a, the second source electrode 173b, the third source electrode 173c, the first drain electrode 175a, the second drain electrode 175b, and the third drain electrode 175c, respectively.

[0139] The data line 171, the reference voltage line 172, the first source electrode 173a, the second source electrode 173b, the third source electrode 173c, the first drain electrode 175a, the second drain electrode 175b, the third drain electrode 175c, the dummy data line 171d, the dummy reference voltage line 172d, the first dummy source electrode 173da, the second dummy source electrode 173db, the third dummy source electrode 173dc, the first dummy drain electrode 175da, the second dummy drain electrode 175db, and the third dummy drain electrode 175dc may be formed in the same process, may be located in the same layer, and are referred to as data conductors.

[0140] A gate insulating film 140 is disposed between the gate conductor and the data conductor. For example, the gate insulating film 140 is disposed between the gate line 121 and the data line 171. That is, the gate line 121 and the data line 171 can overlap each other with the gate insulating film 140 therebetween. Also, the gate insulating film 140 is disposed between the gate line 121 and the reference voltage line 172. That is, the gate line 121 and the reference voltage line 172 can overlap each other with the gate insulating film 140 therebetween. Similarly, the gate insulating film 140 is disposed between the gate line 121 and the dummy data line 171d. That is, the gate line 121 and the dummy data line 171d can overlap each other with the gate insulating film 140 therebetween. Also, the gate insulating film 140 is disposed between the gate line 121 and the dummy reference voltage line 172d. That is, the gate line 121 and the dummy reference voltage line 172d can overlap each other with the gate insulating film 140 therebetween.

[0141] The two metal layers with the insulating film therebetween are insulated from each other. However, due to various reasons such as the insulating film being deposited thinly during the process or being damaged during the etching of the metal layer, a short circuit defect may occur between the two metal layers that should be insulated from each other. For the short circuit defects between the gate line 121 and the data line 171 and between the gate line 121 and the reference voltage line 172, they are relatively easy to be detected in the early stage during the process. In contrast, for the short circuit defects between the gate line 121 and the dummy data line 171d and between the gate line 121 and the dummy reference voltage line 172d, they are relatively difficult to be detected in the early stage. Since the dummy pixels are blocked by the light-blocking member 220, the short circuit defects are not easily detected. If these defects are found after attaching a polarizing plate, a printed circuit board, etc., a relatively large loss may occur when the product is discarded.

[0142] In this embodiment, the dummy data line 171d includes openings 911 and 912, and the dummy reference voltage line 172d includes openings 951 and 952, so that even if a short circuit defect occurs, it is possible to prevent the gate signal applied to the gate line 121 from changing. In the absence of these openings, if a short circuit occurs between the dummy data line 171d and the gate line 121, or if a short circuit occurs between the dummy reference voltage line 172d and the gate line 121, a load occurs in the signal applied to the gate line 121, and thus the gate signal may change. In this embodiment, the dummy data line 171d includes openings 911 and 912 in a portion adjacent to the overlapping portion with the gate line 121, so that even if a short circuit occurs between the dummy data line 171d and the gate line 121, it is possible to minimize the load on the gate signal, and further minimize the change amplitude of the gate output waveform. Also, the dummy reference voltage line 172d includes openings 951 and 952 in a portion adjacent to the overlapping portion with the gate line 121, so that even if a short circuit occurs between the dummy reference voltage line 172d and the gate line 121, it is possible to minimize the load on the gate signal, and further minimize the change amplitude of the gate output waveform.

[0143] A protective film 180 may be disposed on the data conductor. The protective film 180 may be formed of an organic insulating material or an inorganic insulating material, and may be formed as a single-layer film or a multi-layer film. At this time, the organic insulating material may also be formed of a color filter.

[0144] The protective film 180 may include a first contact hole 185a overlapping with the first drain electrode 175a. Also, the protective film 180 may include a second contact hole 185b overlapping with the second drain electrode 175b.

[0145] A pixel electrode 191 and a dummy pixel electrode 191d may be disposed on the protective film 180. The pixel electrode 191 may include a first sub-pixel electrode 191a and a second sub-pixel electrode 191b. The dummy pixel electrode 191d may include a first dummy sub-pixel electrode 191da and a second dummy sub-pixel electrode 191db.

[0146] The first sub-pixel electrode 191a may be connected to the first drain electrode 175a through the first contact hole 185a, and the second sub-pixel electrode 191b may be connected to the second drain electrode 175b through the second contact hole 185b.

[0147] The first sub-pixel electrode 191a and the second sub-pixel electrode 191b can receive data voltages from the first drain electrode 175a and the second drain electrode 175b, respectively. At this time, a part of the data voltage applied to the second drain electrode 175b is divided by the third drain electrode 175c, so that the magnitude of the voltage applied to the second sub-pixel electrode 191b is smaller than the magnitude of the voltage applied to the first sub-pixel electrode 191a. This is the case where the data voltages applied to the first sub-pixel electrode 191a and the second sub-pixel electrode 191b are positive (+). On the contrary, in the case where the data voltages applied to the first sub-pixel electrode 191a and the second sub-pixel electrode 191b are negative (-), the voltage applied to the first sub-pixel electrode 191a is smaller than the voltage applied to the second sub-pixel electrode 191b.

[0148] The area of the second sub-pixel electrode 191b can be about 1 times or more and about 2 times or less the area of the first sub-pixel electrode 191a.

[0149] The first sub-pixel electrode 191a and the second sub-pixel electrode 191b can be adjacent in the column direction, the overall shape can be generally quadrilateral, and can include a cross-shaped main trunk composed of a horizontal main trunk 192 and a vertical main trunk 193 intersecting therewith. Also, the first sub-pixel electrode 191a and the second sub-pixel electrode 191b can be divided into four sub-regions by the horizontal main trunk 192 and the vertical main trunk 193, and a plurality of micro-branches 194 are arranged in each sub-region.

[0150] One of the micro-branches 194 of the first sub-pixel electrode 191a and the second sub-pixel electrode 191b extends obliquely in the upper left direction from the horizontal main trunk 192 or the vertical main trunk 193, and the other micro-branch 194 extends obliquely in the upper right direction from the horizontal main trunk 192 or the vertical main trunk 193. Also, the other micro-branch 194 extends in the lower left direction from the horizontal main trunk 192 or the vertical main trunk 193, and the remaining one micro-branch 194 extends obliquely in the lower right direction from the horizontal main trunk 192 or the vertical main trunk 193.

[0151] Each micro-branch 194 can form an angle of about 40 degrees to about 45 degrees with the gate line 121 or the horizontal main trunk 192. Also, the micro-branches 194 of two adjacent sub-regions can be orthogonal to each other.

[0152] The first dummy sub-pixel electrode 191da may overlap with the first dummy drain electrode 175da, but is not connected to the first dummy drain electrode 175da. The second dummy sub-pixel electrode 191db may overlap with the second dummy drain electrode 175db, but is not connected to the second dummy drain electrode 175db. The dummy pixel electrode 191d is set to a floating state, and no voltage is applied to the dummy pixel electrode 191d.

[0153] The dummy pixel electrode 191d may have a planar shape similar to that of the pixel electrode 191.

[0154] Next, the counter display panel 200 will be described.

[0155] A light-blocking member 220 may be disposed on the second substrate 210. The light-blocking member 220 is also referred to as a black matrix and can prevent light leakage. The light-blocking member 220 may overlap with the gate line 121 and the data line 171. Also, the light-blocking member 220 may overlap with the dummy data line 171d, the dummy reference voltage line 172d, and the dummy pixel electrode 191d. That is, since the dummy pixels are not part of the display screen, they are blocked by the light-blocking member 220.

[0156] A plurality of color filters 230 may be disposed on the second substrate 210 and the light-blocking member 220. Most of the color filters 230 are present in the region surrounded by the light-blocking member 220 and may also extend relatively long along the column length of the pixel electrode 191. Each color filter 230 may display one of the primary colors such as red, green, and blue. However, it is not limited to the primary colors of red, green, and blue, and may also display one of cyan, magenta, yellow, and white series colors.

[0157] The above has described the case where the light-blocking member 220 and the color filter 230 are located on the second substrate 210. However, the present embodiment is not limited thereto. At least any one of the light-blocking member 220 and the color filter 230 may also be located on the first substrate 110.

[0158] A cover film 240 may be disposed on the color filter 230 and the light-blocking member 220.

[0159] A common electrode 270 may be disposed on the cover film 240.

[0160] A polarizer (not shown) may be disposed on the outer surfaces of the thin film transistor display panel 100 and the opposing display panel 200. The polarization axes of the two polarizers may be orthogonal to each other, and one of the polarization axes may be parallel to the gate line 121. For a reflective display device, one of the two polarizers may be omitted.

[0161] The pixel electrode 191 that receives the data voltage and the common electrode 270 of the opposing display panel 200 that receives the common voltage generate an electric field together, thereby determining the direction of the liquid crystal molecules in the liquid crystal layer 3 between the two electrodes 191 and 270. The polarization of the light passing through the liquid crystal layer 3 changes according to the direction of the liquid crystal molecules determined as described above.

[0162] The first sub-pixel electrode 191a, the second sub-pixel electrode 191b, and the common electrode 270 form liquid crystal capacitors Clca and Clcb, thereby maintaining the applied voltage even after the thin film transistor is turned off. At this time, the edge of the microdivision part 194 distorts the electric field to form a horizontal component perpendicular to the edge of the microdivision part 194, and the tilt direction of the liquid crystal molecules is determined by the direction determined by the horizontal component. Therefore, the liquid crystal molecules initially tend to tilt in a direction perpendicular to the edge of the microdivision part 194. However, the directions of the horizontal components of the electric fields generated by the edges of the adjacent microdivision parts 194 are opposite, and the intervals between the microdivision parts 194 are narrow, so the liquid crystal molecules that tend to tilt in opposite directions tilt together in a direction parallel to the length direction of the microdivision part 194.

[0163] In this embodiment, the length directions in which the microdivision parts 194 of one pixel extend are all four directions, so the total number of directions in which the liquid crystal molecules tilt can also be four directions. Diversifying the tilt directions of the liquid crystal molecules as described above can increase the reference viewing angle of the display device.

[0164] Next, refer to Figure 10 The description of the display device according to an embodiment is as follows.

[0165] Since the display device according to Figure 10 the embodiment shown has the same parts as the display device according to Figures 1 to 9 the embodiment shown, the description of the same parts is omitted. The difference between this embodiment and the above embodiment is that the dummy reference voltage line does not include an opening, which will be further described below.

[0166] Figure 10 is a plan view showing a display device according to an embodiment. Figure 10 Shows any one pixel of the display device and the adjacent dummy pixels.

[0167] A display device according to an embodiment includes a gate line 121, a data line 171 intersecting the gate line 121, and a dummy data line 171d. Also, the display device according to an embodiment may further include a reference voltage line 172 intersecting the gate line 121 and a dummy reference voltage line 172d.

[0168] In the above embodiment, the dummy data line 171d includes openings 911 and 912, and the dummy reference voltage line 172d includes openings 951 and 952. In this embodiment, the dummy data line 171d includes openings 911 and 912, but the dummy reference voltage line 172d does not include an opening.

[0169] The dummy data line 171d includes openings 911 and 912 in a portion adjacent to an overlapping portion with the gate line 121. The openings 911 and 912 of the dummy data line 171d may include an upper opening 911 located above the overlapping portion with the gate line 121 in a plane and a lower opening 912 located below the overlapping portion with the gate line 121 in a plane. Portions of the dummy data line 171d on both sides of the openings 911 and 912 of the dummy data line 171d are electrically insulated from each other.

[0170] Next, refer to Figure 11 A description of a display device according to an embodiment is as follows.

[0171] Since the display device according to Figure 11 the embodiment shown has the same parts as the display device according to Figures 1 to 9 the embodiment shown, a description of the same parts is omitted. The difference between this embodiment and the above embodiment is that the dummy data line does not include an opening, which will be further described below.

[0172] Figure 11 is a plan view showing a display device according to an embodiment. Figure 11 Shows any one pixel of the display device and a neighboring dummy pixel.

[0173] A display device according to an embodiment includes a gate line 121, a data line 171 intersecting the gate line 121, and a dummy data line 171d. Also, the display device according to an embodiment may further include a reference voltage line 172 intersecting the gate line 121 and a dummy reference voltage line 172d.

[0174] In the above embodiment, the dummy data line 171d includes openings 911 and 912, and the dummy reference voltage line 172d includes openings 951 and 952. In this embodiment, the dummy reference voltage line 172d includes openings 951 and 952, but the dummy data line 171d does not include an opening.

[0175] Dummy reference voltage line 172d includes openings 951 and 952 in a portion located adjacent to and overlapping with gate line 121. Openings 951 and 952 of dummy reference voltage line 172d may include an upper opening 951 located on the upper side of the overlapping portion with gate line 121 in a plane and a lower opening 952 located on the lower side of the overlapping portion with gate line 121 in a plane. Portions of dummy reference voltage line 172d on both sides of openings 951 and 952 of dummy reference voltage line 172d are electrically insulated from each other.

[0176] Next, refer to Figure 12 A description of a display device according to an embodiment is as follows.

[0177] Since the display device according to Figure 12 the embodiment shown has the same parts as the display device according to Figures 1 to 9 the embodiment shown, a description of the same parts is omitted. The difference between this embodiment and the above embodiment is that the dummy data line and the dummy reference voltage line do not include lower openings, which will be further described below.

[0178] Figure 12 is a plan view showing a display device according to an embodiment. Figure 12 Shows any one pixel of the display device and adjacent dummy pixels.

[0179] A display device according to an embodiment includes gate line 121, data line 171 intersecting with gate line 121, and dummy data line 171d. Further, a display device according to an embodiment may also include reference voltage line 172 intersecting with gate line 121 and dummy reference voltage line 172d.

[0180] In the above embodiment, dummy data line 171d includes upper opening 911 and lower opening 912, and dummy reference voltage line 172d includes upper opening 951 and lower opening 952. In this embodiment, dummy data line 171d includes upper opening 911, and dummy reference voltage line 172d includes upper opening 951. Dummy data line 171d does not include a lower opening, and dummy reference voltage line 172d does not include a lower opening.

[0181] Portions of dummy data line 171d on both sides of upper opening 911 of dummy data line 171d are electrically insulated from each other. Portions of dummy reference voltage line 172d on both sides of upper opening 951 of dummy reference voltage line 172d are electrically insulated from each other.

[0182] Next, refer to Figure 13 A description of a display device according to an embodiment is as follows.

[0183] Since according toFigure 13 The display device of the embodiment shown has the same parts as the display device of the embodiment according to Figures 1 to 9 the embodiment shown, so the description of the same parts is omitted. The difference between this embodiment and the above embodiment is that the dummy data line and the dummy reference voltage line do not include the upper opening, which will be further described below.

[0184] Figure 13 is a plan view showing a display device according to an embodiment. Figure 13 Shows any one pixel of the display device and the adjacent dummy pixels.

[0185] A display device according to an embodiment includes a gate line 121, a data line 171 intersecting the gate line 121, and a dummy data line 171d. Further, a display device according to an embodiment may further include a reference voltage line 172 intersecting the gate line 121 and a dummy reference voltage line 172d.

[0186] In the above embodiment, the dummy data line 171d includes an upper opening 911 and a lower opening 912, and the dummy reference voltage line 172d includes an upper opening 951 and a lower opening 952. In this embodiment, the dummy data line 171d includes a lower opening 912, and the dummy reference voltage line 172d includes a lower opening 952. The dummy data line 171d does not include the upper opening, and the dummy reference voltage line 172d does not include the upper opening.

[0187] The portions of the dummy data line 171d on both sides of the lower opening 912 of the dummy data line 171d are electrically insulated from each other. The portions of the dummy reference voltage line 172d on both sides of the lower opening 952 of the dummy reference voltage line 172d are electrically insulated from each other.

[0188] Next, referring to Figures 14 to 16 The description of the display device according to an embodiment is as follows.

[0189] Since the display device of the embodiment according to Figures 14 to 16 the embodiment shown has the same parts as the display device of the embodiment according to Figures 1 to 9 the embodiment shown, so the description of the same parts is omitted. The difference between this embodiment and the above embodiment is that the data line includes a first data line and a second data line, which will be further described below.

[0190] Figure 14 is an equivalent circuit diagram showing a pixel of a display device according to an embodiment, Figure 15 is showing Figure 14 a plan view of the pixel shown, Figure 16 is a plan view showing a dummy pixel of a display device according to an embodiment.

[0191] A display device according to an embodiment includes a plurality of signal lines GL, DL1, DL2, and a plurality of pixels PX connected thereto.

[0192] The signal lines GL, DL1, DL2 include a gate line GL for transmitting a gate signal, a first data line DL1 for transmitting a first data voltage, and a second data line DL2 for transmitting a second data voltage.

[0193] A first switching element T1 is formed which is connected to the gate line GL and the first data line DL1, and a second switching element T2 is formed which is connected to the gate line GL and the second data line DL2. The first switching element T1 and the second switching element T2 are connected to the same gate line GL.

[0194] A first liquid crystal capacitor Clca connected to the first switching element T1 is formed in the first sub-pixel PXa, and a second liquid crystal capacitor Clcb connected to the second switching element T2 is formed in the second sub-pixel PXb.

[0195] A first terminal of the first switching element T1 is connected to the gate line GL, a second terminal is connected to the first data line DL1, and a third terminal is connected to the first liquid crystal capacitor Clca.

[0196] A first terminal of the second switching element T2 is connected to the gate line GL, a second terminal is connected to the second data line DL2, and a third terminal is connected to the second liquid crystal capacitor Clcb.

[0197] Observing the operation of the display device according to an embodiment, when a gate-on voltage is applied to the gate line GL, the first switching element T1 and the second switching element T2 connected thereto are turned on. Different voltages are applied to the first data line DL1 and the second data line DL2, so that the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb are charged with different voltages. Therefore, the lateral visibility can be improved by changing the voltages charged to the first sub-pixel PXa and the second sub-pixel PXb within one pixel PX.

[0198] Hereinafter, with reference to Figure 15 The structure of one pixel of the display device according to an embodiment is described as follows.

[0199] On a first substrate (not shown), a gate line 121 and a sustain electrode line 131 extending in a first direction may be arranged. And, a first gate electrode 124a and a second gate electrode 124b protruding from the gate line 121 are formed. A sustain electrode 135 protruding from the sustain electrode line 131 is formed. The sustain electrode line 131 and the sustain electrode 135 may function as a shielding electrode in a structure using an organic film under the pixel electrode 191.

[0200] The shape and arrangement of the sustain electrode line 131 and the sustain electrode 135 can be variously changed.

[0201] Although not shown in the drawings, a gate insulating film may be disposed on the gate line 121, the first gate electrode 124a, the second gate electrode 124b, the sustain electrode line 131, and the sustain electrode 135.

[0202] The first semiconductor 154a and the second semiconductor 154b may be disposed on the gate insulating film. The first semiconductor 154a may overlap with the first gate electrode 124a, and the second semiconductor 154b may overlap with the second gate electrode 124b.

[0203] The first data line 171a and the second data line 171b extending in the second direction may be disposed on the gate insulating film. The second direction is a direction intersecting the first direction, and may be, for example, a direction perpendicular to the first direction.

[0204] Pixels are arranged in a matrix form on a first substrate (not shown). That is, a plurality of pixel columns and a plurality of pixel rows may be formed. The first data line 171a may be located at the left edge portion of each pixel column, and the second data line 171b may be located at the right edge portion of each pixel column.

[0205] The first source electrode 173a protruding from the first data line 171a and the first drain electrode 175a spaced apart from the first source electrode 173a may be disposed on the gate insulating film. The first source electrode 173a and the first drain electrode 175a may overlap with the first gate electrode 124a. Further, the second source electrode 173b protruding from the second data line 171b and the second drain electrode 175b spaced apart from the second source electrode 173b may be disposed on the gate insulating film. The second source electrode 173b and the second drain electrode 175b may overlap with the second gate electrode 124b.

[0206] The first gate electrode 124a, the first semiconductor 154a, the first source electrode 173a, and the first drain electrode 175a constitute the first switching element T1. The second gate electrode 124b, the second semiconductor 154b, the second source electrode 173b, and the second drain electrode 175b constitute the second switching element T2. The channels of the first switching element T1 and the second switching element T2 may be formed in the first semiconductor 154a and the second semiconductor 154b between the first source electrode 173a and the second source electrode 173b and the first drain electrode 175a and the second drain electrode 175b.

[0207] Although the illustration is omitted, a protective film may be disposed on the first data line 171a, the second data line 171b, the first switching element T1, and the second switching element T2. The protective film may include a first contact hole 185a overlapping with the first drain electrode 175a. And it may include a second contact hole 185b overlapping with the second drain electrode 175b.

[0208] A pixel electrode 191 may be disposed on the protective film. The pixel electrode 191 may include a first sub-pixel electrode 191a and a second sub-pixel electrode 191b. The first sub-pixel electrode 191a may be connected to the first drain electrode 175a through the first contact hole 185a, and the second sub-pixel electrode 191b may be connected to the second drain electrode 175b through the second contact hole 185b. The first sub-pixel electrode 191a may be connected to the first switching element T1, and the second sub-pixel electrode 191b may be connected to the second switching element T2. The first sub-pixel electrode 191a and the second sub-pixel electrode 191b may be located within one pixel and separated from each other with the gate line 121 therebetween. The first sub-pixel electrode 191a and the second sub-pixel electrode 191b may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof.

[0209] The area of the first sub-pixel electrode 191a may be smaller than the area of the second sub-pixel electrode 191b.

[0210] The first sub-pixel electrode 191a and the second sub-pixel electrode 191b may be adjacent in the column direction, the overall shape may be generally quadrilateral, and may include a cross-shaped main trunk composed of a horizontal main trunk 192 and a vertical main trunk 193 intersecting therewith. And the first sub-pixel electrode 191a and the second sub-pixel electrode 191b may be divided into four sub-regions by the horizontal main trunk 192 and the vertical main trunk 193, and a plurality of micro-branches 194 are disposed in each sub-region.

[0211] One of the micro-branches 194 of the first sub-pixel electrode 191a and the second sub-pixel electrode 191b extends obliquely in the upper left direction from the horizontal main trunk 192 or the vertical main trunk 193, and the other micro-branch 194 extends obliquely in the upper right direction from the horizontal main trunk 192 or the vertical main trunk 193. And the other micro-branch 194 extends in the lower left direction from the horizontal main trunk 192 or the vertical main trunk 193, and the remaining one micro-branch 194 extends obliquely in the lower right direction from the horizontal main trunk 192 or the vertical main trunk 193.

[0212] Each micro-branch 194 may form an angle of about 40 degrees to about 45 degrees with the gate line 121 or the horizontal main trunk 192. And the micro-branches 194 of two adjacent sub-regions may be orthogonal to each other.

[0213] On a second substrate (not shown) facing the first substrate (not shown), a color filter (not shown), a light-blocking member (not shown), a cover film (not shown), and a common electrode (not shown) may be disposed. And, a liquid crystal layer (not shown) may be disposed between the first substrate (not shown) and the second substrate (not shown).

[0214] Hereinafter, with reference to Figure 16 A description of the structure of a dummy pixel of a display device according to an embodiment will be given below.

[0215] On the first substrate, a gate line 121 and a dummy data line 171d intersecting the gate line 121 may be disposed. A gate insulating film may be disposed between the gate line 121 and the dummy data line 171d. That is, the gate line 121 and the dummy data line 171d may overlap each other with the gate insulating film therebetween.

[0216] The dummy data line 171d may extend in a direction substantially parallel to the data line 171. The dummy data line 171d may include a first dummy data line 171da and a second dummy data line 171db located on both sides with respect to the dummy pixel. The first dummy data line 171da may be located on the left side of the dummy pixel electrode 191d, and the second dummy data line 171db may be located on the right side of the dummy pixel electrode 191d. The first dummy data line 171da and the second dummy data line 171db are set to a floating state, and no signal is applied to the first dummy data line 171da and the second dummy data line 171db.

[0217] The first dummy data line 171da and the second dummy data line 171db include openings 921, 922, 961, 962 located in portions adjacent to the overlapping portion with the gate line 121.

[0218] The openings 921, 922 of the first dummy data line 171da may include an upper opening 921 located on the upper side of the overlapping portion with the gate line 121 in a plane and a lower opening 922 located on the lower side of the overlapping portion with the gate line 121 in a plane. Portions of the first dummy data line 171da located on both sides with respect to the openings 921, 922 are separated from each other. For example, a portion of the first dummy data line 171da located above the upper opening 921 and a portion of the first dummy data line 171da located below the upper opening 921 are separated from each other. And, a portion of the first dummy data line 171da located above the lower opening 922 and a portion of the first dummy data line 171da located below the lower opening 922 are separated from each other. Accordingly, portions of the first dummy data line 171da located on both sides of the openings 921, 922 of the first dummy data line 171da are electrically insulated from each other.

[0219] In the present embodiment, the first dummy data line 171da includes openings 921 and 922 in a portion adjacent to the overlapping portion with the gate line 121, so that even if a short circuit occurs between the first dummy data line 171da and the gate line 121, the load of the gate signal can be minimized, and thus the change amplitude of the gate output waveform can be minimized.

[0220] The openings 961 and 962 of the second dummy data line 171db may include an upper opening 961 located on the upper side of the overlapping portion with the gate line 121 in a plane and a lower opening 962 located on the lower side of the overlapping portion with the gate line 121 in a plane. The portions of the second dummy data line 171db located on both sides with respect to the openings 961 and 962 are separated from each other. For example, the portion of the second dummy data line 171db located above the upper opening 961 and the portion of the second dummy data line 171db located below the upper opening 961 are separated from each other. Also, the portion of the second dummy data line 171db located above the lower opening 962 and the portion of the second dummy data line 171db located below the lower opening 962 are separated from each other. Therefore, the portions of the second dummy data line 171db located on both sides of the openings 961 and 962 of the second dummy data line 171db are electrically insulated from each other.

[0221] In the present embodiment, the second dummy data line 171db includes openings 961 and 962 in a portion adjacent to the overlapping portion with the gate line 121, so that even if a short circuit occurs between the second dummy data line 171db and the gate line 121, the load of the gate signal can be minimized, and thus the change amplitude of the gate output waveform can be minimized.

[0222] In the dummy pixel region, a first dummy gate electrode 124da and a second dummy gate electrode 124db protruding from the gate line 121 may also be arranged. Also, a first dummy semiconductor 154da overlapping with the first dummy gate electrode 124da and a second dummy semiconductor 154db overlapping with the second dummy gate electrode 124db may be arranged. And a first dummy source electrode 173da protruding from the first dummy data line 171da and a first dummy drain electrode 175da separated from the first dummy source electrode 173da may be arranged. The first dummy source electrode 173da and the first dummy drain electrode 175da may overlap with the first dummy gate electrode 124da. And a second dummy source electrode 173db protruding from the second dummy data line 171db and a second dummy drain electrode 175db separated from the second dummy source electrode 173db may be arranged.

[0223] The second dummy source electrode 173db and the second dummy drain electrode 175db may overlap with the second dummy gate electrode 124db. Also, a dummy pixel electrode 191d may be disposed between the first dummy data line 171da and the second dummy data line 171db. The dummy pixel electrode 191d may include a first dummy sub-pixel electrode 191da and a second dummy sub-pixel electrode 191db. The first dummy sub-pixel electrode 191da may overlap with the first dummy drain electrode 175da, but is not connected to the first dummy drain electrode 175da. The second dummy sub-pixel electrode 191db may overlap with the second dummy drain electrode 175db, but is not connected to the second dummy drain electrode 175db. The dummy pixel electrode 191d is set to a floating state, and no voltage is applied to the dummy pixel electrode 191d.

[0224] The first dummy data line 171da, the second dummy data line 171db, the first dummy gate electrode 124da and the second dummy gate electrode 124db, the first dummy semiconductor 154da and the second dummy semiconductor 154db, the first dummy source electrode 173da and the second dummy source electrode 173db, the first dummy drain electrode 175da and the second dummy drain electrode 175db, the first dummy sub-pixel electrode 191da and the second dummy sub-pixel electrode 191db may have planar shapes respectively similar to those of the first data line 171a, the second data line 171b, the first gate electrode 124a and the second gate electrode 124b, the first semiconductor 154a and the second semiconductor 154b, the first source electrode 173a and the second source electrode 173b, the first drain electrode 175a and the second drain electrode 175b, the first sub-pixel electrode 191a and the second sub-pixel electrode 191b.

[0225] The number and arrangement pattern of the switching elements described above may be changed in various ways. Also, according to various connection methods of the switching elements, the driving method of the display device may be changed in various ways. Also, the shape of the pixel electrode and the arrangement pattern of the pixels described above may be changed in various ways.

[0226] Also, although the liquid crystal display device in which the display device displays an image by driving liquid crystal located between two substrates has been described above, the present embodiment is not limited thereto. The display device according to the present embodiment may also be constituted by an organic light emitting display device, an electrophoretic display device, an electro-wetting display device, etc. Moreover, it may also be constituted by next-generation display devices such as a micro light emitting diode (Micro LED) display device, a quantum dot light emitting diode (QLED) display device, a quantum dot organic light emitting diode (QD-OLED) display device.

[0227] The embodiments of the present invention have been described in detail above. However, the scope of the rights of the present invention is not limited thereto. Various modifications and improved forms made by those skilled in the art using the basic concepts of the present invention defined in the claims also fall within the scope of the rights of the present invention.

Claims

1. A display device, comprising: a substrate; gate lines located on the substrate; data lines intersecting the gate lines; pixels connected to the gate lines and the data lines; dummy data lines located at an edge portion on the substrate and intersecting the gate lines; and dummy reference voltage lines located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy data lines include openings in portions adjacent to the overlapping portions with the gate lines, portions of the dummy data lines on both sides of the openings of the dummy data lines are electrically insulated from each other, the dummy reference voltage lines include openings in portions adjacent to the overlapping portions with the gate lines, portions of the dummy reference voltage lines on both sides of the openings of the dummy reference voltage lines are electrically insulated from each other.

2. The display device according to claim 1, wherein the openings of the dummy data lines include: an upper opening located above the overlapping portion with the gate line in a plane; and a lower opening located below the overlapping portion with the gate line in a plane.

3. The display device according to claim 1, wherein the number of the openings of the dummy data lines is greater than the number of the gate lines.

4. The display device according to claim 3, wherein the number of the openings of the dummy data lines is twice the number of the gate lines.

5. The display device according to claim 1, wherein, Further comprising: a gate insulating film located between the gate lines and the data lines and between the gate lines and the dummy data lines, wherein the gate lines and the data lines overlap each other with the gate insulating film therebetween, the gate lines and the dummy data lines overlap each other with the gate insulating film therebetween.

6. The display device according to claim 5, wherein the gate lines extend in a first direction, the data lines extend in a second direction perpendicular to the first direction, the dummy data lines extend in the second direction.

7. The display device according to claim 1, wherein, Further comprising: dummy pixels located at an edge portion on the substrate and between the data lines and the dummy data lines, wherein the dummy pixels are set in a floating state.

8. The display device according to claim 7, wherein the dummy data lines are set in a floating state.

9. The display device according to claim 1, wherein the display device includes multiple gate lines, multiple data lines, and multiple pixels, the multiple pixels are arranged in a matrix form, each of the gate lines is connected to pixels in the same row among the multiple pixels, each of the data lines is alternately connected to pixels on the left side and pixels on the right side of the data line among the multiple pixels.

10. The display device according to claim 9, wherein data voltage with different polarities is applied to adjacent data lines among the multiple data lines.

11. The display device according to claim 1, wherein the data lines include a first data line and a second data line, the dummy data lines include a first dummy data line and a second dummy data line, The first dummy data line and the second dummy data line each include an opening portion in a part adjacent to an overlapping portion with the gate line.

12. A display device, comprising: a substrate; gate lines located on the substrate; data lines and reference voltage lines intersecting the gate lines; pixels connected to the gate lines, the data lines, and the reference voltage lines; dummy reference voltage lines located at an edge portion on the substrate and intersecting the gate lines; dummy data lines located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy reference voltage line includes an opening portion in a part adjacent to an overlapping portion with the gate line, portions of the dummy reference voltage line on both sides of the opening portion of the dummy reference voltage line are electrically insulated from each other, and the dummy reference voltage line is located between the dummy data line and the data line.

13. The display device according to claim 12, wherein the dummy data line includes an opening portion in a part adjacent to an overlapping portion with the gate line, portions of the dummy data line on both sides of the opening portion of the dummy data line are electrically insulated from each other.

14. The display device according to claim 13, wherein, It further includes: dummy pixels located at an edge portion on the substrate and between the data line and the dummy data line, wherein the dummy pixels are set to a floating state.

15. The display device according to claim 14, wherein the dummy reference voltage line and the dummy data line are set to a floating state.

16. The display device according to claim 12, wherein the opening portion of the dummy reference voltage line includes: an upper opening portion located on an upper side of an overlapping portion with the gate line in a plane; and a lower opening portion located on a lower side of an overlapping portion with the gate line in a plane.

17. A display device, comprising: a substrate; gate lines and data lines located on the substrate and intersecting each other; a reference voltage line located on the substrate and applied with a constant voltage; a first transistor and a second transistor connected to the gate lines and the data lines; a third transistor connected to the gate lines, the second transistor, and the reference voltage line; a first sub-pixel electrode connected to the first transistor; a second sub-pixel electrode connected to the second transistor; a dummy data line located at an edge portion on the substrate and intersecting the gate lines; a dummy reference voltage line located at an edge portion on the substrate and intersecting the gate lines, wherein the dummy data line includes an opening portion in a part adjacent to an overlapping portion with the gate line, portions of the dummy data line on both sides of the opening portion of the dummy data line are electrically insulated from each other, the dummy reference voltage line includes an opening portion in a part adjacent to an overlapping portion with the gate line, portions of the dummy reference voltage line on both sides of the opening portion of the dummy reference voltage line are electrically insulated from each other.

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