Power control systems, storage systems, and methods for reducing peak current

Abstract

This disclosure provides a power control system, a storage system, and a method for reducing peak current. The storage system includes a storage cell array and a plurality of peripheral circuits operatively coupled to the storage array. The power control circuitry can be configured to individually control the power application to each of the plurality of peripheral circuits and the storage cell array. Inserting switching devices across different power domains to achieve the same sequential wake-up path for peripheral circuits connected to different power domains can reduce peak current.

Description

Technical Field

[0001] The techniques described in the embodiments of this disclosure generally relate to memory, and more specifically, to power control systems, storage systems, and methods for reducing peak current. Background Technology

[0002] Static random-access memory (SRAM) is a type of semiconductor memory that uses a bistable latch circuit system to store each bit in a memory array. SRAM maintains data in the memory array without requiring refresh when powered, but it remains volatile, meaning the data will eventually be lost when the memory is not powered. Power gating and voltage holding techniques are typically implemented on the memory array to reduce power consumption. For example, the power gate can be used to disconnect peripheral items in deep sleep mode and disconnect both peripheral items and the memory array in shutdown mode. Summary of the Invention

[0003] This disclosure provides a power control system, including: a power rail configured to receive a power supply voltage signal; a first head-end circuit connected to the power rail and having a first output terminal configured to provide a first output voltage signal in a first power domain; a second head-end circuit connected to the power rail and having a second output terminal configured to provide a second output voltage signal in a second power domain; and a control switch connected between the first head-end circuit and the second head-end circuit and configured to selectively interconnect the first output terminal and the second output terminal.

[0004] This disclosure provides a storage system, including: a storage cell array; a first plurality of peripheral circuits connected to the storage cell array; a second plurality of peripheral circuits connected to the storage cell array; a power rail configured to receive a power supply voltage signal; a first power control unit, including: a first head-end circuit connected to the power rail and having a first output terminal connected to the first plurality of peripheral circuits to provide a first output voltage signal in a first power domain; and a second head-end circuit connected to the power rail and having a second output terminal connected to the second plurality of peripheral circuits to provide a second output voltage signal in a second power domain; and a second power control unit, including: a third head-end circuit. A first head-end circuit is connected to the power rail and has a third output terminal connected to a third plurality of peripheral circuits to provide a third output voltage signal in a third power domain; a second head-end circuit is connected to the power rail and has a second output terminal connected to the second plurality of peripheral circuits to provide a second output voltage signal in a second power domain; a first control switch is connected between the first head-end circuit and the second head-end circuit and configured to selectively interconnect the first output terminal and the second output terminal; and a second control switch is connected between the second head-end circuit and the third head-end circuit and configured to selectively interconnect the second output terminal and the third output terminal.

[0005] This disclosure provides a method for reducing peak current, comprising: providing a memory array; providing a first plurality of peripheral circuits connected to the memory array; providing a second plurality of peripheral circuits connected to the memory array; providing a first head-end circuit having a first output terminal, wherein the first head-end circuit is connected to a power rail and the first output terminal is connected to the first plurality of peripheral circuits; providing a second head-end circuit having a second output terminal, wherein the second head-end circuit is connected to the power rail and the second output terminal is connected to the second plurality of peripheral circuits; in response to a sleep mode command, disconnecting the first head-end circuit to disconnect the first plurality of peripheral circuits from the power rail; in response to the sleep mode command, disconnecting the second head-end circuit to disconnect the second plurality of peripheral circuits from the power rail; in response to a wake-up mode command, turning on the first head-end circuit to connect the first plurality of peripheral circuits to a first supply voltage in a first power domain; and in response to the wake-up mode command, interconnecting the first output terminal of the first head-end circuit and the second output terminal of the second head-end circuit to supply the first supply voltage to the second plurality of peripheral circuits without turning on the second head-end circuit. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example memory device 100 according to some embodiments.

[0007] Figure 2 A block diagram of an example memory device 200 is shown, which includes a circuit system for reducing peak current in wake-up mode.

[0008] Figure 3 This is an example circuit diagram 300 illustrating an implementation of a wake-up path for a memory on a different power domain according to some embodiments.

[0009] Figure 4 This is a flowchart illustrating an example method for reducing peak current during wake-up mode. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature and another element(s) shown in the diagrams. Besides the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0012] For example, some memory architectures for Static Random Access Memory (SRAM) devices have two power management modes. In shutdown mode, the memory array (where information is stored) and peripheral circuitry of the memory array are disconnected to conserve power. When it is necessary to maintain the data stored by the memory device, a deep sleep power management mode can be used to conserve power while maintaining the stored information. In deep sleep mode, power to the memory array is maintained while peripheral devices or circuitry such as input / output (I / O) circuitry and other control circuitry are disconnected.

[0013] The power gate is used to disconnect peripheral devices during deep sleep mode and also to disconnect peripheral items and the memory array during shutdown mode. When the memory exits shutdown mode, the power gate is used to increase the internal supply voltage of the memory device, which can cause a large wake-up inrush current.

[0014] Power gating is an integrated circuit design technique that reduces power consumption by shutting off current to unused circuit blocks. Typically, low-leakage PMOS transistors are used as head-end switches to implement power gating, shutting off power to sections of the design in standby or sleep modes. In other instances, NMOS head-end switches can also be used as sleep transistors. Power gating helps reduce standby or leakage power. However, power gating can impact architectural design and may increase area due to the metal traces used for wiring.

[0015] In some instances, SRAM memory devices contain multiple power domains to reduce power consumption. However, traditionally, different power domains need to be woken up in different sequences to reduce peak current. Separate paths introduce design complexity due to increased area and metal trace routing.

[0016] In some instances, the disclosed solutions include inserting switches, such as pass-gate PMOS devices, across different power domains to achieve the same sequential wake-up path for circuit blocks connected to different power domains, thereby reducing peak current.

[0017] Figure 1 This is a block diagram illustrating an example memory device 100 according to some embodiments. Memory device 100 may be a random access memory, such as a static random access memory (SRAM) device, or another type of memory device, such as a dynamic random-access memory (DRAM) device. Figure 1 As shown, the memory device 100 includes at least one memory array 102 and input / output units 104 (I / O units) comprising a plurality of I / O cells 104a, 104b, 104c, ... 104n in other circuitry. The input / output units 104 can be powered by a power supply 106, which may be referred to below as VDD.

[0018] Memory array 102 may include a plurality of memory cells (also referred to as bit cells) arranged in a matrix of rows and columns. Each memory cell in memory array 102 is operable to store one bit of information. For example, in some SRAM implementations, each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (typically ground) such that one of two memory nodes can be occupied by information to be stored, where complementary information is stored at the other memory node. Other memory cells are arranged within the scope of this disclosure.

[0019] Memory array 102 may include multiple word lines and multiple bit line pairs. Each memory cell of memory array 102 may be connected to a word line and a bit line pair. A word line is operable to activate access to a memory cell connected to a row of word lines. A bit line pair is used to access information stored or to be stored in the memory cell activated by the word line. Although for ease of discussion, memory device 100 is shown to include only one memory array 102, memory device 100 may include multiple memory arrays 102.

[0020] I / O unit 104 controls the inflow and outflow of data, address, and control signals into and out of memory array 102. In some instances, I / O unit 104 includes multiple I / O units, each of which can be configured to connect to multiple peripheral circuits that can be biased using different power domains. The peripheral circuits may include circuitry that provides various functions of the memory device 100 associated with memory array 102. Examples of peripheral circuitry may include word line drivers. Other types of peripheral circuitry are also possible.

[0021] In some instances, during the operation of memory array 102, subsets of multiple peripheral circuits may need to be powered down and woken up at different times or at different power levels. Therefore, subsets of peripheral circuits with similar biases need to be connected to the same power domain. Typically, memory device 100 includes multiple peripheral circuits requiring multiple power domains, where one power domain can be used to power one subset of the multiple peripheral circuits, while a different power domain can be used to power another subset of the peripheral circuits.

[0022] Figure 2A block diagram of an example memory device 200 is shown, including a circuit system for reducing peak current in wake-up mode. In some examples, each I / O cell (104a, 104b, ... 104n) included in I / O cell 104 is configured to connect to multiple subsets of peripheral circuits including peripheral circuits A1 202, A2 204, and B 206. Although only three different subsets of peripheral circuits are disclosed in example 200, multiple other subsets of peripheral circuits are possible. Each subset of peripheral circuits can be powered by a corresponding power domain. For example, power domain A1 can be used to power peripheral circuit A1 202, power domain A2 can be used to power peripheral circuit A2 204, power domain B can be used to power peripheral circuit B 206, and so on.

[0023] In some instances, the memory device 200 may include different power management modes, including a shutdown mode, a sleep mode, and a wake-up mode. In shutdown mode, the memory array 102 and its peripheral circuitry (202, 204, 206) are disconnected to conserve power. However, during operation of the memory array 102, different peripheral circuitry (202, 204, 206) may need to switch to wake-up mode at different times.

[0024] In some instances, memory power management modes may utilize headend circuitry 208, including headends A1 208, A2 210, and B 212, to conserve power-off current from different power domains. For example, a low-leakage PMOS transistor may be implemented as a headend switch to turn different power domains of the various peripheral circuits 202, 204, and 206 on and off as needed. Other implementations of headend circuitry 208 are also possible.

[0025] In some instances, when a power domain used to power a large number of peripheral circuits (e.g., power domain B powering peripheral circuit B 206) switches from sleep mode to wake-up mode, the peak wake-up current can be large because all peripheral circuits B 206 are turned on simultaneously. A disclosed solution to achieve a wake-up path with the same sequence by inserting wake-up path switching device 214 across different power domains reduces the peak wake-up current by gradually turning on portions of peripheral circuits B 206 instead of turning them all on simultaneously. In the disclosed instance, the wake-up path switching device 214 can be a pass-gate PMOS device. Other implementations of the wake-up path switching device 214 are also possible.

[0026] In the absence of the disclosed solution including wake-up path switching device 214, peripheral circuit A1 202 can be switched to wake-up mode by turning on head terminal A1 208, peripheral circuit A2 204 can be switched to wake-up mode by turning on head terminal A2 210, and peripheral circuit B 206 can be switched to wake-up mode by turning on head terminal B 212. When a specific subset of peripheral circuits is extensively implemented within memory device 200 (e.g., peripheral circuit B 206 in the disclosed example), turning on the head terminal circuit (head terminal B 212 in the disclosed example) of the specific subset controlling the peripheral circuits (peripheral circuit B 206) causes a sudden surge in current. However, if a subset of peripheral circuit B 206 is switched to wake-up mode, the peak wake-up current can be reduced.

[0027] One method for reducing peak wake-up current may include connecting a subset of peripheral circuitry B 206 to a separate power domain and using control logic to delay the switching of that subset to wake-up mode. However, this implementation may require additional metal wiring and additional control logic, which can ultimately lead to increased area and power consumption. The disclosed example of implementing wake-up path switching device 214 across different power domains allows a subset of peripheral circuitry B 206 to be switched to wake-up mode when different power domains, such as power domain A1 or power domain A2, switch to wake-up mode. Regarding... Figure 3 The implementation and function of the wake-up mode switching device 214 are further described.

[0028] Figure 3 This is an example circuit diagram 300 illustrating an implementation of wake-up paths for memory on different power domains according to some embodiments. In the disclosed circuit diagram 300, each of I / O units 104a, I / O unit 104b, ... I / O unit 104n is connected to a VDD power supply 106, which can be used to configure power domain VDDHD_DR and power domain VDDHD_DR_NAP. Although regarding... Figure 3 Only two power domains are publicly disclosed, but other power domains are also possible.

[0029] In some instances, I / O unit 104a includes: a header circuit 302, which can be turned on to configure the power domain VDDHD_DR; and a header circuit 306, which can be turned on to configure the power domain VDDHD_DR_NAP. In some instances, I / O unit 104b includes: a header circuit 304, which can also be turned on to configure the power domain VDDHD_DR; and a header circuit 306, which can be turned on to configure the power domain VDDHD_DR_NAP. Header circuits 302, 304, and 306 can be implemented using PMOS transistors.

[0030] For example, in the disclosed embodiment, PMOS transistor 302 may be configured with a source terminal connected to VDD power supply 106 and a gate terminal connected to the SD_1 signal. After biasing PMOS transistor 302 to pull the SD_1 signal low, PMOS transistor 302 may be turned on and its drain terminal may be configured to be connected to the VDDHD_DR power domain of peripheral circuit A1 202. PMOS transistor 306 may be configured with a source terminal connected to VDD power supply 106 and a gate terminal connected to the SDX signal. After biasing PMOS transistor 306 to pull the SDX signal low, PMOS transistor 306 may be turned on and its drain terminal may be configured to be connected to the VDDHD_DR_NAP power domain of peripheral circuit B 206. Similarly, in the disclosed I / O unit 104b, PMOS transistors 304 and 306 can be connected in a manner similar to the SD_2 signal for biasing PMOS transistor 304 and the SDX signal for biasing PMOS transistor 306, so as to configure peripheral circuits A2 204 and B 206 respectively.

[0031] In some instances, each I / O unit 104 is configured to connect to peripheral circuit B 206 such that simultaneously turning on all peripheral circuits B 206 can cause a large surge in VDD current. (See also: Regarding...) Figure 2 As described, to reduce peak wake-up current, wake-up path switching device 214 can be implemented to wake up a subset of peripheral circuits B 206 gradually instead of waking up all peripheral circuits B 206 at the same time.

[0032] In some instances, a pass-gate PMOS device 308 can be used to implement a wake-up path switch device 214. For example, the source terminal of the pass-gate PMOS device 308 can be connected to the drain terminal of a PMOS transistor 302 or PMOS transistor 304 configured to pass the VDDHD_DR power domain. The drain terminal of the pass-gate PMOS device 308 can be connected to the drain terminal of a PMOS transistor 306 configured to pass the VDDHD_DR_NAP power domain. A NAPSEL signal can be connected to the input of inverter pairs 310, 312 and the output of the inverter pairs, and NAPSELD is connected to the gate terminal of the pass-gate PMOS device 308 and configured to bias the pass-gate PMOS 308 to turn on or off depending on whether a sequential wake-up path to peripheral circuit B 206 is enabled.

[0033] For example, initially, when peripheral circuits 202, 204, and 206 are configured in sleep mode, the PMOS transistors associated with headend circuits 302, 304, and 306 are set to logic high. After determining that peripheral circuit A1 202 will switch to wake-up mode, headend circuit 302 is turned on by biasing the SD_1 signal to logic low. In response, peripheral circuit A1 202 connected to the power domain VDDHD_DR can switch to wake-up mode.

[0034] In the disclosed example, peripheral circuit B 206 is configured to switch to wake-up mode after peripheral circuit A1 202 has been configured to be in wake-up mode. Therefore, while peripheral circuit A1 is configured to be in wake-up mode, the implemented pass-gate PMOS device 308 can be used to switch at least a subset of peripheral circuit B 206 to wake-up mode. For example, the NAPSEL signal can be set to 0 or a logic low value, and the corresponding NAPSELD signal is set to a logic low signal. The NAPSELD signal connected to the gate of the pass-gate PMOS device 308 turns on the pass-gate PMOS device 308, so that a subset of peripheral circuits B 206 connected to the wake-up path of peripheral circuit A1 202 can be switched to wake-up mode, even if the headend circuit 306 is not turned on.

[0035] Similarly, another subset of peripheral circuitry B 206 can be switched to wake-up mode by configuring headend circuitry 304 to be turned on by biasing the SD_2 signal to a logic low value. In other instances where memory device 200 includes additional peripheral circuitry, other subsets of peripheral circuitry B 206 can also be switched to wake-up mode without biasing headend circuitry 306 to be turned on. Therefore, when headend circuitry 306 is configured to be turned on by biasing the SDX signal to a logic low value, a subset of peripheral circuitry B 206 can already operate in wake-up mode without causing a sudden surge in current, because all peripheral circuitry B 206 switches to wake-up mode simultaneously without requiring additional metal wiring or additional control logic.

[0036] Figure 4This is a flowchart illustrating an example method 400 for reducing peak current in a memory device during wake-up mode. For example, at a first operation illustrated in blocks 402 through 410, a memory device, such as memory device 200, is provided. In some instances, at operation 402, a memory array, such as memory array 102, is provided. In some instances, at operation 404, a first plurality of peripheral circuits, such as peripheral circuitry A1 202, are provided. The first plurality of peripheral circuits are connected to memory array 102 and configured to support the operation of memory array 102. In some instances, at operation 406, a second plurality of peripheral circuits, such as peripheral circuitry B 206, are provided. The second plurality of peripheral circuits are connected to memory array 102 and are also configured to support the operation of memory array 102.

[0037] In some instances, at operation 408, a first head-end circuit, such as head-end circuit A1 208, is provided. The first head-end circuit includes at least two terminals, one of which is connected to a power rail, such as power supply 106, and the other terminal, which is the output of the first head-end circuit, is connected to a first plurality of peripheral circuits. The first head-end circuit is configured to supply a power supply voltage to the first plurality of peripheral circuits in a first power domain.

[0038] In some instances, at operation 410, a second head-end circuit, such as head-end circuit B 212, is provided. The second head-end circuit includes at least two terminals, one of which is connected to a power rail, such as power supply 106, and the other terminal, which is the output of the second head-end circuit, is connected to a second plurality of peripheral circuits. The second head-end circuit is configured to supply power voltage to the second plurality of peripheral circuits in a second power domain.

[0039] In some instances, at operation 412, in response to a sleep mode command, the first headend circuitry can be configured to disconnect a first plurality of peripheral circuits from the power rails. Similarly, at operation 414, in response to receiving a sleep mode command, the second headend circuitry can be configured to disconnect a second plurality of peripheral circuits from the power rails. For example, if a PMOS transistor device is used to implement the disclosed first and second headend circuitries from operations 412 and 414 (similar to...) Figure 3 The implementation described above, using PMOS transistors 302 and 306, allows the head-end circuit to be disconnected by controlling the gate voltage of the PMOS transistor. When the gate voltage of the implemented PMOS transistor becomes a logic high value, the PMOS transistor is disconnected, and the first and second peripheral circuits can also be disconnected. Other implementations are also possible.

[0040] In some instances, at operation 416, in response to a wake-up command, the first headend circuitry can be configured to connect a first plurality of peripheral circuits to the power rail. In some instances, the second headend circuitry can still be configured to disconnect a second plurality of peripheral circuits from the power rail.

[0041] In some instances, at operation 418, further in response to a wake-up command, the outputs of the first head-end circuit and the second head-end circuit can be interconnected with a switching device. Therefore, selectively turning on the switch interconnected with the outputs of the first and second head-end devices allows the second plurality of peripheral circuits to be energized without necessarily turning on the second head-end switch. In memory devices where the second plurality of peripheral circuits are extensively implemented and controlled by a single control signal, the disclosed configuration allows a subset of the second plurality of peripheral circuits to be turned on occasionally. Not turning on all implemented second plurality of peripheral circuits simultaneously reduces the peak current experienced by the memory device.

[0042] This disclosure therefore includes embodiments of a power control system comprising: a power rail configured to receive a power supply voltage signal; a first head-end circuit connected to the power rail and having a first output configured to provide a first output voltage signal in a first power domain; a second head-end circuit connected to the power rail and having a second output configured to provide a second output voltage signal in a second power domain; and a control switch connected between the first head-end circuit and the second head-end circuit and configured to selectively interconnect the first output and the second output.

[0043] In a related embodiment, the first head-end circuit includes a first PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a first head-end control signal, the first head-end control signal being selectively controlled to turn on the first head-end circuit during a wake-up mode and to turn off the first head-end circuit during a sleep mode.

[0044] In a related embodiment, the drain terminal of the first PMOS transistor is configured as the first output terminal.

[0045] In a related embodiment, the second head-end circuit includes a second PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a second head-end control signal, the second head-end control signal being selectively controlled to turn on the second head-end circuit during a wake-up mode and to turn off the second head-end circuit during a sleep mode.

[0046] In a related embodiment, the drain terminal of the second PMOS transistor is configured as the second output terminal.

[0047] In a related embodiment, the control switch includes a third PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the source terminal is connected to the first output terminal, the drain terminal is connected to the second output terminal, and the gate terminal is configured to receive a switch control signal.

[0048] In a related embodiment, the switch control signal is configured to selectively cause the third PMOS transistor to either form an electrical connection between the first output terminal and the second output terminal, or to disconnect the electrical connection between the first output terminal and the second output terminal.

[0049] In related embodiments, the first power domain is configured to supply power to at least a first peripheral circuit, and the second power domain is configured to supply power to at least a second peripheral circuit.

[0050] In related embodiments, the first peripheral circuit and the second peripheral circuit are included in the circuitry surrounding the memory array.

[0051] In related embodiments, the circuitry surrounding the memory array includes a word line driver, a decoder, and a readout amplifier.

[0052] In a related embodiment, the storage array is an SRAM storage array.

[0053] According to other embodiments, a storage system includes: a storage cell array; a first plurality of peripheral circuits connected to the storage cell array; a second plurality of peripheral circuits connected to the storage cell array; a power rail configured to receive a power supply voltage signal; a first power control unit; and a second power control unit. The first power control unit includes: a first headend circuit connected to the power rail and having a first output terminal connected to the first plurality of peripheral circuits to provide a first output voltage signal in a first power domain; and a second headend circuit connected to the power rail and having a second output terminal connected to the second plurality of peripheral circuits to provide a second output voltage signal in a second power domain. The second power control unit includes: a third headend circuit connected to the power rail and having a third output terminal connected to the third plurality of peripheral circuits to provide a third output voltage signal in a third power domain; and a second headend circuit connected to the power rail and having a second output terminal connected to the second plurality of peripheral circuits to provide a second output voltage signal in a second power domain. The storage system further includes: a first control switch connected between a first head-end circuit and a second head-end circuit and configured to selectively interconnect a first output terminal and a second output terminal; and a second control switch connected between a second head-end circuit and a third head-end circuit and configured to selectively interconnect a second output terminal and a third output terminal.

[0054] In a related embodiment, the first headend circuit includes a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a first headend control signal, the first headend control signal being selectively controlled to turn on the first headend circuit during a wake-up mode and to turn off the first headend circuit during a sleep mode.

[0055] In a related embodiment, the second head-end circuit includes a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a second head-end control signal, the second head-end control signal being selectively controlled to turn on the second head-end circuit during a wake-up mode and to turn off the second head-end circuit during a sleep mode.

[0056] In a related embodiment, the first control switch includes a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the source terminal is connected to the first output terminal, the drain terminal is connected to the second output terminal, and the gate terminal is configured to receive a first switch control signal, the first switch control signal being configured to selectively cause the PMOS transistor to either form an electrical connection between the first output terminal and the second output terminal or disconnect the electrical connection between the first output terminal and the second output terminal.

[0057] In a related embodiment, the second control switch includes a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the source terminal is connected to the second output terminal, the drain terminal is connected to the third output terminal, and the gate terminal is configured to receive a second switch control signal, the second switch control signal being configured to selectively cause the PMOS transistor to either form an electrical connection between the second output terminal and the third output terminal or disconnect the electrical connection between the second output terminal and the third output terminal.

[0058] In a related embodiment, the storage cell array is an SRAM storage array.

[0059] According to another embodiment, a method for reducing peak current in a memory device during a wake-up mode includes providing: a memory array; a first plurality of peripheral circuits connected to the memory array; a second plurality of peripheral circuits connected to the memory array; a first headend circuit having a first output terminal, wherein the first headend circuit is connected to a power rail and the first output terminal is connected to the first plurality of peripheral circuits; and a second headend circuit having a second output terminal, wherein the second headend circuit is connected to a power rail and the second output terminal is connected to the second plurality of peripheral circuits. The memory device is operated by disconnecting the first headend circuit in response to a sleep mode command to disconnect the first plurality of peripheral circuits from the power rail and by disconnecting the second headend circuit in response to a sleep mode command to disconnect the second plurality of peripheral circuits from the power rail. The memory device is further operated by turning on the first headend circuit in response to a wake-up mode command to connect the first plurality of peripheral circuits to a first supply voltage in a first power domain and by interconnecting the first output terminal of the first headend circuit and the second output terminal of the second headend circuit in response to a wake-up mode command to supply the first supply voltage to the second plurality of peripheral circuits without turning on the second headend circuit.

[0060] In related embodiments, a PMOS transistor device having a source terminal, a drain terminal, and a gate terminal is used to interconnect the first output terminal of the first head-end circuit and the second output terminal of the second head-end circuit, wherein the source terminal of the PMOS transistor device is connected to the first output terminal of the first head-end circuit, the drain terminal of the PMOS transistor device is connected to the second output terminal of the second head-end circuit, and wherein the method further includes: applying a switching control signal to the gate terminal of the PMOS transistor device.

[0061] In a related embodiment, the switch control signal is configured to selectively cause the PMOS transistor device to form an electrical connection or disconnect the electrical connection between the first output terminal of the first head-end circuit and the second output terminal of the second head-end circuit.

[0062] This disclosure outlines various embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A power control system comprising: a power rail configured to receive a power supply voltage signal; a first headend circuit connected to the power rail and having a first output configured to provide a first output voltage signal in a first power domain, wherein the first power domain includes a first MOSFET device; a second headend circuit connected to the power rail and having a second output configured to provide a second output voltage signal in a second power domain, wherein the second power domain includes a second MOSFET device; and a control switch connected between the first headend circuit and the second headend circuit and configured to selectively interconnect the first output and the second output, wherein the first power domain is configured to power a first peripheral circuit and the second power domain is configured to power a second peripheral circuit, wherein in response to a sleep mode command, the first headend circuit disconnects the first peripheral circuit from the power rail, wherein in response to the sleep mode command, the second headend circuit disconnects the second peripheral circuit from the power rail, wherein in response to a wake mode command, the first headend circuit connects the first peripheral circuit to a first supply voltage in the first power domain, and wherein in response to the wake mode command, the control switch interconnects the first headend circuit and the second output of the second headend circuit to supply the first supply voltage to the second peripheral circuit without turning on the second headend circuit.

2. The power control system of claim 1, wherein the first MOSFET device includes a first PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a first headend control signal that is selectively controlled to turn on the first headend circuit during a wake mode and to turn off the first headend circuit during a sleep mode.

3. The power control system of claim 2, wherein the drain terminal of the first PMOS transistor is configured as the first output.

4. The power control system of claim 1, wherein the second MOSFET device includes a second PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a second headend control signal that is selectively controlled to turn on the second headend circuit during a wake mode and to turn off the second headend circuit during a sleep mode.

5. The power control system of claim 4, wherein the drain terminal of the second PMOS transistor is configured as the second output.

6. The power control system of claim 1, wherein the control switch includes a third PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the source terminal is connected to the first output, the drain terminal is connected to the second output, and the gate terminal is configured to receive a switch control signal. ​ 7. The power control system of claim 6, wherein the switch control signal is configured to selectively cause the third PMOS transistor to: form an electrical connection between the first output terminal and the second output terminal, or break the electrical connection between the first output terminal and the second output terminal.

8. The power control system of claim 1, wherein the first and second peripheral circuits comprise circuitry external to a memory array.

9. The power control system of claim 8, wherein the circuitry peripheral to the storage array comprises: word line drivers, decoders, and sense amplifiers.

10. The power control system of claim 8, wherein the memory array is an SRAM memory array.

11. A memory system comprising: an array of memory cells; a first plurality of peripheral circuits connected to the array of memory cells; a second plurality of peripheral circuits connected to the array of memory cells; a power supply rail configured to receive a supply voltage signal; a first power control unit comprising: a first head-end circuit connected to the power supply rail and having a first output terminal connected to the first plurality of peripheral circuits to provide a first output voltage signal in a first power domain; and a second head-end circuit connected to the power supply rail and having a second output terminal connected to the second plurality of peripheral circuits to provide a second output voltage signal in a second power domain; a second power control unit comprising: a third head-end circuit connected to the power supply rail and having a third output terminal connected to a third plurality of peripheral circuits to provide a third output voltage signal in a third power domain; and a fourth head-end circuit connected to the power supply rail and having a fourth output terminal connected to the second plurality of peripheral circuits to provide the second output voltage signal in the second power domain; a first control switch connected between the first head-end circuit and the second head-end circuit and configured to selectively interconnect the first and second output terminals; and a second control switch connected between the fourth head-end circuit and the third head-end circuit and configured to selectively interconnect the fourth and third output terminals, wherein in response to a wake-up mode command, the first head-end circuit connects the first plurality of peripheral circuits to a first supply voltage in a first power domain, and wherein in response to the wake-up mode command, the first control switch interconnects the output terminals of the first and second head-end circuits to supply the first supply voltage to the second plurality of peripheral circuits without turning on the second head-end circuit.

12. The memory system of claim 11, wherein the first head-end circuit comprises a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a first head-end control signal that is selectively controlled to turn on the first head-end circuit during a wake-up mode and to turn off the first head-end circuit during a sleep mode.

13. The memory system of claim 11, wherein the second head-end circuit comprises a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is configured to receive a second head-end control signal that is selectively controlled to turn on the second head-end circuit during a wake-up mode and to turn off the second head-end circuit during a sleep mode.

14. The memory system of claim 11, wherein the first control switch comprises a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the source terminal is connected to the first output terminal, the drain terminal is connected to the second output terminal, and the gate terminal is configured to receive a first switch control signal configured to selectively cause the PMOS transistor to: form an electrical connection between the first output terminal and the second output terminal or to break the electrical connection between the first output terminal and the second output terminal.

15. The memory system of claim 11, wherein the second control switch comprises a PMOS transistor having a source terminal, a drain terminal, and a gate terminal, wherein the source terminal is connected to the fourth output terminal, the drain terminal is connected to the third output terminal, and the gate terminal is configured to receive a second switch control signal configured to selectively cause the PMOS transistor to: form an electrical connection between the fourth output terminal and the third output terminal or to break the electrical connection between the fourth output terminal and the third output terminal.

16. The memory system of claim 11, wherein the array of memory cells is an SRAM memory array.

17. A method of reducing peak current of a memory device, comprising: providing a memory array; providing a first plurality of peripheral circuits connected to the memory array; providing a second plurality of peripheral circuits connected to the memory array; providing a first head-end circuit having a first output terminal, wherein the first head-end circuit is connected to a power rail and the first output terminal is connected to the first plurality of peripheral circuits; providing a second head-end circuit having a second output terminal, wherein the second head-end circuit is connected to the power rail and the second output terminal is connected to the second plurality of peripheral circuits; in response to a sleep mode command, turning off the first head-end circuit to disconnect the first plurality of peripheral circuits from the power rail; in response to the sleep mode command, turning off the second head-end circuit to disconnect the second plurality of peripheral circuits from the power rail; in response to a wake-up mode command, turning on the first head-end circuit to connect the first plurality of peripheral circuits to a first supply voltage in a first power domain; and in response to the wake-up mode command, interconnecting the output terminals of the first head-end circuit and the second head-end circuit to supply the first supply voltage to the second plurality of peripheral circuits without turning on the second head-end circuit.

18. The method of claim 17, wherein the output terminals of the first and second headend circuits are interconnected using a PMOS transistor device having a source terminal, a drain terminal, and a gate terminal, wherein the source terminal of the PMOS transistor device is connected to the output terminal of the first headend circuit, the drain terminal of the PMOS transistor device is connected to the output terminal of the second headend circuit, and wherein the method further comprises: applying a switch control signal to the gate terminal of the PMOS transistor device.

19. The method of claim 18, wherein the switch control signal is configured to selectively cause the PMOS transistor to form an electrical connection between the output terminal of the first headend circuit and the output terminal of the second headend circuit or to break the electrical connection between the output terminal of the first headend circuit and the output terminal of the second headend circuit.

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