Memory device for transmitting small swing data signal and operation method thereof

Abstract

A memory device and an operating method thereof are disclosed, the memory device including a buffer die and a core die, the buffer die outputting a first power supply voltage to a first through substrate via (e.g., through silicon via (TSV)) and receiving a small swing data signal generated based on the first power supply voltage from a second TSV, the core die being electrically connected to the buffer die through the first TSV and the second TSV, the core die including a first unit capacitor electrically connected to the first TSV and configured to block a first noise introduced into the first power supply voltage received through the first TSV. The core die outputs the small swing data signal to the second TSV.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2020-0008118 filed on January 21, 2020, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0110861 filed on September 1, 2020, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the inventive concepts disclosed herein relate to a memory device and an operating method thereof, and more particularly, to a memory device that is driven with a low power supply voltage and transmits a small-swing data signal and an operating method thereof. Background Art

[0003] A semiconductor memory device can store data or can output stored data. Nowadays, in order to make the semiconductor memory device highly integrated and to make the operation speed faster, a technology for stacking the memory dies of the semiconductor memory device three-dimensionally has been developed. The three-dimensionally stacked memory dies can be electrically connected by using through-substrate vias (e.g., through-silicon vias (also called through-silicon vias)) (TSVs). For example, the memory dies of the semiconductor memory device can be supplied with a power supply voltage through the TSVs, or data signals can be transmitted or received through the TSVs.

[0004] Meanwhile, as circuits included in semiconductor memory devices are miniaturized and highly integrated, the number of TSVs included in the semiconductor memory devices increases, and due to the increase in the number of TSVs, power consumption increases. Therefore, a technology for reducing power consumption of semiconductor devices (e.g., the amount of power consumed by TSVs) is required. Summary of the invention

[0005] Embodiments of the inventive concept provide a memory device that is driven with a low power supply voltage and is capable of reducing power consumption by transmitting a small-swing data signal having a voltage lower than that of a general data signal, and an operating method thereof.

[0006] According to an exemplary embodiment, a memory device includes: a buffer die that outputs a first power supply voltage to a first through substrate via (e.g., through silicon via) (TSV) and receives a first small swing data signal generated based on the first power supply voltage from a second TSV; and a first core die that is electrically connected to the buffer die through the first TSV and the second TSV, the first core die including a first unit capacitor that is electrically connected to the first TSV and configured to block a first noise introduced into the first power supply voltage received through the first TSV. The first core die outputs the small swing data signal to the second TSV. The voltage of the high level of the first small swing data signal may be lower than the first power supply voltage.

[0007] According to an exemplary embodiment, a memory device includes: a buffer die that outputs a first power supply voltage to a first through substrate via (e.g., through silicon via) (TSV) and outputs a small swing data signal generated based on the first power supply voltage to a second TSV; and a core die that is electrically connected to the buffer die through the first TSV and the second TSV, the core die including a first unit capacitor that is electrically connected to the first TSV and configured to block a first noise introduced into the first power supply voltage received through the first TSV. The core die receives the small swing data signal from the second TSV. The voltage of the high level of the small swing data signal may be lower than the first power supply voltage.

[0008] According to an exemplary embodiment, a memory device includes a buffer die and a core die electrically connected to the buffer die through a first through substrate via (e.g., through silicon via) (TSV) and a second TSV, and an operating method of the memory device includes the following steps: supplying a first power supply voltage from the buffer die to the core die through the first TSV; blocking or reducing a first noise introduced to the first power supply voltage through a first unit capacitor of the core die, the first unit capacitor being electrically connected to the first TSV; generating a small swing data signal at the buffer die or the core die based on the first power supply voltage; and transmitting the small swing data signal through the second TSV. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the inventive concept will become apparent by describing in detail exemplary embodiments of the inventive concept with reference to the attached drawings.

[0010] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the inventive concept.

[0011] Figure 2A is a cross-sectional view of a general memory device.

[0012] Figure 2B is a cross-sectional view of a memory device including a cell capacitor according to an embodiment of the inventive concept.

[0013] Figure 3 is a detailed diagram showing the Figure 1 Circuit diagram of the transmitter.

[0014] Figure 4 is a detailed diagram showing the Figure 1 Circuit diagram of the transmitter.

[0015] Figure 5 is a detailed diagram showing the Figure 1 Circuit diagram of the receiver.

[0016] Figure 6 is a perspective view of a memory device according to an embodiment of the inventive concept.

[0017] Figure 7 is a detailed diagram showing the Figure 6 Figure 1 shows a diagram of the die area.

[0018] Figure 8 is a block diagram illustrating a memory system according to an embodiment of the inventive concept.

[0019] Fig. 9 is a detailed diagram showing the Figure 8 A block diagram of a memory device.

[0020] Fig.10 is a flowchart illustrating an operating method of a memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0021] Below, the embodiments of the inventive concept are described in detail and clearly so that those skilled in the art can easily implement the inventive concept. Below, for ease of description, similar components are represented by using the same or similar reference numerals.

[0022] In the following figures or in the detailed description, a module may be connected to any other component except the components shown in the figures or described in the detailed description. The modules or components may be directly connected or indirectly connected. The modules or components may be connected by communication or may be physically connected.

[0023] In the following drawings and detailed description, the terms "first direction DR1", "second direction DR2", and "third direction DR3" will be used. The first direction DR1 may be a direction parallel to a buffer die and a core die included in a memory device. The second direction DR2 may be a direction perpendicular to the first direction DR1. The third direction DR3 may be a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. In this case, the third direction DR3 may be a direction parallel to a through substrate via (e.g., through silicon via) (TSV) penetrating the memory device. However, it is noted that ordinals such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish such elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, terms that refer to specific ordinal or directional numbers (e.g., "first" in a specific claim) may be described using different ordinal or directional numbers elsewhere (e.g., "second" in the specification or another claim).

[0024] Figure 1is a block diagram illustrating a memory device 100 according to an embodiment of the inventive concept. Figure 1 , the memory device 100 may include a buffer die 110 and a core die 120. In an exemplary embodiment, the buffer die 110 and the core die 120 may be provided by different wafers. The memory device 100 may be a device that stores data or outputs stored data. The memory device 100 may be a high bandwidth memory (HBM) of a three-dimensional structure. For example, the memory device 100 may be a dynamic random access memory (DRAM) used in electronic devices such as computers, laptop computers, smart phones, etc.

[0025] The buffer die 110 may include a power line distributor 111, a first driver circuit 112, and an interface circuit 113. The power line distributor 111 may be a transmission power supply voltage V DD , power supply voltage V DDQL and the power supply voltage V SS The power supply voltage V DD 、V DDQL and V SS It can be a voltage used to drive the memory device 100. For example, the power supply voltage V DD 、V DDQL and V SS It can be used to drive the first driver circuit 112, the interface circuit 113 and the second driver circuit 121. In an exemplary embodiment, the power supply voltage V can be provided from an external power supply device (not shown). DD 、V DDQL and V SS .

[0026] The power supply voltage V indicates the voltage of a specific node DD 、V DDQL and V SS Can be used to represent a specific node itself. For example, the power supply voltage V DD 、V DDQL and V SS Each of may represent an intermediate node or may represent a voltage of an intermediate node. However, the inventive concept is not limited thereto. For example, the power supply voltage V DD 、V DDQL and V SS It should be interpreted according to the context of the embodiments.

[0027] In an exemplary embodiment, the power supply voltage V DD It can be a high voltage used to drive the memory device 100. The power supply voltage V DDQL can be lower than the supply voltage V DD The power supply voltage V SS can be lower than the supply voltage V DDQLFor example, the power supply voltage V DD It can be about 1.1V. The power supply voltage V DDQL It can be about 0.4V. The power supply voltage V SS It can be approximately 0V.

[0028] In an exemplary embodiment, the memory device 100 may be used together with a power supply voltage V DD and the power supply voltage V DDQL , instead of using only the supply voltage V DD When the power supply voltage V transmitted through at least one TSV DD is replaced by a relatively low supply voltage V DDQL When the power consumption of the memory device 100 (eg, the power consumption at the corresponding TSV) can be reduced.

[0029] The example is shown as a power line distributor 111 including three power supply voltages V DD 、V DDQL and V SS , but the inventive concept is not limited thereto. For example, the power line distributor 111 may also include any other power supply voltage necessary for the operation of the memory device 100, or the power supply voltage V may be omitted or changed according to the design or process of the memory device 100. DD 、V DDQL and V SS The power line distributor 111 can output the power supply voltage V through the corresponding TSVs in the N TSVs. DD 、V DDQL and V SS The number N of TSVs connected to the power line distributor 111 may be increased or decreased according to the design or process of the memory device 100 .

[0030] TSV may be an electrode that physically penetrates at least one of the buffer die 110 and the core die 120 and transmits a power supply voltage or an electrical signal (such as a data signal). For better understanding, Figure 1 The example in FIG. 1 is shown as TSV connecting the buffer die 110 and the core die 120. However, the TSV may physically penetrate the buffer die 110 or the core die 120, and the microbump connected to the TSV may be placed between the buffer die 110 and the core die 120. The microbump may be an element that joins different dies (e.g., the buffer die 110 and the core die 120). This will refer to Figure 2A and Figure 2B Describe more fully.

[0031] The first driver circuit 112 may include a transmitter Tx and a receiver Rx. The transmitter Tx of the first driver circuit 112 may be based on a power supply voltage VDD 、V DDQL and V SS The receiver Rx of the first driver circuit 112 can be driven by at least one of the power supply voltages V and can output the data signal received from the interface circuit 113 to the second driver circuit 121 through one or more corresponding TSVs. DD 、V DDQL and V SS The interface circuit 113 may receive the data signal received from the second driver circuit 121 through one or more corresponding TSVs and may output the data signal to the interface circuit 113 .

[0032] The interface circuit 113 may be connected to an electronic device (e.g., a memory controller) different from the memory device 100. The interface circuit 113 may include a sense amplifier SA and a trigger FF. The sense amplifier SA may be a circuit that amplifies a small data signal. The trigger FF may be a circuit that holds or stores data corresponding to the amplified small data signal. The interface circuit 113 may transmit a data signal received from the first driver circuit 112 electrically connected thereto to a different electronic device. In addition, the interface circuit 113 may output a data signal received from a different electronic device to the first driver circuit 112.

[0033] The core die 120 may include a unit capacitor, a second driver circuit 121, and a memory cell array 122. The memory cell array 122 may include a plurality of memory cells. Each memory cell (e.g., a DRAM cell) in the memory cell array 122 may include a transistor and a capacitor connected to the transistor. The capacitor of the memory cell may store data. The unit capacitor disclosed herein may be arranged to be separated from the capacitors of the plurality of memory cells and formed by the same manufacturing process as the manufacturing process of the capacitors of the memory cells. In this case, the unit capacitor and the capacitor of the memory cell may be arranged at the same height. For example, the unit capacitor and the capacitor of the memory cell may be formed at the same time. The capacitance of the unit capacitor may be greater than the capacitance of the capacitor of one memory cell. The unit capacitor may be a decoupling capacitor physically formed in the core die 120 and may block or reduce noise. Noise may be unwanted energy introduced from an adjacent circuit, such as leakage current. For example, noise may be a power supply voltage V DD 、V DDQL and V SS AC components or large currents introduced intermittently.

[0034] In an exemplary embodiment, the cell capacitors may be placed at a supply voltage V received from the buffer die 110. DDThe path through which the voltage is transmitted to the core die 120 and the path through which another voltage is transmitted, thereby reducing the influence of noise. For example, the unit capacitor can reduce the power supply voltage V DD The AC component of the power supply voltage V DDQL The cell capacitor can be disposed in an empty area of ​​the core die 120, so that the space efficiency of the memory device 100 is maximized. Figure 7 The arrangement of the unit capacitors is described more fully.

[0035] The second driver circuit 121 may include a transmitter Tx and a receiver Rx. The transmitter Tx of the second driver circuit 121 may be based on a power supply voltage V DD 、V DDQL and V SS The receiver Rx of the second driver circuit 121 may be driven by at least one of the power supply voltages V and may output a data signal received from the memory cell array 122 to the first driver circuit 112 through one or more corresponding TSVs. DD 、V DDQL and V SS The first driver circuit 112 may be driven by at least one of the first and second driver circuits 114 , may receive a data signal received from the first driver circuit 112 through one or more corresponding TSVs, and may output the data signal to the memory cell array 122 .

[0036] For example, the transmitter Tx of the second driver circuit 121 may be similar in function to the transmitter Tx of the first driver circuit 112. The receiver Rx of the second driver circuit 121 may be similar in function to the receiver Rx of the first driver circuit 112. Figure 3 and Figure 4 The transmitter Tx is described more fully. Figure 5 The receiver Rx is described more fully.

[0037] In an exemplary embodiment, the data signal transmitted between the first driver circuit 112 and the second driver circuit 121 through the TSV may be a small swing data signal. The voltage of the small swing data signal (hereinafter, the voltage of the data signal may represent a voltage range between a high level and a low level of the data signal) may be lower than the voltage of a general data signal. For example, the voltage of the general data signal may be between the power supply voltage V DD to the power supply voltage V SS The voltage of the small swing data signal can be within the range of the power supply voltage V DDQL to the power supply voltage V SS The power supply voltage V DDQL can be lower than the supply voltage V DDFor example, when a small-swing data signal is transmitted between the buffer die 110 and the core die 120, power consumption of the memory device 100 (eg, the amount of power consumed at the corresponding TSV) may be reduced.

[0038] In an exemplary embodiment, the cell capacitor of the core die 120 blocks or reduces the power supply voltage V DD 、V DDQL and V SS The small swing data signal between the first driver circuit 112 and the second driver circuit 121 can be improved in reliability because the small swing data signal has a low voltage. For example, the small swing data signal may be susceptible to noise such as leakage current. Since the unit capacitor of the core die 120 blocks or reduces noise, the distortion or deformation of the small swing data signal can be minimized.

[0039] The memory cell array 122 may include a plurality of memory cells each configured to store data and output the stored data. The memory cell array 122 may be electrically connected to the second driver circuit 121. The memory cell array 122 may output the data stored therein to the transmitter Tx of the second driver circuit 121. The memory cell array 122 may store a data signal from the receiver Rx of the second driver circuit 121.

[0040] For better understanding, the example is shown as the buffer die 110 connected to one core die 120, but the inventive concept is not limited thereto. For example, the memory device 100 may further include at least one additional core die similar in structure to the core die 120. Figure 2A , Figure 2B and Figure 6 A memory device 100 including multiple core dies is more fully described.

[0041] As described above, according to the embodiments of the inventive concept, by using a voltage lower than the power supply voltage V DD The power supply voltage V DDQL And the memory device 100 with reduced power consumption is provided using a low voltage small swing data signal. In addition, the memory device 100 with improved reliability of the small swing data signal can be provided by blocking or reducing noise in the core die 120 through the cell capacitor.

[0042] Figure 2A is a cross-sectional view of a general memory device MD. Figure 2A, the memory device MD may include a buffer die 110 and first to third core dies 120a to 120c sequentially stacked in the third direction DR3. The example is shown as the memory device MD including three core dies 120a to 120c, but the inventive concept is not limited thereto. In example embodiments, the number of core dies included in the memory device MD may be increased or decreased.

[0043] The buffer die 110 may include a power line distributor 111, a first driver circuit 112, and an interface circuit 113. The power line distributor 111 may include a power supply voltage V PPE , power supply voltage V SS , power supply voltage V DD , data signal Data and power supply voltage V DDQL The power supply voltage V PPE It can be a very high voltage for driving the memory device MD. The power supply voltage V PPE It can be a pumping voltage. DD can be lower than the supply voltage V PPE The power supply voltage V DDQL can be lower than the supply voltage V DD The power supply voltage V SS can be lower than the supply voltage V DDQL The data signal Data may include data to be stored in the memory device MD or data read from the memory device MD.

[0044] The power line distributor 111 may be connected to the first to third core dies 120a to 120c through corresponding feed lines FL. The feed line FL may include at least one microbump and at least one TSV connected continuously. The feed line FL may be a conductive line through which a power supply voltage is supplied or a data signal is transmitted. The feed line FL may include first to fifth feed lines FL1 to FL5.

[0045] For example, the power line distributor 111 can transmit the power supply voltage V PPE The power line distributor 111 can supply the power supply voltage V to the first core die 120a to the third core die 120c through the second feed line FL2. SS The power line distributor 111 can supply the power supply voltage V to the first core die 120a to the third core die 120c through the third feeding line FL3. DD The power line distributor 111 can supply the power supply voltage V to the first core die 120a to the third core die 120c through the fifth feeding line FL5. DDQL The power is supplied to the first to third core dies 120a to 120c.

[0046] For example, the power line distributor 111 may output the data signal Data to the first to third core dies 120 a to 120 c through the fourth feeding line FL4 or may receive the data signal Data from the first to third core dies 120 a to 120 c through the fourth feeding line FL4 .

[0047] The first driver circuit 112 and the interface circuit 113 may be circuits formed in the buffer die 110. The first driver circuit 112 and the interface circuit 113 may be electrically connected to the power line distributor 111.

[0048] The first core die 120a may include a second driver circuit 121a. The second driver circuit 121a may be Figure 1 The second core die 120b may include a third driver circuit 121b. The third core die 120c may include a fourth driver circuit 121c. The second to fourth driver circuits 121a to 121c may be electrically connected to the power line distributor 111 through first to fifth feed lines FL1 to FL5.

[0049] Meanwhile, as the memory device MD is miniaturized and highly integrated, the physical size of the buffer die 110 and the first to third core dies 120a to 120c can become smaller. In addition, a low voltage power supply voltage V DDQL To improve the power efficiency of the memory device MD. Figure 1 1. In the memory device 100, a highly integrated memory device MD driven using low power may be susceptible to noise.

[0050] Figure 2B 1 is a cross-sectional view of a memory device 100 including a unit capacitor according to an embodiment of the inventive concept. Figure 2B, the memory device 100 may include a buffer die 110 and a first core die 120a to a third core die 120c. In an exemplary embodiment, the buffer die 110 and the first core die 120a to the third core die 120c may be arranged in parallel. The buffer die 110 may include a power line distributor 111, a first driver circuit 112, and an interface circuit 113. Each of the first core die 120a to the third core die 120c may include a driver circuit (e.g., 121a, 121b, or 121c) and a plurality of unit capacitors. The buffer die 110 and the first core die 120a to the third core die 120c may be connected by a first feeder FL1 to a fifth feeder FL5. In an example embodiment, the buffer die 110 and the first core die 120a to the third core die 120c may come from different wafers. For example, the buffer die may be from a first wafer, and the first through third core dies 120 a through 120 c may be from a second wafer different from the first wafer.

[0051] The power line distributor 111, the first driver circuit 112, the interface circuit 113, the second driver circuit 121a to the fourth driver circuit 121c and the first feeder line FL1 to the fifth feeder line FL5 are similar to Figure 2A The power line distributor 111, the first driver circuit 112, the interface circuit 113, the second to fourth driver circuits 121a to 121c, and the first to fifth feeding lines FL1 to FL5 are described herein, and therefore, additional description will be omitted to avoid redundancy.

[0052] According to an embodiment of the inventive concept, each of the first to third core dies 120a to 120c may include a plurality of unit capacitors respectively disposed adjacent to the first to fifth feed lines FL1 to FL5. For example, the unit capacitors may be disposed adjacently in the first direction DR1 or the second direction DR2 relative to the TSV penetrating the core die. The unit capacitors may be formed in the core die. The unit capacitors may be decoupling capacitors that block or reduce noise introduced from adjacent feed lines.

[0053] For example, the unit capacitors 123a-1, 123b-1, and 123c-1 may block or reduce the power supply voltage V SS The second feed line FL2 is introduced to supply the power supply voltage V PPE The unit capacitors 123a-2, 123b-2, and 123c-2 can prevent or reduce the noise introduced into the power supply voltage V SS The unit capacitors 123a-3, 123b-3, and 123c-3 can block or reduce the noise introduced into the power supply voltage V DDThe unit capacitors 123a-4, 123b-4, and 123c-4 can block or reduce the noise introduced into the power supply voltage V DDQL The noise of the fifth feed line FL5.

[0054] In an exemplary embodiment, the unit capacitor may be arranged in an empty area of ​​the core die. For example, the unit capacitors 123a-1 to 123a-4 in the first core die 120a may be placed in a space where the second driver circuit 121a is not arranged. Because the unit capacitors 123a-1 to 123a-4 are arranged in the empty space of the first core die 120a, the physical size of the first core die 120a of the memory device 100 may not increase. For example, the unit capacitors 123b-1 to 123b-4 in the second core die 120b may be placed in a space where the third driver circuit 121b is not arranged. Because the unit capacitors 123b-1 to 123b-4 are arranged in the empty space of the second core die 120b, the physical size of the second core die 120b of the memory device 100 may not increase. For example, the unit capacitors 123c-1 to 123c-4 in the third core die 120c may be placed in a space where the fourth driver circuit 121c is not arranged. Since the unit capacitors 123c-1 to 123c-4 are disposed in the empty space of the third core die 120c, the physical size of the third core die 120c of the memory device 100 may not be increased. In example embodiments, the unit capacitors 123a-2, 123b-2, and 123c-2 may be omitted. Figure 7 The empty region in which the unit capacitor is disposed is described more fully.

[0055] Figure 3 is a detailed diagram showing the Figure 1 The circuit diagram of the transmitter Tx. Figure 3 , the transmitter Tx can be based on the power supply voltage V DD 、V DDQL and V SS The first data signal DT1 , the second data signal DT2 , and the clock signal CLK may be driven and generate a small swing data signal. Figure 3 The transmitter Tx can be Figure 1 The transmitter Tx of the first driver circuit 112 may be Figure 1 The transmitter Tx of the second driver circuit 121.

[0056] The transmitter Tx may include a multiplexer MUX, a first transistor M1, and a second transistor M2. The multiplexer MUX may be based on a power supply voltage V DD and V SS The power supply voltage VDD The first capacitor node NC1 supplied to the multiplexer MUX may be connected to the first unit capacitor C C1 The first unit capacitor C C1 It can block or reduce the voltage introduced to the power supply V DD If Figure 3 The transmitter Tx includes Figure 1 In the second driver circuit 121, the first unit capacitor C C1 can be a cell capacitor formed simultaneously with the capacitor of the memory cell, if Figure 3 The transmitter Tx includes Figure 1 In the first driver circuit 112, the first unit capacitor C C1 A typical capacitor may be formed in the form of a metal oxide semiconductor (MOS) capacitor.

[0057] The multiplexer MUX may receive a first data signal DT1, a second data signal DT2, and a clock signal CLK. The first data signal DT1 may be a signal including a logic value corresponding to the information to be transmitted by the transmitter Tx. The second data signal DT2 may be an inverted version of the first data signal DT1. The clock signal CLK may be a signal in which a high logic state and a low logic state are periodically repeated. The clock signal CLK may be used to control the synchronization timing of the multiplexer MUX.

[0058] The multiplexer MUX may generate a pull-up signal PU and a pull-down signal PD based on the first data signal DT1, the second data signal DT2 and the clock signal CLK. The logic value of the pull-up signal PU may correspond to the logic value of the first data signal DT1. The logic value of the pull-down signal PD may correspond to the logic value of the second data signal DT2.

[0059] The first transistor M1 may be connected between the second capacitor node NC2 and the first transmission node NT1 and may operate in response to the pull-up signal PU. The second capacitor node NC2 may receive the power supply voltage V DDQL The second capacitor node NC2 may be connected to the second unit capacitor C C2 The second unit capacitor C C2 It can block or reduce the voltage introduced to the power supply V DDQL If Figure 3 The transmitter Tx includes Figure 1 In the second driver circuit 121, the second unit capacitor C C2 can be a cell capacitor formed simultaneously with the capacitor of the memory cell, if Figure 3 The transmitter Tx includes Figure 1 In the first driver circuit 112, the second unit capacitor CC2 The first transmission node NT1 may be connected to a DQ pad (also called a pad), and a small-swing data signal may be generated at the DQ pad.

[0060] In an exemplary embodiment, when the first transistor M1 is turned on in response to the pull-up signal PU, the power supply voltage V DDQL May be supplied to the first transmission node NT1. In this case, the voltage corresponding to the small swing data signal generated at the DQ pad may increase. That is, the first transistor M1 may be a pull-up transistor. In this case, the second transistor M2 may be turned off.

[0061] The second transistor M2 may be connected between the first transmission node NT1 and the ground node Vss, and may operate in response to the pull-down signal PD. The first transmission node NT1 may be connected to a DQ pad.

[0062] In an exemplary embodiment, when the second transistor M2 is turned on in response to the pull-down signal PD, the power supply voltage V SS May be supplied to the first transmission node NT1. In this case, the voltage corresponding to the small swing data signal generated at the DQ pad may be reduced. That is, the second transistor M2 may be a pull-down transistor. In this case, the first transistor M1 may be turned off.

[0063] A small swing data signal may be generated at the DQ pad. A voltage corresponding to the small swing data signal may be determined based on the operation of the first transistor M1 and the operation of the second transistor M2. The voltage of the small swing data signal may be varied from the power supply voltage V DDQL to the power supply voltage V SS For example, the small-swing data signal may have a voltage ranging from 0V to 0.4V (eg, low level=0V and high level=0.4V).

[0064] In an exemplary embodiment, the first transistor M1 may be an NMOS transistor, and the second transistor M2 may be an NMOS transistor. DD and V SS A general transmitter of a CMOS structure driven by a PMOS transistor can use a PMOS transistor as a pull-up transistor and an NMOS transistor as a pull-down transistor. In contrast, a transmitter Tx according to an embodiment of the inventive concept can use a power supply voltage V DD Low supply voltage V DDQL A voltage of the DQ pad is formed, and may include a pull-up transistor and a pull-down transistor each implemented with an NMOS transistor for low voltage driving.

[0065] In an example embodiment, if Figure 3 The transmitter Tx includes Figure 1 In the second driver circuit 121, the first unit capacitor C C1 and the second unit capacitor C C2 Each of may be a cell capacitor formed simultaneously with the capacitor of the memory cell, if Figure 3 The transmitter Tx includes Figure 1 In the first driver circuit 112, the first unit capacitor C C1 and the second unit capacitor C C2 Each of may be a typical capacitor formed in the form of a MOS capacitor.

[0066] Figure 4 is a detailed diagram showing the Figure 1 The circuit diagram of the transmitter Tx. Figure 4 FIG. 4 shows a transmitter Tx implemented according to another embodiment. Figure 4 , the transmitter Tx can be based on the power supply voltage V DD and V SS and can be driven based on the first data signal DT1, the second data signal DT2, and the power supply voltage V generated at the voltage regulator REG. DDL Generates small swing data signals. Figure 4 The transmitter Tx can be Figure 1 The transmitter Tx of the first driver circuit 112 may be Figure 1 The transmitter Tx of the second driver circuit 121.

[0067] and Figure 3 The transmitter Tx is different. Figure 4 The transmitter Tx can be based on the power supply voltage V generated at the voltage regulator REG DDL The voltage regulator REG may be a device for generating a power supply voltage V adjustable within a given range. DDL The power supply voltage V DDL The voltage value can be greater than the power supply voltage V SS voltage value, and can be less than the power supply voltage V DD For example, the power supply voltage V DDL can be in the range from 0.4V to 0.7V. According to the operation of the voltage regulator REG, the power supply voltage V DDL The voltage value can vary in the range from 0.4V to 0.7V.

[0068] In an exemplary embodiment, Figure 1 The memory device 100 may include a voltage regulator REG that converts the power supply voltage VDDL The power line distributor 111 is provided to the buffer die 110. For example, the voltage regulator REG may be included in the buffer die 110 and the core die 120, respectively. The power supply voltage V DDL The power line distributor 111 provides power to the transmitter Tx of the core die 120. The core die 120 may include a circuit that blocks or reduces the power supply voltage V DDL The noise of the unit capacitor (for example, the fourth unit capacitor C C4 ).

[0069] The transmitter Tx may include a comparator, a first transistor M1, a second transistor M2, and a third transistor M3. The comparator may compare the voltage of the fourth capacitor node NC4 with the voltage of the second transmission node NT2, and may generate a comparison signal COMP. The comparison signal COMP may be a signal that controls the third transistor M3 to be turned on when the voltage of the fourth capacitor node NC4 is greater than the voltage of the second transmission node NT2.

[0070] The core die 120 may include a unit capacitor (eg, a third unit capacitor C C3 ). For example, the second transmission node NT2 can be connected to the third unit capacitor C C3 .if Figure 4 The transmitter Tx includes Figure 1 In the second driver circuit 121, the third unit capacitor C C3 can be a cell capacitor formed simultaneously with the capacitor of the memory cell, if Figure 4 The transmitter Tx includes Figure 1 In the first driver circuit 112, the third unit capacitor C C3 A typical capacitor may be formed in the form of a MOS capacitor.

[0071] The fourth capacitor node NC4 may receive the power supply voltage V from the voltage regulator REG. DDL The fourth capacitor node NC4 may be connected to the fourth unit capacitor C C4 The fourth unit capacitor C C4 It can block or reduce the voltage introduced to the power supply V DDL If Figure 4 The transmitter Tx includes Figure 1 In the second driver circuit 121, the fourth unit capacitor C C4 can be a cell capacitor formed simultaneously with the capacitor of the memory cell, if Figure 4 The transmitter Tx includes Figure 1 In the first driver circuit 112, the fourth unit capacitor CC4 A typical capacitor may be formed in the form of a MOS capacitor.

[0072] The third transistor M3 may be connected between the first capacitor node NC1 and the second transmission node NT2 and may operate in response to the comparison signal COMP. The first capacitor node NC1 may receive the power supply voltage V DD The first capacitor node NC1 may be connected to the first unit capacitor C C1 The first unit capacitor C C1 It can block or reduce the voltage introduced to the power supply V DD noise.

[0073] The first transistor M1 may be connected between the second transmission node NT2 and the first transmission node NT1 and may operate in response to the first data signal DT1. The first data signal DT1 may be a signal including a logic value corresponding to the information to be transmitted by the transmitter Tx. The first transmission node NT1 may be connected to a DQ pad. A small swing data signal may be generated at the DQ pad. The first transistor M1 may be a pull-up transistor.

[0074] The second transistor M2 may be connected between the first transmission node NT1 and the ground node Vss and may operate in response to the second data signal DT2. The second data signal DT2 may be an inverted version of the first data signal DT1. The second transistor M2 may be a pull-down transistor.

[0075] A small swing data signal may be generated at the DQ pad. A voltage corresponding to the small swing data signal may be determined based on the operation of the first transistor M1 to the third transistor M3. The voltage of the small swing data signal may be derived from the power supply voltage V DDL to the power supply voltage V SS For example, the power supply voltage V SS Can be 0V. Supply voltage V DDL The supply voltage V DDL The value of can be changed by the voltage regulator REG.

[0076] In an exemplary embodiment, the first transistor M1 may be an NMOS transistor, the second transistor M2 may be an NMOS transistor, and the third transistor M3 may be an NMOS transistor. The transmitter Tx may generate a small swing data signal by using an NMOS transistor suitable for low voltage driving.

[0077] Figure 5 is a detailed diagram showing the Figure 1 The circuit diagram of the receiver Rx. Figure 5 , the receiver Rx can be based on the power supply voltage VDDQL and V SS is driven and can be based on the reference voltage V REF To determine the logic level of the small swing data signal. Figure 5 The receiver Rx can be Figure 1 The receiver Rx of the first driver circuit 112 may be Figure 1 The receiver Rx of the second driver circuit 121.

[0078] The receiver Rx may include first to fifth transistors T1 to T5 and a boost capacitor C B The first transistor T1 may be connected between the first receiving node NR1 and the output node No, and may operate in response to a voltage of the input node Ni. The input node Ni may receive a small swing data signal. The output node No may be a node forming a voltage of a determined logic level of the small swing data signal.

[0079] The second transistor T2 may be connected between the first receiving node NR1 and the second receiving node NR2 and may respond to the reference voltage V REF The reference voltage V REF Can be used as a reference for determining the logic level of a small swing data signal. For example, the reference voltage V REF It can be 0.2V.

[0080] The third transistor T3 may be connected between the second reception node NR2 and the ground node Vss, and may operate in response to a voltage of the second reception node NR2.

[0081] The fourth transistor T4 may be connected between the output node No and the ground node Vss, and may operate in response to the voltage of the second reception node NR2.

[0082] The fifth transistor T5 may be connected between the fifth capacitor node NC5 and the first receiving node NR1 and may operate in response to the voltage of the second receiving node NR2. The fifth capacitor node NC5 may receive the power supply voltage V DDQL The fifth capacitor node NC5 may be connected to the fifth unit capacitor C C5 The fifth unit capacitor C C5 It can block or reduce the voltage introduced to the power supply V DDQL If Figure 5 The receiver Rx includes Figure 1 In the second driver circuit 121, the fifth unit capacitor C C5 can be a cell capacitor formed simultaneously with the capacitor of the memory cell, if Figure 5 The receiver Rx includes Figure 1In the first driver circuit 112, the fifth unit capacitor C C5 It may be a typical capacitor formed with, for example, a MOS capacitor.

[0083] Boost capacitor C B can be connected between the input node Ni and the second receiving node NR2. In an exemplary embodiment, when the boost capacitor C B When the voltage of the input node Ni is transmitted to the second receiving node NR2, the receiver Rx can determine the logic level of the small-swing data signal more accurately and faster.

[0084] Figure 6 is a perspective view of a memory device 100 according to an embodiment of the inventive concept. Figure 6 , the memory device 100 may include a buffer die 110 and first to third core dies 120a to 120c sequentially stacked in a third direction DR3. The buffer die 110 may be connected to the first core die 120a through a microbump. The first core die 120a may be connected to the second core die 120b through a microbump. The second core die 120b may be connected to the third core die 120c through a microbump.

[0085] Each of the first to third die 120a to 120c may include a plurality of die regions RG. The die region RG may include a lower region supplied with a power supply voltage through a corresponding micro bump, a lower region where the micro bump does not exist or cannot be provided, and an empty lower region.

[0086] In an exemplary embodiment, the buffer die 110 and the first to third core dies 120a to 120c may include a plurality of TSVs overlapping the micro bumps in the third direction DR3 and penetrating the buffer die 110 and the first to third core dies 120a to 120c. The TSVs may be electrically connected to the corresponding micro bumps.

[0087] Figure 7 is a detailed diagram showing the Figure 6 Diagram of the core die area RG. Figure 7 , the core die region RG viewed from the third direction DR3 is shown. The core die region RG may include a plurality of lower regions arranged in the first direction DR1 and the second direction DR2. Each lower region may be a region supplied with a power supply voltage, a region in which a microbump cannot be set, or an empty region. The number of lower regions included in the core die region RG, the size of the lower regions, and the shape of the lower regions are shown by way of example, but the inventive concept is not limited thereto. The number of lower regions included in the core die region RG and the size of the lower regions may be increased or decreased, and the shape of the lower regions may be changed.

[0088] By the power supply voltage V SS The lower area of ​​the marker can be connected to a supply voltage V SS The power supply voltage V PPE The lower area of ​​the marker can be connected to a supply voltage V PPE The power supply voltage V DD The lower area of ​​the marker can be connected to a supply voltage V DD The power supply voltage V DDQL The lower area of ​​the marker can be connected to a supply voltage V DDQL of micro bumps.

[0089] The lower region marked by no micro bump may be a region where the micro bump is not disposed or where the micro bump cannot be disposed according to the design or process of the memory device 100 .

[0090] The lower region marked by empty may represent an empty region (e.g., a circuit-free region) of the core die. In an exemplary embodiment, a cell capacitor may be disposed in the lower region marked by empty. The cell capacitor may block or reduce noise introduced from a TSV adjacent in the first direction DR1 or the second direction DR2 and through which a power supply voltage is transmitted.

[0091] Figure 8 1 is a block diagram illustrating a memory system 1000 according to an embodiment of the inventive concept. Figure 8 , the memory system 1000 may include a memory device 100 and a memory controller 200. The memory controller 200 may transmit an address ADDR and a command CMD to the memory device 100 for the purpose of storing data in the memory device 100 or reading data stored in the memory device 100.

[0092] In an exemplary embodiment, the address ADDR may include a row address RA and a column address CA. The instruction CMD may include an activation instruction, a write instruction, a read instruction, or a precharge instruction. However, the inventive concept is not limited thereto. For example, the address ADDR may include various types of addresses, and the instruction CMD may include various types of instructions.

[0093] Under the control of the memory controller 200 , the memory device 100 may store data received from the memory controller 200 or may transmit data stored therein to the memory controller 200 .

[0094] In an exemplary embodiment, the memory device 100 may be a dynamic random access memory (DRAM), and the memory controller 200 and the memory device 100 may communicate with each other based on a double data rate (DDR) interface. However, the inventive concept is not limited thereto. For example, the memory device 100 may be one of various memory devices (such as static random access memory (SRAM), synchronous DRAM (SDRAM), magnetic RAM (MRAM), ferroelectric RAM (FRAM), resistive RAM (ReRAM), and phase change RAM (PRAM)), and the memory controller 200 and the memory device 100 may communicate with each other based on various interfaces (such as low power DDR (LPDDR), universal serial bus (USB), modular multi-level converter (MMC), peripheral component interconnect (PCI), high-speed PCI (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), small computer system interface (SCSI), enhanced standard (small / system) device interface (ESDI), and integrated drive electronics (IDE)).

[0095] The memory device 100 may be based on a power supply voltage V DD Low supply voltage V DDQL The memory device 100 may be a low-power memory device that is driven and stores data based on a low-voltage, small-swing data signal. The memory device 100 may be a device that includes three-dimensionally stacked memory dies (eg, a buffer die and a core die). Figure 8 The memory device 100 may be Figure 1 The memory device 100 or Figure 6 A memory device 100 is provided.

[0096] Fig. 9 is a diagram showing a method according to an example embodiment Figure 8 A block diagram of a memory device 100 is shown. Figure 8 and Fig. 9 , the memory device 100 may include a command decoder 131 , a control logic circuit 132 , a memory cell array 122 , and an interface circuit 113 .

[0097] The command decoder 131 may receive a command CMD from the memory controller 200 . The command decoder 131 may provide a result of decoding the command CMD to the control logic circuit 132 .

[0098] The control logic circuit 132 may control the components of the memory device 100 based on the decoding result from the instruction decoder 131. For example, the control logic circuit 132 may control at least a portion of the X-decoder X-DEC, the Y-decoder Y-DEC, and the interface circuit 113 so that an operation corresponding to the decoding result of the instruction decoder 131 (such as a read operation or a write operation) is performed.

[0099] The memory cell array 122 may include a plurality of memory cells. The plurality of memory cells may be connected to word lines and bit lines. The word lines may be connected to an X-decoder X-DEC, and the bit lines may be connected to a Y-decoder Y-DEC.

[0100] The interface circuit 113 may exchange data with the memory controller 200. The interface circuit 113 may include a sense amplifier SA and a flip-flop FF. The sense amplifier SA may be a circuit that amplifies an analog signal. The flip-flop FF may be a circuit that holds or stores a data signal.

[0101] In an exemplary embodiment, the memory device 100 may be implemented using a buffer die and a core die that are stacked three-dimensionally. For example, the interface circuit 113 may include Figure 1 The memory cell array 122 may be included in the buffer die 110. Figure 1 At least a portion of the control logic circuit 132 (eg, a driver circuit) may be included in the core die 120. Figure 1 In the core die 120.

[0102] Fig.10 is a flowchart illustrating an operating method of a memory device according to an embodiment of the inventive concept. The memory device may be Figure 1 The memory device 100 of FIG. Figure 1 and Fig.10 , the memory device 100 may include a buffer die 110 and a core die 120 electrically connected to the buffer die 110 through first and second TSVs.

[0103] In operation S110, the memory device 100 may transmit the power supply voltage V DD 、V DDQL and V SS At least one of the power lines is supplied from the power line distributor 111 of the buffer die 110 to the core die 120. In an exemplary embodiment, the cell capacitor of the core die 120 can block or reduce the voltage introduced to the power supply voltage V DD 、V DDQL and V SS at least one noise of at least one of the.

[0104] In an exemplary embodiment, the core die 120 may be connected to the buffer die 110 through first to fourth TSVs. The first to third TSVs may transmit the power supply voltage V DD 、V DDQL and V SS The fourth TSV can transmit a small swing data signal between the first driver circuit 112 and the second driver circuit 121. The chip 120 may include a power supply voltage V DD 、V DDQL and V SS The first to third unit capacitors correspond to the first to third unit capacitors. The first to third unit capacitors can block or reduce the introduction of the power supply voltage V DD 、V DDQL and V SS The first noise to the third noise.

[0105] In operation S120, the memory device 100 may generate a small swing data signal based on the power supply voltage supplied in operation S110. In an exemplary embodiment, the memory device 100 may generate a small swing data signal based on the power supply voltage V DD 、V DDQL and V SS In operation S130 , the memory device 100 may transmit the small swing data signal generated in operation S120 through one or more corresponding TSVs.

[0106] In an exemplary embodiment, the memory device 100 may transmit a small swing data signal from the core die 120 to the buffer die 110. For example, in operation S120, the transmitter Tx included in the core die 120 of the memory device 100 may transmit a small swing data signal based on the power supply voltage V DD 、V DDQL and V SS In operation S110, the power supply voltage V transmitted through one or more corresponding TSVs may be used to generate a small swing data signal. DD 、V DDQL and V SS to drive the transmitter Tx of the core die 120. In operation S130, the memory device 100 may transmit the small swing data signal from the transmitter Tx of the core die 120 to the receiver Rx of the buffer die 110 through one or more corresponding TSVs.

[0107] In an exemplary embodiment, the memory device 100 may transmit a small swing data signal from the buffer die 110 to the core die 120. For example, in operation S120, the transmitter Tx included in the buffer die 110 of the memory device 100 may transmit a small swing data signal based on the power supply voltage VDD 、V DDQL and V SS Generate a small swing data signal. In operation S130, the memory device 100 may transmit the small swing data signal from the transmitter Tx of the buffer die 110 to the receiver Rx of the core die 120 through one or more corresponding TSVs. In operation S110, the power supply voltage V transmitted through one or more corresponding TSVs may be used to generate a small swing data signal. DD 、V DDQL and V SS To drive the receiver Rx of the core die 120 .

[0108] In an exemplary embodiment, the voltage of the small swing data signal may be varied from the power supply voltage V SS to the power supply voltage V DDQL within the range.

[0109] According to the inventive concept, a memory device is provided, which is driven with a low power supply voltage and can reduce power consumption by transmitting a small-swing data signal having a voltage lower than that of a general data signal, and an operating method thereof.

[0110] Furthermore, a memory device and an operating method thereof are provided, in which an influence caused by noise is reduced by blocking any other voltage through a cell capacitor of a core die and reliability of data stored in the memory device is improved.

[0111] While the inventive concept has been described with reference to exemplary embodiments of the inventive concept, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A memory device, comprising: a buffer die configured to: output a first power supply voltage to a first through substrate via, output a second power supply voltage to a third through substrate via, output a third power supply voltage to a fourth through substrate via, and receive a first small swing data signal generated based on the first power supply voltage to the third power supply voltage from the second through substrate via; as well as a first core die electrically connected to the buffer die through a first through substrate via and a second through substrate via, and further electrically connected to the buffer die through a third through substrate via and a fourth through substrate via, the first core die including a first unit capacitor electrically connected to the first through substrate via and configured to block a first noise introduced into a first power supply voltage received through the first through substrate via, the first core die being configured to generate a first small swing data signal based on the first power supply voltage to a third power supply voltage, and output the first small swing data signal to the second through substrate via, The high level voltage of the first small swing data signal is lower than the first power supply voltage, the second power supply voltage is lower than the first power supply voltage, and the third power supply voltage is lower than the second power supply voltage.

2. The memory device according to claim 1, in, First chip bare die: Also included is a second unit capacitor connected to the third through substrate via and configured to block a second noise introduced into a second power supply voltage received through the third through substrate via.

3. The memory device according to claim 2, wherein: The first core die also includes a transmitter configured to be driven based on the first power supply voltage to the third power supply voltage and generate a first small swing data signal, and The transmitter includes: a multiplexer configured to be driven based on a first power supply voltage and a third power supply voltage and to generate a pull-up signal and a pull-down signal based on a first data signal, a second data signal corresponding to an inverted version of the first data signal, and a clock signal; a first transistor connected between a first node configured to receive a second power supply voltage and a second node configured to output a first small-swing data signal, and configured to operate in response to a pull-up signal; and The second transistor is connected between the second node and a third node configured to receive a third power supply voltage and is configured to operate in response to a pull-down signal.

4. The memory device according to claim 3, wherein: The first transistor and the second transistor are NMOS transistors.

5. The memory device according to claim 2, further comprising: a voltage regulator configured to provide a second supply voltage to the buffer die, The first core die includes a transmitter, which is driven based on a first power supply voltage to a third power supply voltage and is configured to generate a first small swing data signal, and The transmitter includes: a comparator configured to compare a second power supply voltage with a voltage of a first node and output a comparison signal; a first transistor connected between a second node and a first node, the second node being configured to receive the first power supply voltage, the first transistor being configured to operate in response to the comparison signal; a second transistor connected between the first node and a third node configured to output a first small-swing data signal, the second transistor being configured to operate in response to the first data signal; and a third transistor connected between a third node and a fourth node configured to receive a third power supply voltage, the third transistor being configured to operate in response to a second data signal, the second data signal corresponding to an inverted version of the first data signal.

6. The memory device according to claim 2, wherein: The buffer die includes a receiver driven based on the second power supply voltage and the third power supply voltage and configured to determine a logic level of the first small-swing data signal, and The receiver includes: a first transistor connected between the first node and an output node forming a voltage of a determined logic level and configured to operate in response to a voltage of an input node configured to receive a first small-swing data signal; a second transistor connected between the first node and the second node and configured to operate in response to a reference voltage used as a reference for determining a logic level; a third transistor connected between the second node and a third node configured to receive a third power supply voltage and configured to operate in response to a voltage of the second node; a fourth transistor connected between the output node and the third node and configured to operate in response to a voltage of the second node; a fifth transistor connected between a fourth node and the first node and configured to operate in response to a voltage of the second node, the fourth node being configured to receive a second power supply voltage; and A boost capacitor is connected between the input node and the second node.

7. The memory device according to claim 2, wherein: The voltage of the first small-swing data signal is within a range from the third power supply voltage to the second power supply voltage.

8. The memory device according to claim 1, wherein: The first die includes a memory cell array having a plurality of memory cells, Each of the plurality of memory cells includes a transistor and a capacitor connected to the transistor and configured to store data, and The first unit capacitor and the capacitor of the memory unit are located at the same height.

9. The memory device according to claim 1, wherein: The buffer die and the first core die come from different wafers.

10. The memory device of claim 1, further comprising: a second core die, arranged in parallel with the buffer die and the first core die, and configured to receive a first power supply voltage through a first feed line including a first through-substrate via and transmit or receive a first small-swing data signal through a second feed line including a second through-substrate via, The first feed line includes a first microbump disposed between the buffer die and the first core die and a second microbump disposed between the first core die and the second core die, and The second feed line includes a third micro-bump disposed between the buffer die and the first core die and a fourth micro-bump disposed between the first core die and the second core die.

11. The memory device according to claim 1, wherein: The buffer die includes: a power line distributor configured to output a first power supply voltage to a first through substrate via; a first driver circuit driven based on a first power supply voltage and including a receiver configured to receive a first small swing data signal from a second through substrate via and a transmitter configured to output a second small swing data signal to the second through substrate via; and The interface circuit is electrically connected to the first driver circuit and includes a flip-flop configured to hold the first small-swing data signal and a sense amplifier configured to amplify the first small-swing data signal.

12. The memory device according to claim 1, wherein: The first die also includes: a second driver circuit driven based on the first power supply voltage and including a transmitter configured to output the first small swing data signal to the second through substrate via and a receiver configured to receive the second small swing data signal from the second through substrate via; and The memory cell array is configured to store data corresponding to the first small swing data signal and data corresponding to the second small swing data signal.

13. A memory device, the memory device comprising: a buffer die configured to: output a first power supply voltage to a first through substrate via, output a second power supply voltage to a third through substrate via, output a third power supply voltage to a fourth through substrate via, generate a small swing data signal based on the first power supply voltage to the third power supply voltage, and output the small swing data signal to the second through substrate via; as well as a core die electrically connected to the buffer die through first and second through substrate vias, further electrically connected to the buffer die through third and fourth through substrate vias, the core die including a first unit capacitor electrically connected to the first through substrate via and configured to block a first noise introduced into a first power supply voltage received through the first through substrate via, the core die configured to receive a small swing data signal from the second through substrate via, The high level voltage of the small swing data signal is lower than the first power supply voltage, the second power supply voltage is lower than the first power supply voltage, and the third power supply voltage is lower than the second power supply voltage.

14. The memory device according to claim 13, wherein: The core die also includes a second unit capacitor connected to the third through-substrate via and configured to block a second noise introduced to a second power supply voltage received through the third through-substrate via.

15. The memory device of claim 14, wherein: The buffer die includes a transmitter that is driven based on a first power supply voltage to a third power supply voltage and configured to generate a small swing data signal, and The transmitter includes: a multiplexer configured to be driven based on a first power supply voltage and a third power supply voltage and to generate a pull-up signal and a pull-down signal based on a first data signal, a second data signal corresponding to an inverted version of the first data signal, and a clock signal; a first transistor connected between a first node configured to receive a second power supply voltage and a second node configured to output a small-swing data signal, and the first transistor is configured to operate in response to a pull-up signal; and The second transistor is connected between the second node and a third node configured to receive a third power supply voltage, and the second transistor is configured to operate in response to the pull-down signal.

16. The memory device of claim 14, wherein: The buffer die includes a transmitter driven based on a first power supply voltage to a third power supply voltage and configured to generate a small swing data signal, and The transmitter includes: a comparator configured to compare the second power supply voltage with the voltage of the first node and output a comparison signal; a first transistor connected between a second node and the first node, the second node being configured to receive a first power supply voltage, and the first transistor being configured to operate in response to a comparison signal; a second transistor connected between the first node and a third node configured to output a small-swing data signal, and the second transistor is configured to operate in response to the first data signal; and A third transistor is connected between the third node and a fourth node configured to receive a third power supply voltage, and the third transistor is configured to operate in response to a second data signal corresponding to an inverted version of the first data signal.

17. The memory device of claim 14, wherein: The core die includes a receiver driven based on a second power supply voltage and a third power supply voltage and configured to determine a logic level of the small swing data signal, and The receiver includes: a first transistor connected between the first node and an output node forming a voltage of a determined logic level and configured to operate in response to a voltage of an input node configured to receive a small swing data signal; a second transistor connected between the first node and the second node and configured to operate in response to a reference voltage used as a reference for determining a logic level; a third transistor connected between the second node and a third node configured to receive a third power supply voltage and configured to operate in response to a voltage of the second node; a fourth transistor connected between the output node and the third node and configured to operate in response to a voltage of the second node; a fifth transistor connected between a fourth node and the first node and configured to operate in response to a voltage of the second node, the fourth node being configured to receive a second power supply voltage; and A boost capacitor is connected between the input node and the second node.

18. A method of operating a memory device, the memory device comprising a buffer die and a core die electrically connected to the buffer die through a first through substrate via and a second through substrate via, wherein: The core die is further electrically connected to the buffer die through a third through substrate via and a fourth through substrate via, the method comprising the following steps: supplying a first supply voltage from the buffer die to the core die through a first through substrate via; blocking or reducing a first noise introduced to a first power supply voltage by a first unit capacitor of the core die, the first unit capacitor being electrically connected to a first through-substrate via; supplying a second power supply voltage from the buffer die to the core die through a third through substrate via, the second power supply voltage being less than the first power supply voltage; supplying a third power supply voltage from the buffer die to the core die through a fourth through substrate via, the third power supply voltage being less than the second power supply voltage; generating a small swing data signal at a buffer die or a core die based on the first power supply voltage to the third power supply voltage, wherein a high level of the small swing data signal has a voltage lower than the first power supply voltage; and The small swing data signal is transmitted through the second through substrate via.

19. The method according to claim 18, further comprising the steps of: A second noise introduced to the second power supply voltage is blocked or reduced by a second unit capacitor of the core die, the second unit capacitor being electrically connected to the third through-substrate via.

20. The method according to claim 19, in, The voltage of the small-swing data signal is within a range from the third power supply voltage to the second power supply voltage.

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