Monolithic high voltage transceiver connected to two different power supply voltage domains

Abstract

A transceiver device and a method are disclosed for interfacing between at least two different voltage domains, namely a first supply voltage domain having a higher first supply voltage and a second supply voltage domain having a lower second supply voltage. The transceiver device has a first interface powered by the first supply voltage and adapted for interfacing with at least one external first digital device operating in the first supply voltage domain, a second interface powered by the second supply voltage and adapted for interfacing with an external communication bus operating in the second supply voltage domain, a first internal communication link adapted for transferring transmission data, which can be generated by the external first digital device operating in the first supply voltage domain, from the first interface to the second interface, and a second internal communication link adapted for transferring transmission data, which can be supplied from the external communication bus operating in the second supply voltage domain, from the second interface to the first interface.

Description

TECHNICAL FIELD

[0001] The present invention relates to a transceiver device for interfacing between at least two different voltage domains, and to a method of interfacing between at least two different voltage domains. BACKGROUND

[0002] In the automotive industry, in addition to efforts to reduce CO2 emissions, mild hybrid electric vehicles (MHEV) have been introduced, which have two board net voltage domains, in particular, on the one hand a board net voltage domain of 12 V or 24 V, and on the other hand a board net voltage domain of 48 V. In such MHEV, electric power high power applications including vehicle electric motors, such as electric starter generators, are connected to the board net of 48 V, which typically operate in the range of 1 to 15 kW.

[0003] Controller Area Network (CAN) bus is commonly used in automotive and industrial automation applications. The CAN bus system was developed by Bosch in 1983 and publicly released in 1986 together with Intel. The CAN bus has evolved into a bus standard in automotive and industrial automation applications and is described in ISO 11898. In the case of extended CAN FD, which was developed by Bosch in 2011 and released in 2012, the CAN bus can support bit rates up to 8 Mbps if the network topology is properly terminated.

[0004] In MHEV, 12 V board net electronic control units (ECU) and 48 V board net units are connected to the same Controller Area Network (CAN) bus network. To implement such a 12 V / 48 V hybrid CAN network, the CAN transceiver of the ECU running at 48 V must tolerate common mode differences and have provisions to limit the maximum potential voltage on the CAN bus line and limit the reverse current into the CAN bus line.

[0005] In a 12 V / 48 V hybrid CAN network, the ECU running at 48 V typically has four power connector pins:

[0006] V BN48 : 48 V board net connector (e.g. K1.40),

[0007] GND 48 : 48 V board net ground connector (e.g. K1.41),

[0008] V BN12 / 24 : 12 V or 24 V board net connector (e.g. K1.30), and

[0009] GND 12 / 24: 12V or 24V board net ground connector (e.g. K1.31).

[0010] 48V CAN transceiver is typically connected between the 12V / 24V voltage power domain and the 48V voltage power domain as shown and further described below. Figure 1

[0011] In MHEVs, the ground of the two board net domains (power voltage domains) is connected somewhere. The location of this common ground connection depends on the car manufacturer. Although the ground is connected somewhere, the car transient processes in combination with the (long) wiring harness can cause a ground offset and common mode transients between the ECU ground pin, i.e. GND 12 / 24 and GND 48 . This can cause communication disturbances. In addition, a ground failure situation can occur, resulting in a high voltage difference between GND 12 / 24 and GND 48 .

[0012] To overcome these problems present in current 48V ECUs, a CAN transceiver with high voltage galvanic isolation is used to process or connect to the two board net domains. As a galvanic isolation barrier, the following methods can be used: (voltage) transformer, capacitor or optocoupler. All these known galvanic isolation barriers are expensive solutions, because such a CAN transceiver consists of multiple integrated circuit dies in one package (multi-chip module package). Even worse, a discrete solution can be applied comprising a separate CAN transceiver device and one or more separate galvanic isolation devices.

[0013] Although the above description of the background of the invention relates to prior art ECUs running on a 48V, 48V CAN transceiver and 12V / 48V or 24V / 48V hybrid CAN network, which ECUs have been developed in the automotive industry for MHEVs, as will be disclosed hereinafter, the invention has been developed initially in this technical field, but the invention can be applied generically to interfacing with other bus systems, such as the Local Interconnect Network (LIN) bus (as described in ISO 17987) and the FlexRay bus (as described in ISO 17458-1 to 17458-5), or more generally to interfacing between different power voltage domains having different power supply voltages than 12 / 24V and 48V (as used in the automotive industry). SUMMARY

[0014] The invention relates to a transceiver device for interfacing between at least two different voltage domains, and to a method of interfacing between at least two different voltage domains.

[0015] ​It is a general object of the present invention to provide an apparatus for digital interfacing between a high voltage power domain and a low voltage power domain and a method for digital interfacing between a high voltage power domain and a low voltage power domain to reduce or eliminate the impact of ground offset, common mode transient and ground failure scenarios without electrical isolation, thereby enabling a solution with a single integrated circuit die. Further objects of the present invention include providing common mode tolerance and taking measures to prevent high voltage and current passing from one domain to the other.

[0016] This object is achieved by the subject matter having the features according to the independent claims. Preferred and advantageous embodiments are described in the dependent claims. In particular, the object is achieved by a transceiver apparatus according to the appended independent claim 1 and a method according to the appended independent claim 19. Further embodiments of the invention are described in the dependent claims.

[0017] According to a first exemplary embodiment of the present invention, a transceiver apparatus is provided for interfacing between at least two different voltage domains, namely a first power supply voltage domain having a higher first power supply voltage and a second power supply voltage domain having a lower second power supply voltage, wherein the transceiver apparatus has:

[0018] a first interface powered by the first power supply voltage and adapted to interface with at least one external first digital device operating in the first power supply voltage domain;

[0019] a second interface powered by the second power supply voltage and adapted to interface with an external communication bus operating in the second power supply voltage domain;

[0020] a first internal communication link adapted to transfer transmission data, which can be generated (or can be generated) by the external first digital device operating in the first power supply voltage domain, from the first interface to the second interface, and

[0021] a second internal communication link adapted to transfer transmission data, which can be supplied (or can be supplied, or can be provided) from the external communication bus operating in the second power supply voltage domain, from the second interface to the first interface. Here, in particular, the reception data can originate from a device operating in the second power supply voltage domain and connected to the communication bus.

[0022] By providing the first internal communication and the second internal communication for transmitting transmission data and receiving data, the impact of ground offset, common mode transient and ground failure scenarios can be addressed for duplex transmission without providing electrical isolation. This, in turn, enables the following advantageous embodiments.

[0023] The transceiver device according to the first exemplary embodiment of the present application can have more than one first internal communication link and second internal communication link, e.g. a further first internal communication link and second internal communication link for transmitting the device mode indication signal and a yet further first internal communication link and second internal communication link for transmitting the device status information signal.

[0024] In an advantageous embodiment of the present application, the transceiver device comprising the first interface, the second interface, the first internal communication link and the second internal communication link, in particular the further first internal communication link and the second internal communication link, can be implemented as a monolithic integrated circuit. In a particular advantageous embodiment thereof, the monolithic integrated circuit is implemented in silicon-on-insulator (SOI) technology.

[0025] In an embodiment of the present application, the transceiver device can further have at least two ground pins, comprising a first ground pin adapted for connection to a ground potential of the first power supply voltage domain and a second ground pin adapted for connection to a ground potential of the second power supply voltage domain.

[0026] In an embodiment of the present application, the transceiver device can further have a common mode and ground offset range in a range starting from more than about ±3 V but not more than about ±70 V.

[0027] In an embodiment of the present application, the first power supply voltage is essentially a nominal 48 V or higher. In an embodiment of the present application, the second power supply voltage is essentially a nominal 12 V or essentially a nominal 24 V.

[0028] In an embodiment of the present application, the first interface can have a transmission data input adapted for receiving transmission data, e.g. from a first digital device operating in the first power supply voltage domain, and a reception data output adapted for transmitting reception data, e.g. to a second digital device operating in the first power supply voltage domain.

[0029] In a further development of this embodiment, the first digital device and the second digital device operating in the first power supply voltage domain can be the same digital device, and / or the first digital device and the second digital device operating in the first power supply voltage domain can jointly form a microcontroller unit.

[0030] In an embodiment of the present application, the second interface can have at least one communication bus pin adapted for transmitting transmission data to and / or receiving reception data from an external communication bus operating in the second power supply voltage domain.

[0031] In a further development of this embodiment, the external communication bus operating in the second power supply voltage domain can be selected from the group consisting of a CAN bus, a Flexray bus, a LIN bus and an Ethernet.

[0032] In a first particular embodiment of the application, the first and second internal communication links can be based on differential voltage transmission with respect to the transmission of transmit data and receive data, respectively.

[0033] In a second particular embodiment of the application, which is an alternative to the first particular embodiment of the application as described above, the first and second internal communication links are based on digital current loop transmission with respect to the transmission of transmit data and receive data, respectively.

[0034] By implementing the first and second internal communication links as being based on differential voltage transmission or on digital current loop transmission, the internal communication links provide tolerance to ground offset, common mode transients, and minimize reverse current into the lines of the second (lower) power supply voltage domain in case of ground failure.

[0035] In a further development of the first particular embodiment of the application, the first internal communication link can comprise a first differential voltage transmitter and a first differential voltage receiver. The first differential voltage transmitter can be referenced, in particular can be operated from, the first power supply voltage domain and can be adapted to receive transmit data generated by a first digital device operating in the first power supply voltage domain via the first interface, to generate and output a first differential voltage signal for transmitting the transmit data. The first differential voltage receiver can be referenced, in particular can be operated from, the second power supply voltage domain and can be adapted to receive the differential voltage signal transmitted by the first differential voltage transmitter, to transmit a first single-ended digital signal for transmitting the transmit data to an external communication bus operating in the second power supply voltage domain via the second interface.

[0036] In a respective further development of the first particular embodiment of the application, the second internal communication link can comprise a second differential voltage transmitter and a second differential voltage receiver. The second differential voltage transmitter can be referenced, in particular can be operated from, the second power supply voltage domain and can be adapted to receive receive data supplyable from an external communication bus operating in the second power supply voltage domain via the second interface, to generate and output a second differential voltage signal for transmitting the receive data. The second differential voltage receiver can be referenced, in particular can be operated from, the first power supply voltage domain and can be adapted to receive the differential voltage signal transmitted by the second differential voltage transmitter, to transmit a second single-ended digital signal for transmitting the receive data to a second digital device operating in the first power supply voltage domain via the first interface.

[0037] In a corresponding further development of the first specific embodiment of the present application, the first differential voltage transmitter can have a first switch-based H-bridge, which can be referenced, in particular operated from, a first supply voltage domain, the first differential voltage receiver can have a first voltage divider resistor ladder and a first comparator, which can be referenced, in particular operated from, a second supply voltage domain. The first voltage divider resistor ladder can have a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, the first resistor substantially having a second resistance value, the second resistor substantially having a first resistance value, the third resistor substantially having the first resistance value, the fourth resistor substantially having the second resistance value. A ratio between the first resistance value and the second resistance value can be determined from the following equation:

[0038] (R2 / R1) = (V1 / V2)-1,

[0039] wherein R1 is the first resistance value, R2 is the second resistance value, V1 is a nominal value of the first supply voltage, V2 is a nominal value of the second supply voltage.

[0040] A first differential voltage signal output from the first switch-based H-bridge can be applied across the series connection consisting of the first resistor to the fourth resistor. The first voltage divider resistor ladder can output a first auxiliary differential voltage signal from a first connection point connected between the first resistor and the second resistor to a second connection point connected between the third resistor and the fourth resistor. A third connection point connected between the second resistor and the third resistor can be connected to the second domain ground. The first comparator has an input, an inverting input and an output, and can receive the first auxiliary differential voltage signal applied to its input and its inverting input, and can output a first single-ended digital signal from its output.

[0041] In a corresponding further development of the first specific embodiment of the present application, the second differential voltage transmitter can have a second switch-based H-bridge, which can be referenced, in particular operated from, a second supply voltage domain, the second differential voltage receiver can have a second voltage divider resistor ladder and a second comparator, which can be referenced, in particular operated from, a first supply voltage domain. The second voltage divider resistor ladder can have a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, the first resistor substantially having a second resistance value, the second resistor substantially having a first resistance value, the third resistor substantially having the first resistance value, the fourth resistor substantially having the second resistance value. A ratio between the first resistance value and the second resistance value can be determined from the following equation:

[0042] (R2 / R1) = (V1 / V2)-1,

[0043] wherein R1 is a first resistance value, R2 is a second resistance value, V1 is a nominal value of a first supply voltage, and V2 is a nominal value of a second supply voltage.

[0044] A second differential voltage signal output from the second switch-based H-bridge can be applied across a series connection of the first resistor to the fourth resistor. A second voltage divider resistance ladder can output a second auxiliary differential voltage signal between a first connection point connected between the first resistor and the second resistor and a second connection point connected between the third resistor and the fourth resistor. A third connection point connected between the second resistor and the third resistor can be connected to the first domain ground. The second comparator has an input, an inverting input, and an output, and can receive the second auxiliary differential voltage signal applied to its input and its inverting input, and can output a second single-ended digital signal from its output.

[0045] As mentioned above, in a second particular embodiment of the application, which is an alternative to the first particular embodiment as described above, the first internal communication link and the second internal communication link are based on digital current loop transmission, respectively with respect to transmission of transmit data and receive data.

[0046] In a further development of the second particular embodiment of the application, the first internal communication link can comprise a first transconductance transmitter and a first digital differential current loop receiver. The first transconductance transmitter can be referenced, in particular can be operated powered by, the first supply voltage domain, and can be adapted to receive a first input voltage via the first interface for carrying transmit data generated by a first digital device operating in the first supply voltage domain, to convert the first input voltage into a first differential current output for transmission of the transmit data and to output it. The first digital differential current loop receiver can be referenced, in particular can be operated powered by, the second supply voltage domain, and can be adapted to receive the first differential current output, to convert said first differential current output into a first single-ended digital signal for transmission of the transmit data and to output it via the second interface to an external communication bus operating in the second supply voltage domain.

[0047] In a corresponding further development of the second specific embodiment of the application, the second internal communication link can comprise a second transconductance transmitter and a second digital differential current loop receiver. The second transconductance transmitter can be referenced, in particular can be operated, powered by the second supply voltage domain, and can be adapted to receive, via the second interface, a second input voltage for carrying received data that can be supplied from an external communication bus operating in the second supply voltage domain, to convert the second input voltage into a second differential current output for transmitting the received data and to output it. The second digital differential current loop receiver can be referenced, in particular can be operated, powered by the first supply voltage domain, and can be adapted to receive the second differential current output, to convert it into a second single-ended digital signal for transmitting the received data and to output it via the first interface to a second digital device operating in the first supply voltage domain.

[0048] In a corresponding further development of the second specific embodiment of the application, the first transconductance transmitter has a first branch and a second branch, the first branch having a first current source and a first switch connected in series, the first current source being adapted to generate a first current, the second branch having a second current source and a second switch connected in series, the second current source being adapted to generate a second current. The first branch and the second branch are connected in parallel between a first connection point and a second connection point. The second current is opposite in direction to the first current. The first connection point represents a first output connected to a first line of the first internal communication link, the second connection point represents a second output connected to a second line of the first internal communication link.

[0049] The first digital differential current loop receiver has a first voltage divider resistor ladder and a first differential current loop voltage comparator, which are referenced, in particular are operated, powered by the second supply voltage domain. The first voltage divider resistor ladder has a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, the first resistor having substantially a second resistance value, the second resistor having substantially a first resistance value, the third resistor having substantially the first resistance value, the fourth resistor having substantially the second resistance value.

[0050] A first differential current I1_loop signal output from the first transconductance transmitter is applied over the series connection consisting of the first resistor to the fourth resistor. The first voltage divider resistor ladder outputs a first auxiliary differential voltage V1_aux signal between a first connection point connected between the first resistor and the second resistor and a second connection point connected between the third resistor and the fourth resistor. A third connection point connected between the second resistor and the third resistor can be connected to the second domain ground. The first differential current loop voltage comparator has an input, an inverting input and an output, and receives the first auxiliary differential voltage signal applied to its input and its inverting input, outputs a first single-ended digital signal from its output.

[0051] A first voltage V1 and a first auxiliary voltage V1_aux generated by a first differential current I1_loop flowing through a series connection consisting of the first resistor to the fourth resistor can be determined from the following equations:

[0052] V1 = 2 * (R1 + R2) * I1_loop, and

[0053] V1_aux = 2 * R1 * I1_loop,

[0054] where R1 is a first resistance value and R2 is a second resistance value.

[0055] The first transconductance transmitter has a first branch and a second branch, the first branch having a first current source and a first switch connected in series, the first current source being adapted to generate a first current, the second branch having a second current source and a second switch connected in series, the second current source being adapted to generate a second current. The first branch and the second branch are connected in parallel between a first connection point and a second connection point. The second current is opposite in direction to the first current. The first connection point represents a first output connected to a first line of the second internal communication link, the second connection point represents a second output connected to a second line of the second internal communication link.

[0056] The second differential current loop receiver has a second voltage divider resistor ladder and a second differential current loop voltage comparator operating with reference, in particular powered by, a second supply voltage domain. The second voltage divider resistor ladder has a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, the first resistor having substantially a second resistance value, the second resistor having substantially a first resistance value, the third resistor having substantially the first resistance value, the fourth resistor having substantially the second resistance value.

[0057] A second differential current I2_loop signal output from the second transconductance transmitter is applied over a series connection consisting of the first resistor to the fourth resistor. The second voltage divider resistor ladder outputs a second auxiliary differential voltage V2_aux signal between a first connection point connected between the first resistor and the second resistor and a second connection point connected between the third resistor and the fourth resistor. A third connection point connected between the second resistor and the third resistor can be connected to the first domain ground. The second differential current loop voltage comparator has an input, an inverting input and an output and outputs a first single-ended digital signal from its output with reference to a first auxiliary differential voltage signal applied to its input and its inverting input.

[0058] A second voltage V2 and a second auxiliary voltage V2_aux generated by a second differential current I2_loop flowing through a series connection consisting of the first resistor to the fourth resistor can be determined from the following equations:

[0059] V2 = 2 * (R1 + R2) * I2_loop, and

[0060] V2_aux = 2 * R1 * I2_loop,

[0061] wherein R1 is a first resistance value and R2 is a second resistance value.

[0062] According to a second exemplary embodiment of the present application, an electrical network system, in particular an electronic control unit (ECU), having a higher first power supply voltage domain and a lower second power supply voltage domain is provided, as well as a transceiver device according to the first exemplary embodiment of the present application as described above for interfacing between the first power supply voltage domain and the second power supply voltage domain.

[0063] According to a third exemplary embodiment of the present application, a vehicle having an electrical network system, in particular an electronic control unit (ECU), according to the second exemplary embodiment of the present application is provided.

[0064] According to a fourth exemplary embodiment of the present application, a method for interfacing between at least two different voltage domains, namely a first power supply voltage domain having a higher first power supply voltage and a second power supply voltage domain having a lower second power supply voltage, is provided, wherein the method uses a transceiver device having a first interface, a second interface, a first internal communication link and a second internal communication link. The method has the following steps:

[0065] supplying the first interface by the first power supply voltage and interfacing by the first interface with at least one external first digital device operating in the first power supply voltage domain;

[0066] supplying the second interface by the second power supply voltage and interfacing by the second interface with an external communication bus operating in the second power supply voltage domain;

[0067] transferring, by the first interface, transmission data generated by the external first digital device operating in the first power supply voltage domain via the first internal communication link to the second interface, in particular further to the external communication bus operating in the second power supply voltage domain; and

[0068] transferring, by the second interface, reception data supplied from the external communication bus operating in the second power supply voltage domain via the second internal communication link to the first interface, in particular further to the external second digital device operating in the first power supply voltage domain. Here, in particular, the reception data can originate from a device operating in the second power supply voltage domain and connected to the communication bus.

[0069] In a first specific embodiment of the present application, the method can further comprise operating the first internal communication link and the second internal communication link in a differential voltage transmission mode.

[0070] In a second particular embodiment of the application, which is an alternative to the first particular embodiment of the application, the method can further comprise operating the first internal communication link and the second internal communication link in a digital current loop transmission mode.

[0071] In an embodiment of the application, the transceiver arrangement comprising the first interface, the second interface, the first internal communication link and the second internal communication link can be implemented as a monolithic integrated circuit. In an advantageous embodiment thereof, the monolithic integrated circuit is implemented in silicon-on-insulator (SOI) technology.

[0072] In an embodiment of the application, the transceiver arrangement can further have at least two ground pins, including a first ground pin adapted for connection to a ground potential of the first power supply voltage domain and a second ground pin adapted for connection to a ground potential of the second power supply voltage domain.

[0073] In an embodiment of the application, the transceiver arrangement can further have a common mode and ground offset range in the range from greater than about ±3V but not more than about ±70V.

[0074] In an embodiment of the application, the first power supply voltage is substantially nominal 48V or higher. In an embodiment of the application, the second power supply voltage is substantially nominal 12V or substantially nominal 24V. BRIEF DESCRIPTION OF DRAWINGS

[0075] In the following, exemplary embodiments of the application are described in detail with reference to the following drawings.

[0076] Figure 1 A schematic block diagram of an electrical network system, e.g. an electronic control unit (ECU), is shown having a first power supply voltage domain, a second power supply voltage domain and a transceiver arrangement having an electrical isolation barrier in a conventional manner for interfacing between the first power supply voltage domain and the second power supply voltage domain.

[0077] Figure 2 A schematic block diagram of an electrical network system, e.g. an electronic control unit (ECU), is shown having a first power supply voltage domain, a second power supply voltage domain and a transceiver arrangement for interfacing between the first power supply voltage domain and the second power supply voltage domain according to the application.

[0078] Figure 3 A schematic block diagram of a transceiver arrangement for interfacing between a first power supply voltage domain and a second power supply voltage domain according to a first embodiment of the application is shown, and its core functionality is shown.

[0079] Figure 4A schematic block diagram of a transceiver device for interfacing between a first power supply voltage domain and a second power supply voltage domain according to a second embodiment of the application is shown, and its core functionality is shown.

[0080] Figure 5 A schematic block diagram of a transceiver device for interfacing between a first power supply voltage domain and a second power supply voltage domain according to a third embodiment of the application is shown, and its core functionality is shown.

[0081] Figure 6 A schematic block diagram of a transceiver device for interfacing between a first power supply voltage domain and a second power supply voltage domain according to a third embodiment of the application is shown, and its core functionality is shown. Figure 5 A schematic block diagram of a transceiver device for interfacing between a first power supply voltage domain and a second power supply voltage domain according to a third embodiment of the application is shown, and its core functionality is shown.

[0082] For the sake of brevity, features which will be described with respect to a particular drawing figure will similarly or identically appear in another drawing figure if such features are not described again. Similar or identical elements in different drawing figures have the same reference numerals. DETAILED DESCRIPTION

[0083] Figure 1 A schematic block diagram of an electrical network system 10, e.g. an electronic control unit (ECU), is shown, having a first power supply voltage domain 12, a second power supply voltage domain 14, and a transceiver device 96 having an electrical isolation barrier 98 in a conventional manner for interfacing between the first power supply voltage domain 12 and the second power supply voltage domain 14.

[0084] For example, the electrical network system 10 is a hybrid CAN network of 12V / 48V or 24V / 48V in a MHEV (not shown), and the transceiver device 96 is a CAN transceiver of 48V of the MHEV, in which the first power supply voltage is substantially nominal 48V and the second power supply voltage is substantially nominal 12V or 24V. The CAN transceiver 96 of 48V has an electrical isolation barrier 98 in a conventional manner, which can be implemented according to one of the following methods: (voltage) transformer, capacitor or optocoupler.

[0085] The first power supply voltage domain (or high voltage power supply domain) 12 is supplied by a first (or high) power supply voltage via a pair of pins 54, 56, i.e. a high voltage / first domain power supply 54 (e.g. a nominal 48V automotive board net power supply, commonly referred to as V BN48 ) and a high voltage / first domain ground (e.g. a ground connector of the 48V automotive board net, commonly referred to as GND 48 ).

[0086] The second supply voltage domain (or low voltage supply domain) 14 is powered by a second (or low) supply voltage via a pair of pins 72, 74, namely a low voltage / second domain supply 72 (e.g., a nominal 12V or 24V automotive board net supply, commonly referred to as V BN12 / 24 ) and a low voltage / second domain ground 74 (e.g., a 12V or 24V automotive board net ground connector / GND 12 / 24 ).

[0087] The electrical network system 10 of the MHEV includes in the first (high) supply voltage domain 12 an electric motor, such as an electric starter generator 50, a first voltage converter 52 (i.e., 48V / 12V), a second voltage converter (i.e., 12V / VDD1), a microcontroller unit 32 for controlling operation of the electric motor 50 via a drive line including a gate driver unit (GDU) 42, a power stage 46 for driving the electric motor 50, and the electric motor 50.

[0088] The 48V input of the first voltage converter 52 is connected to the high voltage / first domain supply 54 (V BN48 ). The 12V output of the first voltage converter 52 is connected to a first connection point 59, which is also connected to the 12V input of the second voltage converter 60. The VDD1 (e.g., 5V) output of the second voltage converter 60 is connected to a voltage supply input of the microcontroller 32. Therein, the microcontroller 32 outputs control signals via a first control signal line 40 to control inputs of the GDU 42. The GDU 42 outputs control signals via a second control signal line 44 to control inputs of the power stage 46. The power stage 46 outputs high power drive voltages and drive currents for driving the electric motor 50 of the MHEV via a drive signal line 48.

[0089] The second supply voltage domain (or low voltage supply domain) 14 is powered by a second (or low) supply voltage via a pair of pins 72, 74, namely a low voltage / second domain supply 72 (e.g., a nominal 12V or 24V automotive board net supply, commonly referred to as V BN12 / 24 ) and a low voltage / second domain ground 74 (e.g., a 12V or 24V automotive board net ground connector / GND 12 / 24 ).

[0090] The electrical network system 10 of the MHEV includes in the second (low) supply voltage domain 14 a CAN bus 24 including a CAN bus high voltage line 26 and a CAN bus low voltage line 28 for connecting to various ECUs and to devices of the second (low) supply voltage domain 14.

[0091] In Figure 1The transceiver device 96, which is implemented as a conventional 48V CAN transceiver, comprises the following pins in the first (high) voltage domain 12: VDD1, TXD, RXD and GND48. In addition, the conventional 48V CAN transceiver comprises the following pins in the second (low) voltage domain 14: VDD2, CANH, CANL and GND12. These pins are functionally similar and correspond to Figure 2 The pins of the 48V CAN transceiver shown in Figure 2 are further described.

[0092] The conventional 48V CAN transceiver 96 has an electrical isolation between the pins in the first (high) voltage domain 12 and the pins in the second (low) voltage domain 14. The electrical isolation barrier can be implemented as comprising one of an electrical isolation transformer, an electrical isolation capacitor or an electrical isolation optocoupler.

[0093] Figure 2 A schematic block diagram of an electrical network system 10, e.g. an electronic control unit (ECU), according to the present invention is shown, wherein the electrical network system 10 has a first supply voltage domain 12, a second supply voltage domain 14, and a transceiver device 100 according to the present invention for interfacing between the first supply voltage domain 12 and the second supply voltage domain 14.

[0094] Figure 2 The electrical network system 10 shown in Figure 1 corresponds to the electrical network system 10 shown in Figure 1 but with the first exception that the transceiver device 100 according to the present invention replaces the conventional transceiver device 96 implemented as a 48V CAN transceiver in Figure 2

[0095] Figure 1 instead of having an electrical isolation barrier 98, Figure 2 The transceiver device 100 according to the present invention shown in

[0096] ​​There can be more than one first and second internal communication link, for example, a further first and second internal communication link for transmitting a mode signal (or device mode indication signal), for example, from the second voltage supply domain to the first voltage supply domain, a further first and second internal communication link for transmitting a wake-up signal, for example, from the first voltage supply domain to the second voltage supply domain, and a further first and second internal communication link for transmitting a device status information signal.

[0097] The first (high) supply voltage domain 12 and the second (low) supply voltage domain 14 are independently interfaced externally of the transceiver device 100 by means of an electrically isolated flyback converter 70. The second (low) supply voltage terminal of the electrically isolated flyback converter 70 is powered (or connected to) by the low voltage / second domain power supply 72 via a fourth diode 80. The first (high) supply voltage terminal of the electrically isolated flyback converter 70 is connected to the first connection point 59 via a second diode 76, thus to the 12V input terminal of the second voltage converter 60. The first connection point 59 is buffered to the high voltage / first domain ground 56 via a third capacitor 78.

[0098] As shown in Figure 2 The transceiver device 100 is used for interfacing between at least two different voltage domains 12 and 14, including a first supply voltage domain 12 having a higher first supply voltage and a second supply voltage domain 14 having a lower second supply voltage. The transceiver device 100 has a first interface 110 powered by the first supply voltage and adapted for interfacing with at least one external first digital device 20 operating in the first supply voltage domain 12, and a second interface 120 powered by the second supply voltage and adapted for interfacing with an external communication bus 24 operating in the second supply voltage domain 14.

[0099] As shown in Figure 2 The transceiver device 100 additionally has a first internal communication link 130 adapted for transferring transmitted data, which can be generated by the external first digital device 20 operating in the first supply voltage domain 12, from the first interface 110 to the second interface 120, and a second internal communication link 170 adapted for transferring received data, which can be supplied from the external communication bus 24 operating in the second supply voltage domain 14, from the second interface 120 to the first interface 110. The received data can originate from a device operating in the second supply voltage domain 14 and connected to the communication bus 24.

[0100] The first internal communication link 130 and the second internal communication link 170 together enable a bidirectional transfer of transmission data and reception data between a digital device 30 (e.g. a microcontroller unit (MCU) 32) operating in the first (high) power supply voltage domain 12 and a communication bus 24 (e.g. a CAN bus) operating in the second (low) power supply voltage domain 14.

[0101] The internal communication links 130, 170 can tolerate ground shifts, common mode transients between the first power supply voltage domain 12 (which can be implemented as a 12V / 24V domain of an MHEV) and the second power supply voltage domain 14 (which can be implemented as a 48V domain of an MHEV) and minimize reverse current into the CAN bus lines in case of a ground failure scenario.

[0102] The transceiver device 100 according to the present application does not have and does not need an electrical isolation barrier (see for example Figure 1 98) for which one of the following methods is traditionally known: transformer, capacitor or optocoupler. All of these electrical isolation barriers are expensive solutions because according to Figure 1 the transceiver device 96 (e.g. CAN transceiver) shown in

[0103] In contrast, the transceiver device 100 according to the present application has a first internal communication link 130 and a second internal communication link 170 and can have more than one first and second internal communication link as described above. Thus, with all these components, the transceiver device 100 can be implemented as a monolithic integrated circuit.

[0104] Advantageously, the monolithic integrated circuit, in particular the monolithic integrated circuit comprising the first internal communication link 130 and the second internal communication link 170, is implemented in silicon-on-insulator (SOI) technology, in particular high-voltage SOI technology. This has been shown by internal feasibility studies by the inventors, while implementing this in e.g. CMOS technology is very difficult if not impossible.

[0105] It is noted that the transceiver device 100 has at least two ground pins 114, 124 comprising a first power supply voltage (or first domain ground, GND 48 ) 114 ground pin adapted for connection to the ground potential 56 of the first power supply voltage domain 12 and a second power supply voltage (or second domain ground, GND 12 / 24 ) 124 adapted for connection to the ground potential 74 of the second voltage power supply domain 14. Thus, the transceiver device 100 can have a common mode and ground shift range from about ±3V to about ±70V.

[0106] The first power supply voltage can be substantially 48V or higher, nominally. The second power supply voltage can be substantially 12V or substantially 24V, nominally. This enables the transceiver device 100 to be used in automotive applications, such as in light hybrid electric vehicles (MEHVs).

[0107] like Figure 2 As further shown, the first interface 110 has: a data transmission input terminal 116, adapted to receive transmitted data, for example, from a first digital device 20 operating in the first power supply voltage domain 12; and a data reception output terminal 118, adapted to transmit received data, for example, to a second digital device 22 operating in the first power supply voltage domain 12. Here, the first digital device 20 and the second digital device 22 operating in the first power supply voltage domain 12 may be the same digital device 30. Alternatively, the first digital device 20 and the second digital device 22 operating in the first power supply voltage domain 12 may jointly form a microcontroller unit 32.

[0108] like Figure 2 As further shown, the second interface 120 has a CAN high pin 126 and a CAN low pin 128, which together are used to transmit data to and / or receive data from the CAN bus, which serves as an external communication bus 24 operating in the second power supply voltage domain 14. The communication bus 24 can be selected from the group consisting of CAN bus, Flexray bus, LIN bus, and Ethernet.

[0109] In the transceiver device 100 according to the present invention, with regard to the transmission of transmitted data and the transmission of received data, respectively, the first internal communication link 130 and the second internal communication link 170 may be based on differential voltage transmission, as will be referred to below. Figure 4 Further explanation.

[0110] Alternatively, in the transceiver device 100 according to the invention, the first internal communication link 130 and the second internal communication link 170 may be based on digital current loop transmission for the transmission of transmitted data and the transmission of received data, respectively, as will be referred to below. Figure 5 and 6 Further explanation.

[0111] The transceiver device 100 can be implemented as a 48V CAN transceiver. Thus, as... Figure 2 As shown, the transceiver device or 48V CAN transceiver 100 includes the following pins in the first (high) voltage domain 12: for the first power supply voltage (corresponding to...) Figure 1 V in IO The power input pin 112, the first power supply voltage (or the first domain ground, corresponding to) Figure 1 GND in48 ) ground pin 114, a transmit data input 116 (corresponding to TXD in Figure 1 ), a receive data output 118 (corresponding to RXD in Figure 1 ), and a mode port (not referenced) connected to the microcontroller via a mode control signal line 38.

[0112] Furthermore, the transceiver device 100 itself comprises in the second (low) voltage domain 14 the following pins: a power input pin 122 for the second supply voltage (corresponding to BAT Figure 1 in 12 ) which is connected to the low voltage / second domain power supply 72 (corresponding to V Figure 1 in BN12 / 24 ); a ground pin 124 for the second supply voltage (or second domain ground, corresponding to GND Figure 1 in 12 ) which is connected to the low voltage / second domain ground 74 (corresponding to GND Figure 1 in 12 / 24 ); at least one communication bus pin which is implemented here (where the communication bus 24 is a CAN bus) as a CAN high pin 126 and a CAN low pin 128; and a wake-up port (not referenced) connected to a wake-up voltage.

[0113] The low voltage / second domain power supply 72 (V BN12 / 24 ) is connected via a fifth diode 82 to the power input pin 122 for the second supply voltage (BAT 12 ). The output for the second supply voltage (BAT 12 ) to the power input pin 122 is buffered via a third capacitor 84 and a fourth capacitor 86 to the second domain ground 124.

[0114] The 48V CAN transceiver further comprises in the second (low) voltage domain 14 the pins VBUF (not referenced) and INHN (not referenced). VBUF is connected to an external buffer capacitor (or fifth capacitor) 94 which is used to stabilize the internal voltage supply of the CAN transceiver IP within the 48V CAN transceiver device. The INHN output is typically an open drain output which is used to switch on and off an external power supply circuit or device which supplies power to the microcontroller unit 32 depending on the 48V CAN transceiver mode. In the embodiment shown in Figure 2 , the INHN switches on and off the electrically isolated inverter 70.

[0115] In Figure 2In the illustrated embodiment, the wake-up voltage is connected to the wake-up port via a wake-up voltage line 92 including a first resistor 88, and connected to the second domain ground 124 via a second resistor 90. When the 48V CAN transceiver is in low-power mode, the WAKE pin can be used to detect wake-up events, such as V. WAKE The rising edge of the signal. After detecting a wake-up event, the 48V CAN transceiver will power on the microcontroller unit 32 via the INHN output. Based on the wake-up source, i.e., V... WAKE The source, the transceiver device 100 connected to the WAKE pin, can have a wide range of internal and external circuitry.

[0116] Figure 3 A schematic block diagram of a transceiver device 100 for interfacing between a first power supply voltage domain 12 and a second power supply voltage domain 14 according to a first embodiment of the present invention is shown, and its core functions are illustrated.

[0117] The transceiver device 100 has a first internal communication link 130, which includes a first link transmitter 132 and a first link receiver 134, and is capable of transmitting data in the direction from the first interface 110 to the second interface 120. The transceiver device 100 also has a second internal communication link 170, which includes a second link transmitter 172 and a second link receiver 174, and is capable of transmitting received data in the opposite direction from the second interface 120 to the first interface 110.

[0118] Figure 4 A schematic block diagram of a transceiver device 100 for interfacing between a first power supply voltage domain 12 and a second power supply voltage domain 14 according to a second embodiment of the present invention is shown, and its core functions are illustrated, wherein a first internal communication link 130 and a second internal communication link 170 are used to transmit and receive data respectively using the principle of differential voltage transmission.

[0119] exist Figure 4 In the illustrated embodiment, the transceiver device 100, in terms of transmitting and receiving data respectively, indicates that the first internal communication link 130 and the second internal communication link 170 are based on differential voltage transmission.

[0120] exist Figure 4In the illustrated embodiment, the first internal communication link 130 is implemented as a first differential voltage transmission link 140. In embodiments using differential voltage transmission, the first link transmitter 132 is implemented as a first differential voltage transmitter 141, which operates, in particular, powered by a first power supply voltage domain 12. The first differential voltage transmitter 141 is adapted to receive transmission data generated by a first digital device 20 operating in the first power supply voltage domain 12 via a first interface 110, and is also adapted to generate and output a first differential voltage signal for transmitting the transmission data. The first link receiver 134 is implemented as a first differential voltage receiver 144, which operates, in particular, powered by a second power supply voltage domain 14. The first differential voltage receiver 144 is adapted to receive the differential voltage signal transmitted by the first differential voltage transmitter 141, and is also adapted to transmit a first single-ended digital signal for transmitting the transmission data to an external communication bus 24 via a second interface 120, the external communication bus 24 operating in the second power supply voltage domain 14 and implemented as a CAN bus with a CAN high-voltage line 26 and a CAN low-voltage line 28.

[0121] In the first differential voltage transmission link 140, the first differential voltage transmitter 141 has a first switch-based H-bridge 142, which operates with reference to, in particular, being powered by, a first power supply voltage domain 12, and the first differential voltage receiver 144 has a first voltage divider resistor ladder 145 and a first comparator 146, which operates with reference to, in particular, being powered by, a second power supply voltage domain 14.

[0122] like Figure 4 As shown, the first switch-based H-bridge 142 includes a first switch 142-1, a second switch 142-2, a third switch 142-3, and a fourth switch 142-4. The second switch 142-2 and the first switch 142-1 are connected in series, and the series-connected second switch 142-2 and the first switch 142-1 are connected to a first power supply voltage V. IO grounded with the first domain GND 48 Between, the first power supply voltage V IO Powered via power input pin 112, this first domain is grounded (GND). 48 Power is supplied via the ground pin 114 of the first power supply voltage. Similarly, the fourth switch 142-4 and the third switch 142-3 are connected in series, and the series-connected fourth switch 142-4 and third switch 142-3 are connected to the first power supply voltage V. IO grounded with the first domain GND 48 Between, the first power supply voltage V IO Powered via power input pin 112, this first domain is grounded (GND). 48Power is supplied via the ground pin 114 of the first power supply voltage. Thus, the second switch 142-2 and the first switch 142-1, connected in series, are powered by the first power supply voltage V. IO grounded with the first domain GND 48 The fourth switch 142-4 and the third switch 142-3, which are connected in series, are connected in parallel. The first line 140-1 of the first differential communication link 140 or the first output terminal of the first switch-based H-bridge 142 is connected to the connection point between the third switch 142-3 and the fourth switch 142-4. The second line 140-2 of the first communication link 140 or the second output terminal of the first switch-based H-bridge 142 is connected to the connection point between the first switch 142-1 and the second switch 142-2.

[0123] like Figure 4 As further illustrated, the first switch 142-1 and the third switch 142-3 are coupled in the sense that they switch simultaneously, i.e., open and closed. Similarly, the second switch 142-2 and the fourth switch 142-4 are coupled in the sense that they switch simultaneously, i.e., open and closed. When switching to a high state (or a low state), the input signal to the first switch-based H-bridge 142 will simultaneously turn on the coupled first switch 142-1 and the third switch 142-3, while turning off the coupled second switch 142-2 and the fourth switch 142-4. Conversely, when switching to a low state (or a high state), the input signal to the first switch-based H-bridge 142 will simultaneously turn off the coupled first switch 142-1 and the third switch 142-3, while turning on the coupled second switch 142-2 and the fourth switch 142-4.

[0124] During operation, when the input signal carrying the transmitted data transitions to a high state (or a low state), the first output line 140-1 of the first differential communication link 140 presents a first domain ground (GND). 48 The potential of 114 is given, while the second output line 140-2 of the first differential communication link 140 presents the first power supply voltage (V). IO The potential of 112. Conversely, when the input signal transitions to a low state (or a high state), the first output line 140-1 of the first differential communication link 140 presents the first power supply voltage (V). IO The potential of 112 is given, while the second output line 140-2 of the first differential communication link 140 is grounded in the first domain (GND). 48 The potential of 114. Therefore, the first line 140-1 and the second line 140-2 of the first differential communication link 140 always have opposite potentials relative to each other, and thus, the first differential communication link 140 transmits the differential voltage carrying the transmitted data.

[0125] like Figure 4As further shown, the first voltage divider resistor ladder 145 has a first resistor 145-1, a second resistor 145-2, a third resistor 145-3, and a fourth resistor 145-4 connected in series. The first resistor 145-1 has a substantially second resistance value R2, the second resistor 145-2 has a substantially first resistance value R1, the third resistor 145-3 has a substantially first resistance value R1, and the fourth resistor 145-4 has a substantially second resistance value R2. The ratio between the first resistance value and the second resistance value can be determined from the following equation:

[0126] (R2 / R1)=(V1 / V2)-1,

[0127] Wherein, R1 is the first resistance value, R2 is the second resistance value, V1 is the nominal value of the first power supply voltage, and V2 is the nominal value of the second power supply voltage.

[0128] A first differential voltage signal, output from the first switch-based H-bridge 142 via the first line 140-1 and the second line 140-2 of the first differential communication link 140, is applied to a series connection consisting of a first resistor 145-1 to a fourth resistor 145-4. Then, a first voltage divider resistor ladder 145 outputs a first auxiliary differential voltage signal between a first connection point 145-5 connected between the first resistor 145-1 and the second resistor 145-2 and a second connection point 145-6 connected between the third resistor 145-3 and the fourth resistor 145-4. A third connection point 145-7 connected between the second resistor 145-2 and the third resistor 145-3 is connected to a second ground (GND). 12 / 24 )124.

[0129] The first comparator 146 has an input terminal 146-1, an inverting input terminal 146-2, and an output terminal 146-3, and receives a first auxiliary differential voltage signal applied to its input terminal 146-1 and its inverting input terminal 146-2. The first comparator 146 outputs a first single-ended digital signal carrying transmitted data from its output terminal 146-3.

[0130] Accordingly, in Figure 4In the illustrated embodiment, the second internal communication link 170 is implemented as a second differential voltage transmission link 180. In embodiments using differential voltage transmission, the second link transmitter 172 is implemented as a second differential voltage transmitter 181, which operates, in particular, powered by the second power supply voltage domain 14. The second differential voltage transmitter 181 is adapted to receive received data supplied from an external communication bus 24 operating in the second power supply voltage domain 14 via a second interface 120, and is also adapted to generate and output a second differential voltage signal for transmitting the received data. The second link receiver 174 is implemented as a second differential voltage receiver 184, which operates, in particular, powered by the first power supply voltage domain 12. The second differential voltage receiver 184 is adapted to receive the differential voltage signal transmitted by the second differential voltage transmitter 181, and is also adapted to transmit a second single-ended digital signal for transmitting the received data to a second digital device 22 operating in the first power supply voltage domain 12 via a first interface 110.

[0131] In the second differential voltage transmission link 180, the second differential voltage transmitter 181 has a second switch-based H-bridge 182, which operates with reference to, in particular, being powered by the second power supply voltage domain 14, and the second differential voltage receiver 184 has a first voltage divider resistor ladder 185 and a first comparator 186, which operates with reference to, in particular, being powered by the first power supply voltage domain 12.

[0132] like Figure 4 As shown, the second switch-based H-bridge 182 includes a first switch 182-1, a second switch 182-2, a third switch 182-3, and a fourth switch 182-4. The first switch 182-1 and the second switch 182-2 are connected in series, and the series-connected first switch 182-1 and second switch 182-2 are connected to a second power supply voltage V. BUF With the second domain ground GND 12 / 24 Between, the second power supply voltage V BUF Powered via power input pin 122, this second domain is grounded (GND). 12 / 24 Power is supplied via the ground pin 124 of the second power supply voltage. Similarly, the third switch 182-3 and the fourth switch 182-4 are connected in series, and the series-connected third switch 182-3 and fourth switch 182-4 are connected to the second power supply voltage V. BUF With the second domain ground GND 12 / 24 Between, the second power supply voltage V BUF Powered via power input pin 122, this second domain is grounded (GND). 12 / 24 Power is supplied via the ground pin 124 of the second power supply voltage. Thus, the first switch 182-1 and the second switch 182-2, connected in series, are powered by the second first power supply voltage V. BUF With the second domain ground GND 12 / 24The third switch 182-3 and the fourth switch 182-4, which are connected in series, are connected in parallel. The first line 180-1 of the second differential communication link 180 or the first output terminal of the second switch-based H-bridge 182 is connected to the connection point between the third switch 182-3 and the fourth switch 182-4. The second line 180-2 of the second differential communication link 180 or the second output terminal of the second switch-based H-bridge 182 is connected to the connection point between the first switch 182-1 and the second switch 182-2.

[0133] like Figure 4 As further illustrated, the first switch 182-1 and the third switch 182-3 are coupled in the sense that they switch simultaneously, i.e., open and closed. Similarly, the second switch 182-2 and the fourth switch 182-4 are coupled in the sense that they switch simultaneously, i.e., open and closed. When switching to a high state (or a low state), the input signal to the first switch-based H-bridge 182 will simultaneously turn on the coupled first switch 182-1 and the third switch 182-3, while turning off the coupled second switch 182-2 and the fourth switch 182-4. Conversely, when switching to a low state (or a high state), the input signal to the first switch-based H-bridge 182 will simultaneously turn off the coupled first switch 182-1 and the third switch 182-3, while turning on the coupled second switch 182-2 and the fourth switch 182-4.

[0134] During operation, when the input signal carrying the received data transitions to a high state (or a low state), the first output line 180-1 of the second differential communication link 180 presents a second domain ground (GND). 12 / 24 The voltage is 124V, while the second output line 180-2 of the second differential communication link 180 presents the first power supply voltage (V). BUF The potential of 122. Conversely, when the input signal transitions to a low state (or a high state), the first output line 180-1 of the second differential communication link 180 presents the second supply voltage (V). BUF The potential of 122, while the second output line 180-2 of the second differential communication link 180 is grounded in the second domain (GND). 12 / 24 The potential of 124. Therefore, the first line 180-1 of the second differential communication link 180 and the second line 180-2 of the second differential communication link 180 always have opposite potentials relative to each other, and thus, the second differential communication link 180 transmits the differential voltage carrying the received data.

[0135] like Figure 4As further shown, the second voltage divider resistor ladder 185 has a first resistor 185-1, a second resistor 185-2, a third resistor 185-3, and a fourth resistor 185-4 connected in series. The first resistor 185-1 has a substantially second resistance value R2, the second resistor 185-2 has a substantially first resistance value R1, the third resistor 185-3 has a substantially first resistance value, and the fourth resistor 185-4 has a substantially second resistance value. The ratio between the first resistance value and the second resistance value can be determined from the following equation:

[0136] (R2 / R1)=(V1 / V2)-1,

[0137] Wherein, R1 is the first resistance value, R2 is the second resistance value, V1 is the nominal value of the first power supply voltage, and V2 is the nominal value of the second power supply voltage.

[0138] The second differential voltage signal output from the second switch-based H-bridge 182 is applied to the series connection consisting of the first resistor 185-1 to the fourth resistor 185-4. Then, the second voltage divider resistor ladder 185 outputs a second auxiliary differential voltage signal between the first connection point 185-5 connected between the first resistor 185-1 and the second resistor 185-2, and the second connection point 185-6 connected between the third resistor 185-3 and the fourth resistor 185-4. The third connection point 185-7 connected between the second resistor 185-2 and the third resistor 185-3 is connected to the first domain ground (GND). 48 114.

[0139] The second comparator 186 has an input terminal 186-1, an inverting input terminal 186-2, and an output terminal 186-3, and receives a second auxiliary differential voltage signal applied to its input terminal 186-1 and its inverting input terminal 186-2. The second comparator 186 outputs a second single-ended digital signal carrying the received data from its output terminal 186-3.

[0140] Figure 5 A schematic block diagram of a transceiver device 100 for interfacing between a first power supply voltage domain 12 and a second power supply voltage domain 14 according to a third embodiment of the present invention is shown, and its core functions are illustrated, wherein a first internal communication link 130 and a second internal communication link 170 transmit and receive data respectively using the principle of digital current loop transmission.

[0141] exist Figure 5In the illustrated embodiment, the first internal communication link 130 is implemented as a first digital current loop transmission link 150, which has a first link transmitter 132 implemented as a first transconductance transmitter 151. The first transconductance transmitter 151 is referenced, and particularly operates powered by a first power supply voltage domain 12. The first transconductance transmitter 151 is adapted to receive a first input voltage via a first interface 110 for carrying transmission data generated by a first digital device 20 operating in the first power supply voltage domain 12, and is also adapted to convert the first input voltage into a first differential current for transmitting the transmission data and output it. The first differential current is, in particular, a bidirectional current, carried by a first line 150-1 and a second line 150-2 of the first digital current loop transmission link 150, thereby forming a bidirectional current loop capable of representing the dominant and recessive levels of the transmitted data stream. The first transconductance transmitter 151 may be based on an active H-bridge driver circuit.

[0142] In the first digital current loop transmission link 150, the first link receiver 134 is implemented as a first digital differential circuit loop receiver 154, which operates, in particular, powered by the second power supply voltage domain 14. The first digital differential current loop receiver 154 is adapted to receive a first differential current output, and also to convert the first differential current output into a first single-ended digital signal for transmitting data and output it via the second interface 120 to an external communication bus 24 operating in the second power supply voltage domain 14.

[0143] The first digital differential current loop receiver 154 has a first voltage divider resistor ladder 155 and a first differential current loop voltage comparator 156, which is referenced and, in particular, operated by being powered by a second power supply voltage domain 14.

[0144] The first voltage divider resistor ladder 155 has a first resistor 155-1, a second resistor 155-2, a third resistor 155-3, and a fourth resistor 155-4 connected in series. The first resistor 155-1 has a second resistance value R2, the second resistor 155-2 has a first resistance value R1, the third resistor 155-3 has a first resistance value R1, and the fourth resistor 155-4 has a second resistance value R2.

[0145] The first differential current signal output from the first transconductance transmitter 151 is applied to the series connection consisting of the first resistor 155-1 to the fourth resistor 155-4. Then, the first voltage divider resistor ladder 155 outputs a first auxiliary differential voltage signal between the first connection point 155-5 connected between the first resistor 155-1 and the second resistor 155-2 and the second connection point 155-6 connected between the third resistor 155-3 and the fourth resistor 155-4. The third connection point 155-7 between the second resistor 155-2 and the third resistor 155-3 can be connected to the second ground (GND). 12 / 24 )124.

[0146] The first differential current loop voltage comparator 156 has an input terminal 156-1, an inverting input terminal 156-2, and an output terminal 156-3, and receives a first auxiliary differential voltage signal applied to its input terminal 156-1 and its inverting input terminal 156-2. The first differential current loop voltage comparator 156 outputs a first single-ended digital signal carrying transmitted data from its output terminal 156-3. The transmitted data is then also transmitted via the second interface 120 to an external communication bus 24 operating in the second power supply voltage domain 14.

[0147] The first voltage V1 and the first auxiliary voltage V1_aux generated by the first differential current 11_loop flowing through the series connection consisting of the first resistor 155-1 to the fourth resistor 155-4 can be determined from the following equation:

[0148] V1 = 2*(R1+R2)*I1_loop, and

[0149] V1_aux = 2 * R1 * I1_loop,

[0150] Where R1 is the first resistance value and R2 is the second resistance value.

[0151] Accordingly, in Figure 5In the illustrated embodiment, the second internal communication link 170 is implemented as a second digital current loop transmission link 190, which has a second link transmitter 172 implemented as a second transconductance transmitter 191. The second transconductance transmitter 191 is operated, particularly powered by the second power supply voltage domain 12. The second transconductance transmitter 191 is also adapted to receive, via the second interface 120, a second input voltage for carrying received data supplied from an external communication bus 24 operating in the second power supply voltage domain 14, and to convert the second input voltage into a second differential current output, particularly a bidirectional current output, for transmitting the received data, and to output it. Moreover, the second differential current, particularly the bidirectional current, is carried by the first line 190-1 and the second line 190-2 of the second digital current loop transmission link 190, thereby forming a bidirectional current loop capable of representing the dominant and recessive levels of the received data stream. The second transconductance transmitter 191 may be based on an active H-bridge driver circuit.

[0152] Furthermore, accordingly, in Figure 5 In the embodiment shown, the second digital current loop transmission link 190 has a second link receiver 174, which is implemented as a second digital differential current loop receiver 194.

[0153] The second digital differential current loop receiver 194 is adapted to receive a second differential current output and also to convert it into a second single-ended digital signal for transmitting received data and output it via the first interface 110 to a second digital device 22 operating in the first power supply voltage domain 12.

[0154] The second digital differential current loop receiver 194 has a second voltage divider resistor ladder 195 and a second differential current loop voltage comparator 196, which is referenced and, in particular, operated by being powered by the first power supply voltage domain 12.

[0155] The second voltage divider resistor ladder 195 has a first resistor 195-1, a second resistor 195-2, a third resistor 195-3, and a fourth resistor 195-4 connected in series. The first resistor 195-1 has a second resistance value R2, the second resistor 195-2 has a first resistance value R1, the third resistor 195-3 has a first resistance value, and the fourth resistor 195-4 has a second resistance value.

[0156] The second differential current signal output from the second transconductance transmitter 191 is applied to the series connection consisting of the first resistor 195-1 to the fourth resistor 195-4. Then, the second voltage divider resistor ladder 195 outputs a second auxiliary differential voltage signal between the first connection point 195-5 connected between the first resistor 195-1 and the second resistor 195-2 and the second connection point 195-6 connected between the third resistor 195-3 and the fourth resistor 195-4. The third connection point 195-7 between the second resistor 195-2 and the third resistor 195-3 can be connected to the first domain ground (GND). 48 114.

[0157] The second voltage V2 and the second auxiliary voltage V2_aux generated by the second differential current I2_loop flowing through the series connection consisting of the first resistor to the fourth resistor (195-1, ..., 195-4) can be determined from the following equation:

[0158] V2 = 2*(R1+R2)*I2_loop, and

[0159] V2_aux = 2 * R1 * I2_loop,

[0160] Where R1 is the first resistance value and R2 is the second resistance value.

[0161] The second differential current loop voltage comparator 196 has an input terminal 196-1, an inverting input terminal 196-2, and an output terminal 196-3, and receives a first auxiliary differential voltage signal applied to its input terminal 196-1 and its inverting input terminal 196-2. The second differential current loop voltage comparator 196 outputs a second single-ended digital signal carrying the received data from its output terminal 196-3. The received data is then also transmitted via the first interface 110 to a second digital device 22 operating in the first power supply voltage domain 12.

[0162] Figure 6 It shows Figure 5 The diagram shown is a schematic block diagram of a transceiver device 100 according to a third embodiment of the present invention, and illustrates its core functions, wherein details of a first transconductance transmitter 151 and a second transconductance transmitter 191 are shown.

[0163] The first transconductance transmitter 151 has a first branch and a second branch. The first branch has a first current source 151-1 and a first switch 151-2 connected in series. The first current source 151-1 is used to generate a first current. The second branch has a second current source 151-3 and a second switch 151-4 connected in series. The second current source 151-3 is used to generate a second current. The first branch and the second branch are connected in parallel between a first connection point 152-1 and a second connection point 152-2. The second current is in the opposite direction to the first current. The first connection point 152-1 represents a first output connected to a first output line 150-1 of the first digital current loop communication link 150. The second connection point 152-2 represents a second output connected to a second output line 150-2 of the first digital current loop communication link 150, which transmits data from the first interface 110 to the second interface 120.

[0164] The second transconductance transmitter 191 has a first branch and a second branch. The first branch has a first current source 191-1 and a first switch 191-2 connected in series. The first current source 191-1 is used to generate a first current. The second branch has a second current source 191-3 and a second switch 191-4 connected in series. The second current source 191-3 is used to generate a second current. The first branch and the second branch are connected in parallel between a first connection point 192-1 and a second connection point 192-2. The second current is in the opposite direction to the first current. The first connection point 192-1 represents a first output connected to a first output line 190-1 of the second digital current loop communication link 190. The second connection point 192-2 represents a second output connected to a second output line 190-2 of the second digital current loop communication link 190, which transmits received data from the second interface 120 to the first interface 110.

[0165] Exemplary embodiments have been presented in this specification with respect to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including details different from those selected, may be implemented. The appended claims are intended to cover all possible exemplary embodiments.

[0166] Additionally, it should be noted that "having" or "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. Furthermore, it should be noted that a feature or step described above with reference to one of the embodiments described above may also be used in combination with other features or steps of other embodiments described above. Reference numerals in the claims should not be construed as limiting.

[0167] List of reference signs

[0168] 10. Electrical network systems, such as electronic control units

[0169] 12 First power supply voltage domain

[0170] 14 Second power supply voltage domain

[0171] 20 A first digital device operating in a first power supply voltage domain

[0172] 22 A second digital device operating in the first power supply voltage domain

[0173] 24. Communication buses, such as the CAN bus.

[0174] 26 CAN bus high-voltage line

[0175] 28 CAN bus low voltage line

[0176] 30 The same digital device operating in the first power supply voltage domain

[0177] 32. Microcontroller Unit (MCU)

[0178] 34 Data transmission cable

[0179] 36. Receive data cable

[0180] 38 mode control signal lines

[0181] 40 First control signal line

[0182] 42 Gate Driver Units (GDUs)

[0183] 44 Second control signal line

[0184] 46 power stages

[0185] 48 drive signal lines

[0186] 50 electric drive motor

[0187] 52 First voltage converter, such as 48V / 12V

[0188] 54 High Voltage / First Domain Power Supply

[0189] For example, a 48V automotive power supply / V BN48 (Kl.40)

[0190] 56 High Voltage / First Domain Grounding

[0191] For example, the grounding / GND of a 48V automotive power grid. 48 (Kl.41)

[0192] 58 First Diode

[0193] 60 Second voltage converter, such as 12V / VDD1

[0194] 62 First Capacitor

[0195] 64 Second capacitor

[0196] 70 Electrically Isolated Inverter

[0197] 72 Low-voltage / Second Domain Power Supply

[0198] For example, automotive mains power supplies with a nominal voltage of 12V or 24V / V BN12 / 24 (Kl.30)

[0199] 74 Low voltage / second domain grounding

[0200] For example, the grounding / GND of a 12V or 24V automotive power supply. 12 / 24 (Kl.31)

[0201] 76 Second Diode

[0202] 78 Third Capacitor

[0203] 80 Fourth Diode

[0204] 82 Fifth Diode

[0205] 84 Third Capacitor

[0206] 86 Fourth capacitor

[0207] 87. Third voltage converter, such as 12V / VDD2 or 24V / VDD2

[0208] 88 First Resistor

[0209] 90 Second Resistor

[0210] 92 Wake-up Voltage Line

[0211] 94 Fifth capacitor / buffer capacitor

[0212] 96. Transceiver device (prior art)

[0213] 98 Electrical isolation barrier

[0214] 100 transceiver device

[0215] 110 First (Digital) Interface

[0216] 112 First power supply voltage / V IO power input pin

[0217] 114 First power supply voltage / First domain ground / GND 48 ground pin

[0218] 116 Data Input Pin

[0219] 118 Receive Data Output (Pin)

[0220] 120 Second interface / e.g., CAN bus interface

[0221] 122 Second power supply voltage / VBUF power input pin

[0222] 124 Second power supply voltage / Second domain ground / GND 12 / 24 ground pin

[0223] 126 CAN high pins

[0224] 128 CAN low pins

[0225] 130 First internal communication link

[0226] 130-1 First line of the first link

[0227] 130-2 Second line of the first link

[0228] 132 First Link Transmitter

[0229] 134 First Link Receiver

[0230] 140 First differential voltage communication link

[0231] 140-1 First line of the first link

[0232] 140-2 Second line of the first link

[0233] 141 First Differential Voltage Transmitter

[0234] 142 The first switch-based H-bridge

[0235] 142-1 First Switch

[0236] 142-2 Second Switch

[0237] 142-3 Third Switch

[0238] 142-4 Fourth Switch

[0239] 144 First Differential Voltage Receiver

[0240] 145 First voltage divider resistance ladder

[0241] 145-1 First Resistor

[0242] 145-2 Second Resistor

[0243] 145-3 Third Resistor

[0244] 145-4 Fourth Resistor

[0245] 145-5 First Connection Point

[0246] 145-6 Second Connection Point

[0247] 145-7 Center Connection Point

[0248] 146 First Comparator

[0249] 146-1 Input Terminal

[0250] 146-2 Inverting Input Terminal

[0251] 146-3 Output terminal

[0252] 150 First Digital Current Loop Communication Link

[0253] 150-1 First line of the first link

[0254] 150-2 Second line of the first link

[0255] 151 First transconductance transmitter

[0256] 151-1 First Current Source

[0257] 151-2 First Switch

[0258] 151-3 Second Current Source

[0259] 151-4 Second Switch

[0260] 152-1 First Connection Point

[0261] 152-2 Second Connection Point

[0262] 154 First Digital Differential Current Loop Receiver

[0263] 155 First (Differential Current Loop Voltage) Voltage Divider Resistance Ladder

[0264] 155-1 First Resistor

[0265] 155-2 Second Resistor

[0266] 155-3 Third Resistor

[0267] 155-4 Fourth Resistor

[0268] 155-5 First Connection Point

[0269] 155-6 Second Connection Point

[0270] 155-7 Center Connection Point

[0271] 156 First (Differential Current Loop Voltage) Comparator

[0272] 156-1 Input Terminal

[0273] 156-2 Inverting Input Terminal

[0274] 156-3 Output Terminal

[0275] 170 Second internal communication link

[0276] 170-1 First line of the second link

[0277] 170-2 Second line of the second link

[0278] 172 Second Link Transmitter

[0279] 174 Second Link Receiver

[0280] 180 Second differential voltage communication link

[0281] 180-1 First line of the second link

[0282] 180-2 Second line of the second link

[0283] 181 Second Differential Voltage Transmitter

[0284] 182 Second Switch-Based H-Bridge

[0285] 182-1 First Switch

[0286] 182-2 Second Switch

[0287] 182-3 Third Switch

[0288] 182-4 Fourth Switch

[0289] 184 Second Differential Voltage Receiver

[0290] 185 Second voltage divider resistor ladder

[0291] 185-1 First Resistor

[0292] 185-2 Second Resistor

[0293] 185-3 Third Resistor

[0294] 185-4 Fourth Resistor

[0295] 185-5 First Connection Point

[0296] 185-6 Second Connection Point

[0297] 185-7 Central Connection Point

[0298] 186 Second Comparator

[0299] 186-1 Input Terminal

[0300] 186-2 Inverting Input Terminal

[0301] 186-3 Output Terminal

[0302] 190 Second digital current loop communication link

[0303] 190-1 First line of the second link

[0304] 190-2 Second line of the second link

[0305] 191 Second transconducting transmitter

[0306] 191-1 First Current Source

[0307] 191-2 First Switch

[0308] 191-3 Second Current Source

[0309] 191-4 Second Switch

[0310] 192-1 First Connection Point

[0311] 192-2 Second Connection Point

[0312] 194 Second Digital Differential Current Loop Receiver

[0313] 195 Second (Differential Current Loop Voltage) Voltage Divider Resistance Ladder

[0314] 195-1 First Resistor

[0315] 195-2 Second Resistor

[0316] 195-3 Third Resistor

[0317] 195-4 Fourth Resistor

[0318] 195-5 First Connection Point

[0319] 195-6 Second Connection Point

[0320] 195-7 Central Connection Point

[0321] 196 Second (Differential Current Loop Voltage) Comparator

[0322] 196-1 Input Terminal

[0323] 196-2 Inverting Input Terminal

[0324] 196-3 Output terminal.

Claims

1. A transceiver device (100) for interfacing between at least two different voltage domains (12, 14), namely a first supply voltage domain (12) having a higher first supply voltage and a second supply voltage domain (14) having a lower second supply voltage, characterized in that, The transceiver device (100) has: a first interface (110) powered by the first supply voltage and adapted to interface with at least one external first digital device (20) operating in the first supply voltage domain (12); a second interface (120) powered by the second supply voltage and adapted to interface with an external communication bus (24) operating in the second supply voltage domain (14); a first internal communication link (130) adapted to transfer transmission data generated by the external first digital device (20) operating in the first supply voltage domain (12) from the first interface (110) to the second interface (120), and a second internal communication link (170) adapted to transfer reception data supplied from the external communication bus (24) operating in the second supply voltage domain (14) from the second interface (120) to the first interface (110); the first and second internal communication links (130, 170) are based on differential voltage transmission (140, 180) with respect to transmission of transmission data and reception data, respectively; the first internal communication link (130) comprises: a first differential voltage transmitter (141) operating referenced, powered by the first supply voltage domain (12), adapted to receive the transmission data generated by the first digital device (20) operating in the first supply voltage domain (12) via the first interface (110), and adapted to generate and output a first differential voltage signal for transmission of the transmission data, and a first differential voltage receiver (144) operating referenced, powered by the second supply voltage domain (14), adapted to receive the differential voltage signal transmitted by the first differential voltage transmitter (141), and adapted to transmit a first single-ended digital signal for transmission of the transmission data via the second interface (120) to the external communication bus (24) second digital device (26) operating in the second supply voltage domain (14), in particular wherein the second internal communication link (170) comprises: a second differential voltage transmitter (181) operating referenced, powered by the second supply voltage domain (14), adapted to receive the reception data supplied from the external communication bus (24) operating in the second supply voltage domain (14) via the second interface (120), and adapted to generate and output a second differential voltage signal for transmission of the reception data, and a second differential voltage receiver (184) operating referenced, powered by the first supply voltage domain (12), adapted to receive the differential voltage signal transmitted by the second differential voltage transmitter (181), and adapted to generate and output a second single-ended digital signal for transmission of the reception data via the first interface (110) to the external first digital device (20) operating in the first supply voltage domain (12). a second differential voltage receiver (184), operating referenced, powered by said first supply voltage domain (12), adapted to receive said differential voltage signal transmitted by said second differential voltage transmitter (171) and adapted to transmit, via said first interface (110), a second single-ended digital signal for transmitting said received data to said second digital device (22) operating in said first supply voltage domain (12).

2. The transceiver apparatus (100) according to claim 1, characterized in that, having at least one of the following features: i) said transceiver device (100) is implemented as a monolithic integrated circuit, in particular wherein said monolithic integrated circuit is implemented in silicon-on-insulator, SOI, technology; ii) said transceiver device (100) has at least two ground pins (114, 124), including a first ground pin (114) adapted to be connected to a ground potential of said first supply voltage domain (12) and a second ground pin (124) adapted to be connected to a ground potential of said second supply voltage domain (14); iii) said transceiver device (100) has a common mode and ground offset range in a range starting from greater than ± 3 V but not exceeding ± 70 V; iv) said first supply voltage is nominal 48 V or higher; v) said second supply voltage is nominal 12 V or is nominal 24 V.

3. The transceiver apparatus (100) according to claim 1 or 2, characterized in that, said first interface (110) has: a transmit data input (116) adapted to receive said transmit data from said first digital device (20) operating in said first supply voltage domain (12), and a receive data output (118) adapted to transmit said received data to a second digital device (22) operating in said first supply voltage domain (12), in particular: wherein said first and second digital devices (20, 22) operating in said first supply voltage domain (12) are the same digital device (30), and / or wherein said first and second digital devices (20, 22) operating in said first supply voltage domain (12) together form a microcontroller unit (32).

4. The transceiver apparatus (100) according to claim 1 or 2, characterized in that, said second interface (120) has: at least one communication bus pin (126, 128) adapted to transmit said transmit data to and / or receive said received data from said communication bus (24) operating in said second supply voltage domain (14), in particular: wherein said external communication bus (24) operating in said second supply voltage domain (14) is selected from the group consisting of a CAN bus, a Flexray bus, a LIN bus and an Ethernet.

5. The transceiver device (100) according to claim 1, characterized in that: said first differential voltage transmitter (131, 141) has a first switch-based H-bridge (142) operating referenced, powered by said first supply voltage domain (12), and said second differential voltage receiver (184) has a second switch-based H-bridge (144) operating referenced, powered by said second supply voltage domain (14). the first differential voltage receiver (134, 144) has a first voltage divider resistor ladder (145) and a first comparator (146) operating with reference to a supply voltage supplied by the second supply voltage domain (14), wherein the first voltage divider resistor ladder (145) has a first resistor (145-1) with a second resistance value R2, a second resistor (145-2) with a first resistance value R1, a third resistor (145-3) with the first resistance value R1, and a fourth resistor (145-4) with the second resistance value R2 connected in series, wherein the first differential voltage signal output from the first switch-based H-bridge (142) is applied across the series connection consisting of the first to fourth resistors (145-1,..., 145-5), wherein the first voltage divider resistor ladder (145) outputs a first auxiliary differential voltage signal between a first connection point (145-5) connected between the first and second resistors (145-1, 145-2) and a second connection point (145-6) connected between the third and fourth resistors (145-3, 145-4), and wherein the first comparator (146) has an input (146-1), an inverting input (146-2), and an output (146-3), and receives the first auxiliary differential voltage signal applied to its input (146-1) and its inverting input (146-2), and outputs the first single-ended digital signal from its output (146-3), in particular, wherein a ratio between the first resistance value and the second resistance value is determined from the following equation: (R2 / R1) = (V1 / V2) - 1, wherein R1 is the first resistance value, R2 is the second resistance value, V1 is a nominal value of the first supply voltage, and V2 is a nominal value of the second supply voltage; in particular, wherein: the second differential voltage transmitter (181) has a second switch-based H-bridge (182) operating with reference to a supply voltage supplied by the second supply voltage domain (14), and the second differential voltage receiver (184) has a second voltage divider resistor ladder (185) and a second comparator (186) operating with reference to a supply voltage supplied by the first supply voltage domain (12), wherein the second voltage divider resistor ladder (185) has a first resistor (185-1) with a second resistance value R2, a second resistor (185-2) with a first resistance value R1, a third resistor (185-3) with the first resistance value R1, and a fourth resistor (185-4) with the second resistance value R2 connected in series, wherein the second differential voltage signal output from the second switch-based H-bridge (182) is applied across the series connection consisting of the first to fourth resistors (185-1,..., 185-5), wherein the second voltage divider resistor ladder (185) outputs a second auxiliary differential voltage signal between a first connection point (185-5) connected between the first and second resistors (185-1, 185-2) and a second connection point (185-6) connected between the third and fourth resistors (185-3, 185-4), and wherein the second comparator (186) has an input (186-1), an inverting input (186-2), and an output (186-3), and receives the second auxiliary differential voltage signal applied to its input (186-1) and its inverting input (186-2), and outputs the second single-ended digital signal from its output (186-3), wherein the second voltage divider resistor ladder (185) has a series connection of a fifth resistor (185-1), a sixth resistor (185-2), a seventh resistor (185-3) and an eighth resistor (185-4), the fifth resistor (185-1) having a second resistance value R2, the sixth resistor (185-2) having a first resistance value R1, the seventh resistor (185-3) having the first resistance value R1, the eighth resistor (185-4) having the second resistance value R2, wherein the second differential voltage signal output from the second switch-based H-bridge (182) is applied over the series connection consisting of the fifth to eighth resistors (185-1,..., 185-4), wherein the second voltage divider resistor ladder (185) outputs a second auxiliary differential voltage signal between a third connection point (185-5) connected between the fifth and sixth resistors (185-1, 185-2) and a fourth connection point (185-6) connected between the seventh and eighth resistors (185-3, 185-4), and wherein the second comparator (186) has an input terminal (186-1), an inverting input terminal (186-2) and an output terminal (186-3) and receives the second auxiliary differential voltage signal applied to its input terminal (186-1) and its inverting input terminal (186-2) and outputs the second single-ended digital signal from its output terminal (186-3); In particular, wherein the ratio between the first resistance value and the second resistance value is determined from the following equation: (R2 / R1) = (V1 / V2) - 1, wherein R1 is the first resistance value, R2 is the second resistance value, V1 is the nominal value of the first supply voltage and V2 is the nominal value of the second supply voltage.

6. An electrical network system (10), which is an electronic control unit, characterized in that a first supply voltage domain (12) having a higher voltage and a second supply voltage domain (14) having a lower voltage, and a transceiver device (100) for interfacing between the first supply voltage domain and the second supply voltage domain according to any one of claims 1 to 5.

7. A vehicle characterized by comprising: The vehicle has an electrical network system (10) according to claim 6, wherein the electrical network system is an electronic control unit.

8. A method of interfacing between at least two different voltage domains, a first supply voltage domain (12) having a higher first supply voltage and a second supply voltage domain (14) having a lower second supply voltage, characterized in that, The method uses a transceiver device (100) having a first interface (110), a second interface (120), a first internal communication link (130) and a second internal communication link (170), wherein the method has the following steps: supplying the first interface (110) with the first supply voltage and interfacing with at least one external first digital device (20) operating in the first supply voltage domain (12) via the first interface (110); supplying the second interface (120) with the second supply voltage and interfacing with an external communication bus (24) operating in the second supply voltage domain (14) via the second interface (120); By means of said first interface (110), transmission data generated by said external first digital device (20) operating in said first power supply voltage domain (12) are transferred via said first internal communication link (130) to said second interface (120), in particular further to said external communication bus (24) operating in said second power supply voltage domain (14); and By means of said second interface (120), reception data supplied from said external communication bus (24) operating in said second power supply voltage domain (24) are transferred via said second internal communication link (170) to said first interface (110), in particular further to said external second digital device (22) operating in said first power supply voltage domain (12); wherein, with respect to the transmission of transmission data and reception data, respectively, said first internal communication link (130) and said second internal communication link (170) are based on differential voltage transmission (140, 180); Said first internal communication link (130) comprises: a first differential voltage transmitter (141), operating referenced, powered by said first power supply voltage domain (12), said first differential voltage transmitter (141) being adapted to receive, via said first interface (110), said transmission data generated by said first digital device (20) operating in said first power supply voltage domain (12), and to generate and output a first differential voltage signal for transmitting said transmission data, and a first differential voltage receiver (144), operating referenced, powered by said second power supply voltage domain (14), said first differential voltage receiver (144) being adapted to receive said differential voltage signal transmitted by said first differential voltage transmitter (141), and to transmit, via said second interface (120), a first single-ended digital signal for transmitting said transmission data to said external communication bus (24) second digital device (26) operating in said second power supply voltage domain (14), in particular wherein said second internal communication link (170) comprises: a second differential voltage transmitter (181), operating referenced, powered by said second power supply voltage domain (14), said second differential voltage transmitter (181) being adapted to receive, via said second interface (120), said reception data supplied from said external communication bus (24) operating in said second power supply voltage domain (14), and to generate and output a second differential voltage signal for transmitting said reception data, and a second differential voltage receiver (184), operating referenced, powered by said first power supply voltage domain (12), said second differential voltage receiver (184) being adapted to receive said differential voltage signal transmitted by said second differential voltage transmitter (171), and to transmit, via said first interface (110), a second single-ended digital signal for transmitting said reception data to said second digital device (22) operating in said first power supply voltage domain (12).

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