LDPC decoding method and device

Abstract

The present invention provides a method for generating LDPC soft information, comprising reading hard bit data corresponding to data stored in an NVM; performing LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output; if the LDPC hard decision decoding result is a failure, reading soft bit data associated with the hard bit data; mapping the hard decision decoding output and the soft bit data into soft information; and performing LDPC soft decision decoding based on the soft information. The technical solution of the present invention can reduce the number of repeated flash reads, improve throughput, and increase decoding success rate.

Description

Technical Field

[0001] The present invention relates to a low density parity check code (LDPC) decoding method and a device thereof, and more particularly to a soft information generation method in an LDPC decoding process. Background Art

[0002] Low-density parity-check (LDPC) codes have excellent performance under iterative decoding, but they exhibit an error floor phenomenon in high signal-to-noise ratio areas. Compared with traditional Reed-Solomon (RS) codes and Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes (such as Figure 1 Compared with the curve indicated by "RS / BCH" in Figure 1 As shown in the curve indicated by "LDPC" in the figure, when the raw bit error rate (RBER) is within a certain range, the frame error rate (FER) of the LDPC decoding scheme gradually decreases; as the RBER further decreases, the LDPC FER drops sharply, and this area is called the waterfall region. After the sharp drop in the waterfall region, the LDPC FER usually decreases slowly or even stops decreasing, and this area is generally called the error plateau. The area where the FER changes relatively smoothly in the error plateau is generally used as the working area of the LDPC system (such as Figure 1 In this region, the LDPC system has a low FER and can meet the application requirements.

[0003] Storage devices commonly use non-volatile memory (NVM) as a storage medium. Common NVM types include NAND flash, phase-change memory, FeRAM, and MRAM. Data stored in NVM is susceptible to corruption to some extent. To overcome this issue, fault-tolerant codecs are often used to protect data stored on NVM when accessing it. Research is underway to use LDPC in NVM to improve data reliability in storage devices.

[0004] During LDPC decoding, data read from the NVM is typically first decoded using hard decision decoding. Soft decision decoding is then used if the hard decision fails. Soft decision decoding requires several bits of soft information. Multiple NVM read operations are required to obtain the necessary soft information. However, these multiple read operations consume the NVM's read bandwidth and increase the read time.

[0005] like Figure 2 As shown, usually, during the soft decision decoding process, the soft information (≥2 bits) is spelled out by reading the NVM multiple times. Generally, the soft information is derived from one hard bit and one or more soft bits. Figure 2 As shown, as an example, the bit sequence 200 stored (written) in the NVM is a bit sequence of all 0s. When the bit sequence is read out from the NVM, due to the characteristics of the NVM itself, there may be some erroneous bits, resulting in the read bit sequence not necessarily being the originally stored all-0 bit sequence. The read bit sequence is called a hard bit (HB) sequence. The hard decision decoding is performed on the read hard bit (HB) sequence 210 to obtain a bit sequence 220 output by the hard decision decoding. In the hard decision decoding, a hard decision decoding result indicating whether the hard decision decoding is successful or not is also output (not shown). Figure 2 In the example, the bit sequence 220 output by the hard decision decoding is different from the bit sequence 200 stored in the NVM. Accordingly, the hard decision decoding result is failure.

[0006] exist Figure 2 In the example shown in FIG1 , in response to a hard decision decoding failure, soft bit (SB) sequence SB0 230 and soft bit sequence SB1 240 associated with hard bit (HB) sequence 210 are read from the NVM. Hard bit sequence 210, soft bit sequence 230, and soft bit sequence 240 are mapped to soft information, and LDPC soft decoding is performed using the soft information.

[0007] It should be noted that different manufacturers have different definitions of hard bits and soft bits. For example, a hard bit can be the bit value read through a "normal read" or a "retry read," while a soft bit is the value read using V+Δv and V-Δv, respectively, on either side of the threshold voltage V of the aforementioned read operation. By setting different Δv, one or more soft bits can be generated for a single hard bit. A hard bit and one or more soft bits constitute soft information. In the prior art, an "XOR" operation can also be performed on two or more read soft bits, and the resulting result can also be referred to as "soft information." This shows that soft bits are based on and associated with hard bits. The above is just one example of hard and soft bits, and the present invention is not limited to the specific types and operations described above.

[0008] Continue to read Figure 2 , Figure 2 The first bit 210-1 in the hard bit (HB) sequence 210, the first bit (230-1) in the soft bit (SB) sequence 230, and the first bit (240-1) in the soft bit sequence 240 together form a three-bit first soft information SI-1, which is 000. It is understood that other soft information may also exist, such as Figure 2 As shown by Figure 2The fifth soft information SI-5 composed of the fifth bit 210-5 in the hard bit sequence 210, the fifth bit 230-5 in the soft bit sequence 230, and the fifth bit 240-5 in the soft bit sequence 240 is 100. Figure 2 The tenth soft information SI-10 composed of the tenth bit 210-10 in the hard bit sequence 210, the tenth bit 230-10 in the soft bit sequence 230, and the tenth bit 240-10 in the soft bit sequence 240 is 010, and so on. Each of the above soft information includes the original hard bit read from the NVM (in this example, 1 bit, for example Figure 2 ), and the soft bits associated with the hard bit (2 bits in this example, e.g. Figure 2 It should be understood that the soft information according to the embodiment of the present invention is not limited to the above number of bits.

[0009] Since the error rate of the hard bit sequence read from the Flash is high when hard decision decoding fails, the accuracy of soft information in the prior art is low, which in turn affects the decoding speed and decoding success rate.

[0010] In summary, when hard decision decoding fails and soft decoding is initiated, the hard bits need to be read from the flash again. This has the following disadvantages: (1) multiple flash reads result in a decrease in read throughput; (2) when hard decision decoding fails, the hard bits read from the flash have a high error rate, thus affecting the decoding speed and decoding success rate. Summary of the Invention

[0011] The present invention aims to improve the decoding efficiency when LDPC is used for NVM.

[0012] According to a first aspect of the present invention, a method for generating LDPC soft information is provided, comprising: instructing to read hard bit data for data stored in a storage device; receiving a result of LDPC hard decision decoding based on the hard bit data and a hard decision decoding output, and in response to a result of the LDPC hard decision decoding being a failure, instructing to read soft bit data associated with the hard bit data; and instructing to map the hard decision decoding output and the soft bit data into soft information for use in performing LDPC soft decision decoding.

[0013] According to one embodiment of the present invention, the method further includes cyclically performing the following operations: if the result of the LDPC soft decision decoding is a failure, determining whether the number of failures of the LDPC soft decision decoding exceeds a first number; if it does not exceed the first number; instructing to read the first updated soft bit data associated with the hard bit data; and instructing to map the hard decision decoding output and the first updated soft bit data into first updated soft information for performing LDPC soft decision decoding.

[0014] According to one embodiment of the present invention, it further includes cyclically performing the following operations: if the number of failures of the LDPC soft decision decoding exceeds a first number; determining whether the number of LDPC hard decision decoding exceeds a second number; if it does not exceed the second number, instructing to read the updated hard bit data for the data stored in the storage device; receiving the updated LDPC hard decision decoding result and the updated hard decision decoding output of the LDPC hard decision decoding based on the updated hard bit data, and if the result of the updated LDPC hard decision decoding is a failure, instructing to read the second updated soft bit data associated with the updated hard bit data; instructing to map the updated hard decision decoding output and the second updated soft bit data into second updated soft information for LDPC soft decision decoding.

[0015] According to a second aspect of the present invention, there is provided an LDPC decoding method, comprising: reading hard bit data for data stored in a storage device; performing LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output; if the result of the LDPC hard decision decoding is a failure, reading soft bit data associated with the hard bit data; mapping the hard decision decoding output and the soft bit data into soft information; and performing LDPC soft decision decoding based on the soft information.

[0016] According to an embodiment of the second aspect of the present invention, the present invention further includes cyclically performing the following operations: if the result of the LDPC soft decision decoding is a failure, determining whether the number of failures of the LDPC soft decision decoding exceeds a first number; if it does not exceed the first number; reading the first updated soft bit data associated with the hard bit data; mapping the hard decision decoding output and the first updated soft bit data into first updated soft information; and performing LDPC soft decision decoding based on the first updated soft information.

[0017] According to an embodiment of the second aspect of the present invention, the present invention further includes: cyclically performing the following operations: if the number of failures of the LDPC soft decision decoding exceeds the first number; then determining whether the number of LDPC hard decision decoding exceeds the second number; if it does not exceed the second number, reading the updated hard bit data for the data stored in the storage device; performing LDPC hard decision decoding based on the updated hard bit data to obtain the updated LDPC hard decision decoding result and the updated hard decision decoding output, if the result of the updated LDPC hard decision decoding is failure, then reading the second updated soft bit data associated with the updated hard bit data; mapping the updated hard decision decoding output and the second updated soft bit data to second updated soft information; and performing LDPC soft decision decoding based on the second updated soft information.

[0018] According to an embodiment of the second aspect of the present invention, the mapping is a log-likelihood ratio mapping.

[0019] According to an embodiment of the second aspect of the present invention, the storage device is a flash memory.

[0020] According to a third aspect of the present invention, a method for LDPC decoding is provided, comprising: a control device instructing to read hard bit data for data stored in a storage device; a soft information generator storing the hard bit data; an LDPC decoder performing LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output; the control device receiving the LDPC hard decision decoding result and the hard decision decoding output based on the hard bit data from the LDPC decoder; the control device instructing to read soft bit data associated with the hard bit data in response to a result of the LDPC hard decision decoding being a failure; the soft information generator receiving at least the hard decision decoding output from the LDPC decoder and mapping the hard decision decoding output and the soft bits into soft information; the LDPC decoder performing LDPC soft decision decoding based on the soft information to obtain an LDPC soft decision decoding result, and sending the LDPC soft decision decoding result to the control device.

[0021] According to an embodiment of the third aspect of the present invention, it further includes cyclically performing the following operations: if the result of the LDPC soft decision decoding is failure, the control device determines whether the number of failures of the LDPC soft decision decoding exceeds the first number; if it does not exceed the first number; the control device instructs to read the first updated soft bit data associated with the hard bit data; the soft information generator maps the hard decision decoding output and the first updated soft bit data into first updated soft information; and the LDPC decoder performs LDPC soft decision decoding on the first updated soft information.

[0022] According to an embodiment of the third aspect of the present invention, the method further includes cyclically performing the following operations: if the control device determines that the number of failures of the LDPC soft decision decoding exceeds a first number; the control device determines whether the number of LDPC hard decision decoding exceeds a second number; if it does not exceed the second number, the control device instructs reading updated hard bit data for the data stored in the storage device; the LDPC decoder performs LDPC hard decision decoding based on the updated hard bit data to obtain an updated LDPC hard decision decoding result and an updated hard decision decoding output; if the control device determines that the result of the updated LDPC hard decision decoding is a failure, the control device instructs reading second updated soft bit data associated with the updated hard bit data; the soft information generator maps the updated hard decision decoding output and the second updated soft bit data into second updated soft information; and the LDPC decoder performs LDPC soft decision decoding based on the second updated soft information.

[0023] According to a fourth aspect of the present invention, an LDPC decoding device is provided, comprising: a device for reading hard bit data for data stored in a storage device; a device for performing LDPC hard decision decoding based on the hard bit data to obtain a result of the LDPC hard decision decoding and a hard decision decoding output; a device for reading soft bit data associated with the hard bit data if the result of the LDPC hard decision decoding is a failure; a device for mapping the hard decision decoding output and the soft bit data into soft information; and a device for performing LDPC soft decision decoding based on the soft information.

[0024] According to a fifth aspect of the present invention, a device for generating LDPC soft information is provided, comprising: a device for instructing the reading of hard bit data for data stored in a storage device; a device for receiving a result of LDPC hard decision decoding based on the hard bit data and a hard decision decoding output, and a device for instructing the reading of soft bit data associated with the hard bit data if the result of the LDPC hard decision decoding is a failure; and a device for instructing the mapping of the hard decision decoding output and the soft bit data into soft information for use in performing LDPC soft decision decoding.

[0025] According to a sixth aspect of the present invention, there is provided an LDPC decoding system, comprising: a soft information generator, an LDPC decoder, and a control device, wherein the soft information generator is configured to: store hard bit data and / or soft bit data for data stored in a storage device; receive at least a hard decision decoding output from the LDPC decoder, and map the hard decision decoding output and the soft bits into soft information; the LDPC decoder is configured to perform LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output, and / or perform LDPC soft decision decoding based on the soft information to obtain an LDPC soft decision decoding result; and the control device is configured to: instruct reading of hard bit data for data stored in the storage device; receive a result and a hard decision decoding output of LDPC hard decision decoding performed based on the hard bit data, and in response to a result of the LDPC hard decision decoding being a failure, instruct reading of soft bit data associated with the hard bit data; and instruct mapping the hard decision decoding output and the soft bit data into soft information for performing LDPC soft decision decoding.

[0026] According to an embodiment of the sixth aspect of the present invention, the control device is further used to cyclically perform the following operations: if the result of the LDPC soft decision decoding is failure, determine whether the number of failures of the LDPC soft decision decoding exceeds a first number; if it does not exceed the first number; instruct to read the first updated soft bit data associated with the hard bit data; instruct to map the hard decision decoding output and the first updated soft bit data into first updated soft information for LDPC soft decision decoding.

[0027] According to an embodiment of the sixth aspect of the present invention, it further includes cyclically performing the following operations: if the number of failures of the LDPC soft decision decoding exceeds a first number; then determining whether the number of LDPC hard decision decoding exceeds a second number; if it does not exceed the second number, then instructing to read the updated hard bit data for the data stored in the storage device; receiving the updated LDPC hard decision decoding result and the updated hard decision decoding output of the LDPC hard decision decoding based on the updated hard bit data, and if the result of the updated LDPC hard decision decoding is a failure, then instructing to read the second updated soft bit data associated with the updated hard bit data; and instructing to map the updated hard decision decoding output and the second updated soft bit data into second updated soft information for LDPC soft decision decoding.

[0028] According to an embodiment of the sixth aspect of the present invention, the system is implemented by an application-specific integrated circuit (ASIC).

[0029] According to a seventh aspect of the present invention, there is provided a computer program comprising computer program code which, when loaded into and executed on a computer system, causes the computer system to perform the method described above.

[0030] According to an eighth aspect of the present invention, there is provided a program comprising program code which, when loaded into a storage device and executed on the storage device, causes the storage device to perform the method described above.

[0031] The technical solution of the present invention can reduce the number of repeated readings of NVM, improve throughput, and increase decoding success rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the error platform of the LDPC decoding scheme is shown;

[0033] Figure 2 A schematic diagram of performing LDPC decoding on memory read data under the prior art is shown;

[0034] Figure 3 A system block diagram of an LDPC decoding system according to an embodiment of the present invention is shown;

[0035] Figure 4 A flow chart of a method for LDPC decoding according to one aspect of the present invention is shown;

[0036] Figure 5 A signal flow diagram of an LDPC decoding method according to an embodiment of the present invention is shown;

[0037] Figure 6 A flow chart of an LDPC decoding method according to an embodiment of the present invention is shown;

[0038] Figure 7 A flow chart of a method for generating LDPC soft information according to one aspect of the present invention is shown;

[0039] Figure 8 A flow chart of a method for generating LDPC soft information according to an embodiment of the present invention is shown;

[0040] Figure 9 A schematic block diagram of a device for generating LDPC soft information according to another aspect of the present invention is shown;

[0041] Figure 10 A flow chart of a method for LDPC decoding according to another aspect of the present invention is shown;

[0042] Figure 11 A flowchart of an LDPC decoding method according to an embodiment of the present invention is shown;

[0043] Figure 12 A schematic block diagram showing an apparatus for generating LDPC soft information according to another aspect of the present invention; and

[0044] Figure 13 A schematic diagram of performing LDPC decoding on memory read data according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0045] The specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0046] According to the prior art, when soft decoding is initiated after hard decision decoding fails, the hard bits must be re-read from memory, resulting in drawbacks such as reduced throughput and a low decoding success rate. Therefore, efficiently generating or constructing soft information can improve throughput and increase decoding success rates.

[0047] Figure 3 FIG. 1 shows a system block diagram of an LDPC decoding system according to an embodiment of the present invention. Figure 3 As shown, an LDPC decoding system according to one embodiment of the present invention includes: a soft information generator 10, an LDPC decoder 20 and a control device 30, wherein the soft information generator 10 is used to: store hard bit data and / or soft bit data for data stored in a storage device; receive and store at least a hard decision decoding output from the LDPC decoder, and map the hard decision decoding output and the soft bit (if any) into soft information.

[0048] Data stored in a storage device typically refers to data read from a storage device, such as a flash memory. This data primarily includes user data, system data, and parity bits. This data may contain errors. LDPC decoding can be performed on this data to obtain the correct user and system data.

[0049] The soft information generator 10 can receive the output result from the LDPC decoder 20. It should be understood that "receiving the output result from the LDPC decoder 20" herein can mean directly receiving the output result from the LDPC decoder 20 or indirectly receiving the output result from the LDPC decoder 20 through other components. For example, the control device 30 can receive the output result from the LDPC decoder 20, and then the soft information generator 10 receives the output result from the control device 30.

[0050] After receiving the hard decision decoding output and hard decision decoding result from LDPC decoder 20, soft information generator 10 determines that the decoding was successful if the hard decision decoding result from LDPC decoder 20 is successful, and no further soft bit reading is required. If the hard decision decoding result is unsuccessful, soft bit data associated with the hard bit data must be read and the hard decision decoding output and the soft bit data must be mapped to form soft information. The soft information corresponding to a hard bit is typically two or more bits, consisting of one hard bit and several soft bits, typically two soft bits. However, the present invention is not limited to the specific numbers of hard bits and soft bits.

[0051] The above mapping can be, for example, a log-likelihood ratio (LLR) mapping. LLR mapping is widely used in LDPC decoding. For example, regardless of whether the transmitter sends a bit 1 or a bit 0, the receiver may misjudge it. Assuming that a signal r is received, the ratio of the probability p(r|b=0) that it is correctly judged as 0 to the probability p(r|b=1) that it is correctly judged as 1 is the likelihood ratio p(r|b=0) / p(r|b=1). Then, the logarithm of this likelihood ratio can be obtained as LLR=ln[p(r|b=0) / p(r|b=1)].

[0052] It should be noted that soft information can be directly decoded, but preferably, an LLR mapper first maps the soft information into LLRs, which are then fed into the decoder. Soft-decision decoding can be identical to hard-decision decoding, but soft-decision decoding offers greater error correction capabilities because the LLRs mapped from the soft information are more accurate.

[0053] Specifically, the hard bit consists of only one bit, so the LLR can only be mapped to, for example, +4 and -4. However, the soft information corresponding to the hard bit consists of multiple bits, so the LLR can be mapped to, for example, +5, +2, -2, and -5. This ensures that the input information is accurate and the decoding success rate is improved.

[0054] like Figure 3 As shown, the LDPC decoder 20 can perform LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output. In addition, the LDPC decoder 20 can also perform LDPC soft decision decoding based on the soft bit data to obtain an LDPC soft decision decoding result.

[0055] Those skilled in the art will appreciate that decoder 20 can be any known or future-developed decoder capable of both hard-decision decoding and soft-decision decoding. It should also be understood that hard-decision decoding and soft-decision decoding can be performed uniformly by the same entity or by separate entities. For example, LDPC decoder 20 can include separate hard-decision decoders (not shown) and soft-decision decoders (not shown), i.e., the hard-decision decoder only performs hard-decision decoding, while the soft-decision decoder only performs soft-decision decoding. The present invention does not impose any limitations on whether LDPC decoder 20 is integrated or separate.

[0056] The decoder 20 can determine whether the decoding is successful (decoding result) and generate a decoding output during decoding. The decoding result and / or the decoding output can then be sent to the control device 30 for further processing.

[0057] Although Figure 3 While control device 30 is shown as a single control device, it can also be comprised of multiple separate control devices, each with its own distinct functions and cooperating with each other. For example, control device 30 can include a result analyzer responsible for analyzing the decoding results and transmitting them to the host. The host can then modify policies or issue other instructions based on the analysis results. This will be described in more detail later.

[0058] Various embodiments of the present invention will be explained below in conjunction with the soft information generator 10 , the decoder 20 , and the control device 30 .

[0059] Figure 4 A flow chart of an LDPC decoding method according to an embodiment of the present invention is shown. Figure 5 FIG. 1 shows a signal flow diagram of an LDPC decoding method according to an embodiment of the present invention. Figure 4 and Figure 5 As shown, the method according to the embodiment of the present invention includes the following operations.

[0060] In a first operation S100, the control device 30 instructs the reading of hard bit data corresponding to data stored in the storage device. The hard bit data corresponding to data stored in the storage device refers to the hard bits used to make hard decisions on data read from the flash memory. These hard bits can be the original hard bits or hard bits subsequently read back in. The hard bits have been described above and will not be further elaborated here.

[0061] It should also be understood that the “reading instruction” mentioned above may be that the control device 30 issues a reading instruction, and other components (such as the soft information generator 20) perform the reading action, or the control device 30 itself directly performs the reading.

[0062] In a second operation S200, the soft information generator stores the hard bit data. The soft information generator 10 may store the hard bit data in a memory therein.

[0063] In the third operation S300, the LDPC decoder performs LDPC hard decision decoding based on the hard bit data to obtain the LDPC hard decision decoding result and hard decision decoding output. It should be understood that the result of the hard decision decoding described in the present invention refers to whether the hard decision decoding is successful. The result can be a success or a decoding failure. These results can be sent to the control device 30. If the decoding is successful, it means that the flash memory data has been successfully decoded. The hard decision decoding output described here refers to the output result obtained after the data is hard decision decoded, and the result can be a correct result or an incorrect result. In other words, if the hard decision decoding output is a correct result, the hard decision decoding result indicates that the decoding is successful, and if the hard decision decoding output is an incorrect result, the hard decision decoding result indicates that the decoding failed.

[0064] In a fourth operation S400 , the control device 30 receives a result of LDPC hard decision decoding based on the hard bit data and a hard decision decoding output from the LDPC decoder 20 .

[0065] Next, we discuss the case where decoding fails.

[0066] If the result of the LDPC hard decision decoding is a failure, then in a fifth operation S500 , the control device 30 instructs reading of soft bit data associated with the hard bit data in response to the result of the LDPC hard decision decoding being a failure.

[0067] As described in the background art, soft bit data is always based on and associated with hard bit data, and has different definitions depending on the manufacturer, which will not be described in detail here.

[0068] In the sixth operation S600, the soft information generator 10 receives at least the hard decision decoding output from the LDPC decoder 20 and maps the hard decision decoding output and the soft bits into soft information. Soft information consists of the hard decision output and the corresponding soft bits. Compared to hard bits, soft information contains more information, thus improving decoding accuracy. Furthermore, performing LLR mapping on soft information also helps improve the decoding success rate. This has been described in detail above and will not be repeated here.

[0069] In a seventh operation S700 , the LDPC decoder 20 performs LDPC soft decision decoding based on the soft information to obtain an LDPC soft decision decoding result, and sends the LDPC soft decision decoding result to the control device 30 .

[0070] It is understood that the LDPC decoder 20 can decode the soft information in two ways: success and failure. If successful, it means that the data read from the storage device has been successfully decoded. If unsuccessful, further processing is performed. The further processing will be described in detail below.

[0071] In the prior art, if hard decision decoding fails, soft information mapping is performed between the hard bits and the corresponding soft bits. In the embodiments of the present invention, when hard decision decoding fails, soft information mapping is performed between the output of hard decision decoding and the corresponding soft bits. In the prior art, if soft information decoding fails, hard bits are immediately retrieved and new soft information mapping and decoding are performed based on them. This undoubtedly increases the number of data reads and thus reduces throughput.

[0072] Figure 6 A flow chart of an LDPC decoding method according to an embodiment of the present invention is shown.

[0073] like Figure 6 As shown, according to one embodiment of the present invention, the process further includes cyclically executing the following operations S500-S700.

[0074] Specifically, if Figure 6 As shown, first, in a first operation S100 , the control device 30 instructs to read hard bit data for data stored in the storage device.

[0075] Then, in a second operation S200, the soft information generator 10 stores the hard bit data. The soft information generator 10 may store the hard bit data in a memory therein.

[0076] Next, in a third operation S300, the LDPC decoder 20 performs LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output.

[0077] Furthermore, in a fourth operation S400 , the control device 30 receives a result of LDPC hard decision decoding based on the hard bit data and a hard decision decoding output from the LDPC decoder 20 .

[0078] The result of hard decision decoding can be success or failure. If it is successful, it means that the decoding of memory data is successful. Figure 6 The process is shown in the following figure.

[0079] The following focuses on the case where decoding fails.

[0080] If the result of the LDPC hard decision decoding is a failure, the operation proceeds to the fifth operation S500. In the fifth operation S500, the control device 30 instructs to read the soft bit data associated with the hard bit data in response to the result of the LDPC hard decision decoding being a failure.

[0081] As described in the background art, soft bit data is always based on and associated with hard bit data, and has different definitions depending on the manufacturer, which will not be described in detail here.

[0082] Furthermore, in the sixth operation S600, the soft information generator 10 receives at least the hard decision decoding output from the LDPC decoder 20 and maps the hard decision decoding output and the soft bits into soft information. Soft information is composed of the hard decision output and the corresponding soft bits. In another example, soft information is derived from the hard decision output and the corresponding soft bits. Compared to hard bits, soft information contains more information and therefore has higher decoding accuracy. Furthermore, performing LLR mapping on the soft information also helps improve the decoding success rate. This has been described in detail above and will not be repeated here.

[0083] In the seventh operation S700 , the LDPC decoder 20 performs LDPC soft decision decoding based on the soft information to obtain a result of the LDPC soft decision decoding. In a further embodiment, the result of the LDPC soft decision decoding is further sent to the control device 30 .

[0084] If the soft decision decoding is successful, it means that the decoding of the memory data is successful. After the decoding is successful, the decoding process ends. Figure 6 shown.

[0085] If the result of the LDPC soft decision decoding is failure, the control device 30 determines whether the number of failures of the LDPC soft decision decoding exceeds a first number N; if it does not exceed the first number N (see Figure 6), the control device 30 instructs the reading of first updated soft bit data associated with the hard bit data, and the process returns to operation S500. It should be understood that the first updated soft bit data referred to herein is based on the original hard bit data or the newly read soft bit data associated with the original hard bit data. In this case, the newly read soft bit data replaces the original soft bit data. In another embodiment, the newly read soft bit data is used together with the original soft bit data.

[0086] Then, the soft information generator 10 maps the hard decision decoding output and the first updated soft bit data into the first updated soft information (S600). At this time, the updated soft information will replace the original soft information for further soft decision decoding. It will be understood by those skilled in the art that although Figure 6 The terms “updated soft bit data” and “first updated soft information” are not directly given, but each cycle or iteration will generate corresponding updated data content.

[0087] The LDPC decoder 20 performs a new round of LDPC soft decision decoding on the first updated soft information ( S700 ).

[0088] from Figure 6 As can be seen from FIG, if the LDPC decoder 20 fails to decode the soft information, the control device 30 will again instruct to read the soft bit data based on the original hard bit data for the stored data.

[0089] After reading the new soft bit data, the soft information generator generates new soft information. The LDPC decoder 20 then decodes the new soft information. If the decoding is successful, a success report is issued, indicating that the memory data was successfully decoded. After successful decoding, the operation ends.

[0090] If it fails, the control device 30 may request to read new soft bits again, and perform multiple soft information mapping and soft decoding based on the hard decision decoding output of the original hard bits and the newly read soft bits (and / or previously read soft bits).

[0091] The first number N can be set by those skilled in the art based on practical needs. A larger N facilitates decoding with fewer hard bits, but it also may result in excessive, invalid decoding of soft information, thereby reducing throughput. A smaller N reduces the number of soft information decoding attempts for the same hard bit, but it may also waste opportunities for successful decoding for that hard bit. Those skilled in the art will select an appropriate N based on practical needs and memory design requirements.

[0092] Reference again Figure 6According to one embodiment of the present invention, it further includes: if the control device 30 determines that the number of failures of the LDPC soft decision decoding exceeds a first number N; then the control device 30 determines whether the number of failures of the LDPC hard decision decoding exceeds a second number M; if it does not exceed the second number M, perform operations S100-S700.

[0093] It can be seen from the description in the previous paragraph that after multiple decoding failures, the control device 30 can change the strategy to perform further hard decision decoding.

[0094] Specifically, if the number of failures of the LDPC soft decision decoding exceeds the first number N, it means that the success probability of multiple soft decision decodings under the same hard decision output is already low, and the decoding strategy needs to be changed to increase the possibility of decoding success.

[0095] In this case, the control device 30 may continue to determine whether the number of times of the LDPC hard decision decoding exceeds the second number M; if it does not exceed the second number, the control device 30 may instruct to read the updated hard bit data for the data stored in the storage device, that is, return to Figure 6 The updated hard bit data may be new hard bits that are re-read.

[0096] Therefore, the LDPC decoder 20 may perform LDPC hard decision decoding based on the updated hard bit data to obtain an updated LDPC hard decision decoding result and an updated hard decision decoding output ( S300 ).

[0097] If the control device 30 determines that the result of the updated LDPC hard decision decoding is a failure, the control device 30 instructs reading of second updated soft bit data associated with the updated hard bit data ( S500 ).

[0098] The second updated soft bit data referred to herein refers to the soft bit data associated with the updated hard bit data. The term "second" is used to distinguish the updated soft bit data associated with the original hard bit data (i.e., the first updated soft bit data) for ease of understanding. Those skilled in the art will appreciate that the terms "first" and "second" are dynamic concepts. As the hard bits are continuously updated and iterated, the original "second soft bit data" may be referred to as "first soft bit data" in the next cycle, while the newly read soft bit data may be referred to as "second soft bit data." The terms "first," "second," and "updated" in this disclosure are dynamic, not static, concepts.

[0099] After reading new soft bits based on the updated hard bits, the soft information generator 10 may map the updated hard decision decoding output and the second updated soft bit data into second updated soft information ( S600 ).

[0100] Then, the LDPC decoder 20 may perform LDPC soft decision decoding based on the second updated soft information ( S700 ).

[0101] It will be appreciated that if any of the above decoding attempts succeed, a report of successful decoding can be made, for example, to the control device 30. This indicates that the stored data has been successfully decoded, and the current operation is terminated. However, if the number of failed decoding attempts for the hard bits exceeds the second number M, this indicates that the probability of successful decoding is very low, and in this case, a decoding failure is reported.

[0102] As can be seen from the above description, compared with the prior art, after decoding of soft information fails, the present invention does not immediately read a new hard bit. Instead, it reads soft bits multiple times based on the same hard bit, combines the output obtained by hard decision decoding based on the hard bit with the read-in new soft bit to form new soft information, and continuously decodes the newly generated soft information until the soft information still cannot be decoded after a certain number of times, at which time it reads a new hard bit.

[0103] LDPC is an iterative decoding algorithm. During the iteration process, a bit determines whether to change its value based on information transmitted by other bits. Therefore, each iteration results in a corrected codeword. After the iteration, the corrected codeword is verified to be legal. If it is, the decoding is successful, a success report is issued, and the current run ends. Otherwise, the next iteration begins until the maximum number of iterations is exceeded. One embodiment of the present invention utilizes soft information, which is composed of codewords after hard decision decoding and newly read soft bits, during soft-decision decoding, resulting in a high soft-decoding success rate.

[0104] It can be seen from the above description that how to generate soft information plays an important role in whether decoding can be successful, so the present invention will further discuss how to generate effective soft information. Figure 7 A flow chart of a method for generating LDPC soft information according to one aspect of the present invention is shown.

[0105] like Figure 7As shown, according to another aspect of the present invention, a method for generating LDPC soft information is also provided, the method comprising: in operation S1000, instructing to read hard bit data for data stored in a storage device; in operation S2000, receiving a result of LDPC hard decision decoding based on the hard bit data and a hard decision decoding output; in operation S3000, in response to a result of the LDPC hard decision decoding being a failure, instructing to read soft bit data associated with the hard bit data; in operation S4000, instructing to map the hard decision decoding output and the soft bit data into soft information for performing LDPC soft decision decoding.

[0106] According to one embodiment of the present invention, hard bit data may include one or more hard bits, with one bit being illustratively provided in this example. Soft bit data may include one or more soft bits, with two bits being illustratively provided in this example. It should be understood that the above numbers are merely examples and the present invention is not limited to these specific numbers. Numerous variations are possible.

[0107] The above methods and operations can be implemented separately in Figure 3 As described above, the control device 30 may include a result analysis device and a host (not shown). The result analysis device may be a device capable of recording, summarizing, analyzing, and / or forwarding the output results of the LDPC decoder 20. The result analysis device may be implemented in any appropriate manner, such as software, hardware, firmware, or a combination thereof. The host may be a PC, a digital processor, a dedicated controller, or other device capable of receiving and sending various data, instructions, and other content from / to the result analysis device.

[0108] In addition, the control device 30 can also be a result analysis device, that is, the result analysis device is responsible for all recording, summarizing, analyzing, processing, indicating and other functions without forwarding information to an external host (such as a PC). This has the advantage of improving processing speed.

[0109] Operations S1000-S3000 may be performed by the result analyzer alone or by the result analyzer and the host together. For example, the host may perform steps S1000, S3000, and S4000, while the result analyzer may perform S2000. Specifically, the host may issue an instruction to read hard bit data for data stored in the storage device. Figure 3) After hard decision decoding is performed on the hard bit data, the result analyzer can receive the decoding result and decoding output and transfer it to the host. The host performs subsequent operations based on the decoding result. For example, after the hard decision decoding fails, the host can instruct to read the updated soft bit data and instruct the soft information generator 10 (see Figure 3 ) to generate updated soft information.

[0110] The above is just one example. In another embodiment, when the result analyzer receives the decoding result (for example, when the decoding fails), it can directly instruct to read the soft bits without reporting to the host.

[0111] Furthermore, for operations S1000 and S3000, "instructing to read" can be performed by one execution entity (e.g., the control device 30), i.e., the entity issues a read instruction and also performs a further read operation; "instructing to read" can also be performed by different execution entities, e.g., one entity (e.g., the control device 30) issues a read instruction and instructs another entity (e.g., the soft information generator 10) to perform a "read" operation. The present invention is not limited to the specific execution entities described above.

[0112] Figure 8 A flow chart of a method for generating LDPC soft information according to an embodiment of the present invention is shown.

[0113] like Figure 8 As shown, in operation S1000, an instruction is given to read hard bit data corresponding to data stored in a storage device. "Instructing to read" herein may include one or more execution entities. For example, one entity issues an instruction to read, instructing another entity to perform the read action. Alternatively, the entity issuing the instruction itself may perform the read action. The present invention is not limited to a specific number of entities.

[0114] Next, in operation S2000, a result of LDPC hard decision decoding performed based on the hard bit data and a hard decision decoding output are received.

[0115] The result of hard decision decoding can be success or failure. If it is successful, it means that the decoding of memory data is successful, and the operation ends at this time. Figure 8 The process is shown in the following figure.

[0116] The following focuses on the case where decoding fails.

[0117] When the result of the hard decision decoding is a failure, in operation S3000 , in response to the result of the LDPC hard decision decoding being a failure, an instruction is given to read soft bit data associated with the hard bit data.

[0118] In operation S4000, the hard decision decoding output and the soft bit data are mapped into soft information for performing LDPC soft decision decoding.

[0119] Next, the LDPC soft decision decoding result is determined to be successful. If the LDPC soft decision decoding result is a failure, operations S3000-S4000 are executed repeatedly until the number of LDPC soft decision decoding failures exceeds the first number N. If the soft decision decoding is successful, the decoding is reported as successful and the current operation ends.

[0120] Specifically, the method of generating LDPC soft information of the present invention further includes cyclically performing the following operations: if the result of the LDPC soft decision decoding is failure, determining whether the number of failures of the LDPC soft decision decoding exceeds the first number N; if it does not exceed the first number N; instructing to read the first updated soft bit data associated with the hard bit data (S3000); instructing to map the hard decision decoding output and the first updated soft bit data into the first updated soft information for LDPC soft decision decoding (S4000).

[0121] The above embodiment describes the case where the number of LDPC soft decision decoding failures does not exceed the first number N. Another embodiment in which the number of LDPC soft decision decoding failures exceeds the first number N is described below.

[0122] Further Figure 8 As shown, if the number of LDPC soft decision decoding failures exceeds the first number N, the method for generating LDPC soft information of the present invention further includes cyclically performing operations S1000-S4000 until the number of LDPC hard decision decoding failures exceeds the second number M. If decoding is successful during this period, the decoding success is reported and the current operation ends.

[0123] Specifically, the method for generating LDPC soft information of the present invention further includes cyclically performing the following operations: if the number of failures of the LDPC soft decision decoding exceeds a first number N; then determining whether the number of LDPC hard decision decoding exceeds a second number M; if it does not exceed the second number M, then instructing to read updated hard bit data for the data stored in the storage device (S1000); receiving the updated LDPC hard decision decoding result and the updated hard decision decoding output of the LDPC hard decision decoding based on the updated hard bit data (S2000), and if the result of the updated LDPC hard decision decoding is a failure, then instructing to read second updated soft bit data associated with the updated hard bit data (S3000); and instructing to map the updated hard decision decoding output and the second updated soft bit data into second updated soft information for LDPC soft decision decoding (S4000).

[0124] It is understood that the determination of whether the number of times is exceeded can be performed in the result analyzer or in the host. The present invention is not limited to the entity in which it is performed.

[0125] It is also understood that the operations S1000-S4000 described above and the subsequent iterative loop method can be implemented solely in the result analysis device and / or the host, regardless of the soft information generator 10 and the LDPC decoder 20. In other words, the implementation of the above-mentioned operations S1000-S4000 and the subsequent iterative loop method does not depend on whether the soft information generator 10 and the LDPC decoder 20 exist. Those skilled in the art can implement the above-mentioned operations separately in the result analysis device and / or the host, and use them in different types of scenarios. The result analysis device can be implemented in various ways, such as software, hardware, firmware, and general / application-specific integrated circuits (ASICs).

[0126] Figure 9 Schematic block diagram of a device for generating LDPC soft information according to another aspect of the present invention is shown. Figure 9 As shown, the device of the present invention includes: a first device M10, used to instruct the reading of hard bit data for data stored in a storage device; a second device M20, used to receive the result of LDPC hard decision decoding based on the hard bit data and the hard decision decoding output; a third device M30, used to instruct the reading of soft bit data associated with the hard bit data in response to the result of the LDPC hard decision decoding being a failure; and a fourth device M40, used to instruct the mapping of the hard decision decoding output and the soft bit data into soft information for performing LDPC soft decision decoding.

[0127] The above-mentioned device can be implemented by software or by hardware, such as circuit, and the present invention does not limit the implementation method thereof.

[0128] According to another aspect of the present invention, Figure 10 As shown, a method for LDPC decoding is also provided, including: in operation S910, reading hard bit data for data stored in a storage device; in operation S920, performing LDPC hard decision decoding based on the hard bit data to obtain a result of LDPC hard decision decoding and a hard decision decoding output; if the result of the LDPC hard decision decoding is failure, then in operation S930, reading soft bit data associated with the hard bit data; in operation S940, mapping the hard decision decoding output and the soft bit data into soft information; in operation S950, performing LDPC soft decision decoding based on the soft information.

[0129] The above method can be implemented together in an integrated device including a soft information generator, an LDPC decoder and a control device, or can be implemented in the form of software in a device capable of running the software.

[0130] Figure 11 A flowchart of an LDPC decoding method according to an embodiment of the present invention is shown.

[0131] like Figure 11 As shown, first, in operation S910, hard bit data of data stored in the storage device is read. This reading action can be performed by the soft information generator 10 or the processing device 30. The reading here does not limit the specific execution entity.

[0132] Next, in operation S920, LDPC hard decision decoding is performed based on the hard bit data to obtain the result of LDPC hard decision decoding and the hard decision decoding output. Generally, this operation can be performed at the LDPC decoder. The result of LDPC hard decision decoding includes two situations: decoding success and decoding failure, and the hard decision decoding output includes the codeword after decoding success or the codeword output after failure. If successful, it is considered that the decoding of the stored data is successful, and this operation ends at this time. Figure 11 shown.

[0133] If the result of the LDPC hard decision decoding is failure, then in operation S930, the soft bit data associated with the hard bit data is read. Soft bits are always associated with specific hard bits, which has been described in detail above and will not be repeated here.

[0134] Furthermore, in operation S940, the hard decision decoding output and the soft bit data are mapped into soft information. In this case, the generated soft information includes the error codeword output by the hard decision decoding and the read soft bits.

[0135] Finally, in operation S950, LDPC soft decision decoding is performed based on the soft information.

[0136] like Figure 11 As shown, the LDPC decoding method further includes: if the result of the LDPC soft decision decoding is failure, then loopingly performing operations S930 to S950 until a specific condition is met.

[0137] Specifically, the method of the present invention further includes cyclically performing the following operations: if the result of the LDPC soft decision decoding is failure, determining whether the number of failures of the LDPC soft decision decoding exceeds the first number N; if it does not exceed the first number N; reading the first updated soft bit data associated with the hard bit data (S930); mapping the hard decision decoding output and the first updated soft bit data into first updated soft information (S940); and performing LDPC soft decision decoding based on the first updated soft information (S950).

[0138] According to one embodiment of the present invention, Figure 11 As shown, the method of the present invention further includes: cyclically performing the following operations: if the number of failures of the LDPC soft decision decoding exceeds a first number N; determining whether the number of LDPC hard decision decoding exceeds a second number M; if it does not exceed the second number M, reading updated hard bit data for the data stored in the storage device (S910); performing LDPC hard decision decoding based on the updated hard bit data to obtain an updated LDPC hard decision decoding result and an updated hard decision decoding output (S920); if the result of the updated LDPC hard decision decoding is a failure, reading second updated soft bit data associated with the updated hard bit data (S930); mapping the updated hard decision decoding output and the second updated soft bit data into second updated soft information (S940); and performing LDPC soft decision decoding based on the second updated soft information (S950).

[0139] Those skilled in the art will appreciate that the terms "first" and "second" are dynamic concepts. As hard bits are continuously updated and iterated, the original "second soft bit data" may be indicated as "first soft bit data" in the next cycle, while the newly read soft bit data may be referred to as "second soft bit data." The terms "first," "second," and "updated" in this disclosure are dynamic, not static, concepts.

[0140] After reading new soft bits based on the updated hard bits, the updated hard decision decoding output and the second updated soft bit data may be mapped into second updated soft information.

[0141] Then, LDPC soft decision decoding may be performed based on the second updated soft information.

[0142] It can be understood that if any of the above decoding attempts succeeds, the decoding is reported as successful, and the current run ends. However, if the number of decoding failures for the hard bits exceeds the second number M, it means that the probability of successful decoding is very low, and in this case, the decoding is reported as failed.

[0143] As can be seen from the above description, compared with the prior art, after decoding of soft information fails, the present invention does not immediately read a new hard bit. Instead, it reads soft bits multiple times based on the same hard bit data, combines the output obtained by hard decision decoding based on the hard bit data with the read-in new soft bits to form new soft information, and continuously decodes the newly generated soft information until the soft information still cannot be decoded after a certain number of times, at which time it reads a new hard bit.

[0144] LDPC is an iterative decoding algorithm. During the iteration process, a bit determines whether to change its value based on information transmitted by other bits. Therefore, each iteration results in a corrected codeword. After the iteration, the corrected codeword is verified to be legal. If it is, decoding is successful; otherwise, the next iteration begins until a preset maximum number of iterations is exceeded. One embodiment of the present invention utilizes soft information, composed of codewords obtained through hard decision decoding and newly read soft bits, for soft-decision decoding, resulting in a high soft-decoding success rate.

[0145] Figure 12 A schematic block diagram of a device for generating LDPC soft information according to another aspect of the present invention is shown.

[0146] like Figure 12 As shown, the device of the present invention includes: a first device M100, used to read hard bit data for data stored in a storage device; a second device M200, used to perform LDPC hard decision decoding based on the hard bit data to obtain the result of LDPC hard decision decoding and the hard decision decoding output; a third device M300, used to read soft bit data associated with the hard bit data if the result of the LDPC hard decision decoding is a failure; a fourth device M400, used to map the hard decision decoding output and the soft bit data into soft information; and a fifth device M500, used to perform LDPC soft decision decoding based on the soft information.

[0147] The above-mentioned device can be implemented by software or by hardware, such as circuit, and the present invention does not limit the implementation method thereof.

[0148] According to another aspect of the present invention, Figure 3 As shown, an LDPC decoding system is also provided, including: a soft information generator 10, an LDPC decoder 20 and a control device 30, wherein the soft information generator 10 is used to: store hard bit data and / or soft bit data for data stored in a storage device; receive at least a hard decision output from the LDPC decoder, and map the hard decision output and the soft bit into soft information.

[0149] The LDPC decoder 20 is used to perform LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision output, and / or perform LDPC soft decision decoding based on the soft information to obtain an LDPC soft decision decoding result.

[0150] The control device 30 is used to: instruct the reading of hard bit data for data stored in the storage device; receive the result and hard decision output of LDPC hard decision decoding based on the hard bit data, and in response to the result of the LDPC hard decision decoding being a failure, instruct the reading of soft bit data associated with the hard bit data; and instruct the mapping of the hard decision output and the soft bit data into soft information for use in LDPC soft decision decoding.

[0151] According to one embodiment of the present invention, the control device 30 is further used to cyclically perform the following operations: if the result of the LDPC soft decision decoding is a failure, determining whether the number of failures of the LDPC soft decision decoding exceeds a first number; if it does not exceed the first number; instructing to read the first updated soft bit data associated with the hard bit data; instructing to map the hard decision output and the first updated soft bit data into first updated soft information for LDPC soft decision decoding.

[0152] According to one embodiment of the present invention, it further includes cyclically performing the following operations: if the number of failures of the LDPC soft decision decoding exceeds a first number; determining whether the number of LDPC hard decision decoding exceeds a second number; if it does not exceed the second number, instructing to read the updated hard bit data for the data stored in the storage device; receiving the result of the updated LDPC hard decision decoding and the updated hard decision output of the LDPC hard decision decoding based on the updated hard bit data, and if the result of the updated LDPC hard decision decoding is a failure, instructing to read the second updated soft bit data associated with the updated hard bit data; instructing to map the updated hard decision output and the second updated soft bit data into second updated soft information for LDPC soft decision decoding.

[0153] The second updated soft bit data referred to herein refers to the soft bit data associated with the updated hard bit data. The term "second" is used to distinguish the updated soft bit data associated with the original hard bit data (i.e., the first updated soft bit data) for ease of understanding. Those skilled in the art will appreciate that the terms "first" and "second" are dynamic concepts. As the hard bits are continuously updated and iterated, the original "second soft bit data" may be referred to as the "first soft bit data" in the next cycle, while the newly read soft bit data may be referred to as the "second soft bit data." The terms "first," "second," and "updated" in this disclosure are dynamic, not static, concepts.

[0154] Figure 13 FIG. 1 shows a schematic diagram of performing LDPC decoding on memory read data according to an embodiment of the present invention. Figure 13 As shown, as an example, the bit sequence 1300 stored (written) in the NVM is a bit sequence of all 0s. When the bit sequence is read out from the NVM, due to the characteristics of the NVM itself, there may be some erroneous bits. The read bit sequence is called a hard bit (HB) sequence 1310. The hard bit (HB) sequence 1310 is hard-decision decoded to obtain a bit sequence 1320 output by the hard decision decoding. In the hard decision decoding, a hard decision decoding result indicating whether the hard decision decoding is successful or not is also output (not shown). Figure 13 In the example, the bit sequence 1320 output by the hard decision decoding is different from the bit sequence 1300 stored in the NVM. Accordingly, the hard decision decoding result is failure.

[0155] exist Figure 13In the example, in response to a hard decision decoding failure, the soft bit (SB) sequence SB0 1330 and the soft bit sequence SB1 1340 associated with the hard bit (HB) sequence 1310 are read from the NVM. The bit sequence 1320, the soft bit sequence 1330, and the soft bit sequence 1340 output by the hard decision decoding are mapped to soft information, and LDPC soft decoding is performed using the soft information. In one example, the corresponding bits of the bit sequence 1320, the soft bit sequence 1330, and the soft bit sequence 1340 output by the hard decision decoding are mapped to soft information.

[0156] like Figure 13 As shown, by the preferred embodiment of the present invention, compared with the prior art (see Figure 2 ), the present invention does not frequently read in hard bits again after hard decision decoding fails. Instead, it uses the bit sequence 1320 output by hard decision decoding and the soft bit sequence 1330 and soft bit sequence 1340 to generate soft information. And whenever the decoding of soft information fails, hard bits are no longer frequently read in. In the present invention, Figure 13 As shown, within a certain number of soft information decoding failures, there is no need to repeatedly read hard bits. After a soft decision decoding failure, only a new soft bit sequence 1330 and / or a new soft bit sequence 1340 need to be re-read. New hard bits are only re-read when the number of soft decision decoding failures exceeds a certain range. Therefore, the present invention can reduce the number of hard bit re-reads and improve throughput.

[0157] In addition, LDPC is an iterative decoding algorithm. During the iteration process, a bit will decide whether to change its value based on the information transmitted by other bits. Therefore, a corrected codeword will be obtained after one iteration. After the iteration, the corrected codeword will be checked to see if it is a legal codeword. If it is, the decoding is successful and the current run ends. Otherwise, the next iteration will start until the pre-set maximum number of iterations is exceeded.

[0158] Hard decisions have a certain probability of failing to decode correctly, but after multiple decoding iterations in the hard decision phase, the decoded codewords contain fewer erroneous bits. In other words, according to embodiments of the present invention, as the number of iterations increases, more codewords are corrected. In soft decision decoding, embodiments of the present invention utilize soft information, which is composed of codewords after hard decision decoding iterations and newly read soft bits, to improve the success rate of soft decoding.

[0159] According to one aspect of the present invention, the present invention also provides a computer program comprising computer program code, which, when loaded into a computer system and executed on the computer system, causes the computer system to perform the method described above.

[0160] According to another aspect of the present invention, there is also provided a program comprising program codes, which, when loaded into a storage device and executed on the storage device, causes the storage device to execute the method described above.

[0161] It should be understood that each block of the block diagrams and flowcharts, and combinations of blocks in the block diagrams and flowcharts, can be implemented by various means including computer program instructions. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data control device to produce a machine, so that the instructions executed on the computer or other programmable data control device create means for implementing the functions specified in one or more flowchart blocks.

[0162] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data-controlled device to function in a specific manner, so that the instructions stored in the computer-readable memory can be used to manufacture an article of manufacture comprising computer-readable instructions for implementing the functions specified in one or more flowchart blocks. The computer program instructions may also be loaded onto a computer or other programmable data-controlled device to cause a series of operational steps to be performed on the computer or other programmable data-controlled device, thereby producing a computer-implemented process, whereby the instructions executed on the computer or other programmable data-controlled device provide steps for implementing the functions specified in one or more flowchart blocks.

[0163] Thus, the blocks of the block diagrams and flow charts support combinations of means for performing the specified functions, combinations of steps for performing the specified functions, and combinations of program instruction means for performing the specified functions. It should also be understood that each block of the block diagrams and flow charts, and combinations of blocks of the block diagrams and flow charts, can be implemented by a hardware-based special-purpose computer system that performs the specified functions or steps, or by a combination of special-purpose hardware and computer instructions.

[0164] At least a portion of the various blocks, operations, and techniques described above may be implemented using hardware, a control device executing firmware instructions, a control device executing software instructions, or any combination thereof. When implemented using a control device executing firmware and software instructions, the software or firmware instructions may be stored on any computer-readable storage medium, such as a disk, optical disk, or other storage medium, in RAM, ROM, or flash memory, on a control device, on a hard disk, optical disk, or on a magnetic disk, etc. Similarly, the software and firmware instructions may be transmitted to a user or system via any known or desired transmission method, including, for example, on a computer-readable disk or other portable computer storage mechanism or via a communication medium. Communication media typically embodies computer-readable instructions, data structures, sequence modules, or other data in a modulated data signal, such as a carrier wave or other transmission mechanism. By way of example, and not limitation, communication media include wired media, such as a wired network or a single-wire connection, and wireless media, such as acoustic, radio frequency, infrared, and other wireless media. Thus, software and firmware instructions may be transmitted to a user or system via a communication channel, such as a telephone line, a DSL line, a cable television line, a fiber optic cable, a wireless channel, the Internet, or the like (providing such software via a portable storage medium is considered equivalent or interchangeable). The software or firmware instructions may include machine-readable instructions that, when executed by a control device, cause the control device to perform various actions.

[0165] When implemented in hardware, the hardware may include one or more discrete components, an integrated circuit, an application specific integrated circuit (ASIC), and the like.

[0166] It should be understood that the present invention can be implemented in pure software, pure hardware, firmware, or various combinations thereof. Hardware can be, for example, a control device, a dedicated integrated circuit, a large-scale integrated circuit, or the like.

[0167] Although the present invention has been described with reference to examples, this is for purposes of illustration only and not limitation, and changes, additions and / or deletions to the embodiments may be made without departing from the scope of the present invention.

[0168] Those skilled in the art to which these embodiments relate and who have benefited from the teachings presented in the above description and the associated drawings will recognize many modifications and other embodiments of the inventions described herein. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. An LDPC decoding method, comprising: Reading hard bit data for data stored in NVM; performing LDPC hard decision decoding on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output, wherein the hard decision decoding output refers to an output result after hard decision decoding is performed on the hard bit data; If the result of the LDPC hard decision decoding is failure, reading soft bit data associated with the hard bit data; Mapping the hard decision decoding output and the soft bit data into soft information; LDPC soft decision decoding is performed based on the soft information.

2. The method according to claim 1, further comprising cyclically performing the following operations: If the result of the LDPC soft decision decoding is failure, then Determining whether the number of failures of the LDPC soft decision decoding exceeds a first number; If the first number is not exceeded; but reading first updated soft bit data associated with the hard bit data; Mapping the hard decision decoding output and the first updated soft bit data into first updated soft information; LDPC soft decision decoding is performed based on the first updated soft information.

3. The method according to claim 2, further comprising: Perform the following operations in a loop: If the number of failures of the LDPC soft decision decoding exceeds the first number; but Determining whether the number of LDPC hard decision decodings exceeds a second number; If the second number is not exceeded, reading updated hard bit data for the data stored in the NVM; Perform LDPC hard decision decoding based on the updated hard bit data to obtain an updated LDPC hard decision decoding result and an updated hard decision decoding output. If the updated LDPC hard decision decoding result is a failure, then reading second updated soft bit data associated with the updated hard bit data; Mapping the updated hard decision decoding output and the second updated soft bit data into second updated soft information; LDPC soft decision decoding is performed based on the second updated soft information.

4. A method for LDPC decoding, comprising: The control device instructs reading hard bit data of data stored in the NVM; A soft information generator stores the hard bit data; The LDPC decoder performs LDPC hard decision decoding based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output; wherein the hard decision decoding output refers to an output result after hard decision decoding of the hard bit data; The control device receives, from the LDPC decoder, a result of LDPC hard decision decoding performed based on the hard bit data and a hard decision decoding output; In response to a result of the LDPC hard decision decoding being a failure, the control device instructs reading soft bit data associated with the hard bit data; The soft information generator receives at least a hard decision decoding output from the LDPC decoder and maps the hard decision decoding output and the soft bits into soft information; The LDPC decoder performs LDPC soft decision decoding based on the soft information to obtain a result of LDPC soft decision decoding, and sends the result of LDPC soft decision decoding to the control device.

5. The method according to claim 4, further comprising cyclically performing the following operations: If the result of the LDPC soft decision decoding is failure, the control device determines whether the number of failures of the LDPC soft decision decoding exceeds a first number; If the first number of times is not exceeded, the control device instructs reading the first updated soft bit data associated with the hard bit data; The soft information generator maps the hard decision decoding output and the first updated soft bit data into first updated soft information; and the LDPC decoder performs LDPC soft decision decoding on the first updated soft information.

6. The method according to claim 4 or 5, further comprising cyclically performing the following operations: If the control device determines that the number of failures of the LDPC soft decision decoding exceeds a first number, the control device determines whether the number of failures of the LDPC hard decision decoding exceeds a second number. If the second number of times is not exceeded, the control device instructs reading updated hard bit data for the data stored in the NVM; The LDPC decoder performs LDPC hard decision decoding based on the updated hard bit data to obtain an updated LDPC hard decision decoding result and an updated hard decision decoding output. If the control device determines that the result of the updated LDPC hard decision decoding is a failure, the control device instructs reading second updated soft bit data associated with the updated hard bit data; The soft information generator maps the updated hard decision decoding output and the second updated soft bit data into second updated soft information; The LDPC decoder performs LDPC soft decision decoding based on the second updated soft information.

7. An LDPC decoding system, comprising: Soft information generator, LDPC decoder and control device, wherein, The soft information generator is coupled to the control device and the LDPC decoder, stores and outputs to the LDPC decoder an instruction for the control device to read hard bit data corresponding to the data stored in the NVM; The LDPC decoder is further coupled to the control device and outputs to the control device LDPC hard decision decoding performed based on the hard bit data to obtain an LDPC hard decision decoding result and a hard decision decoding output; wherein the hard decision decoding output refers to an output result after hard decision decoding of the hard bit data; In response to a result of the LDPC hard decision decoding being a failure, the control device instructs a read of soft bit data associated with the hard bit data, and instructs a soft information generator to store and output the soft bit data to the LDPC decoder; The soft information generator receives at least a hard decision decoding output, maps the hard decision decoding output and the soft bits into soft information, and outputs the soft information to the LDPC decoder; The LDPC decoder performs LDPC soft decision decoding according to the soft information to obtain a result of the LDPC soft decision decoding, and sends the result of the LDPC soft decision decoding to the control device.

8. The system according to claim 7, wherein the control device is further configured to cyclically perform the following operations: If the result of the LDPC soft decision decoding is failure, determining whether the number of failures of the LDPC soft decision decoding exceeds a first number; If the number of times does not exceed the first number, instructing to read the first updated soft bit data associated with the hard bit data; Instructing to map the hard decision decoding output and the first updated soft bit data into first updated soft information for performing LDPC soft decision decoding.

9. The system according to claim 7 or 8, further comprising cyclically performing the following operations: If the number of failures of the LDPC soft decision decoding exceeds the first number, determining whether the number of failures of the LDPC hard decision decoding exceeds the second number; If the second number of times is not exceeded, instructing to read updated hard bit data for the data stored in the NVM; receiving an updated LDPC hard decision decoding result and an updated hard decision decoding output of LDPC hard decision decoding performed based on the updated hard bit data, and instructing to read second updated soft bit data associated with the updated hard bit data if the result of the updated LDPC hard decision decoding is a failure; Instructing to map the updated hard decision decoding output and the second updated soft bit data into second updated soft information for performing LDPC soft decision decoding.

10. An LDPC decoding device, comprising: Soft information generator, decoder and control device, wherein, The soft information generator is coupled to the control device and the decoder, and the decoder is also coupled to the control device; The control device instructs the hard bit data of the stored data to be read from the NVM, and instructs the hard bit data to be stored in the soft information generator; The decoder receives the hard bit data output by the soft information generator, performs LDPC hard decision decoding on the hard bit data, obtains an LDPC hard decision decoding result and a hard decision decoding output, and transmits the LDPC hard decision decoding result and the hard decision decoding output to the control device; wherein the hard decision decoding output refers to an output result after hard decision decoding the hard bit data; The control device determines whether hard decision decoding fails according to a result of the LDPC hard decision decoding, and if so, instructs reading soft bit data associated with the hard bit data from the NVM, and instructs storing the soft bit data in a soft information generator; The soft information generator receives at least a hard decision decoding output from the control device and / or the decoder, maps the hard decision decoding output and the soft bits into soft information, and outputs the soft information to the decoder; The decoder performs LDPC soft decision decoding according to the soft information to obtain a result of the LDPC soft decision decoding, and sends the result of the LDPC soft decision decoding to the control device.

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