Method for classifying comparators based on comparator bias

Abstract

Various embodiments relate to classifying a comparator (100) based on comparator bias. A method may include applying a first voltage to each of a first input terminal (Inp) and a second input terminal (Inn) of a comparator via a strobe pulse (M5 gate) to generate a plurality of output signals (Out) from the comparator, wherein each output signal has one of a first polarity and a second polarity. The method may also include, in response to each of the plurality of output signals being of the first polarity, applying an external bias voltage (Vinp at Inp, Vinn at Inn) having a second polarity to the comparator via a strobe pulse to generate a second number of output signals. In addition, the method may include identifying the comparator as a reliable comparator in response to each of the second number of output signals having the same polarity.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62 / 786,015, filed on December 28, 2018, and entitled “METHODS OF CLASSIFING COMPARATORS BASED ON COMPARATOR OFFSETS” (the “015 Provisional Application”), and claims the benefit of the filing date of co-pending U.S. Patent Application Serial No. 16 / 294,467, filed on March 6, 2019, and entitled “CLASSIFYING COMPARATORS BASED ON COMPARATOR OFFSETS,” the disclosures of each of which are hereby incorporated by reference herein in their entireties. Technical Field

[0003] The present disclosure relates generally to classifying comparators based on comparator bias, and more particularly, to identifying comparators with suitable bias for reliable key generation. Background Art

[0004] A Physical Unclonable Function (PUF) can be used as a unique physical identifier in a physical structure (e.g., a semiconductor device such as a microprocessor). A PUF based on physical variations that can occur naturally during the semiconductor manufacturing process can allow for differentiation between otherwise identical semiconductor devices. Because semiconductor devices can be slightly different, the operation of the semiconductor device (e.g., the output generated by the semiconductor device) can vary. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] While the present disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0006] Figure 1 depicts a comparator circuit according to one or more embodiments of the present disclosure;

[0007] Figure 2 and Figure 3 is a graph for depicting a statistical distribution of comparator input bias according to one or more embodiments of the present disclosure;

[0008] Figure 4 is a flow chart of an exemplary method of identifying a comparator having a suitable input bias for key generation;

[0009] Figure 5 is an exemplary circuit for generating an external bias voltage according to various embodiments of the present disclosure;

[0010] Figure 6 is an exemplary circuit diagram including a comparator coupled to a resistor string according to one or more embodiments of the present disclosure;

[0011] Figure 7 is a block diagram of an exemplary system according to one or more embodiments of the present disclosure; and

[0012] Figure 8 is a block diagram of an exemplary computing system. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of example specific examples of embodiments in which the present disclosure may be implemented. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0014] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations for describing embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structures or components must be identical in size, composition, configuration, or any other attribute.

[0015] The following description may include examples to help those skilled in the art practice the embodiments disclosed in the present invention. The use of the terms "exemplary", "by way of example" and "for example" means that the relevant description is illustrative, and although the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the embodiments or the present disclosure to the specified components, steps, features or functions, etc.

[0016] It should be readily understood that the components of the embodiments as generally described herein and shown in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0017] In addition, the specific embodiments shown and described are examples only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific embodiments shown and described are exemplary only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the partitioning of logic between block definitions and individual blocks is an example of a specific embodiment. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0018] Those of ordinary skill in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals. For clarity of presentation and description, some figures may show signals as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0019] The various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or implemented with a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof designed to implement the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer when the general-purpose computer is configured to execute computing instructions (e.g., software code) associated with the embodiments disclosed herein.

[0020] Embodiments can be described according to processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts can describe operational actions as sequential processes, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of actions can be rearranged. Processes can correspond to methods, threads, functions, programs, subroutines, subprograms, etc. In addition, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, these functions can be stored or transmitted to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, and the communication media include any media that is conducive to transferring a computer program from one location to another.

[0021] Unless such limitations are explicitly stated, any reference to elements herein using names such as "first," "second," etc. does not limit the number or order of those elements. Instead, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements can be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0022] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0023] Although the manufacturing process may be the same for a variety of devices (e.g., integrated circuits (ICs)), each device may be slightly different due to normal manufacturing variations. More specifically, one or more physical properties of a device may vary from device to device due to the manufacturing process. One or more different physical properties of a device (e.g., an IC) that vary between different devices due to the manufacturing process may be considered a physical unclonable function (PUF) of the device (e.g., if it can be used to generate an electrical function that reflects the variation). Since the devices may be slightly different, the operation of the device (e.g., the output generated by the device) may be different. More specifically, for example, the outputs of various comparator ICs (e.g., the output value of a given output) may vary based on the PUF of the comparator IC. For example, some comparators may have a relatively large input bias, and some comparators may have a relatively small input bias. A comparator with a relatively small bias may have an output that changes polarity due to, for example, noise and / or bias drift (e.g., due to changes in temperature and / or supply voltage). A comparator with a relatively large bias may be more tolerant to noise and bias drift. In other words, a comparator with a relatively large offset may have a more stable output (eg, the output may not change due to noise and offset drift).

[0024] Various embodiments described herein relate to classifying comparators based on comparator bias, and more particularly, to methods of identifying comparators that include suitable biases (e.g., for reliable key generation). More specifically, some embodiments may relate to classifying and identifying comparators for reliable key generation (e.g., PUF key generation) based on the bias values ​​of the comparators, and using the identified comparators to generate reliable keys.

[0025] In order to utilize comparators for key generation (e.g., where each comparator generates one or more bits for a multi-bit key), it may be advantageous for each comparator unit on each integrated circuit to be repeatable. Thus, in some embodiments utilizing comparators for key generation, the comparator output should be the same over the life of the comparator and under all operating conditions (e.g., variations in noise, temperature, and / or supply voltage). Therefore, for key generation, it may be advantageous to utilize comparators with relatively large offsets.

[0026] Instead of measuring the actual precise bias value of each comparator (e.g., by detecting when the comparator output switches), various embodiments disclosed herein identify comparators with sufficient bias via one or more tests. It may not be necessary to measure the actual precise bias value of the comparator. According to some embodiments, during a test phase (e.g., the first test phase), the comparator may be tested by gating the comparator multiple times with two identical inputs (e.g., two inputs tied together). If the polarity of the output of the comparator does not remain the same for each gating, it can be determined that the bias of the comparator is too small, so the output of the comparator may be affected by noise. In these embodiments, comparators with too small bias can be rejected, and the remaining comparators can be grouped (e.g., two groups) according to the comparator output (e.g., comparators with positive output bias (e.g., output with positive polarity) can be divided into one group (e.g., "group 1"), and comparators with negative output bias (e.g., output with negative polarity) can be divided into another group (e.g., "group 2")).

[0027] In addition, the remaining comparators can be tested. More specifically, during another test phase (e.g., a second test phase), an external bias voltage can be provided to each of the remaining comparators. According to some embodiments, the external bias voltage applied to the comparator (i.e., at the input of the comparator) may have a known absolute value and a polarity opposite to the polarity of the bias of the comparator. For example, if the comparator has a positive bias (e.g., in group "1"), a negative external bias voltage can be provided to the comparator. If the comparator has a negative bias (e.g., in group "2"), a positive external bias voltage can be provided to the comparator. The external bias voltage can be determined based on one or more factors. For example, according to some embodiments, the external bias voltage can be selected based on comparator noise, bias drift with temperature, supply voltage and / or time. More specifically, for example, the sum of these parameters can be used to determine the external test voltage.

[0028] In some embodiments, the comparator can be gated multiple times with an external bias voltage. If the polarity of the comparator output does not remain the same as before, or does not remain the same for each gate, the comparator can be rejected. Otherwise, a comparator with an output that remains the same as before and for each gate can be identified as a reliable comparator and can be used as a PUF comparator unit (e.g., in key generation).

[0029] In some embodiments, the absolute value of the bias of the remaining comparators may be equal to or greater than the predefined external bias voltage. In addition, in some embodiments, if the comparator noise and bias drift can be determined empirically (e.g., over temperature, supply voltage, and time), the sum of these parameters can be used as an external test voltage for comparator classification, which can ensure the repeatability of the comparator.

[0030] According to various embodiments, one or more test phases may be used to classify a comparator. For example, in some embodiments, a comparator may be classified as reliable or unreliable based on a first test phase (e.g., where the inputs of the comparators receive the same signal (e.g., the inputs are tied together)) or a second test phase (e.g., where the inputs of the comparators receive a bias voltage). In other embodiments, a comparator may be classified as reliable or unreliable based on more than one test phase (e.g., a first test phase and a second test phase).

[0031] Various embodiments disclosed herein can improve comparator classification. In addition, comparators with relatively high repeatability can be used to generate reliable bits in key generation, thereby improving key generation (e.g., for encryption and decryption). Due to at least these reasons, as described more fully herein, various embodiments of the present disclosure provide technical solutions to one or more problems caused by technologies that cannot be reasonably performed by humans, and various embodiments disclosed herein are rooted in computer technology to overcome the above-mentioned problems and / or challenges. In addition, at least some embodiments disclosed herein can improve computer-related technologies by allowing computers to perform functions that were previously not executable by computers.

[0032] Various embodiments of the present disclosure will now be explained with reference to the drawings.

[0033] Figure 1 An exemplary comparator circuit 100 according to one or more embodiments of the present disclosure is depicted. The comparator circuit 100 includes differential input terminals Inp and Inn, a plurality of switches (e.g., transistors M1-M8), a cross-coupled NAND gate configured as an SR flip-flop, and an output terminal Out. During the envisioned operation, the output signal generated at the output terminal Out may be based on a signal received from the input terminal Inp and a signal received from the input terminal Inn. As will be appreciated by those of ordinary skill in the art, noise, bias, and / or bias drift may affect the output signal. According to various embodiments, depending on the test phase, the input terminal Inp and the input terminal Inn may or may not be configured to receive the same input. More specifically, in one test phase, the input terminal Inp and the input terminal Inn may receive the same input (e.g., the input terminal Inp and the input terminal Inn may be tied together). In another test phase, the input terminal Inp and the input terminal Inn may be configured to receive different signals (e.g., a bias voltage may be applied to the input terminal). The comparator circuit 100 is provided as an exemplary comparator circuit, and the present disclosure is not limited to any particular comparator circuit.

[0034] Figure 22 is a graph 200, which includes region 202 (i.e., to the right of the Y axis; labeled "1") and region 204 (i.e., to the left of the Y axis; labeled "0"). According to some embodiments, a comparator with a positive input bias may be represented on the right side of the Y axis (e.g., in region 202), and a comparator with a negative input bias may be represented on the left side of the Y axis (e.g., in region 204). In addition, the greater the bias of the comparator, the farther the bias is from the Y axis. For example, the bias of a comparator with a 2x bias may be farther from the Y axis than a comparator with a 1x bias. Comparators with biases positioned between dashed lines 206 and 208 have relatively low biases, so the outputs of these comparators may be susceptible to noise and / or bias drift.

[0035] As described above, according to some embodiments, a comparator may be tested by strobing the comparator multiple times with the same input (eg, the two inputs of the comparator are tied together). Figure 1 , multiple strobe pulses may be applied to the gate of the M5 gate while an input (e.g., a voltage) may be applied to each of the input terminals Inp and Inn. If the polarity of the output of the comparator does not remain the same for each strobe, it may be determined that the bias of the comparator is too small (e.g., the output is between dashed lines 206 and 208), and therefore the output of the comparator may be affected by noise or other phenomena that cause bias drift. Note that in at least some embodiments, the strobing and output signal values ​​may occur sequentially. In other words, an output signal value is generated in response to each input strobing.

[0036] In these embodiments, comparators with too little offset may be rejected (e.g., as unreliable), and the remaining comparators may be grouped (e.g., into two groups) based on the comparator output. For example, comparators with positive offset outputs may be grouped in one group (e.g., "Group 1"), and comparators with negative offset outputs may be grouped in another group (e.g., "Group 2").

[0037] In addition, the remaining comparators (e.g., comparators in group 1 and group 2) may be further tested. More specifically, an external bias voltage may be provided to each of the remaining comparators. The external bias voltage applied to the comparator (i.e., at its input terminal) may have a polarity opposite to the polarity of the bias of the comparator. For example, if the comparator has a positive bias (e.g., in group "1"), a negative external bias voltage may be provided to the comparator (e.g., the potential at the input terminal Inp of the comparator is negative relative to the potential at the input terminal Inn of the comparator). If the comparator has a negative bias (e.g., in group "2"), a positive external bias voltage may be provided to the comparator (e.g., the potential at the input terminal Inp of the comparator is positive relative to the potential at the input terminal Inn of the comparator). The absolute value of the applied bias voltage may be selected so as to be within a predetermined range suitable for PUF generation.

[0038] In some embodiments, each comparator can be gated multiple times with an external bias voltage. Figure 1 , multiple strobe pulses may be applied to the gate of the gate of transistor M5, while an external voltage may be applied to the input terminal Inp / Inn. If the output of the comparator changes polarity (e.g., a negative bias is applied to the comparator in group 1 or a positive bias is applied to the comparator in group 2), the amplitude of the bias of the comparator may be less than the amplitude of the external bias voltage, so the bias of the comparator may be too small and the comparator may be rejected (e.g., as unreliable). In other words, if the polarity of the comparator output does not remain the same as before (e.g., as determined via a previous test) or does not remain the same for each strobe, the comparator may be rejected. Otherwise, a comparator with an output that maintains the same polarity for each strobe may be identified as a reliable comparator (e.g., having a suitable bias for reliable key generation). According to some embodiments, a reliable comparator may be used as a PUF comparator unit (e.g., in key generation).

[0039] refer to Figure 3 , which shows a graph 300, i.e., the polarity of the output of a comparator having an input bias positioned between lines 310 and 312 (e.g., at point A or point B), after an external bias voltage is applied to the comparator input, may not remain the same as before (e.g., as determined via a previous test), or may not remain the same for each strobe, and thus the comparator generating this output may be rejected. On the other hand, the polarity of the output to the left of line 312 (region 304) or to the right of line 310 (region 302, e.g., at point C) may remain the same as before and for each strobe, and thus the comparator generating this output may be identified as a reliable comparator (e.g., which may be used as a comparator unit in key generation).

[0040] Figure 44 is a flow chart of an exemplary method 400 for identifying a comparator with a suitable bias for key generation. The method 400 can be arranged according to at least one embodiment described in the present disclosure. In some embodiments, the method 400 can be performed by a device or system, such as the circuit 100 (see Figure 1 ), circuit 500 (see Figure 5 ), circuit 600 (see Figure 6 ), System 800 (see Figure 8 ), one or more components of a device or system, or another system or device. In these and other embodiments, the method 400 may be performed based on the execution of instructions stored on one or more non-transitory computer-readable media. Although shown as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0041] The method 400 may begin at block 402, where a first voltage may be applied to each of a first input and a second input of a comparator (e.g., via multiple strobing) to generate a plurality of output signals from the comparator, and the method 400 may proceed to block 404. For example, each output signal may have one of a first polarity (e.g., positive bias) and a second polarity (e.g., negative bias).

[0042] At block 404, in response to each of the plurality of output signals being of the first polarity, an external bias voltage may be applied to the comparator (e.g., via a plurality of strobes) to generate a second number of output signals from the comparator, and the method 400 may proceed to block 406. For example, a first voltage may be applied to a first input terminal, and a second voltage may be applied to a second input terminal (e.g., a plurality of times) to generate a second number of output signals from the comparator, wherein a difference between the first voltage and the second voltage may be equal to the external bias voltage having the second polarity.

[0043] At block 406 , in response to each of the second number of output signals having the same polarity, the comparator may be identified as a reliable comparator.

[0044] Without departing from the scope of the present disclosure, method 400 may be modified, added or omitted. For example, the operations of method 400 may be implemented in different orders. In addition, the operations and actions outlined are provided only as examples, and some of the operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without departing from the essence of the disclosed embodiments. For example, a reliable comparator may be used to generate a key that may be used for data encryption and / or data decryption. More specifically, a reliable comparator may be used as a unit for generating one or more bits of a multi-bit key, as further described below.

[0045] Figure 5 An exemplary circuit 500 for generating an external bias voltage is shown. The circuit 500, which may also be referred to as a "resistor string", may include a plurality of switches (e.g., transistors M10-M13), a plurality of resistors R1-R3, and output terminals out1 and out2. In some embodiments, the output terminals out1 and out2 may be coupled to a comparator (e.g., Figure 1 For example, the output terminal out1 may be coupled to one input terminal of the comparator, and the output terminal out2 may be coupled to another input terminal of the comparator.

[0046] In addition, depending on the configuration of transistors M10-M13, output terminals out1 and out2 may be coupled together or may not be coupled together. Therefore, according to at least some embodiments, transistors M10-M13 may be configured so that output terminals out1 and out2 may be coupled together during one stage of the comparator test process (e.g., by turning on both transistors M10 and M12, or both transistors M11 and M13), as described herein. In this example, output terminals out1 and out2 may output a first voltage (e.g., provided to two inputs of the comparator). In addition, transistors M10-M13 may be configured so that output terminals out1 and out2 are not coupled together during another stage of the comparator test process, also as described herein (e.g., by turning on transistors M10 and M13 while setting transistors M11 and M12 to disconnect, or by turning on transistors M11 and M12 while setting transistors M10 and M13 to disconnect). In this example, the output terminal out1 can output a first voltage (e.g., provided to one input of a comparator), and out2 can output a second voltage (e.g., provided to another input of the comparator). Circuit 500 is provided as an example of a circuit for generating an external bias voltage, and other circuits for generating bias voltages are within the scope of the present disclosure. According to various embodiments, the controller 510 can be configured to control the configuration of transistors M10-M13 (e.g., via one or more control signals).

[0047] Figure 6 602 (eg, Figure 1 comparator 100), resistor string 604 (eg, Figure 5 circuit 500) and controller 610 (eg, Figure 5 6. As depicted, the output of resistor string 604 is coupled to the input of comparator 602. System 600 is provided as an example system including a comparator and a resistor string, and other systems and / or devices including a resistor string coupled to a comparator are within the scope of the present disclosure.

[0048] Figure 7 An exemplary system 700 according to various embodiments of the present disclosure is shown. The system 700, which can be configured to encrypt data and decrypt data (e.g., a password), includes an encryption module 702, a key generation module 704, and a decryption module 706. For example, the key generation module 704 may include one or more comparators for generating a key that can be used to encrypt data and / or decrypt data. More specifically, each comparator of the key generation module 704 may be configured to generate one or more bits of a multi-bit key. In addition, according to one or more embodiments disclosed herein, one or more comparators of the key generation module 704 may be identified as reliable comparators.

[0049] Figure 8 An exemplary system 800 according to at least one embodiment described herein is shown. The system 800 may include any suitable system, device, or apparatus configured to classify comparators. The system 800 may include a processor 810, a memory 820, a data store 830, and a communication device 840, all of which may be communicatively coupled. The data store 830 may include various types of data, such as bias polarity of one or more comparators, test information (e.g., associated with one or more comparators), reliability information (e.g., associated with one or more comparators), or any other information related to classifying comparators based on comparator bias.

[0050] Generally speaking, the processor 810 may include any suitable special or general-purpose computer, computing entity, or processing device including various computer hardware or software modules, and may be configured to execute instructions stored on any applicable computer-readable storage medium. For example, the processor 810 may include a microprocessor, a microcontroller, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other digital circuit or analog circuit configured to interpret and / or execute program instructions and / or process data.

[0051] Despite Figure 8 820, data storage 830, or both. In some embodiments, the processor 810 may retrieve program instructions from the data storage 830 and load the program instructions into the memory 820. In one embodiment, instructions for executing the method 400 may be stored in the memory 820 and executed by the processor 810.

[0052] After the program instructions are loaded into the memory 820, the processor 810 can execute the program instructions, such as instructions for executing one or more frames of the method 200 and / or method 300 as described herein. According to various embodiments, the processor 810 can perform one or more test operations. For example, the processor 810 can apply a first voltage to each input of the comparator and process the first output generated by the comparator. In addition, the processor 810 can identify the comparator as an unreliable comparator based on the first output. In addition, the processor 810 can apply a bias voltage to the comparator and process the second output generated by the comparator. In addition, based on the second output, the processor 810 can identify the comparator as a reliable comparator or an unreliable comparator.

[0053] Memory 820 and data storage 830 may include computer-readable storage media or one or more computer-readable storage media for carrying or having computer-executable instructions or data structures stored thereon. Such computer-readable storage media may be any available media that can be accessed by a general or special purpose computer (such as processor 810).

[0054] By way of example and not limitation, such computer-readable storage media may include non-transitory computer-readable storage media, including random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory devices (e.g., solid-state memory devices), or any other storage medium that can be used to carry or store computer-executable instructions or required program code in the form of data structures and can be accessed by general or special-purpose computers. Combinations of the above may also be included within the scope of computer-readable storage media. Computer-executable instructions may include, for example, instructions and data configured to cause the processor 810 to perform a specific operation or a set of operations.

[0055] The communication unit 840 may include any component, device, system, or combination thereof configured to transmit or receive information over a network. In some embodiments, the communication unit 840 may communicate with other devices at other locations, the same location, or even other components within the same system. For example, the communication unit 840 may include a modem, a network card (wireless or wired), an infrared communication device, a wireless communication device (such as an antenna), and / or a chipset (such as a Bluetooth device, an 802.6 device (e.g., a metropolitan area network (MAN), a WiFi device, a WiMax device, a cellular communication facility, etc.), etc. The communication unit 840 may allow data to be exchanged with a network and / or any other device or system described in the present disclosure. For example, the communication unit 840 may allow the system 800 to communicate with other systems and / or devices.

[0056] Without departing from the scope of the present disclosure, modifications, additions, or omissions may be made to the system 800. For example, the data store 830 may be a plurality of different storage media located in a plurality of locations and accessed by the processor 810 over a network.

[0057] As mentioned above, the embodiments described herein may include the use of a special purpose or general purpose computer (e.g., Figure 8 processor 810, as discussed in more detail below. In addition, as described above, the embodiments described herein may use computer-readable media (e.g., Figure 8 The memory 820 or the data storage device 830 is implemented.

[0058] Various embodiments relate to methods for classifying comparators. For example, the method may include gating the comparator multiple times with a bias voltage to generate multiple output signals from the comparator. In addition, in response to each of the multiple output signals having the same polarity, the comparator is identified as a reliable comparator.

[0059] According to one or more other embodiments, the method may include applying a first voltage to each of a first input terminal and a second input terminal of a comparator (e.g., via multiple gating) to generate a plurality of output signals from the comparator. Each output signal may include one of a first polarity and a second polarity. In addition, the method may include applying a bias voltage having a second polarity to the comparator (e.g., via multiple gating) to generate a second number of output signals in response to each of the plurality of output signals being of the first polarity. In addition, the method may include identifying the comparator as a reliable comparator in response to each of the second number of output signals having the same polarity.

[0060] In one or more other embodiments, the method may include, for each of a plurality of comparators, gating the comparator with a first voltage at each of a first input and a second input of the comparator to generate a plurality of output signals from the comparator, each output signal having one of a first polarity and a second polarity. In addition, the method may include gating the comparator with an external bias voltage having a second polarity in response to each of the plurality of output signals having a first polarity to generate a second number of output signals from the comparator. In addition, the method may include identifying the comparator as a reliable comparator in response to each of the second number of output signals having a first polarity. The method may also include generating a key via a plurality of reliable comparators.

[0061] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general hardware of a computing system (e.g., a computer-readable medium, a processing device, etc.). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general hardware), specific hardware implementations or combinations of software and specific hardware implementations are possible and contemplated.

[0062] The terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims), are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “comprising” should be interpreted as “including but not limited to,” etc.).

[0063] Additionally, if a specific number of an introduced claim recitation is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more"); this is also true of the use of definite articles used to introduce claim recitations.

[0064] Furthermore, even if a particular number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the basic recitation of "two recitations" in the absence of other modifiers means at least two recitations or two or more recitations). Furthermore, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three of A, B, and C, etc.

[0065] In addition, any discrete word or phrase presenting two or more additional terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, either of the two terms, or both of the two terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0066] Although the present invention is described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated embodiments and the described embodiments without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features of another embodiment while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A method for classifying comparators based on comparator bias, comprising: gating the comparator with a first input voltage at each of a first input and a second input of the comparator to generate a plurality of output signals from the comparator; In response to the generated plurality of output signals all having the same polarity, gating the comparator a plurality of times with an external bias voltage to generate another number of output signals from the comparator, the external bias voltage having a polarity opposite to that of the plurality of output signals; as well as In response to each of the another number of output signals having and maintaining the same polarity as the plurality of output signals, the comparator is identified as a reliable comparator. 2 . The method of claim 1 , further comprising identifying the comparator as an unreliable comparator in response to each of the plurality of output signals having a different polarity. 3 . The method of claim 1 , wherein the external bias voltage has a polarity opposite to a polarity of the another number of output signals. The method of claim 1 , further comprising generating a key via the trusted comparator. The method of claim 4 , wherein generating the key comprises generating at least one bit of the key via the reliable comparator.

6. The method of claim 4, further comprising at least one of encrypting data and decrypting data using the key.

7. A method for classifying comparators based on comparator bias, comprising: applying a first voltage to each of a first input terminal and a second input terminal of a comparator via a strobe pulse to generate a plurality of output signals from the comparator, each output signal having one of a first polarity and a second polarity; In response to each of the plurality of output signals being of the first polarity, applying an external bias voltage having the second polarity to the comparator via a strobe pulse to generate a second number of output signals, the second polarity being opposite to the first polarity of the plurality of output signals; as well as In response to each of the second number of output signals having a same polarity and maintaining a same polarity as the plurality of output signals, the comparator is identified as a reliable comparator.

8. The method of claim 7 , wherein applying the external bias voltage comprises applying the first voltage to the first input of the comparator and applying a second voltage to the second input to generate the second number of output signals from the comparator, the difference between the first voltage and the second voltage comprising a voltage equal to the external bias voltage. 9 . The method of claim 8 , further comprising generating each of the first voltage and the second voltage via a voltage generating circuit, the voltage generating circuit comprising a plurality of switches, a plurality of resistors, and a plurality of output terminals.

10. The method of claim 7, further comprising at least one of encrypting data and decrypting data with the reliable comparator. The method of claim 7 , further comprising generating the first voltage via a resistor string. 12 . The method of claim 11 , further comprising generating the external bias voltage via the resistor string. 13 . The method of claim 11 , wherein generating the external bias voltage comprises generating a second voltage via the resistor string, a difference between the first voltage and the second voltage comprising the external bias voltage. 14 . The method of claim 13 , wherein applying the external bias voltage to the comparator comprises applying the first voltage to the first input of the comparator and applying the second voltage to the second input of the comparator.

15. A method for classifying comparators based on comparator bias for reliable key generation, the method comprising: For each comparator in the multiple comparators: gating the comparator with a first voltage at each of a first input and a second input of the comparator to generate a plurality of output signals from the comparator, each output signal having one of a first polarity and a second polarity; in response to each of the plurality of output signals having the first polarity, gating the comparator with an external bias voltage having the second polarity to generate a second number of output signals from the comparator, the second polarity being opposite to the first polarity of the plurality of output signals; as well as identifying the comparator as a reliable comparator in response to each of the second number of output signals having the first polarity; as well as The key is generated via multiple reliable comparators.

16. The method of claim 15, wherein generating the key comprises generating the key comprising a plurality of bits, each bit of the plurality of bits being generated via one of the plurality of reliable comparators.

17. The method of claim 15, further comprising at least one of encrypting data and decrypting the data using the key.

18. A method for classifying comparators based on comparator bias, comprising: applying a first voltage a plurality of times to each of a first input and a second input of a comparator to generate a first number of output signals from the comparator; in response to the first number of output signals being all positive or all negative, applying the first voltage to the first input terminal a plurality of times and applying a second voltage to the second input terminal to generate a second number of output signals from the comparator, the difference between the first voltage and the second voltage comprising an external bias voltage, the external bias voltage having a negative value if each of the first number of output signals has a positive value, and the external bias voltage having a positive value if each of the first number of output signals has a negative value; as well as The comparator is identified as a reliable comparator in response to each of the second number of output signals being positive or negative and maintaining the same value as the first number of output signals.

19. The method of claim 18, further comprising generating one or more bits of a multi-bit encryption key via the reliable comparator.

Images