Configurable data paths for memory blocks

Abstract

Systems and methods are described for enabling a memory device integrated in a memory module or system to disable one or more data bits, nibbles, or bytes of the memory device. The memory device may be further configured to disable error or redundancy checking associated with the disabled data bits, nibbles, or bytes, to mask errors associated with the disabled data bits, nibbles, or bytes, and / or to inhibit refresh of a memory array portion associated with the disabled data bits, nibbles, or bytes.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 787,039, filed on December 31, 2018; the entirety of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to semiconductor memory devices, and more particularly to systems and methods for configurable data paths for memory modules or systems in which the memory is used. Background Art

[0004] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, etc. Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc., may require an external power supply to maintain its data. In contrast, non-volatile memory can retain its stored data even without external power supply. Non-volatile memory can be used in a variety of technologies, including flash memory (e.g., NAND and NOR), phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), etc. Improving memory devices may generally include increasing memory cell density, increasing read / write speeds or otherwise reducing operation latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other criteria. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a representative block diagram schematically illustrating a memory device.

[0006] Figure 2 is a representative block diagram schematically illustrating a configurable data path for a memory module.

[0007] Figure 3 is a representative block diagram schematically illustrating a channel of a x16 memory device integrated in a memory module.

[0008] Figure 4 and 5 is a representative flow chart illustrating a method for disabling nibbles of a memory device integrated in a memory module. DETAILED DESCRIPTION

[0009] Data paths that can transfer multiple bits in parallel are often used to facilitate rapid transfer of information into and out of a memory device. By integrating multiple such memory devices into a memory package, memory module, etc., a wide data bus (e.g., where the number of bits is equal to the sum of the widths of the data paths of each of the constituent memory devices) can be provided. Some memory modules and / or memory packages may be restricted (e.g., by manufacturing or industry standards) to use a data bus with a predetermined number of bits. If the constituent memory devices provide more bandwidth than is necessary to fully fill the data bus, or more bits than are required by the application, at least some of the memory devices will have unused data paths. The power consumed by the circuits corresponding to these unused data paths may still contribute to the overall power consumption of the memory module or memory package.

[0010] To overcome this and other challenges, systems and methods for configurable data paths for memory modules, including dual in-line memory modules (DIMMs) and / or systems in which the memory is used, are disclosed herein. The disclosed systems and methods provide a mechanism for configuring a data path of a memory device by disabling at least a portion thereof (e.g., in response to a host command, a mode register setting, or configuration by a manufacturer during its packaging / assembly). In one embodiment, configuration of the data path may also involve disabling error correction code (ECC) or cyclic redundancy check (CRC) features to prevent the disabled portion of the data path from triggering inaccurate error detection.

[0011] As will be further discussed below, the elements of the currently disclosed technology described in the context of a particular paragraph and / or the accompanying drawings may be combined with the elements described in the context of other paragraphs and / or the accompanying drawings. In addition, all elements of the technology disclosed herein are not required to practice the technology. In addition, for the sake of clarity, several details of the structure and / or process that describe some important aspects of the technology that are well-known and often associated with memory devices but may unnecessarily obscure are not described in the following description. In addition, although the following disclosure describes several embodiments of the technology, several other embodiments of the technology have different configurations or different components from those described in this section. Thus, the technology may have other embodiments with additional elements and / or without several elements described below with reference to the accompanying drawings.

[0012] Figure 11 is a block diagram schematically illustrating a memory device 100 according to an embodiment of the present technology. The memory device 100 may include an array of memory cells, such as a memory array 150. The memory array 150 may include a plurality of memory banks, and each memory bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. The memory cells may include any of a number of different memory media types, including capacitance, magnetoresistive, ferroelectric, phase change, etc. The selection of the word lines WL may be performed by a row decoder 140, and the selection of the bit lines BL may be performed by a column decoder 145. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transfer gate (TG), which may be used as a switch. The memory array 150 may also include plate lines and corresponding circuitry for managing their operation.

[0013] The memory device 100 may employ a plurality of external terminals including command and address terminals (C / A) coupled to a command bus and an address bus to receive a command signal (CMD) and an address signal (ADDR). The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, data terminals DQ and DQS, power supply terminals VDD, VSS, VDDQ, and VPP.

[0014] The address signal and the bank address signal may be supplied to the command and address terminal (C / A). The address signal and the bank address signal supplied to the address terminal may be transferred to the address decoder 110 via the command / address input circuit 105. The address decoder 110 may receive the address signal and supply a decoded row address signal (XADD) to the row decoder 140, and supply a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive a bank address signal (BADD) and supply the bank address signal to both the row decoder 140 and the column decoder 145.

[0015] The command / address input circuit 105 may be supplied with a command and address signal C / A and a chip select signal CS from a memory controller. The command signal may represent various memory commands from the memory controller (e.g., including access commands (which may include read and write commands) and refresh commands). The select signal CS may be used to select the memory device 100 in response to the command and address provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, the command and address may be decoded and a memory operation may be performed. The command signal CMD may be provided to the command decoder 115 as an internal command signal ICMD via the command / address input circuit 105. The command decoder 115 may include a circuit for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., a row command signal for selecting a word line and a column command signal for selecting a bit line). The internal command signal may also include output and input activation commands, such as a timing command CMDCK. The command decoder 115 may further include one or more registers 117 for tracking various counts or values ​​(eg, a count of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100 ).

[0016] The memory device 100 may also include a data path disabling circuit 168 to disable a portion of a data path and disable functionality associated with the disabled data path. Figures 2 to 4 In some embodiments further described, the data path disabling circuit 168 employs one or more bits programmed in the mode register 118 (or other signals as described later) to cause the I / O circuit 160 to disable one or more nibbles of DQ and, when a byte is disabled, to disable a data strobe, such as DQSU, associated with the disabled byte. For example, the data path disabling circuit 168 may also disable the CRC code and ECC functionality associated with the disabled data path portion by masking or suppressing any ECC or cyclic redundancy check (CRC) errors associated with the disabled data portion and suppressing activation of an error alert signal (e.g., ALERT from the error controller 162). The data path disabling circuit 168 may also cause the refresh controller 112 to skip a refresh of the portion of the memory array 150 associated with the disabled data and / or mask any ECC errors generated from such a refresh operation.

[0017] When a read command is issued and the row address and the column address are supplied to the read command in time, read data may be read from the memory cells specified by these row addresses and column addresses in the memory array 150. The read command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160 so that read data may be output from the data terminals DQ and DQS via the read / write amplifier 155 and the input / output circuit 160 according to the DQS strobe signal.

[0018] When a write command is issued and the row address and column address are supplied to the command in time, the write data may be supplied to the data terminal. The write command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160 so that the write data may be received by the data receiver in the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155. The write data may be written in the memory cell specified by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write delay WL information. The write delay WL information may be programmed in the memory device 100, for example, in the mode register 118. The write delay WL information may be defined according to the clock cycle of the CK clock signal. For example, the write delay information WL may be the number of clock cycles of the CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0019] In the following about Figures 2 to 4 In some embodiments further described, the data path disabling circuit 168 may disable a portion of the data terminals DQ and DQS based on the value of a field in the mode register 118 or in response to a command from a connected host device. Figure 3 Further discussed, for X16 SDRAM memory devices (with 16-bit data bus DQ) used in DIMMs or systems with 40-bit data bus per channel, the mode register 118 may include a path disable bit, which when set may cause the data path disable circuit 168 to cause the I / O circuit 160 to disable the upper byte of the data bus DQ. The data path disable circuit 168 may also cause the I / O circuit 160 to disable the upper data strobe DQSU associated with the disabled upper byte. The DIMM or system may employ three X16 SDRAMs, where one of the three SDRAMs has the path disable bit in the mode register 118 set so that the upper byte of that third SDRAM is disabled, resulting in 40 bits of output data DQ (i.e., 16 bits each for two of the SDRAMs and 8 bits for the third SDRAM).

[0020] Power supply potentials VDD and VSS may be supplied to the power supply terminals. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0021] A power supply potential VDDQ may also be supplied to the power supply terminal. The power supply potential VDDQ may be supplied to the input / output circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0022] An input buffer included in the clock input circuit 120 may receive an external clock signal. For example, the input buffer may receive CK and CKF signals. The clock input circuit 120 may receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 130. The internal clock circuit 130 may provide various phase and frequency controlled internal clock signals based on the received internal clock signal ICLK. For example, the internal clock circuit 130 may include a clock path ( ) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1 100). The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data may be output from and input to the memory device 100 at different data rates. When high memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to the timing generator 135 and various internal clock signals may be generated accordingly.

[0023] The memory device 100 may be connected to any of a number of electronic devices or components thereof that are capable of utilizing memory to temporarily or permanently store information. For example, the host device of the memory device 100 may be a computing device (e.g., a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet, a digital reader, a digital media player)) or some component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device may be a network device (e.g., a switch, a router, etc.) or a digital image, audio and / or video recorder, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, the host device may be directly connected to the memory device 100, although in other embodiments, the host device may be indirectly connected to the memory device (e.g., through a network connection or through an intermediate device).

[0024] Figure 2 is a representative block diagram 200 schematically illustrating a configurable data path for a memory module 210. The memory module 210 integrates M SDRAM memory devices per channel 250; Figure 2 Depiction Figure 1 2. Two examples of memory devices 100 are shown: memory device #0 220a and memory device #(M-1) 220b integrated in channel (S=0) 250. Each memory device 220a and 220b includes a number of data terminals or bits (DQ), the number depending on the location of the memory device in the memory module 210, as well as other factors discussed below. For example, memory device #0 220a includes Nx4 data bits 225a, and memory device #(M-1) 220b includes (NK)x4 data bits 225b, where K is the number of nibbles of data bits disabled from memory device #(M-1) 220b, as described below. The memory module 210 also includes a P-bit data bus 240 coupled to the bits of each memory device. That is, the Nx4 bits of memory device 220a and the (NK)x4 bits of memory device 220b are coupled to a P-bit data bus 240, and in the example where there are only two memory devices in the memory module or system, P will be equal to (Nx4)+((NK)x4) bits. In some embodiments, only the non-disabled bits (e.g., the (NK)x4 data bits 225b of memory device 220b) are coupled to the data bus 240, while the disabled Kx4 bits remain unconnected or held at a quiescent voltage. In other embodiments, all data bits of all integrated memory devices are coupled to the data bus 240, although the disabled Kx4 data bits may be internally deactivated.

[0025] In different embodiments, memory devices 220a and 220b include different numbers of data bits (DQs). For example, a x4 device includes 4 data bits (1 data nibble), a x8 device includes 8 data bits (2 data nibbles), a x16 device includes 16 data bits (2 data bytes or 4 data nibbles), and a x32 device includes 32 data bits (4 data bytes or 8 data nibbles). As discussed above, N can represent the number of data nibbles in the data bits of the memory device, thus, in some instances, if the memory device 220a is configured as a x4 device, then N=1 and the data bits 225a are equal to 4 bits; in other instances, if configured as an x8 device, then N=2 and the data bits 225a are equal to 8 bits; in other instances, if configured as an x16 device, then N=4 and the data bits 225a are equal to 16 bits; and in other instances, if configured as an x32 device, then N=8 and the data bits 225a are equal to 32 bits.

[0026] In some embodiments, when ECC is not enabled, the number of data bits P in the data bus 240 may be 32 bits, and when ECC is enabled, the number of data bits P in the data bus 240 may be 36 bits, 40 bits, or other number of bits according to system requirements. Typically, there is 1 ECC bit for every 8 bits (bytes) of data bits. For a dual channel memory module without ECC, the data bus 240 may be 64 bits; for a dual channel memory module with ECC, the data bus 240 may be 72 bits, 80 bits, or other number of bits, where 8 bits can be used for error correction. The DRAM configuration can be controlled via the mode register 118 ( Figure 1 ), fuse blowing configuration during factory test, or external voltage levels on the die pad or (several) package pins.

[0027] For example, in an embodiment where ECC is enabled and the data bus 240 is 72 bits, if x4 memory devices are used in the memory module 210 (x4 memory devices have 1 nibble of data bits, so N=1), then nine memory devices may be used to populate each channel of the memory module 210, i.e., M=9. Nine memory devices each having 4 data bits (1 nibble of data each) would result in 36 bits per channel (M*N*4=9*1*4=36). For this example where the nine memory devices provide all the data and ECC bits required for each channel of the dual channel memory module 210, no additional memory modules would be needed, so K=0 (nibbles are not disabled because no additional memory modules are needed in this case).

[0028] In an embodiment where x16 memory devices are used in the memory module 210 (x16 memory devices have 4 data nibbles, so N=4), three memory devices may be used to populate each channel of the memory module 210, i.e., M=3. Three memory devices each having 16 data bits (each having 4 data nibbles) result in 48 bits per channel (M*N*4=3*4*4=48). For example, if the memory device is used in a DIMM or system with a 36-bit data bus per channel with ECC enabled, 12 bits (3 nibbles) of one of the three memory devices may be disabled, so K=3. The number of data bits available after three nibbles of one memory device are disabled is given by ((M*N)-K)*4=((3*4)-3)*4=36 bits. Alternatively, if the memory device is used in a DIMM or system with a 40-bit data bus per channel, 8 bits (2 nibbles or 1 byte) of one of the three memory devices may be disabled, so K=2. The number of data bits available after two nibbles of a memory device are disabled is given by ((M*N)-K)*4=((3*4)-2)*4=40 bits. This will be discussed below with respect to Figure 3 Further discussion.

[0029] In other embodiments, different relationships or values ​​may be used. For example, where x32 memory devices are used in a DIMM or system with a 36-bit data bus per channel, M=2 (two x32 modules are employed), N=8 (each x32 memory device has eight nibbles), and K=7 (seven nibbles are disabled from one memory device). That is, given the number of data nibbles used for each memory device in memory module 210 (where each memory device has the same number of data nibbles), the data bits P of data bus 240 may be satisfied by the following equation: P=4*((M*N)-K), where M is the number of N data nibbles memory devices in the memory module, and K is the number of nibbles that may be disabled from a data nibble of one of the M memory devices.

[0030] Each memory device 100 may include path disable bit(s) in the mode register 118, as described above with respect to Figure 1 To simplify the following discussion, the mode register of memory device 220a is Figure 2230a, and the mode register of memory device 220b is represented as 230b. Mode registers 230a and 230b may include one or more bits to determine which data nibbles (if any) are disabled in the respective memory devices 220a and 220b. In some embodiments, mode registers 230a and 230b include byte disable bits that, when set, may disable the upper byte of data DQ and the upper data strobe DQSU and mask ECC and CRC error alarms, as described above with respect to Figure 1 In other embodiments, the mode registers 230a and 230b may include a number of bits that indicate which nibbles are disabled (and mask the ECC / CRC errors associated with those disabled nibbles). For example, an x16 memory device may include a 2-bit datapath disable bit in the mode register 118 to indicate which of the 4 nibbles are disabled. For example, a datapath disable bit setting of 1'b00 may indicate that no nibbles are disabled (e.g., Figure 3 ); 1'b01 disables only the upper nibble, 1'b10 disables the upper byte (e.g., Figure 3 ), and 1'b11 disables the upper three nibbles (e.g., if Figure 3 The memory devices in are integrated into 36-bit channels, then this would be a third X16 memory device configuration).

[0031] In some embodiments, the mode register may include a number of bits that can indicate not only whether to disable certain half bytes but also which half bytes are disabled. For example, a 2-bit half byte disable field can indicate that 3 different half byte positions are disabled (e.g., 1'b00 can indicate that a half byte is not disabled, 1'b01 can indicate that the high three half bytes are disabled, 1'b10 can indicate that the low three half bytes are disabled, and 1'b11 can indicate that the high and low half bytes are disabled). The ability to select which half bytes to disable can be used to, for example, consider signal integrity criteria or factory test results. For example, if some data bits in the memory device are defective in some aspects, those data bits can be half bytes that are selected to be disabled. In addition, in order to minimize crosstalk and noise injection into adjacent circuits, it may be preferred to disable certain half bytes over other half bytes. In some embodiments, the selection of disabling half bytes is determined by the layout of the memory device 100 in the memory module 210. For example, based on the addressing of the memory devices, the high byte (e.g., when using x16 devices) may have the most significant address bits that may correspond to the bytes that are selected to be disabled (e.g., for six x16 DDR5 SDRAMs, data bits DQ[47:40] of each level of three DRAMs may be disabled, leaving DQ[39:0]).

[0032] In some embodiments, other methods of disabling nibbles or bytes of a memory device are possible, including, for example, generating a nibble disable signal from a configuration fuse that is blown during factory testing. Additionally or alternatively, a signal tied to a constant voltage such as power or ground (e.g., soldered on a PCB) may be used to determine whether to disable a nibble / byte and / or which nibbles / bytes to disable.

[0033] In some embodiments, memory devices 220a and 220b are DDR4 or DDR5 SDRAM memories, and memory module 210 is a small outline dual in-line memory module (SODIMM), a registered DIMM, or any other single or dual channel memory module integrating multiple DDR4 or DDR5 SDRAM memory devices. For a dual channel DDR5 SODIMM, memory channels 250 may be 0 ( Figure 2 S=0) or 1 as depicted in .

[0034] In some embodiments, disabling a nibble or data byte of a memory device includes masking, suppressing, or disabling any error alarms that may be generated from the disabled nibble. For example, when ECC is enabled, because these unused data bits that are not part of the P-bit data bus 240 may have unknown states, particularly during refresh, they may trigger an erroneous ECC error, parity error, or other error state. In these embodiments, those error alarms may be masked by error masking logic, thereby preventing them from propagating to the memory controller or host, or the error generation logic may be gated so that such errors do not occur in the first place. Additionally, typical responses that would be triggered in response to such error events may be prevented from occurring. For example, in the DRAM memory device mode register 118 ( Figure 1 In the case where write CRC errors are enabled in the data path disabling circuit 168 ( Figure 1 This typical response may be used by the error controller 162 ( Figure 1In other embodiments, the CRC generator may ignore the disabled nibbles when generating the CRC codes associated with the data nibbles and the error controller may ignore the disabled data nibbles when comparing the CRC codes thereby avoiding CRC errors associated with the disabled data nibbles. In other embodiments, other methods of disabling the effects or operations of these unused data bits may include disabling refresh of these data terminals, powering off circuits associated only with these data terminals, latching these data bits to a known state (e.g., to ground or VDDQ), latching a strobe signal, disabling a data mask signal, etc.

[0035] Figure 3 3 is a representative block diagram 300 schematically illustrating a channel of three x16 memory devices 320a, 320b, and 320c integrated in an ECC-enabled memory module 310. In the example of FIG. 300, a 40-bit per channel data bus 340 and three memory devices are shown. Figure 3 In the example depicted in FIG. 1 , where the number of data nibbles in a x16 memory device is four, one data byte (two data nibbles) may be disabled from one of the memory devices ( Figure 3 0]). Each of the memory devices 320a and 320b may include a mode register 330a and 330b, respectively, with the nth bit MR(n) of these mode registers equal to a logic 0. In this example configuration, each of the data terminals (DQ) 325a and 325b of the memory devices 320a and 320b (respectively) may be 16 bits (DQ[15:0]). If the third x16 memory device 320c includes a mode register 330c with the nth bit (MR(n)) equal to a logic 1, then this may indicate that one byte (two half bytes) is disabled. In this configuration, the data terminal (DQ) 325c of the memory device 320c may be 8 bits (DQ[7:0]). The data strobe associated with the disabled high byte may also be disabled, such as DSQU ( Figure 3 The second channel ( Figure 3 ) may be similarly configured to produce an 80-bit data bus when combined with the first channel.

[0036] Figure 4 4 is a representative flow chart 400 illustrating a method for disabling data bits of a memory device 100 integrated in a memory module 310 according to embodiments herein. Such a method may use, for example, a data path disabling circuit 168 ( Figure 1 ), I / O circuit 160 ( Figure 1 ), refresh controller 112 ( Figure 1 ) and / or error controller 162 ( Figure 1At block 410, the memory device 100 detects a data path disable signal of the memory device 100. Figure 2 As discussed, the data path disable signal may be received from a register stored in mode register 118 ( Figure 1 The data path disable bit in the data path disable field of the register 168 (e.g., from a single high byte disable bit, one or more half byte disable bits, or one or more bit disable bits) is generated. For example, the register output containing the data path disable bit can be coupled to the data path disable circuit 168 ( Figure 1 In other embodiments, the data path disable signal includes other signals, such as fuse outputs or static hardwired signals. Data path disable circuit 168 ( Figure 1 ) The value of the mode register 118 data path disable field or other data path disable signal may be read at power-up (ie, asynchronously), or the data path disable field or signal may be latched synchronously to the clock of the memory device 100.

[0037] At block 420, the memory device 100 disables a portion of the data path corresponding to the detected path disable signal. For example, if a single data path disable signal is utilized, the polarity of the signal may be used to indicate whether to disable one byte of a 16-bit data path. For example, in some embodiments, when the signal is logic high, it may indicate that the high byte of the 16-bit data path is disabled and the high byte strobe associated with the disabled byte is disabled. In other embodiments, a single path disable signal (or Figure 1 100 may indicate that the upper three nibbles of a 16-bit (4-nibble) data path are disabled. In yet other embodiments, multiple path disable signals may be detected at block 410, which may indicate predetermined combinations of data path bits disabled from various positions in the data path. For example, a 3-bit data path disable signal may indicate that up to 7 different bit pattern combinations of different bit lengths are disabled; an 8-bit data path disable signal may indicate that up to 255 different bit pattern combinations are disabled, or may indicate that the data path bits corresponding to the bit positions of the data path disable signal are disabled (e.g., 8'b0000_0000 may indicate that no data path bits are disabled, 8'b0000_0001 may indicate that the LSB is disabled, 8'b1000_0000 may indicate that the MSB is disabled, 8'B1111_0000 may indicate that the upper nibble is disabled, etc.). It will be appreciated that different bit encoding patterns and optimizations may be employed to map the number and values ​​of data path disable signals to the number and bit positions of disabled data path disable bits.

[0038] At block 420, in addition to disabling the portion of the data path corresponding to the detected data path disable signal, the memory device 100 may mask errors associated with the disabled portion of the data path and may also cause the refresh controller 112 ( Figure 1 ) disables refresh of the memory array 150 associated with the disabled data path. For example, the data path disabling circuit 168 ( Figure 1 In some embodiments, IO circuit 160 ( Figure 1 ) may conditionally disable data strobes (eg, DQSU / DQSL) when the corresponding data byte is disabled (eg, if all upper 8 bits are disabled, then IO circuitry 160 may also disable DQSU).

[0039] Figure 5 5 is a representative flow chart 500 illustrating a method for disabling a data nibble of a memory device 100 (e.g., an X16 SDRAM) integrated in a memory module 310 (e.g., a DIMM with a 40-bit data bus per channel) according to embodiments herein. This method may use, for example, a data path disabling circuit 168 ( Figure 1 ), I / O circuit 160 ( Figure 1 ), refresh controller 112 ( Figure 1 ) and / or error controller 162 ( Figure 1 At block 510, the memory device 100 detects a data path disable signal of the memory device 100. Figure 2 As discussed, the data path disable signal may be received from a register stored in mode register 118 ( Figure 1 The data path disable bit in the data path disable field of the register 168 (e.g., from a single high byte disable bit, or one or more high three nibble disable bits) is generated. For example, the register output containing the data path disable bit can be coupled to the data path disable circuit 168 ( Figure 1 In other embodiments, the data path disable signal includes other signals, such as fuse outputs or static hardwired signals. Data path disable circuit 168 ( Figure 1 ) The value of the mode register 118 data path disable field or other data path disable signal may be read at power-up (ie, asynchronously), or the data path disable field or signal may be latched synchronously to the clock of the memory device 100.

[0040] At block 520, the memory device 100 determines a data path disable signal (eg, from Figure 1 Whether the bit in the data path disable field of the mode register 118 in the data path disable circuit 168 ( Figure 1 ) may include combinational logic to decode the polarity of the data path disable field bit or the data path disable signal to determine whether the bit / signal pattern corresponds to a predefined pattern indicating a high byte disable mode. That is, at box 510, after the memory device 100 receives the data path disable signal, it determines the number of signals it receives (e.g., the number of bits or the number of signal lines) and detects the polarity of the received signal or bit. Then, at box 520, it compares this received input with a set of preconfigured commands or operations. Boxes 510 and 520 may be part of digital or analog comparator logic or a comparator and multiplexer, where the bit / signal pattern is compared to the input value and if there is a match, then the command or operation corresponding to the matched pattern is executed or activated. For example, as described above with respect to Figure 4 As discussed, a portion of the received bits or signals may indicate a command or operation to be performed or executed by the memory device and the remaining bits or signals may indicate which bits, nibbles, bytes to be disabled in response to receiving the input. The command or operation may be, for example, to disable certain bits, disable certain nibbles, or disable certain bytes, as further described below with respect to blocks 530, 533, and 534.

[0041] At block 533, if the data path disable signal indicates that the upper data byte is disabled, the memory device 100 may disable the upper 8 bits of DQ (DQ[15:8]) and the upper data byte strobe DQSU. The memory device 100 may also mask errors associated with the disabled data bytes and cause the refresh controller 112 ( Figure 1 ) disables refresh of the memory array 150 associated with the disabled data bytes. For example, the data path disabling circuit 168 ( Figure 1 ) can generate an internal data path disable signal that can be used with combinational logic to gate data enable or error alert (for example, ALERT, DQ, and DQSU can be logically NORed using the internal data path disable signal that is 1'b1 when data path disable is valid).

[0042] If at box 520, the memory device 100 determines that the data path disable signal does not indicate disabling the upper data byte, then at box 530 the memory device 100 determines whether the data path disable signal indicates disabling the upper three data bytes. At box 532, if the memory device 100 determines that the data path disable signal does not indicate disabling the upper three nibbles, then it does not disable a portion or mask any errors. Alternatively, at box 534, if the memory device 100 determines at box 530 that the data path disable signal indicates disabling the upper three nibbles, then it may disable the upper three data nibbles (DQ[15:4]). The memory device 100 may also generate a CRC / ECC error associated with the disabled data nibbles and cause the refresh controller 112 ( Figure 1 ) Disable refresh of the memory array 150 associated with the disabled data nibble.

[0043] Although the present disclosure contains many representative examples, these examples should not be interpreted as limitations on the scope of any disclosed method or claimable content, but rather as descriptions of features that may be peculiar to a particular embodiment of a particular disclosed method. Certain features described in this document in the context of a separate embodiment may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed, in some cases one or more features from the claimed combination may be excluded from the combination, and the claimed combination may involve a sub-combination or a variation of the sub-combination.

[0044] Similarly, while operations are depicted in a particular order in the drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desired results. Furthermore, the separation of various system components in the embodiments described in this patent document and the appendices hereto should not be understood as requiring such separation in all embodiments.

[0045] From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present technology. In addition, while advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily exhibit such advantages that fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments not explicitly shown or described herein.

Claims

1. A memory device, comprising: Memory array; an input / output circuit coupled to the memory array and configured to input or output a plurality of data nibbles based on a plurality of data strobe signals; a mode register configured to store a plurality of bits, each bit indicating whether a cyclic redundancy check CRC is enabled for a corresponding data nibble of the plurality of data nibbles; and A CRC generator is configured to generate a CRC code for each of the plurality of data nibbles for which a corresponding bit of the plurality of bits indicates that the CRC is enabled.

2. The memory device of claim 1 , further comprising: A data path disable circuit is coupled to the input / output circuit, wherein the data path disable circuit is configured to disable one or more of the plurality of data nibbles based on one or more data path disable signals and to disable a data strobe signal when a data byte is disabled.

3. The memory device of claim 2 , wherein the one or more data path disable signals include a data path disable signal generated from an upper byte disable bit stored in the mode register of the memory device, and wherein in response to the upper byte disable bit, the data path disable circuit is configured to disable an upper data byte of the plurality of data nibbles and disable an upper data byte strobe of the plurality of data select signals.

4. The memory device of claim 2 , wherein the one or more data path disable signals are generated based on at least one of: the plurality of bits stored in the mode register of the memory device, a plurality of bits stored in a configuration fuse, an arrangement of one or more signal lines connected to a power supply or ground potential, or a plurality of signals received from outside the memory device.

5. The memory device of claim 2, further comprising a refresh controller, wherein the data path disabling circuit is further configured to cause the refresh controller to skip a refresh operation on a portion of the memory array associated with the disabled one or more data nibbles.

6. The memory device of claim 1, wherein the CRC generator is further configured to exclude from generation of the CRC code data nibbles of the plurality of data nibbles for which corresponding bits of the plurality of bits indicate that CRC is disabled.

7. The memory device of claim 2, wherein the data path disabling circuit is further configured to cause an error controller of the memory device to suppress errors associated with the disabled one or more data nibbles.

8. The memory device of claim 7, wherein suppressing errors associated with the disabled one or more data nibbles comprises preventing error alarms generated from error correction code (ECC) errors associated with the disabled data nibbles from being activated.

9. The memory device of claim 7, wherein suppressing errors associated with the disabled one or more data nibbles comprises preventing an error alarm generated from a CRC error associated with the disabled data nibbles from being activated.

10. The memory device of claim 7, wherein suppressing errors associated with the disabled one or more data nibbles comprises ignoring actions triggered in response to the errors when the errors are associated with the disabled data nibbles.

11. The memory device of claim 10, wherein ignoring an action triggered in response to an error when the error is associated with the disabled one or more data nibbles further comprises rewriting a blocking write command to the memory array.

12. The memory device of claim 1, wherein the memory device is a x8 memory device, and wherein the plurality of data nibbles comprises two data nibbles.

13. The memory device of claim 12, wherein the two data nibbles include an upper data nibble and a lower data nibble, and wherein the plurality of bits include an upper data nibble CRC enable status bit and a lower data nibble CRC enable status bit.

14. A method for disabling a data path of a memory device, the method comprising: receiving one or more data path disable signals; determining a number of received data path disable signals; detecting a polarity of each of the data path disable signals; determining whether the number and the polarity of the data path disable signals match one or more of a set of commands or operations, wherein the set of commands or operations includes disabling one or more data bits, disabling one or more data nibbles, and disabling one or more data bytes of the memory device; executing the one or more commands or operations in response to determining that the number and the polarity of the data path disable signals match one or more commands or operations from the set of commands or operations; and A cyclic redundancy check (CRC) generator is configured to generate a CRC code, wherein configuring the CRC generator includes configuring the CRC generator to suppress error correction code (ECC) or CRC errors associated with at least one of the disabled data bits, data nibbles, or data bytes when generating the CRC code.

15. The method of claim 14, wherein the one or more data path disable signals comprise a data path disable signal generated from an upper byte disable bit stored in a mode register of the memory device.

16. The method of claim 14, wherein the one or more data path disable signals comprise one or more data path disable signals generated from one or more upper three nibble disable bits stored in a mode register of the memory device.

17. The method of claim 14, further comprising configuring a refresh controller to skip a refresh operation on a portion of a memory array of the memory device associated with at least one of the disabled data bits, data nibbles, or data bytes.

18. The method of claim 14, wherein configuring the CRC generator comprises: The CRC generator is configured to exclude at least one of the disabled data bits, data nibbles, or data bytes when generating the CRC code.

19. The method of claim 14, wherein suppressing ECC or CRC errors comprises masking a false alarm signal generated in response to the ECC or CRC errors.

20. A memory device comprising: Memory device; and a controller coupled to the memory device and configured to cause the memory device to: reading a logic value of a group of bits stored in a mode register of the memory device, each bit in the group of bits corresponding to a data nibble in a group of data nibbles; determining whether to enable a cyclic redundancy check (CRC) for each data nibble in the set of data nibbles based at least in part on reading the logic value; and A CRC code is generated for a first subset of the set of data nibbles based at least in part on determining that CRC is enabled for the first subset of the set of data nibbles.

21. The memory apparatus of claim 20, wherein the memory device is a x8 memory device, and wherein the set of data nibbles includes two data nibbles.

22. The memory device of claim 21, wherein the two data nibbles include an upper data nibble and a lower data nibble, and wherein the set of bits includes an upper data nibble CRC enable status bit and a lower data nibble CRC enable status bit.

23. The memory device of claim 20, wherein the controller is further configured to: Generating a CRC code for a second subset of the set of data nibbles is refrained from based at least in part on determining that CRC is disabled for the second subset of the set of data nibbles.

24. The memory device of claim 20, wherein the controller is further configured to: generating a CRC code for a second subset of the set of data nibbles; and Errors associated with the CRC code for the second subset of the set of data nibbles are suppressed based at least in part on determining that CRC is disabled for the second subset of the set of data nibbles.

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