Storage device and method of operating the same

Abstract

A storage device operating in an active mode and a low power mode is provided. The storage device includes a non-volatile memory including a plurality of non-volatile memory cells, and a storage controller configured to process a command input from a host device in the active mode, wherein the storage controller includes a power mode manager adjusting a plurality of power modes, wherein, when a first command is input, the power mode manager predicts an input prediction time of a second command to be input from the host device after the first command, changes from the active mode to the low power mode when a processing operation of the first command is completed, and returns from the low power mode to the active mode when a return time elapses as the input prediction time elapses.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0015838, filed on February 10, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a storage device and a method of operating the same, and more specifically, to a storage device and a method of operating the same that operates in multiple power modes. Background Technology

[0004] Non-volatile memory can retain stored data when the power is turned off. Storage devices, including flash-based non-volatile memory such as embedded multimedia cards (eMMC), universal flash memory (UFS), solid-state drives (SSDs), and memory cards, have become widely used recently and are useful for storing or transferring large amounts of data.

[0005] The storage device operates in active mode when performing operations based on commands received from the host device, and in low-power mode when not performing operations based on commands received from the host device. The storage device can reduce power consumption by operating in low-power mode. Summary of the Invention

[0006] This disclosure provides a storage device and a method for operating the same for predicting the timing of receiving the next command to switch power modes.

[0007] According to the technical concept of this disclosure, a storage device operates in multiple power modes, including an active mode and a low-power mode, wherein the power consumption of the low-power mode is lower than that of the active mode. The storage device includes: a non-volatile memory comprising a plurality of non-volatile memory cells; and a storage controller configured to process commands input from a host device in the active mode. The storage controller includes a power mode manager configured to adjust the multiple power modes, and wherein, when a first command is input, the power mode manager is configured to: predict the input prediction time of a second command to be input from the host device after the first command; change from the active mode to the low-power mode when the processing operation of the first command is completed; and return from the low-power mode to the active mode when the return time has elapsed with the input prediction time.

[0008] According to the technical concept of this disclosure, a method for operating a storage device in multiple power modes, the multiple power modes including an active mode and a low-power mode, wherein the power consumption of the low-power mode is lower than that of the active mode, the method comprising: receiving a first command from a host device; predicting an input prediction time for a second command to be input from the host device after the first command; setting a return time on a timer for returning from the low-power mode to the active mode based on the input prediction time; switching from the active mode to the low-power mode when the processing operation of the first command is completed; and returning from the low-power mode to the active mode when the return time has elapsed.

[0009] According to the technical concept of this disclosure, a storage device operates in multiple power modes, including an active mode and a low-power mode, wherein the power consumption of the low-power mode is lower than that of the active mode. The storage device includes: a non-volatile memory comprising a plurality of non-volatile memory cells; a storage controller configured to process commands input from a host device in the active mode; and a power mode manager configured to adjust the multiple power modes, wherein, when a first command is input, the power mode manager is further configured to: predict the input prediction time of a second command to be input from the host device after the first command; change from the active mode to the low-power mode when the processing operation of the first command is completed; and return from the low-power mode to the active mode when the return time has elapsed with the input prediction time. Attached Figure Description

[0010] Embodiments of the invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which similar reference numerals denote similar elements. In the drawings:

[0011] Figure 1 This is a block diagram illustrating a storage system according to exemplary embodiments of the present disclosure;

[0012] Figure 2 This is a diagram illustrating multiple power modes executed by a storage device according to exemplary embodiments of the present disclosure;

[0013] Figure 3 This is a diagram illustrating a method of operating a storage device according to an exemplary embodiment of the present invention;

[0014] Figure 4A This is a diagram illustrating the time taken for a storage device according to an exemplary embodiment of the present disclosure to return from sleep mode to active mode;

[0015] Figure 4B This is a graph used to describe the time taken for a storage device of a comparative example according to an exemplary embodiment of the present disclosure to return from sleep mode to active mode;

[0016] Figure 5 This is a block diagram of a storage controller according to exemplary embodiments of the present disclosure;

[0017] Figure 6 This is a block diagram illustrating a power mode manager according to an exemplary embodiment of the present disclosure;

[0018] Figure 7A and Figure 7B This is a diagram used to explain the operation of an idle predictor including a neural network model according to exemplary embodiments of the present disclosure;

[0019] Figure 8 This is a diagram illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure;

[0020] Figure 9 This is a diagram illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure;

[0021] Figure 10 This is a diagram illustrating the operation of a workload monitor according to an exemplary embodiment of the present disclosure;

[0022] Figure 11 A diagram illustrating a method of operating a storage device according to an exemplary embodiment of the present disclosure; and

[0023] Figure 12 This is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0024] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram of a storage system 1000 according to an exemplary embodiment of the present disclosure.

[0026] refer to Figure 1 The storage system 1000 may include a storage device 10 and a host 20. The storage system 1000 may be embedded in or implemented as an electronic device. For example, the electronic device may be implemented as a personal computer (PC), a data server, an ultra-mobile PC (UMPC), a workstation, a netbook, network attached storage (NAS), a smart TV, an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device may be a laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, audio equipment, portable multimedia player (PMP), personal navigation device (PND), MP3 player, handheld game console, e-book reader, and / or wearable device.

[0027] The host device 20 can send commands (CMD) to the storage device 10 and manage the overall operation of the storage device 10. The host device 20 can store data in the storage device 10 and read data from the storage device 10. For example, the host device 20 can send commands to the storage device 10 to write data, or it can send read commands to the storage device 10. In an exemplary embodiment, the host device 20 can be implemented as a central processing unit (CPU), processor, microprocessor, application processor (AP), or system-on-a-chip (SoC).

[0028] Storage device 10 can be a solid-state drive (SSD), an embedded multimedia card (eMMC), an embedded universal flash memory (UFS) storage device, a UFS memory card, a compact flash memory (CF), a secure digital storage (SD) memory, a micro-secure digital storage (Micro-SD) memory, a mini-secure digital storage (Mini-SD) memory, an extreme digital storage (xD) memory, or a memory stick. For example, storage device 10 can be any type of storage device capable of storing data.

[0029] Storage device 10 may include storage controller 100, volatile memory 200, voltage generator 300, and clock signal generator 400. Storage controller 100 can control the operation of non-volatile memory 200, voltage generator 300, and clock signal generator 400.

[0030] The storage controller 100 can receive commands (CMD) including read and write commands from the host device 20, and can send / receive data DATA from the host device 20. The storage controller 100 can, in response to a read command, control the non-volatile memory 200 to read the data DATA stored in the non-volatile memory 200 and provide the read data DATA to the host device 20; or the storage controller 100 can, in response to a write command from the host device 20, control the non-volatile memory 200 to write the data DATA to the non-volatile memory 200.

[0031] The storage controller 100 may include a power mode manager 140. The power mode manager 140 may generate a mode change signal PM and send the mode change signal PM to at least one of a voltage generator 300 and a clock signal generator 400, such that the power mode of the storage device 10 may be changed.

[0032] Upon receiving a command CMD, the power mode manager 140 can predict the input prediction time when the next command CMD will be input, and change the power mode of the storage device 10 based on the predicted input prediction time. In an exemplary embodiment, the storage controller 100 may receive a first command CMD1 from the host device 20, and then receive a second command CMD2 after a certain period of time. When the first command CMD1 is input from the host device 20, the power mode manager 140 can predict the input prediction time when the second command CMD2 is predicted to be input to the storage device 10 by using workload information corresponding to the first command CMD1. The power mode manager 140 can determine whether to change the power mode from active mode to low power mode based on the predicted input prediction time, and set the return time from low power mode to active mode. For example, the workload information may include idle history, the size of the command CMD, the type of the command CMD, and / or information related to the continuation of the logical block address corresponding to the command CMD.

[0033] Non-volatile memory 200 can be used as the storage medium of storage device 10. Non-volatile memory 200 can store data provided from host device 20. Non-volatile memory 200 may include a memory cell array comprising non-volatile memory cells that retain stored data even when storage device 10 is powered off. The memory cell array may be divided into multiple memory blocks, and the multiple memory blocks may have a two-dimensional horizontal structure in which memory cells are arranged two-dimensionally on the same plane (or layer) or a three-dimensional (3D) vertical structure in which non-volatile memory cells are arranged three-dimensionally. Memory cells may be single-level cells (SLC) storing one bit of data or multi-level cells (MLC) storing two or more bits of data. However, the invention is not limited thereto; each memory cell may be a three-level cell (TLC) storing 3 bits of data or a four-level cell storing 4 bits of data.

[0034] In an exemplary embodiment, the non-volatile memory 200 may include a plurality of dies or a plurality of chips, each die or chip including an array of memory cells. For example, the non-volatile memory 200 may include a plurality of chips, and each of the plurality of chips may include a plurality of dies. The non-volatile memory 200 may also include a plurality of channels, each channel including a plurality of chips.

[0035] In an exemplary embodiment, the non-volatile memory 200 may include a NAND flash memory device. However, the spirit of this disclosure is not limited thereto, and the non-volatile memory 200 may include various other types of non-volatile memory. For example, the non-volatile memory 200 may include non-volatile memory, and various types of memory, such as magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, nanotube RAM, polymer RAM (PoRAM), nanofloating gate memory (NFGM), holographic memory, molecular electronic memory, or insulator resistance change memory, etc.

[0036] Voltage generator 300 can receive external voltage from host device 20 via an external power supply line. Voltage generator 300 can use the external voltage to generate the internal voltage required for each operation of memory controller 100 and non-volatile memory 200. In an exemplary embodiment, voltage generator 300 can be implemented as a power management integrated circuit (PMIC), power management unit (PMU), etc. Voltage generator 300 can provide the generated internal voltage to memory controller 100 and non-volatile memory 200.

[0037] The voltage generator 300 can regulate the internal voltage supplied to each of the memory controller 100 and the non-volatile memory 200 according to multiple power modes. The voltage generator 300 can regulate the internal voltage supplied to each of the memory controller 100 and the non-volatile memory 200 in response to a mode change signal PM received from the power mode manager 140. For example, the voltage generator 300 can supply voltage to the memory controller 100 and the non-volatile memory 200 such that the storage device 10 performs operations according to a command CMD in an active mode. As another example, the voltage generator 300 can not supply voltage to certain components of the memory controller 100, or can not supply voltage to the non-volatile memory 200, in a low-power mode.

[0038] The clock signal generator 400 can generate various clock signals used in the storage device 10. In an exemplary embodiment, the clock signal generator 400 can be implemented using an oscillator, a phase-locked loop (PLL), a delay phase-locked loop (DLL), etc. The clock signal generator 400 can generate clock signals used in the storage controller 100 and clock signals used in the non-volatile memory 200.

[0039] The clock signal generator 400 can adjust the frequency of the clock signal provided to each of the memory controller 100 and the non-volatile memory 200 according to multiple power modes. The clock signal generator 400 can adjust the frequency of the clock signal provided to each of the memory controller 100 and the non-volatile memory 200 in response to a mode change signal PM. For example, the clock signal frequency in a clock active mode can be higher than the clock signal frequency in a low power mode. For example, the clock signal generator 400 can provide a clock signal with a higher frequency to each of the memory controller 100 and the non-volatile memory 200 in a clock active mode, and the clock signal generator 400 can provide a clock signal with a lower frequency to each of the memory controller 100 and the non-volatile memory 200 in a low power mode.

[0040] Therefore, after the first command CMD1 and the second command CMD2 are input consecutively, the storage device 10 of this disclosure pre-predicts the input prediction time, allowing the storage device 10 to return from the low-power mode to the active mode before the second command CMD2 is input. The power mode manager 140 presets the return time to the active mode, and when the return time has elapsed, sends a mode change signal PM to the voltage generator 300 and the clock signal generator 400, causing the power mode to switch from the low-power mode to the active mode. The return time preset by the power mode manager 140 can be the input prediction time predicted by the storage device 10. Therefore, due to the time spent by the storage device 10 returning from the low-power mode to the active mode, the waiting time occurring when processing the second command CMD2 can be reduced.

[0041] Figure 2 This is a diagram illustrating multiple power modes executed by the storage device 10 according to an exemplary embodiment of the present disclosure.

[0042] refer to Figure 1 and Figure 2 The storage device 10 can operate in multiple power modes. These power modes may include an active mode (AM) and a low-power mode (LPM). When not performing operations due to control by the host device 20, the storage device 10 can switch to low-power mode (LPM) to reduce power consumption. For example, in low-power mode (LPM), internal voltages may not be supplied to at least some components included in the storage device 10, and the frequency of clock signals supplied to the components included in the storage device 10 may be reduced. Therefore, in low-power mode (LPM), the storage device 10 may not process commands (CMD) received from the host device 20, and may process commands (CMD) received from the host device 20 after returning to active mode (AM).

[0043] The low-power mode (LPM) may include an idle mode (IM) and a sleep mode (SM). In an exemplary embodiment, after receiving a first command CMD1, the storage device 10 may determine whether to change from active mode AM to idle mode IM or from active mode AM to sleep mode SM based on the input prediction time before receiving the second command CMD2. For example, after receiving the first command CMD1, the storage device 10 may determine whether to change from active mode AM to idle mode IM or from active mode AM to sleep mode SM based on the input prediction time of predicting when the second command CMD2 will be received.

[0044] In sleep mode SM, the power consumption of storage device 10 can be lower than that in idle mode IM. For example, the number of components of storage device 10 that do not have internal voltage supplied in sleep mode SM can be greater than the number of components that do not have internal voltage supplied in idle mode IM. For example, regarding non-volatile memory 200, internal voltage is supplied to non-volatile memory 200 from voltage generator 300 in idle mode IM, but internal voltage may not be supplied to non-volatile memory 200 from voltage generator 300 in sleep mode SM. In addition, for example, storage controller 100 may receive a clock signal with a lower frequency than that in active mode AM from clock signal generator 400 in idle mode IM, and in sleep mode SM, internal voltage may not be supplied to components of storage controller 100 except for some components (e.g., always-on blocks).

[0045] Figure 3 This is a diagram illustrating a method of operating a storage device 10 according to an exemplary embodiment of the present disclosure.

[0046] refer to Figure 1 and Figure 3 In operation S10, storage device 10 can receive a first command CMD1 from host device 20. In operation S20, storage device 10 can predict the input prediction time for a second command CMD2 to be input to storage device 10 after the first command CMD1. For example, when the first command CMD1 is received, the power mode manager 140 of storage controller 100 can use the workload information related to the first command CMD1 to calculate the input prediction time of the second command CMD2.

[0047] In operation S30, the storage device 10 can set the return time from low-power mode LPM to active mode AM based on the input prediction time. In operation S40, the storage device 10 can switch from active mode AM to low-power mode LPM. When the operation corresponding to the first command CMD1 is completed, the storage device 10 can switch from active mode AM to low-power mode LPM. At this time, low-power mode LPM may include idle mode IM and sleep mode SM, and in operation S40, the storage device 10 can switch the power mode to one of idle mode IM or sleep mode SM. For example, in operation S40, the power mode manager 140 of the storage controller 100 can generate a mode change signal PM and send the generated mode change signal PM to at least one of voltage generator 300 and clock signal generator 400.

[0048] In operation S50, storage device 10 can determine whether the return time has elapsed after switching to low-power mode LPM. When the set return time has elapsed (operation S50, "Yes"), in operation S70, storage device 10 can return from low-power mode LPM to active mode AM. Therefore, storage device 10 can return from low-power mode LPM to active mode AM in advance before receiving the second command CMD2, and can reduce the time required to process the second command CMD2.

[0049] If the set return time has not elapsed (operation S50, "No"), in operation S60, the storage device 10 can determine whether the second command CMD2 has been received from the host device 20. Even if the set return time has not elapsed, when the second command CMD2 is received from the host device 20 (operation S60, "Yes"), the host device 20 can also return from the low-power mode LPM to the active mode AM (operation S70). Therefore, even if the return time set according to the predicted input prediction time has not elapsed, when the second command CMD2 is received, the storage device 10 can process the second command CMD2 by returning to the active mode AM.

[0050] Figure 4A This is a diagram illustrating the time taken for a storage device according to an exemplary embodiment of the present disclosure to return from sleep mode SM to active mode AM. Figure 4B This is a graph used to describe the time it takes for the storage device of the comparative example to return from sleep mode SM to active mode AM. Figure 4A and Figure 4B This is a diagram illustrating an example of returning from sleep mode SM to active mode AM to process a second command.

[0051] refer to Figure 1 and Figure 4AAccording to the present disclosure, the storage device 10 can predict the input prediction time ti_p for the second command CMD2 to be input after the first command CMD1. Taking into account the input prediction time ti_p and the mode switching time td spent returning from sleep mode SM to active mode AM, the storage device 10 can set a return time tr, and after switching from active mode AM to sleep mode SM, when the set return time tr has elapsed, the storage device 10 can return to active mode AM again. Therefore, the storage device 10 according to the present disclosure returns to active mode AM at or before the actual reception time ti corresponding to the actual time of receiving the second command CMD2, thereby reducing the waiting time according to the mode switching time td and reducing the time spent executing the second command CMD2.

[0052] On the other hand, reference Figure 4B According to the comparative example, the storage device performs an operation based on the first command CMD1, and then switches from active mode AM to sleep mode SM. When a second command CMD2 is received after the first command CMD1, the storage device according to the comparative example returns from sleep mode SM to active mode AM. Therefore, since the storage device according to the comparative example returns from sleep mode SM to active mode AM after the actual reception time ti when the second command CMD2 is received, the storage device can perform the operation based on the second command CMD2 after the mode switching time td used for returning from sleep mode SM to active mode AM. A waiting time based on the mode switching time td can be generated, and the time spent executing the operation based on the second command CMD2 can be increased. For example, the time spent executing the operation based on the second command CMD2 can be increased by the mode switching time td.

[0053] Figure 5 This is a block diagram illustrating a storage controller 100 according to an exemplary embodiment of the present disclosure.

[0054] refer to Figure 5 The storage controller 100 may include a processor 110, random access memory (RAM) 120, a command queue 130, a power mode manager 140, a host interface 150, and a memory interface 160. Components of the storage controller 100 (e.g., processor 110, RAM 120, command queue 130, power mode manager 140, host interface 150, and memory interface 160) may communicate with each other via a bus 170.

[0055] Processor 110 may include a central processing unit (CPU) or a microprocessor and may control the overall operation of memory controller 100. In an exemplary embodiment, processor 110 may be implemented as a multi-core processor, such as a dual-core processor or a quad-core processor.

[0056] The memory 120 can operate under the control of the processor 110 and can be used as operational memory, buffer memory, or high-speed cache memory. For example, the RAM 120 can be implemented using volatile memory such as DRAM and static RAM (SRAM) or non-volatile memory such as PRAM and flash memory. The RAM 120 can store firmware and data used to control the memory controller 100. The stored firmware and data can be driven or processed by the processor 110. The software layer structure of the memory controller 100 implemented by firmware may include an interface layer, a flash translation layer (FTL), etc.

[0057] The host interface 150 can receive commands (CMD) from the host device 20, and the host interface 150 can transmit the received commands (CMD) to the command queue 130 via the bus 170. The command queue 130 can store the commands (CMD) received from the host device 20. For example, multiple write commands received from the host device 20 can be queued in the command queue 130, and multiple read commands received from the host device 20 can be queued in the command queue 130. The storage controller 100 may also include a command scheduler (not shown), and the command scheduler can direct commands to non-volatile memory (e.g., in an ordered or unordered manner) in an ordered manner. Figure 1 The 200) provides multiple queued write commands and multiple read commands.

[0058] Command queue 130 can be implemented using software (or firmware) or hardware. Alternatively, command queue 130 can be implemented using a combination of software and hardware. When command queue 130 is implemented using software, the instructions of the program constituting command queue 130 can be loaded into RAM 120 and executed by processor 110.

[0059] When the first command CMD1 is received from the host device 20, the power mode manager 140 can predict the input prediction time when the next second prediction command CMD2 is expected to be input to the storage controller 100 by using the workload information corresponding to the first command CMD1. For example, the workload information may include an idle history in which idle times are recorded, which are the intervals between the time when the storage controller 100 receives each command CMD. In addition, the workload information may include the size of the command CMD, the type of the command CMD, or information related to the contiguousness of the logical block address corresponding to the command CMD.

[0060] The power mode manager 140 can determine whether to switch the power mode from active mode AM to low power mode LPM based on a predicted input prediction time, and when a power mode switch is determined, set a return time from low power mode LPM back to active mode AM. In an exemplary embodiment, the power mode manager 140 may include a timer CT, and the timer CT can set the return time. The power mode manager 140 can generate a mode change signal PM when the set return time has elapsed, and can send the mode change signal PM to at least one of voltage generator 300 and clock signal generator 400 via bus 170, so that the power mode of the storage device 10 can be changed.

[0061] In an exemplary embodiment, the power mode manager 140 can predict input prediction time using workload information by executing an application. The application may include multiple data operations related to performing the prediction, such as arithmetic operations, convolution operations, polling operations, etc. For example, the power mode manager 140 may perform the task based on a neural network, and the application may include a neural network model. The neural network model may include multiple data operations and the inputs, output sizes, weights, biases, etc., of the multiple data operations, which are based on at least one of the following: convolutional neural networks (CNNs), region-based neural networks (R-CNNs), region proposal networks (RPNs), recurrent neural networks (RNNs), stacked deep neural networks (S-DNNs), state-space dynamic neural networks (S-SDNNs), deconvolutional networks, deep belief networks (DBNs), restricted Boltzmann machines (RBMs), fully convolutional networks, long short-term memory (LSTM) networks, classification networks, and various types of neural networks.

[0062] In an exemplary embodiment, the power mode manager 140 may be implemented using a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), or a neural processing unit (NPU). However, the invention is not limited thereto, and the power mode manager 140 may be implemented using various types of acceleration circuits (accelerators) that perform the tasks required to perform the assigned tasks (i.e., perform predictions).

[0063] However, the storage device 10 according to this disclosure is not limited to a power mode manager 140 including a processor or processing unit. A processor included in the storage controller 100 can execute a software-implemented power mode manager 140 to predict input prediction time using workload information.

[0064] Host interface 150 can be configured to communicate with external host device 20 under the control of processor 110. Host interface 150 can receive commands (CMD) from host device 20. At least one of various interface schemes can be applied to host interface 150, and the various interfaces may include Universal Serial Bus (USB), AT Attachment (ATA), Serial AT Attachment (SATA), Parallel AT Attachment (PATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), Load-Delayed DIMM (LRDIMM), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), etc.

[0065] The memory interface 160 can provide an interface between the memory controller 100 and the non-volatile memory 200. For example, internal commands based on commands CMD received from the host device 20 can be sent to the non-volatile memory 200 through the memory interface 160, and write data and read data can be sent and received between the memory controller 100 and the non-volatile memory 200 through the memory interface 160.

[0066] Figure 6 This is a block diagram illustrating a power mode manager 140 according to an exemplary embodiment of the present disclosure.

[0067] refer to Figure 5 and Figure 6 The power mode manager 140 can generate a mode change signal PM by receiving queued commands (e.g., first command CMD1) from the command queue 130. Alternatively, the power mode manager 140 can obtain command information related to the first command CMD1 queued in the command queue 130 to generate the mode change signal PM. The power mode manager 140 may include a workload monitor 141, an idle predictor 143, and a return time determiner 145.

[0068] The workload monitor 141 can monitor the first command CMD1 input to the storage controller 100. Workload information can be stored in the workload monitor 141, and the workload monitor 141 can output workload information IWL corresponding to the first command CMD1. The workload information IWL may include idle history, command size (e.g., the size of the first command CMD1), command type (e.g., the type of the first command CMD1), and logical block address (LBA) information (e.g., information related to the continuity of logical block addresses corresponding to the first command CMD1).

[0069] For example, workload monitor 141 can log information related to input / output between host devices and storage devices. For example, workload monitor 141 can collect information related to the idle time spent from the input of a specific command until the input of the next command, and can store the collected information as idle history.

[0070] Additionally, for example, when the first command CMD1 is received, the workload monitor 141 sends the size of the first command CMD1, the type of the first command CMD1, or information related to the continuity of the logical block address corresponding to the first command CMD1 as the workload information IWL corresponding to the first command CMD1 to the idle predictor 143. The size of the first command CMD1 may vary depending on the size of the data in the first command CMD1, and the type of the first command CMD1 may indicate whether it is a read command, a write command, or another command. The information related to the continuity of the logical block address corresponding to the first command CMD1 may refer to information related to the continuity between the logical block address of the command corresponding to the first command CMD1 and the logical block address corresponding to the first command CMD1.

[0071] The idle predictor 143 can perform operations to predict the input prediction time when a second request CMD2 (i.e., the next request) is received, using the workload information IWL of the first command CMD1. The idle predictor 143 can output prediction result data PD based on the operation result. In an exemplary embodiment, the idle predictor 143 can perform multiple data operations related to performing the prediction, such as arithmetic operations, convolution operations, polling operations, etc. For example, the power mode manager 140 can perform tasks based on a neural network, and the application may include a neural network model.

[0072] The return time determiner 145 can use the prediction result data PD to determine the return time point, and can generate a mode change signal PM based on the determined return time point. The return time determiner 145 can determine the return time point by taking into account the input prediction time and the time taken by the storage device to switch power modes.

[0073] For example, the return time determiner 145 may include a timer CT, and the return time determiner 145 may set a return time point on the timer CT. When the return time point set in the timer CT has elapsed, the return time determiner 145 may generate a mode change signal PM to switch the power mode from low power mode LPM to active mode AM.

[0074] In an exemplary embodiment, each of the workload monitor 141, the idle predictor 143, and the return time determiner 145 may be implemented in software, and each of the workload monitor 141, the idle predictor 143, and the return time determiner 145 is driven by a processing unit included in the power mode manager 140 to perform the operations described above. Alternatively, in an exemplary embodiment, each of the workload monitor 141, the idle predictor 143, and the return time determiner 145 may be implemented in software, and each of the workload monitor 141, the idle predictor 143, and the return time determiner 145 is driven by an external processing unit of the power mode manager 140 to perform the operations.

[0075] Figure 7A and Figure 7B This is a diagram used to illustrate the operation of idle predictors, including neural network models NN1 and NN2.

[0076] refer to Figure 7A and Figure 7B idle predictor (e.g., Figure 6 The idle predictor 143 in the memory can be implemented as a neural network model NN1 or NN2 and can predict the input prediction time. The neural network model NN1 or NN2 can be implemented using software executed by a processing unit included in the storage device (e.g., storage device 10). Figure 7A The neural network model NN1 and Figure 7B The neural network model NN2 is just an example, and the idle predictor 143 is not limited to this and can be implemented as various models.

[0077] refer to Figure 7A The neural network model NN1 can include multiple layers, including an input layer IL, one or more intermediate layers ML, and an output layer OL. The input layer IL can receive input values ​​IV (e.g., ...). Figure 6 The workload information (IWL) and the output layer OL can generate the predicted output value PV (e.g., workload information IWL), and the output layer OL can generate the predicted output value PV (e.g., workload information IWL). Figure 6 The predicted data (PD). The neural network model NN1 can be a deep neural network (DNN).

[0078] Each layer of the neural network model NN1 can include multiple nodes, which are also referred to as neurons in this paper. Each node or neuron can represent an operational unit with one or more inputs and outputs. Each input from multiple nodes in a layer can be provided by each node in adjacent layers. Similarly, outputs can be provided to multiple nodes in adjacent layers.

[0079] In an exemplary embodiment, the input layer IL may have l nodes, and each of the intermediate layers ML may have m nodes, and the output layer OL may have n nodes. Each node in the network may be connected to all nodes in adjacent layers. The number of nodes l, m, and n may be the same or different depending on the application of the neural network model NN1. Although only two intermediate layers ML with the same number of nodes are shown in this disclosure, any number of intermediate layers and different numbers of nodes in each intermediate layer may exist without departing from the scope of the invention.

[0080] refer to Figure 7B In the neural network model NN2, multiple neurons can be arranged in one or more layers. Neurons in a specific layer can receive input from one or more neurons in previous layers, generating output (called "activation") to be transmitted to one or more neurons in the next layer of the neural network model NN2, or generating the output value PVk in the case of the last layer hk of the neural network model NN2. The output value PVk is... Figure 6 The prediction results data PD, and can be provided to Figure 6 Return time determiner 145.

[0081] The neural network model NN2 can include multiple hidden layers h1 to hk. These hidden layers h1 to hk can be connected to each other to use previously output values. The last hidden layer hk can output the output value PVk. The neural network model NN2 can be a recurrent neural network (RNN).

[0082] The input values ​​IV2 to IVk can correspond to the previous output values ​​PV1 to PVk-1, respectively. This can be derived from... Figure 6 The workload information IWL obtains each of the input values ​​IV2 to IVk from its idle history. Therefore, the output value PVk can be used as an input value in the next operation.

[0083] Figure 8 This is a diagram illustrating a method of operating a storage device 10 according to an exemplary embodiment of the present disclosure. Figure 8 Operation S30 is Figure 3 An example of operation S30, and operation S30 may include operations S310 to S330. Figure 8 Operation S40 is Figure 3An example of operation S40, and operation S40 may include operation S410 and operation S420. In an exemplary embodiment, Figure 8 Operation S30 can be performed by Figure 6 The return time determiner 145 is executed.

[0084] refer to Figure 1 and Figure 8 In operation S310, storage device 10 can determine whether the input prediction time is equal to or greater than the mode switching time. For example, storage device 10 can determine whether the input prediction time of the second command CMD to be input to storage device 10 after the first command CMD1 is greater than the mode switching time of storage device 10 switching from low power mode LPM to active mode AM.

[0085] If the input prediction time is less than the mode switching time (operation S310, "No"), then in operation S420, the storage device 10 can maintain the active mode AM without switching the power mode from active mode AM to low power mode LPM. When it is predicted that the second command CMD2 will be received relatively quickly after the first command CMD1 is received, the storage device 10 does not switch the power mode, thereby reducing the waiting time caused by the time spent switching the power mode.

[0086] If the input prediction time is equal to or greater than the mode switching time (operation S310, "Yes"), then in operation S320, the storage device 10 can determine whether the energy saved in low-power mode LPM is equal to or greater than the energy consumed by switching power modes. The power consumption of the storage device 10 in active mode AM can be greater than the power consumption in low-power mode LPM. Therefore, as the storage device 10 maintains low-power mode LPM for an increased period, energy savings can increase. For example, the energy saved in low-power mode LPM can be calculated by multiplying the value obtained by subtracting the power consumption in low-power mode LPM from the power consumption in active mode AM by the time low-power mode LPM is maintained.

[0087] Additionally, storage device 10 can consume power to switch from active mode AM to low-power mode LPM, and can consume power to return from low-power mode LPM to active mode AM. When the energy saved in low-power mode LPM is less than the energy consumed by switching power modes (operation S320, "No"), in operation S420, storage device 10 can maintain active mode AM without switching the power mode from active mode AM to low-power mode LPM. Therefore, even if the input prediction time is greater than the mode switching time and it is determined that there is no energy-saving effect, active mode AM can be maintained without changing the power mode.

[0088] When the energy saved in low power mode LPM is equal to or greater than the energy consumed by switching power modes (operation S320, "Yes"), in operation S330, the storage device 10 can set the return time from low power mode LPM to active mode AM based on the input prediction time and the mode switching time. For example, the return time can be calculated by subtracting the mode switching time from the input prediction time.

[0089] In operation S410, storage device 10 can switch from active mode AM to low-power mode LPM. When the return time set in operation S330 has elapsed, storage device 10 can return from low-power mode LPM to active mode AM.

[0090] Figure 9 This is a diagram illustrating a method of operating a storage device 10 according to an exemplary embodiment of the present invention. Figure 9 Operation S30a is Figure 3 Examples of operation S30, and operation S30a may include operations S311, S313, S321, S323, S331 and S333. Figure 9 Operation S40a is Figure 3 An example of operation S40, and operation S40a may include operations S411, S413, and S420. In an exemplary embodiment, Figure 9 Operation S30a can be performed by Figure 6 The return time determiner 145 is executed.

[0091] In an exemplary embodiment, the low-power mode (LPM) may include an idle mode (IM) and a sleep mode (SM). The power consumption of the storage device 10 in sleep mode (SM) may be lower than that in idle mode (IM).

[0092] refer to Figure 1 and Figure 9 In operation S311, storage device 10 may determine whether the input prediction time is equal to or greater than the idle mode switching time. When storage device 10 determines that the input prediction time is equal to or greater than the idle mode switching time (operation S311, "Yes"), in operation S313, storage device 10 may determine whether the input prediction time is equal to or greater than the sleep mode switching time. In an exemplary embodiment, the idle mode switching time for switching from idle mode IM to active mode AM may be less than the sleep mode switching time for switching from sleep mode SM to active mode AM.

[0093] If the input prediction time is less than the idle mode switching time (operation S311, "No"), then in operation S420, the storage device 10 can maintain the active mode AM without switching the power mode from active mode AM to low power mode LPM. When it is predicted that the second command CMD2 will be received relatively quickly after the first command CMD1 is received, the storage device 10 does not switch the power mode, thereby reducing the waiting time caused by the time spent switching the power mode.

[0094] When the input prediction time is equal to or greater than the sleep mode switching time (operation S313, "Yes"), in operation S321, the storage device 10 can determine whether the power saved in sleep mode SM is equal to or greater than the power consumed by switching power modes. As the storage device 10 maintains sleep mode SM for an increased period, the power savings can increase. For example, the power saved in sleep mode SM can be calculated by multiplying the value obtained by subtracting the power consumption in sleep mode SM from the power consumption in active mode AM by the time sleep mode SM is maintained.

[0095] When the energy saved in sleep power mode is equal to or greater than the energy consumed by switching power modes (operation S321, "Yes"), in operation S331, the storage device 10 can set the return time from sleep mode SM to active mode AM based on the input prediction time and the sleep mode switching time. For example, the return time can be calculated by subtracting the sleep mode switching time from the input prediction time. In operation S411, the storage device 10 can switch from active mode AM to low power mode LPM. When the return time set in operation S331 has elapsed, the storage device 10 can return from sleep mode SM to active mode AM.

[0096] When the power saved in sleep mode SM is less than the power consumed by switching power modes (operation S321, "No"), in operation S420, the storage device 10 can maintain active mode AM without switching the power mode from active mode AM to sleep mode SM. Even if the input prediction time is equal to or greater than the sleep mode switching time, if it is determined that there is no power saving effect (operation S321, "No"), active mode AM can be maintained without changing the power mode (operation S420).

[0097] When the input prediction time is less than the sleep mode switching time (operation S313, "No") and equal to or greater than the idle mode switching time (operation S311, "Yes"), in operation S323, the storage device 10 can determine whether the power saved in idle mode IM is greater than the power consumed by switching power modes. As the storage device 10 maintains idle mode IM for an increased period, the power savings can increase. For example, the power saved in idle mode IM can be calculated by multiplying the value obtained by subtracting the power consumption in idle mode IM from the power consumption in active mode AM by the time idle mode IM is maintained.

[0098] When the energy saved in idle power mode is equal to or greater than the energy consumed by switching power modes (operation S323, "Yes"), in operation S333, the storage device 10 can set the return time from idle mode IM to active mode AM based on the input prediction time and the idle mode switching time. For example, the return time can be calculated by subtracting the idle mode switching time from the input prediction time. In operation S413, the storage device 10 can switch from active mode AM to idle mode IM. When the return time set in operation S333 has elapsed, the storage device 10 can return from idle mode IM to active mode AM.

[0099] When the power saved in idle mode IM is less than the power consumed by switching power modes (operation S323, "No"), in operation S420, the storage device 10 can maintain active mode AM without switching the power mode from active mode AM to idle mode IM. Even if the input prediction time is equal to or greater than the idle mode switching time (operation S311, "Yes") and the input prediction time is less than the sleep mode switching time (operation S313, "No"), if it is determined that there is no power saving effect (operation S323, "No"), active mode AM can be maintained without changing the power mode (operation S420).

[0100] Figure 10 This is a diagram illustrating the operation of a workload monitor 141 according to an exemplary embodiment of the present disclosure.

[0101] refer to Figure 10 The workload monitor 141 can receive commands queued from the command queue 130 and can store idle history corresponding to the commands. The idle history can include information about the idle time spent until the storage device receives a specific command from the host device and then receives the next command. Therefore, the idle history can include information about the first to the nth idle time (e.g., idle Time_1 to idle Time_n), and the information related to idle time stored in the workload monitor 141 can increase over time.

[0102] For example, when a first command CMD1 and a second command CMD2 are received sequentially in command queue 130, information relating to the nth idle time (e.g., idle time_n) from the input of the first command CMD1 until the input of the second command CMD2 can be stored as idle history in workload monitor 141. When storage device 10 receives a new command after the second command CMD2, workload monitor 141 can send the idle history, including information relating to the nth idle time (e.g., idle time_n), as workload information IWL to idle predictor 143.

[0103] Figure 11 This is a diagram illustrating a method of operating a storage device 10 according to an exemplary embodiment of the present disclosure. It can be... Figure 3 After the operation S70 is executed Figure 11 The operations S80 and S90, and in the exemplary embodiment, can be performed by... Figure 10 Workload Monitor 141 Execution Figure 11 Operations S80 and S90.

[0104] refer to Figure 1 and Figure 11 In operation S80, storage device 10 can calculate the idle time between the first command CMD1 and the second command CMD2. For example, the storage device can calculate the idle time between the time when the first command CMD1 is received and the time when the second command CMD2 is received. Storage device 10 can receive the first command CMD1 and then receive the second command CMD2. At this time, storage device 10 can maintain active mode AM after receiving the first command CMD1 and perform the operation of processing the second command CMD2 when the second command CMD2 is input. Alternatively, after performing the operation for processing the first command CMD1, storage device 10 can change the power mode from active mode AM to low power mode LPM and then return to active mode AM to process the second command CMD2.

[0105] In operation S90, storage device 10 can store information related to the idle time calculated in operation S80 as idle history in power mode manager 140; that is, the idle history of power mode manager 140 can be updated. The idle history can be used by storage device 10 to predict the input prediction time of the third command after the second command CMD2. Therefore, with respect to storage device 10 according to this disclosure, as the number of commands CMD received from host device 20 increases, the idle history can be gradually updated, and the accuracy of predicting the input prediction time of the next command CMD can be increased.

[0106] Figure 12 This is a block diagram illustrating a storage system 1000a according to an exemplary embodiment of the present disclosure.

[0107] refer to Figure 12 Storage system 1000a may include storage device 100 and host device 20. Storage device 10a may include storage controller 100a, non-volatile memory 200, power mode manager 130a, voltage generator 300, and clock signal generator 400. Figure 1 Compared to storage device 10, the power mode manager 130a can be configured as a separate module from the storage controller 100a. (See reference...) Figures 1 to 11 The description of the power mode manager 140 can be applied to the power mode manager 130a.

[0108] Upon receiving a command CMD, the power mode manager 130a can predict the input prediction time of the next command CMD and change the power mode of the storage device 10a based on the predicted input prediction time. The power mode manager 130a can determine whether to change the power mode from active mode AM to low power mode based on the predicted input prediction time and set the return time from low power mode LPM back to active mode AM. The power mode manager 130a can generate a mode change signal PM and send the mode change signal PM to at least one of voltage generator 300 and clock signal generator 400, thereby enabling the change of the power mode of the storage device 10a.

[0109] For example, when a first command CMD1 is received from host device 20, power mode manager 130a can predict the input prediction time when a second command CMD2 will be input to storage device 10a by using workload information corresponding to the first command CMD1. Power mode manager 130a can set the return time from low power mode LPM to active mode AM based on the input prediction time, and can generate a mode change signal PM to return to active mode AM before receiving the second command CMD2.

[0110] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device operating in multiple power modes, the multiple power modes including an active mode and a low-power mode, the low-power mode consuming less power than the active mode, the storage device comprising: Non-volatile memory, comprising multiple non-volatile memory cells; as well as The storage controller is configured to process commands input from the host device in the said active mode. The storage controller includes a power mode manager configured to adjust the plurality of power modes. The power mode manager is configured to: predict the input prediction time of a second command to be input from the host device after the first command when the first command is input; change from the active mode to the low power mode when the processing operation of the first command is completed; and return from the low power mode to the active mode when the return time has elapsed with the input prediction time. The power mode manager is further configured to: compare the input prediction time with the mode switching time taken to return from the low-power mode to the active mode; compare the energy saved by executing the low-power mode with the energy consumed by changing from the active mode to the low-power mode; and set the return time based on the input prediction time and the mode switching time. The power mode manager is further configured to change from the active mode to the low power mode based on the comparison result.

2. The storage device of claim 1, wherein, The power mode manager is also configured to return from the low power mode to the active mode when the second command is entered before the return time has elapsed.

3. The storage device of claim 1, wherein, The power mode manager includes: A workload monitor is configured to output workload information including idle history, the idle history including information about idle time, the idle time being the interval between each of a plurality of commands being entered at time; An idle predictor is configured to perform a prediction operation on the input prediction time using the workload information, and output prediction result data based on the operation result; and A return time determiner is configured to use the prediction result data to set the return time.

4. The storage device of claim 3, wherein, The workload information also includes at least one of the following: the size of the first command, the type of the first command, and information about the continuity of the logical block address corresponding to the first command.

5. The storage device of claim 1, wherein, The power mode manager sets the return time based on the input prediction time and the time taken to return from the low power mode to the active mode.

6. A method for operating a storage device in multiple power modes, the multiple power modes including an active mode and a low-power mode, the low-power mode consuming less power than the active mode, the method comprising: Receive the first command from the host device; Predict the input prediction time when a second command will be input from the host device after the first command; Based on the input prediction time, set the return time from the low power mode to the active mode on the timer; When the processing of the first command is completed, switch from the active mode to the low power mode; as well as When the return time has elapsed, the system returns from the low-power mode to the active mode. Setting the return time on the timer includes: The input prediction time is compared with the mode switching time taken to return from the low-power mode to the active mode; The energy saved by implementing the low-power mode is compared with the energy consumed by changing from the active mode to the low-power mode; and Based on the input prediction time and the mode switching time, the return time is set on the timer, and The switching from the active mode to the low power mode includes: switching from the active mode to the low power mode based on the comparison result of the comparison.

7. The method according to claim 6, wherein The low-power mode also includes an idle mode and a sleep mode, wherein the power consumption of the sleep mode is lower than that of the idle mode, and Setting the return time on the timer includes: The input prediction time is compared with the sleep mode switching time taken to return from the sleep mode to the activity mode; Compare the input prediction time with the idle mode switching time taken to return from the idle mode to the active mode; and The return time is set on the timer based on the input prediction time, the sleep mode switching time, and the idle mode switching time.

8. The method of claim 7, wherein, Setting the return time on the timer further includes: if the input prediction time is greater than the sleep mode switching time, comparing the power saved by executing the sleep mode with the power consumed by changing the power mode.

9. The method of claim 7, wherein, Setting the return time on the timer further includes: if the input prediction time is less than the sleep mode switching time and greater than the idle mode switching time, then comparing the power saved by executing the idle mode with the power consumed by changing the power mode.

10. The method of claim 6, wherein, Predicting the input prediction time includes using idle history, including information about idle time, to predict the input prediction time, where idle time is the interval between the times of each of a plurality of commands being input.

11. The method of claim 10, further comprising: Enter the second command; as well as The idle history is updated by storing the idle time between the time the first command was entered and the time the second command was entered in the idle history.

12. A storage device operating in multiple power modes, the multiple power modes including an active mode and a low-power mode, the low-power mode consuming less power than the active mode, the storage device comprising: Non-volatile memory, comprising multiple non-volatile memory cells; The storage controller is configured to process commands input from the host device in the active mode; as well as The power mode manager is configured to adjust the multiple power modes. The power mode manager is further configured to: predict the input prediction time of a second command to be input from the host device after the first command when the first command is input; change from the active mode to the low power mode when the processing operation of the first command is completed; and return from the low power mode to the active mode when the return time has elapsed with the input prediction time. The power mode manager is further configured to: compare the input prediction time with the mode switching time taken to return from the low-power mode to the active mode; compare the energy saved by executing the low-power mode with the energy consumed by changing from the active mode to the low-power mode; and set the return time based on the input prediction time and the mode switching time. The power mode manager is further configured to change from the active mode to the low power mode based on the comparison result.

13. The storage device according to claim 12, further comprising: A voltage generator is configured to provide an internal voltage to each of the non-volatile memory and the memory controller. The power mode manager is further configured to send a mode change signal to the voltage generator when the return time has elapsed. The voltage generator is further configured to change the amplitude of the internal voltage in response to the mode change signal.

14. The storage device of claim 12, further comprising: A clock signal generator provides a clock signal to the memory controller. The power mode manager is further configured to send a mode change signal to the clock signal generator when the return time has elapsed. The clock signal generator is further configured to change the frequency of the clock signal in response to the mode change signal.

15. The storage device of claim 12, wherein, The power mode manager is configured to return from the low power mode to the active mode when the second command is entered before the return time has elapsed.

16. The storage device of claim 12, wherein, The power mode manager includes: A workload monitor is configured to receive the first command from the storage controller and output workload information including idle history, the idle history including information about idle time, the idle time being the interval between each of the input of a plurality of commands; An idle predictor is configured to perform an operation to predict the input prediction time using the workload information, and to output prediction result data based on the operation result; and A return time determiner is configured to use the prediction result data to set the return time.

17. The storage device according to claim 16, wherein, The power mode manager also includes processing circuitry, and The workload monitor, the idle predictor, and the return time determiner are executed by the processing circuit.

18. The storage device according to claim 17, wherein The idle predictor includes a neural network model, and wherein the neural network model is executed by the processing circuitry such that operations for predicting the input prediction time are performed.

19. The storage device of claim 16, wherein, When receiving the second command from the storage controller, the workload monitor is further configured to update the idle history by calculating an idle time, the idle time being an interval between a time point of inputting the first command and a time point of inputting the second command.

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