A gate driving circuit, method, display panel and timing controller

Abstract

The present invention discloses a gate drive circuit, method, display panel and timing controller, wherein the gate drive circuit comprises: a first trigger signal line, a second trigger signal line and a plurality of GOA groups; a plurality of GOA groups are arranged in sequence; each GOA group comprises m rows of GOA units arranged in sequence, m being an even number; in the first group of GOA groups, the first trigger signal line connects the trigger port of the odd-numbered GOA units, and the second trigger signal line connects the trigger port of the even-numbered GOA units; for any GOA group, the output port of the GOA unit in the GOA group is cascaded with the trigger port of the GOA unit at the corresponding position in the latter GOA group; for any GOA unit, the first reset port of the GOA unit is cascaded with the output port of the corresponding n subsequent GOA units, n being an even number. The present invention can effectively control the cost of high-resolution products and is compatible with a variety of high refresh rate modes of display panels.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate drive circuit, method, display panel and timing controller. Background Art

[0002] With the development of 5G (5th Generation Mobile Communication Technology), the upper limit of data transmission has been greatly improved; therefore, high-resolution displays have gradually become popular, and various TV manufacturers have begun to launch high-resolution products. Panel manufacturers have also responded quickly to market demand and quickly invested manpower in the research and development of high-resolution products, such as 8K resolution products. In addition to high PPI (Pixels Per Inch, pixel density), high-resolution products also require high refresh rates. However, due to the high cost of circuit materials for high-resolution products, achieving a high refresh rate will cause the cost of the product to rise rapidly.

[0003] Therefore, there is an urgent need for a solution that can effectively control the cost of high-resolution products and is compatible with high refresh rates. Summary of the invention

[0004] In view of the above problems, the present invention proposes a gate driving circuit, method, display panel and timing controller, which can effectively control the cost of high-resolution products and are compatible with multiple high refresh rate modes of the display panel.

[0005] In the first aspect, the present application provides the following technical solution through an embodiment:

[0006] A gate drive circuit comprises: a first trigger signal line, a second trigger signal line and a plurality of GOA groups; the plurality of GOA groups are arranged in sequence; each of the GOA groups comprises m rows of GOA units arranged in sequence, m being an even number; in the first group of GOA groups, the first trigger signal line is connected to the trigger ports of the GOA units in odd rows, and the second trigger signal line is connected to the trigger ports of the GOA units in even rows; for any GOA group, the output ports of the GOA units in the GOA group are cascaded with the trigger ports of the GOA units at corresponding positions in the next GOA group; for any GOA unit, the first reset port of the GOA unit is cascaded with the output ports of the corresponding n subsequent GOA units, n being an even number.

[0007] Optionally, it also includes: a reset signal line; the reset signal line is connected to the second reset port of each of the GOA units.

[0008] Optionally, it also includes multiple clock signal lines, and the multiple clock signal lines are cyclically connected to the GOA units in sequence.

[0009] Optionally, the number of the clock signal lines is an even number and is not less than 16.

[0010] Optionally, the number of the clock signal lines is 16, m is 8, and n is 12.

[0011] Optionally, it also includes n virtual GOA units; the n virtual GOA units are arranged in sequence; the first reset ports of the last n GOA units are respectively connected to the output ports of the n virtual GOA units.

[0012] In the second aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0013] A gate driving method, applied to the gate driving circuit described in any one of the first aspects above, characterized in that the method includes: after all GOA units are reset before a frame, outputting a first pulse trigger signal to the odd-row GOA units through the first trigger signal line, and outputting a second pulse trigger signal to the even-row GOA units through the second trigger signal line; wherein the first trigger signal line and the second trigger signal line enable the corresponding GOA units to perform row-by-row scanning; and outputting a clock signal to the clock port of the GOA unit to maintain the original refresh rate of the display panel or increase the refresh rate of the display panel.

[0014] Optionally, the number of the clock signals is 16, including the first clock signal to the sixteenth clock signal in sequence; outputting the clock signal to the clock port of the GOA unit through the clock signal line includes:

[0015] The pulses of the third clock signal, the fourth clock signal, the seventh clock signal, the eighth clock signal, the eleventh clock signal, the twelfth clock signal, the fifteenth clock signal and the sixteenth clock signal in the clock signal are respectively advanced by 2H; wherein H represents the time required for scanning one line in the display panel to maintain the original refresh rate; the adjusted clock signal is output to the corresponding clock port of the GOA unit to increase the refresh rate of the display panel.

[0016] Optionally, the number of the clock signals is 16, including the first clock signal to the sixteenth clock signal in sequence; outputting the clock signal to the clock port of the GOA unit through the clock signal line includes:

[0017] The pulses of the second clock signal, the fourth clock signal, the sixth clock signal, the eighth clock signal, the tenth clock signal, the twelfth clock signal, the fourteenth clock signal and the sixteenth clock signal in the clock signal are respectively advanced by 1H; wherein H represents the time required for scanning one line in the display panel to maintain the original refresh rate; the adjusted clock signal is output to the corresponding clock port of the GOA unit to increase the refresh rate of the display panel.

[0018] In the third aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0019] A display panel comprises any gate driving circuit described in the first aspect above.

[0020] In the fourth aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0021] A display device comprises a display panel and a driving circuit for driving the display panel, wherein the driving circuit comprises any gate driving circuit described in the first aspect above.

[0022] In the fifth aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0023] A timing controller having a computer program stored thereon, which implements the steps of any one of the methods described in the first aspect when the program is executed.

[0024] A gate drive circuit provided by an embodiment of the present invention comprises: a first trigger signal line, a second trigger signal line and a plurality of GOA (Gate driver On Array, array gate drive) groups; a plurality of GOA groups are arranged in sequence; each GOA group comprises m rows of GOA units arranged in sequence, m being an even number; in the first group of GOA groups, the first trigger signal line connects the trigger port of the odd-numbered GOA unit, and the second trigger signal line connects the trigger port of the even-numbered GOA unit; for any GOA group, the output port of the GOA unit in the GOA group is cascaded with the trigger port of the GOA unit at the corresponding position in the latter GOA group; for any GOA unit, the first reset port of the GOA unit is cascaded with the output port of the corresponding n-th GOA unit, n being an even number. The above-mentioned gate drive circuit can be well compatible with dual gate line drive (Dual Gate) design, effectively reducing manufacturing cost. At the same time, by independently controlling the odd and even rows of the GOA unit, the display panel can be made compatible with a higher refresh rate by adjusting the timing of the pulse signal.

[0025] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0027] Figure 1 A schematic diagram of a circuit structure of a portion of a gate driving circuit provided by an embodiment of the present invention is shown;

[0028] Figure 2 Shows Figure 1 Schematic diagram of the enlarged structure of the A area in the middle;

[0029] Figure 3 Another circuit structure diagram of a gate driving circuit provided by an embodiment of the present invention is shown;

[0030] Figure 4 A flow chart of a gate driving method provided by an embodiment of the present invention is shown;

[0031] Figure 5 A signal timing diagram of a gate driving circuit in an embodiment of the present invention when it is working is shown;

[0032] Figure 6 Another signal timing diagram when the gate driving circuit in the embodiment of the present invention works is shown;

[0033] Figure 7 Another signal timing diagram of the gate driving circuit in the embodiment of the present invention is shown.

[0034] Reference numerals: 11 - first trigger signal line; 12 - second trigger signal line; 20 - GOA group; 21 - GOA group; 22 - GOA group; 31 - clock signal line; 51 - reset signal line. DETAILED DESCRIPTION

[0035] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] First embodiment

[0037] See also Figure 1 A gate drive circuit provided in an embodiment of the present invention can be well compatible with a dual gate drive (Dual Gate) design when working. The Dual Gate design is an existing pixel connection architecture. The gate drive circuit includes: a first trigger signal line 11, a second trigger signal line 12, a plurality of GOA (Gate driver On Array, array gate drive) groups 20, a plurality of clock signal lines 31 and a reset signal line 51.

[0038] Specifically, multiple GOA groups 20 are arranged in sequence; each GOA group 20 contains m rows of GOA units arranged in sequence, m is an even number, and one GOA unit is a row. In the first group of GOA groups 21, the trigger port of the odd-numbered GOA unit connected by the first trigger signal line 11, and the trigger port of the even-numbered GOA unit connected by the second trigger signal line 12; for any GOA group 20, the output port of the GOA unit in the GOA group 21 is cascaded with the trigger port of the GOA unit at the corresponding position in the next GOA group 22. Further, for any GOA unit, the first reset port of the GOA unit is cascaded with the output port of the corresponding GOA unit after n, n is an even number; multiple clock signal lines 31 are cyclically connected to the GOA units in sequence. The reset signal line 51 is connected to the second reset port of each GOA unit. In this way, multiple GOA units are divided into two groups, an odd array and an even array, and there is no signal connection relationship between each group of GOA units, which are independent of each other and do not affect each other.

[0039] The composition architecture of the GOA unit is not limited. For example, a circuit structure of the P21T1C architecture can be used in a high-resolution display panel to improve reliability. P21T1C represents a driving circuit composed of 21 TFTs (Thin Film Transistors) and 1 capacitor. For details, reference can be made to the existing implementation method, which will not be repeated in this embodiment.

[0040] The number of clock signal lines 31 and GOA units can be determined by the resolution of the driven display panel. For example, in an 8K display panel, the number of GOA units is 4320; the number of clock signal lines 31 is an even number. Specifically, it can be no less than 16, such as 16, 32, and so on. No less than 16 can ensure that a suitable number of GOA units are connected to each clock signal line 31, and the relative number of connections of the GOA units of each clock signal line 31 is reduced, which reduces the load of each clock signal line 31 and avoids the level reduction. Therefore, even when the mobility of carriers in the TFT is reduced under low temperature conditions, the TFT can be guaranteed to open normally, thereby improving the reliability of low temperature startup of the GOA unit. Furthermore, since a large number of clock signal lines 31 is not conducive to the design of a narrow frame of the display panel, the number of clock signal lines 31 can be determined to be 16 after comprehensive consideration of factors such as the low temperature tolerance, cost, compatibility, and frame design of the display panel. When a design of 16 clock signal lines 31 is adopted in an 8K display panel, better compatibility and reliability can be ensured, as well as controllable cost and border design.

[0041] Furthermore, in order to reset the last n rows of GOA units, the gate driving circuit further includes: n dummy GOA units. The n dummy GOA units are arranged in sequence; and the first reset ports of the last n GOA units are respectively connected to the output ports of the n dummy GOA units.

[0042] At this time, the output ports of the GOA units in the last group of GOA groups 20, that is, the last m rows of GOA units, are sequentially cascaded with the trigger ports of the first m rows of virtual GOA units; the first reset ports of the last n GOA units are sequentially connected with the output ports of the n virtual GOA units. The output ports of the first nm rows of virtual GOA units are sequentially cascaded with the trigger ports of the n-m+1th to nth virtual GOA units. The reset signal line 51 is connected to the first reset port and the second reset port of the virtual GOA unit to ensure that the last n GOA units can be accurately reset and trigger line-by-line scanning.

[0043] In this embodiment, m can be 4 and n can be 8; m can be 8 and n can be 12; m can be 12 and n can be 16, and so on. Preferably, when the number of clock signal lines 31 is 16 and is applied to a display panel with a resolution of 8K, m can be 8 and n can be 12. In this way, after cascading, a group delay of 4H reset can be achieved during reset, which can improve the compatibility of 8K displays and avoid abnormal pulse waveforms of reset signals, thereby improving reliability. Among them, H represents the time required to scan 1 line in the display panel to maintain the original refresh rate. For example, for an 8K 120Hz display panel product, the scanning time for 1 line is only 1 / 120Hz / 4500 lines = 1.85us.

[0044] It should be noted that the 8K resolution in a 16:9 display panel is 7680×4320 pixels. The resolution may be different in screens of different ratios. Please refer to the relevant resolution standards or specifications for understanding or interpretation, and will not be repeated in the following text of this embodiment.

[0045] For an example, see Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the circuit structure of the initial part of the gate drive circuit when the number of clock signal lines 31 is 16, m is 8, and n is 12. The GOA units in the first GOA group 21 are Figure 1 The numbers in the sequence are: G1, G2, G3, G4, G5, G6, G7, G8; the GOA units in the second GOA group 22 are Figure 2 The numbers in are: G9, G10, G11, G12, G13, G14, G15, G16. The first trigger signal line 11 is cascaded with the trigger ports of the odd-numbered GOA units in the first group, that is, the trigger ports of G1, G3, G5, and G7; the output ports of G1, G3, G5, and G7 are cascaded with the trigger ports of the GOA units in the second GOA group 22: G9, G11, G13, and G15. The second trigger signal line 12 is cascaded with the trigger ports of the even-numbered GOA units in the first group, that is, the trigger ports of G2, G4, G6, and G8; the output ports of G2, G4, G6, and G8 are cascaded with the trigger ports of the GOA units in the second GOA group 22: G10, G12, G14, and G16. According to the cascade mode between the first GOA group 21 and the second GOA group 22, the cascade relationship between all GOA units can be obtained by analogy. That is, the input mode is: x→x+8, that is, the output of the xth GOA unit is input into the x+8th GOA unit, and x represents the xth GOA unit.

[0046] See also Figure 2 , Figure 2 Shows Figure 2 An enlarged schematic diagram of G1 (A region), wherein CLK is the clock port, Input is the trigger port, Out_c is the output port, Rst_PU is the first reset port, and Tot_Rst is the second reset port; other GOA units and the virtual GOA unit described later are the same as G1, which can be understood by reference and will not be repeated here.

[0047] Furthermore, in order to achieve delayed reset of the grouping, ensure the scanning control of the next frame and improve reliability, starting from the 13th GOA unit, its output port is also cascaded with the first reset port of the GOA unit before 12 rows (including the row where the output GOA unit is located). Please continue to refer to Figure 2Among them, the output ports of G13, G14, G15, and G16 are also connected to the first reset ports of G1, G2, G3, and G4 respectively.

[0048] See also Figure 3 , Figure 3 FIG. 1 is a circuit structure diagram of the end portion of the gate drive circuit when the number of clock signal lines 31 is 16, m is 8, and n is 12. In order to ensure that the GOA unit at the end can be reset, 12 virtual GOA units are set accordingly. Figure 3 The numbers in are: DUM1, DUM2, DUM3, DUM4, DUM5, DUM6, DUM7, DUM8, DUM9, DUM10, DUM11, DUM12, and they are cascaded with the first reset ports of the last 12 GOA units respectively. The trigger ports of DUM1, DUM2, DUM3, DUM4, DUM5, DUM6, DUM7, and DUM8 are cascaded with the output ports of the last 8 GOA units respectively; the output ports of DUM1, DUM2, DUM3, and DUM4 are cascaded with the trigger ports of DUM9, DUM10, DUM11, and DUM12.

[0049] See also Figure 1 and Figure 3 The reset signal line 51 connects the second reset ports of all GOA units and the first reset ports and the second reset ports of all virtual GOA units, ensuring that all GOA units and virtual GOA units can release charges and pull to a low level before driving.

[0050] It should be noted that, in this embodiment, the first trigger signal line 11 is used to transmit the first trigger signal to the GOA unit of the odd row; the second trigger signal line 12 is used to transmit the second trigger signal to the GOA unit of the even row; the first trigger signal and the second trigger signal are used to trigger the corresponding row to start scanning. The reset signal line 51 is used to transmit a reset signal to the GOA unit so that the corresponding TFT in the GOA releases the charge and pulls it to a low level to ensure that the GOA unit works correctly during subsequent scanning. Multiple clock signal lines 31 are used to transmit clock signals to the GOA unit, and the clock signals can be generated by a timing controller; the GOA unit is used to control the clock signal to output the GOA timing of a frame.

[0051] The gate drive circuit provided in this embodiment can be well combined with the Dual Gate design. Compared with the single gate line drive (Single Gate) design, the number of source chips (Source IC) can be reduced to half of the original, effectively reducing the cost of high-resolution product circuit materials. At the same time, considering the Gate delay (gate delay) and Data delay (data delay), the pixel has no charging time. The gate drive circuit of this embodiment can be effectively compatible with the DLG (Dual Line Gate, two lines of gate lines) mode and HSR (Hardware Super Resolution, hardware super resolution) mode after combining the Dual Gate design, thereby improving the refresh rate of the product.

[0052] Moreover, the gate driving circuit of this embodiment divides the GOA units into odd arrays and even arrays, and independently controls them. By adjusting the timing of the pulse signals of the odd rows and even rows, the gate driving circuit can be compatible with different refresh rate modes.

[0053] See also Figure 4 In this embodiment, a gate driving method is also provided, which can be applied to the above-mentioned gate driving circuit to achieve different refresh rates under different control modes. Specifically, the method includes:

[0054] Step S10: After all GOA units are reset before the frame, a first pulse trigger signal is output to the odd-row GOA units through the first trigger signal line, and a second pulse trigger signal is output to the even-row GOA units through the second trigger signal line; wherein the first trigger signal line and the second trigger signal line enable the corresponding GOA units to perform row-by-row scanning.

[0055] See also Figure 5 , in step S10, before the frame is before a frame scan. The way to reset the GOA unit is to release the charge of all GOA units through a reset signal STV0 transmitted through the reset signal line to complete the reset. At the same time, the virtual GOA unit can also be reset. Then, the first pulse trigger signal STV1_A is output to the odd-row GOA unit through the first trigger signal line, and the second pulse trigger signal STV1_B is output to the even-row GOA unit through the second trigger signal line; thereby the odd-row GOA unit and the even-row GOA unit are both triggered and start line-by-line scanning.

[0056] Step S20: outputting a clock signal to the clock port of the GOA unit to maintain the original refresh rate of the display panel or to increase the refresh rate of the display panel.

[0057] In step S20, since there is no signal connection between the odd-numbered GOA units and the even-numbered GOA units, they are independent of each other. Therefore, the time consumed by refreshing a frame can be changed by adjusting the clock signal. In this embodiment, a display panel with a number of 16 clock signals, a resolution of 8K4K (8K on the long side and 4K on the short side), and a refresh rate of 60HZ is used as an example for explanation. The 16 clock signals can be divided into an odd group and an even group, and the 16 clock signals include the first clock signal to the sixteenth clock signal in sequence.

[0058] The specific drive control process is as follows:

[0059] 1. Display with a resolution of 8K4K and a refresh rate of 60HZ.

[0060] Please refer to 5. When the phase difference between the clock signals of odd rows and the clock signals of even rows is 1H, 16 clock signals can be turned on row by row. At this time, the resolution of the display panel is 8K4K and the refresh rate is 60HZ.

[0061] 2. Display with a resolution of 8K2K (8K on the long side and 2K on the short side) and a refresh rate of 120HZ.

[0062] See also Figure 6 First, the pulses of the third clock signal, the fourth clock signal, the seventh clock signal, the eighth clock signal, the eleventh clock signal, the twelfth clock signal, the fifteenth clock signal and the sixteenth clock signal in the clock signal are respectively advanced by 2H; wherein H represents the time required for the display panel to scan one line at the original refresh rate. Then, the adjusted clock signal is output to the corresponding clock port of the GOA unit through the clock signal line to increase the refresh rate of the display panel.

[0063] At this time, in the 16 GOA units corresponding to a set of clock signals: the GOA units in the 1st and 3rd rows are turned on at the same time, the GOA units in the 2nd and 4th rows are turned on at the same time, the GOA units in the 5th and 7th rows are turned on at the same time, the GOA units in the 6th and 8th rows are turned on at the same time, the 9th and 11th rows are turned on at the same time, the 10th and 12th rows are turned on at the same time, the 13th and 15th rows are turned on at the same time, and the 14th and 16th rows are turned on at the same time, that is, the pth and p+2th rows are turned on at the same time, and p is the number of pixel rows of the display panel. The line-by-line scanning time is halved, compatible with the DLG mode, and the display efficiency of 8K2K resolution and 120Hz refresh rate is achieved.

[0064] 3. Display with a resolution of 4K4K (long side is 4K, short side is 4K) and a refresh rate of 120HZ.

[0065] See also Figure 7First, the pulses of the second clock signal, the fourth clock signal, the sixth clock signal, the eighth clock signal, the tenth clock signal, the twelfth clock signal, the fourteenth clock signal and the sixteenth clock signal in the clock signal are advanced by 1H respectively; wherein H represents the time required for the display panel to scan one line at the original refresh rate. Then, the adjusted clock signal is output to the clock port of the corresponding GOA unit through the clock signal line to increase the refresh rate of the display panel.

[0066] At this time, in the 16 GOA units corresponding to a set of clock signals: the GOA units in the 1st and 2nd rows are turned on at the same time, the GOA units in the 3rd and 4th rows are turned on at the same time, the GOA units in the 5th and 6th rows are turned on at the same time, the GOA units in the 7th and 8th rows are turned on at the same time, the 9th and 10th rows are turned on at the same time, the 11th and 12th rows are turned on at the same time, the 13th and 14th rows are turned on at the same time, and the 15th and 16th rows are turned on at the same time, that is, the pth and p+1th rows are turned on at the same time, and p is the number of pixel rows of the display panel. The line-by-line scanning time is halved, achieving a display efficiency of 4K4K resolution and 120Hz refresh rate.

[0067] It can be seen that in this embodiment, a gate driving method is provided, which realizes the independent control of odd and even on and off by grouping the GOA units; it can flexibly realize that each row of pixels is turned on row by row, and it can also realize that the p row and the p+1 row are turned on at the same time, and it can also realize that the p row and the p+2 row are turned on at the same time, thereby effectively doubling the refresh rate while reducing the resolution, and it can be compatible with the original refresh rate, and it is also compatible with at least two modes of increasing resolution. For example, 60Hz can be increased to 120Hz; 75Hz can be increased to 150Hz; 120Hz can be increased to 240Hz.

[0068] It should be noted that, in the gate driving method provided in this embodiment, its specific implementation and the technical effects produced are the same as those in the aforementioned gate driving circuit embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0069] Second embodiment

[0070] Based on the same inventive concept, a second embodiment of the present invention provides a display panel, which includes the gate driving circuit described in any one of the above-mentioned first embodiments.

[0071] It should be noted that the specific implementation and technical effects of the display panel provided in the embodiment of the present invention are the same as those of the first embodiment described above. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the method embodiment described above.

[0072] Third embodiment

[0073] Based on the same inventive concept, a third embodiment of the present invention provides a display device, including a display panel and a driving circuit for driving the display panel, wherein the driving circuit includes any gate driving circuit described in the first embodiment.

[0074] It should be noted that the specific implementation and technical effects of the display device provided in the embodiment of the present invention are the same as those of the first embodiment described above. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the method embodiment described above.

[0075] Fourth embodiment

[0076] Based on the same inventive concept, a fourth embodiment of the present invention further provides a timing controller having a computer program stored thereon, which implements the steps of any one of the methods described in the first embodiment when the program is executed.

[0077] It should be noted that, in the timing controller provided in the embodiment of the present invention, the specific implementation of each of the above steps and the technical effects produced are the same as those in the aforementioned first embodiment. For the sake of brief description, the parts not mentioned in this embodiment can be referred to the corresponding contents in the aforementioned method embodiment.

[0078] The term "and / or" that appears in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship; the word "comprising" does not exclude the existence of elements or steps that are not listed in the claims. The word "one" or "an" placed before an element does not exclude the existence of multiple such elements. The present invention can be implemented with the aid of hardware including several different elements and with the aid of appropriately programmed computers. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

[0079] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0081] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0083] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0084] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A gate drive circuit, characterized in that: include: a first trigger signal line, a second trigger signal line, and a plurality of GOA groups; The multiple GOA groups are arranged in sequence; each of the GOA groups contains m rows of GOA units arranged in sequence, where m is an even number; in the first GOA group, the first trigger signal line is connected to the trigger ports of the GOA units in odd rows, and the second trigger signal line is connected to the trigger ports of the GOA units in even rows; For any GOA group, the output port of the GOA unit in the GOA group is cascaded with the trigger port of the GOA unit at the corresponding position in the next GOA group; For any GOA unit, the first reset port of the GOA unit is cascaded with the output port of the corresponding n subsequent GOA units, where n is an even number; The gate drive circuit is configured to drive a dual gate line design; There is no signal connection relationship between the odd-numbered GOA units and the even-numbered GOA units, and they are independent of each other. The gate drive circuit can be compatible with different refresh rate modes by adjusting the timing of the pulse signals of the odd-numbered rows and the even-numbered rows. It also includes a plurality of clock signal lines, and the plurality of clock signal lines are cyclically connected to the GOA units in sequence.

2. The gate driving circuit according to claim 1, characterized in that: Also includes: Reset signal line; the reset signal line is connected to the second reset port of each GOA unit.

3. The gate driving circuit according to claim 1, characterized in that: The number of the clock signal lines is an even number and is not less than 16.

4. The gate driving circuit according to claim 1, characterized in that: The number of the clock signal lines is 16, m is 8, and n is 12.

5. The gate driving circuit according to claim 1, characterized in that: It also includes n virtual GOA units; the n virtual GOA units are arranged in sequence; the first reset ports of the last n GOA units are respectively connected to the output ports of the n virtual GOA units.

6. A gate driving method, applied to the gate driving circuit according to any one of claims 1 to 5, characterized in that: The method comprises: After all GOA units are reset before the frame, a first pulse trigger signal is output to the odd-numbered GOA units through the first trigger signal line, and a second pulse trigger signal is output to the even-numbered GOA units through the second trigger signal line; wherein the first trigger signal line and the second trigger signal line enable the corresponding GOA units to perform row-by-row scanning; A clock signal is output to the clock port of the GOA unit to maintain the original refresh rate of the display panel or to increase the refresh rate of the display panel.

7. The method according to claim 6, characterized in that The number of the clock signals is 16, including the first clock signal to the sixteenth clock signal in sequence; the clock signal is output to the clock port of the GOA unit through the clock signal line, including: The pulses of the third clock signal, the fourth clock signal, the seventh clock signal, the eighth clock signal, the eleventh clock signal, the twelfth clock signal, the fifteenth clock signal and the sixteenth clock signal in the clock signal are respectively advanced by 2H; wherein H represents the time required for scanning one line at the original refresh rate in the display panel; The adjusted clock signal is output to the corresponding clock port of the GOA unit through the clock signal line to increase the refresh rate of the display panel.

8. The method according to claim 6, characterized in that The number of the clock signals is 16, including the first clock signal to the sixteenth clock signal in sequence; the clock signal is output to the clock port of the GOA unit through the clock signal line, including: The pulses of the second clock signal, the fourth clock signal, the sixth clock signal, the eighth clock signal, the tenth clock signal, the twelfth clock signal, the fourteenth clock signal and the sixteenth clock signal in the clock signal are respectively advanced by 1H; wherein H represents the time required for scanning one line at the original refresh rate in the display panel; The adjusted clock signal is output to the corresponding clock port of the GOA unit through the clock signal line to increase the refresh rate of the display panel.

9. A display panel, characterized in that: The gate drive circuit comprises any one of claims 1 to 5.

10. A display device, characterized in that: It comprises a display panel and a driving circuit for driving the display panel, wherein the driving circuit comprises the gate driving circuit according to any one of claims 1-5.

11. A timing controller having a computer program stored thereon, characterized in that: When the program is executed, the steps of the method described in any one of claims 6 to 8 are implemented.

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