A high refresh rate display screen driving method and device

Abstract

This invention discloses a high refresh rate display screen driving method and apparatus. The method includes the following steps: providing a driving apparatus, wherein a timing unit in the apparatus provides a clock signal and a pulse width signal to a level unit; providing a display panel circuit; using the level unit to control the number of high-level events of each gate line within one frame cycle; using a control unit to obtain the timing interval between two adjacent high levels, and using the timing interval to control the refresh rate of the display panel. By using the level unit to control the number of high-level events of each gate line within one frame cycle and using the control unit to obtain the timing interval between two adjacent high levels, and using the timing interval to control the refresh rate of the display panel, a corresponding timing interval value can be set when producing display screen products in the field of competitive displays to improve the refresh rate of the display screen and improve display quality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a high refresh rate display driving method and apparatus. Background Technology

[0002] The display panel includes multiple scan lines, multiple data lines, multiple sub-pixels, and multiple switching circuits corresponding to each sub-pixel. When the display panel is working, the multiple scan lines output scan signals sequentially, with each scan line outputting a scan signal for an equal duration. These scan signals are used to control the switching circuits. While each scan line outputs a scan signal, the multiple data lines output data signals to the corresponding sub-pixels through the activated switching circuits, causing the corresponding sub-pixels to emit light. Specifically, the horizontally distributed gate lines control the on / off state of the pixel TFTs, and the vertically distributed source lines write the desired data line voltage to the pixel TFTs. When the gate line is high, the pixel TFT is on, and the data line voltage enters the parallel-connected liquid crystal capacitor and storage capacitor; when the gate line is low, the pixel TFT is off, and the data line voltage cannot enter the liquid crystal capacitor and storage capacitor. The data line voltage adjusts the transmittance of the liquid crystal.

[0003] Existing display panels cannot meet the refresh rate requirements of the competitive display field, and the display quality needs to be improved. Summary of the Invention

[0004] The existing display panels have low refresh rates when running competitive video games, which fails to meet the display quality requirements.

[0005] To address the aforementioned issues, a high refresh rate display driving method and apparatus are proposed. By utilizing a level unit to control the number of high-level events of each gate line within a frame cycle and using a control unit to obtain the timing interval between two adjacent high levels, the refresh rate of the display panel is controlled using the timing interval. When producing display products for the competitive display field, an appropriate timing interval value can be set to improve the refresh rate and display quality of the display.

[0006] In a first aspect, a high refresh rate display driving method includes:

[0007] Step 100: A driving device is provided, the driving device including a timing unit, a level unit and a control unit, the timing unit being electrically connected to the level unit, the timing unit and the level unit being electrically connected to the control unit respectively, and the timing unit being used to provide a clock signal and a pulse width signal to the level unit;

[0008] Step 200: Provide a display panel circuit, wherein the level unit is electrically connected to each stage of the gate line in the display panel circuit;

[0009] Step 300: Use the level unit to control the number of high-level times of each gate line within a frame period;

[0010] Step 400: Use the control unit to obtain the timing interval between two adjacent high levels, and use the timing interval to control the refresh rate of the display panel;

[0011] The high level is used to turn on the gate line, and the high level pulse widths in the gate line are equal.

[0012] In conjunction with the high refresh rate display driving method described in this invention, in a first possible implementation, step 200 includes:

[0013] Step 210: Electrically connect the drain of the pixel transistor to the even-numbered data lines, connect the source of the pixel transistor to the pixel, and connect the gate of the pixel transistor to the odd-numbered gate lines.

[0014] Step 220: Electrically connect the drain of the pixel transistor to the odd-numbered data lines, connect the source of the pixel transistor to the pixel, and connect the gate of the pixel transistor to the even-numbered gate lines.

[0015] In conjunction with the first possible embodiment of the first aspect of the present invention, in the second possible embodiment, step 400 includes:

[0016] Step 410: Use the level unit to control the gate line to output a high level, and sequentially turn on the odd-numbered data lines and even-numbered data lines to transmit data voltage to the display panel;

[0017] Step 420: If the difference in the number of adjacent gate lines is equal to the timing interval, then the first row of gate lines and the next row of gate lines are turned on.

[0018] In conjunction with the second possible embodiment of the first aspect of the present invention, in the third possible embodiment, step 400 further includes:

[0019] Step 430: Obtain timing interval information;

[0020] Step 440: Compare the timing interval with a specified threshold. If it is less than the specified threshold, then determine that the refresh rate meets the specified requirements.

[0021] The specified threshold is the maximum timing interval value that meets the refresh rate requirement.

[0022] In conjunction with the third possible implementation of the first aspect of the present invention, in the fourth possible implementation, the specified threshold for the timing interval is 5.

[0023] In a second aspect, a high refresh rate display driving device is provided, which drives the display using the method described in the first aspect, wherein:

[0024] Timing unit;

[0025] Level unit;

[0026] Control unit;

[0027] The timing unit is electrically connected to the level unit;

[0028] The timing unit and the level unit are also electrically connected to the control unit;

[0029] The control unit is electrically connected to the display panel circuit of the display screen;

[0030] The timing unit is used to provide clock signals and pulse width signals to the level unit;

[0031] The level unit is used to control the number of high-level times for each gate line within a frame period;

[0032] The control unit is used to acquire timing interval information between two adjacent high levels and to control the refresh rate of the display panel using the timing interval;

[0033] The high level is used to turn on the gate line, and the high level pulse widths in the gate line are equal.

[0034] In conjunction with the high refresh rate display screen driving device described in this invention, in a first possible embodiment, the display panel circuit structure is as follows:

[0035] The drain of the pixel transistor is electrically connected to the even-numbered column data lines, the source of the pixel transistor is connected to the pixel, and the gate of the pixel transistor is connected to the odd-numbered row gate lines.

[0036] The drain of the pixel transistor is electrically connected to the odd-numbered column data lines, the source of the pixel transistor is connected to the pixel, and the gate of the pixel transistor is connected to the even-numbered row gate lines.

[0037] In conjunction with the first possible implementation of the second aspect of the present invention, in the second possible implementation, the level unit is further used to control the gate line to output a high level, thereby sequentially turning on the odd-numbered data lines and the even-numbered data lines to transmit data voltage to the display panel;

[0038] The control unit is also used for:

[0039] The timing interval is used to determine if the difference in the number of rows of adjacent gate lines is equal to the timing interval. Then, the level unit is controlled to turn on the first row of gate lines and the next row of gate lines.

[0040] In conjunction with the second possible embodiment of the second aspect of the present invention, in the third possible embodiment, the control unit is further configured to:

[0041] Obtain timing interval information;

[0042] The timing interval is compared with a specified threshold. If it is less than the specified threshold, the refresh rate is determined to meet the specified requirements.

[0043] The specified threshold is the maximum timing interval value that meets the refresh rate requirement.

[0044] In conjunction with the third and fourth possible embodiments of the second aspect of the present invention, the specified threshold is 5.

[0045] The high refresh rate display driving method and apparatus described in this invention utilizes a level unit to control the number of high-level events of each gate line within a frame cycle and a control unit to obtain the timing interval between two adjacent high levels. By using the timing interval to control the refresh rate of the display panel, a corresponding timing interval value can be set when producing display products for the competitive display field to improve the refresh rate and display quality of the display. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the connection of the drive device module in this invention;

[0048] Figure 2 This is a schematic diagram of the display panel circuit structure in this invention;

[0049] Figure 3 This is a timing control diagram for each gate line of the present invention;

[0050] Figure 4 This is a first schematic diagram of the driving method in this invention;

[0051] Figure 5 This is a second schematic diagram of the driving method in this invention;

[0052] Figure 6 This is a third schematic diagram of the driving method in this invention;

[0053] Figure 7 This is a fourth schematic diagram of the driving method in this invention. Detailed Implementation

[0054] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0056] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0057] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] The existing display panels have low refresh rates when running competitive video games, which fails to meet the display quality requirements.

[0060] To address the above issues, a high refresh rate display driving method and apparatus are proposed.

[0061] Example 1

[0062] Firstly, such as Figure 4 , Figure 4This is a first schematic diagram of the driving method in this invention; a high refresh rate display screen driving method includes:

[0063] Step 100: Provide a driving device, such as... Figure 1 , Figure 1 This is a schematic diagram of the drive device module connection in this invention; the drive device includes a timing unit 10, a level unit 20, and a control unit 30. The timing unit 10 is electrically connected to the level unit 20, and the timing unit 10 and the level unit 20 are also electrically connected to the control unit 30. The timing unit 10 is used to provide a clock signal and a pulse width signal to the level unit 20. Step 200: A display panel circuit 40 is provided, and the level unit 20 is electrically connected to each level of gate line in the display panel circuit 40. Step 300: The level unit 20 is used to control the number of high-level times of each gate line in one frame period. Step 400: The control unit 30 is used to obtain the timing interval between two adjacent high levels, and the timing interval is used to control the refresh rate of the display panel. Among them, the high level is used to turn on the gate line, and the high-level pulse width in the gate line is equal.

[0064] When the gate line is high, the transistor connected to the gate line is turned on, and the data line connected to the transistor can input data voltage to the pixel unit in the panel.

[0065] The display panel circuit 40 consists of transistors on two adjacent rows of gate lines and their connected pixel units cascaded at odd and even intervals.

[0066] The timing unit 10 is used to provide clock signals and pulse width signals to the level unit 20, control the number of high-level times of each row of gate lines using the level unit 20, and calculate and obtain the timing interval information between two adjacent high levels using the control unit 30. The refresh rate of the display panel is controlled by setting the timing interval value.

[0067] Furthermore, the display panel circuit 40 is, as follows: Figure 2 , Figure 2 Here is a schematic diagram of the display panel circuit 40 in this invention:

[0068] like Figure 5 , Figure 5 This is a second schematic diagram of the driving method in this invention; step 200 includes:

[0069] Step 210: Electrically connect the drain of the pixel transistor to the even-numbered data lines, connect the source of the pixel transistor to the pixel, and connect the gate of the pixel transistor to the odd-numbered gate lines; Step 220: Electrically connect the drain of the pixel transistor to the odd-numbered data lines, connect the source of the pixel transistor to the pixel, and connect the gate of the pixel transistor to the even-numbered gate lines.

[0070] Drain and even-numbered data lines (S2, S4, S6, S8, S10, ..., S...) 2n The pixel transistors are electrically connected, with their gates connected to the odd-numbered rows (G1, G3, G5, G7, G9, ..., G...). 2n-1 The gate line is electrically connected, and the drain is connected to the odd-numbered data lines (S1, S3, S5, S7, S9, ..., S...). 2n-1 The pixel transistors are electrically connected, with their gates connected to the even-numbered rows (G2, G4, G6, G8, G10, ..., G...). 2n Gate line electrical connection.

[0071] Preferably, such as Figure 6 , Figure 6 This is a third schematic diagram of the driving method in this invention; step 400 includes: step 410, using the level unit 20 to control the gate line to output a high level, sequentially turning on the odd-numbered data lines and even-numbered data lines to transmit data voltage to the display panel, such as... Figure 3 , Figure 3 This is a timing control diagram for each gate line of the present invention; Step 420: If the difference in the number of rows of adjacent gate lines is equal to the timing interval, then the first row of gate lines and the next row of gate lines are turned on.

[0072] Refresh rate control principle: When gate line G1 is high, it enables data lines S2, S4, S6, S8, and S10 to supply data voltage (Data) to the panel. Then, G1 is low, enabling it to turn off. Similarly, when gate line G2 is high, data lines S1, S3, S5, S7, and S9 supply data to the panel. Then, G2 is low, enabling it to turn off. This continues until the fifth row of data is written. Then, G1 and G6 are simultaneously enabled, with a timing interval of 5 seconds. After G1 is enabled, data lines S2, S4, S6, S8, and S10 supply data voltage (Data); after G6 is enabled, data lines S1, S3, S5, S7, and S9 supply data voltage (Data). This process continues until G2 and G7 are enabled, until the entire panel data is written.

[0073] The refresh rate control method in this embodiment allows the entire screen to be refreshed twice within one frame, meaning the refresh rate is doubled compared to traditional display panels within one second. This increased refresh rate improves display quality. By using the level unit 20 to control the number of high-level events on each gate line within a frame cycle and using the control unit 30 to obtain the timing interval between two adjacent high levels, the refresh rate of the display panel can be controlled using this timing interval. This allows for setting appropriate timing interval values ​​when producing display products for competitive gaming applications, thereby increasing the refresh rate and improving display quality.

[0074] Furthermore, such as Figure 7 , Figure 7 This is a fourth schematic diagram of the driving method in this invention. Step 400 further includes: step 430, obtaining timing interval information; step 440, comparing the timing interval with a specified threshold, and if it is less than the specified threshold, determining that the refresh rate meets the specified requirements; wherein, the specified threshold is the maximum timing interval value that meets the refresh rate requirements. The smaller the timing interval value, the higher the refresh rate of the display panel controlled by it. The specified threshold is a critical threshold; if the timing interval is less than or equal to the specified threshold, its refresh rate reaches or exceeds the refresh rate performance requirements.

[0075] Example 2

[0076] Secondly, such as Figure 1 A high refresh rate display driving device is disclosed, employing a first aspect of the method for driving the display. The device includes a timing unit 10, a level unit 20, and a control unit 30. The timing unit 10 and level unit 20 are electrically connected to the control unit 30. The control unit 30 is electrically connected to the display panel circuit 40 of the display screen. The timing unit 10 provides a clock signal and a pulse width signal to the level unit 20. The level unit 20 controls the number of high-level pulses per gate line within one frame period. The control unit 30 acquires timing interval information between two adjacent high levels and uses the timing interval to control the refresh rate of the display panel. The high level is used to activate the gate line, and the high-level pulse widths in the gate lines are equal.

[0077] Furthermore, the structure of the display panel circuit 40 is as follows:

[0078] like Figure 2 The drain of the pixel transistor is electrically connected to the even-numbered data lines, the source of the pixel transistor is connected to the pixel, and the gate of the pixel transistor is connected to the odd-numbered gate lines.

[0079] The drain of the pixel transistor is electrically connected to the odd-numbered data lines, the source of the pixel transistor is connected to the pixel, and the gate of the pixel transistor is connected to the even-numbered gate lines.

[0080] like Figure 3 The level unit 20 is also used to control the gate line to output a high level, thereby sequentially turning on the odd-numbered data lines and even-numbered data lines to transmit data voltage to the display panel;

[0081] The control unit 30 is also used to make a judgment based on the timing interval: if the difference in the number of rows of adjacent gate lines is equal to the timing interval, then the control level unit 20 turns on the first row of gate lines and the next row of gate lines.

[0082] The control unit 30 is also used to acquire timing interval information; compare the timing interval with a specified threshold, and if it is less than the specified threshold, determine that the refresh rate meets the specified requirements; wherein, the specified threshold is the maximum timing interval value that meets the refresh rate requirements. Preferably, the specified threshold is 5.

[0083] The present invention provides a high refresh rate display driving method and apparatus. By using a level unit 20 to control the number of high-level times of each gate line in one frame cycle and using a control unit 30 to obtain the timing interval between two adjacent high levels, the refresh rate of the display panel is controlled by the timing interval. When producing display products in the field of competitive display, the corresponding timing interval value can be set to improve the refresh rate of the display and improve the display quality.

[0084] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method of driving a high refresh rate display screen, characterized by, include: Step 100: A driving device is provided, the driving device including a timing unit, a level unit and a control unit, the timing unit being electrically connected to the level unit, the timing unit and the level unit being electrically connected to the control unit respectively, the timing unit being used to provide a clock signal and a pulse width signal to the level unit; Step 200: Provide a display panel circuit, wherein the level unit is electrically connected to each stage of the gate line in the display panel circuit; Step 300: Use the level unit to control the number of high-level times of each gate line within a frame period; Step 400: Use the control unit to obtain the timing interval between two adjacent high levels, and use the timing interval to control the refresh rate of the display panel; The high level is used to turn on the gate line, and the high level pulse widths in the gate line are equal. Step 400 includes: Step 410: Use the level unit to control the gate line to output a high level, and sequentially turn on the odd-numbered data lines and even-numbered data lines to transmit data voltage to the display panel; Step 420: If the difference in the number of rows of adjacent gate lines is equal to the timing interval, then turn on the first row of gate lines and the next row of gate lines. Step 430: Obtain timing interval information; Step 440: Compare the timing interval with a specified threshold. If it is less than the specified threshold, then determine that the refresh rate meets the specified requirements. The specified threshold is the maximum timing interval value that meets the refresh rate requirement.

2. The high refresh rate display screen driving method of claim 1, wherein, Step 200 includes: Step 210: Electrically connect the drain of the pixel transistor to the even-numbered data lines, connect the source of the pixel transistor to the pixel, and connect the gate of the pixel transistor to the odd-numbered gate lines. Step 220: Electrically connect the drain of the pixel transistor to the odd-numbered data lines, connect the source of the pixel transistor to the pixel, and connect the gate of the pixel transistor to the even-numbered gate lines.

3. The high refresh rate display driving method according to claim 1, characterized in that, The specified threshold for the time interval is 5.

4. A high refresh rate display driving apparatus, which is driven by the method according to any one of claims 1 to 3, characterized in that, include: Timing unit; Level unit; Control unit; The timing unit is electrically connected to the level unit; The timing unit and the level unit are also electrically connected to the control unit; The control unit is electrically connected to the display panel circuit of the display screen; The timing unit is used to provide clock signals and pulse width signals to the level unit; The level unit is used to control the number of high-level times for each gate line within a frame period; The control unit is used to acquire timing interval information between two adjacent high levels and to control the refresh rate of the display panel using the timing interval; The high level is used to turn on the gate line, and the high level pulse widths in the gate line are equal.

5. The high refresh rate display screen driving apparatus of claim 4, wherein the first and second display screen driving apparatuses are connected in series. The circuit structure of the display panel is as follows: The drain of the pixel transistor is electrically connected to the even-numbered column data lines, the source of the pixel transistor is connected to the pixel, and the gate of the pixel transistor is connected to the odd-numbered row gate lines. The drain of the pixel transistor is electrically connected to the odd-numbered column data lines, the source of the pixel transistor is connected to the pixel, and the gate of the pixel transistor is connected to the even-numbered row gate lines.

6. The high refresh rate display screen driving apparatus of claim 5, wherein, The level unit is also used to control the gate line to output a high level, thereby sequentially turning on the odd-numbered data lines and even-numbered data lines to transmit data voltage to the display panel. The control unit is also used for: The timing interval is used to determine if the difference in the number of rows of adjacent gate lines is equal to the timing interval. Then, the level unit is controlled to turn on the first row of gate lines and the next row of gate lines.

7. The high refresh rate display screen driving device according to claim 6, characterized in that, The control unit is also used for: Obtain timing interval information; The timing interval is compared with a specified threshold. If it is less than the specified threshold, the refresh rate is determined to meet the specified requirements. The specified threshold is the maximum timing interval value that meets the refresh rate requirement.

8. The high refresh rate display screen driving apparatus of claim 7, wherein, The specified threshold is 5.

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