Memory testing device and testing method thereof
By using the BIST module and test interface in the memory test device, memory devices can be tested using FSM operation commands or direct access commands, which solves the problems of low testing efficiency and high cost in the prior art and improves the yield of memory devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2021-02-09
- Publication Date
- 2026-06-26
AI Technical Summary
Existing technologies are insufficient for effectively testing highly integrated memory devices, resulting in low yields and high testing costs.
A memory testing device, including a BIST module, a test interface, a command FSM module, and a direct access controller, is used to test memory devices through FSM operation commands or direct access commands, reducing reliance on automated testing equipment and improving testing efficiency.
It enables efficient testing of memory devices, reduces testing costs, and improves yield.
Smart Images
Figure CN113257328B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory testing apparatus and method for testing defects in highly integrated memory devices. Background Technology
[0002] Deep submicron (DSM) technology is frequently used to design and manufacture state-of-the-art semiconductor chips, and as memory becomes increasingly embedded, low memory yield has significantly impacted overall device yield. Therefore, repairable memory is being utilized to improve overall chip yield.
[0003] Furthermore, as semiconductor devices become more integrated and complex, several methods for effectively testing them are being investigated. In particular, a method known as BIST (Built-in Self-Test) has been considered for effectively testing memories embedded within semiconductor devices. This method for testing embedded memories can utilize circuits that implement memory testing algorithms. Summary of the Invention
[0004] The present invention provides memory test circuits, test systems, and operating methods with improved testability and debuggability.
[0005] The present invention also provides memory test circuits, test systems, and operating methods that can be tested at low cost.
[0006] One aspect of the present invention is a testing method for a memory testing apparatus connected to a memory device. The testing method includes: receiving a test command, and when the test command is a finite state machine (FSM) operation command, testing the memory device according to the FSM operation command and outputting a result based on pass / fail. However, when the test command is a direct access command, performing an automatic operation test on the input data in a test area based on received address information and outputting a test result, which includes failure information or automatic operation output data.
[0007] Another aspect of the present invention provides a memory testing apparatus connecting an automated test setup and a memory device. The apparatus includes a test interface that receives test commands from the automated test setup and returns test results, and a built-in self-test (BIST) module that accesses the memory device and performs tests. When the test command is a finite state machine (FSM) operation command, the BIST module autonomously generates an address based on the FSM operation command, accesses the memory device, and executes the test process. Furthermore, when the test command is a direct access command, the BIST module performs automated operation tests on the test area of the memory device based on the received address information.
[0008] Another aspect of the present invention provides a memory testing apparatus, comprising: a test interface for receiving test commands from an automated testing equipment and outputting test results, and a BIST module connected to a memory device, for performing at least one test procedure on the entire area of the memory device based on the test commands, or for performing an automated operation test on a specified test area of the memory device through the automated testing equipment and outputting test results.
[0009] However, the aspects of the invention are not limited to those set forth herein. The above and other aspects of the invention will become more apparent to those skilled in the art from the following detailed description of the invention. Attached Figure Description
[0010] Figure 1 This is a block diagram illustrating a memory testing apparatus according to some embodiments of the present invention.
[0011] Figure 2 It is used for explanation Figure 1 A block diagram of the BIST module.
[0012] Figure 3 It is used for explanation Figure 1 A block diagram of a memory device.
[0013] Figure 4 It is used for explanation Figure 2 A block diagram of the FSM module's commands.
[0014] Figure 5 It is used for explanation Figure 2 A block diagram of the direct access controller.
[0015] Figure 6 It is used for explanation Figure 2 Block diagram of a multiplexer.
[0016] Figure 7 This is a flowchart illustrating a test method according to some embodiments of the present invention.
[0017] Figure 8 This is a flowchart illustrating a test method according to some embodiments.
[0018] Figure 9 This is a conceptual diagram used to illustrate the process of a test method according to some embodiments.
[0019] Figure 10 This is a flowchart illustrating a test method according to some embodiments. Detailed Implementation
[0020] In the following description, embodiments of the technical concept according to the present invention will be illustrated with reference to the accompanying drawings.
[0021] Figure 1 This is a block diagram illustrating a memory testing apparatus according to some embodiments of the present invention. Figure 2 It is used for detailed explanation. Figure 1 A block diagram of the BIST module, and Figure 3 It is used for detailed explanation. Figure 1 A block diagram of the memory device 20. (Refer to...) Figure 1 According to some embodiments of the present invention, a memory testing apparatus 1 is connected to an automated testing equipment 2 and includes a BIST module 10 and a memory device 20.
[0022] Automatic Test Equipment (ATE) 2 is a device that automatically tests at least one device under test (DUT), and can test whether the memory device 20 is defective by applying a stimulus signal to the memory test device 1, which is the device under test, and check the response signal (pass / fail) to the stimulus signal.
[0023] ATE 2 can connect to an external server via an interface. The server can provide a user interface to offer an environment where users can create test programs tailored to the characteristics of the device under test (DUT). Furthermore, the server sends the test programs to ATE 2 and can provide a user interface at ATE 2 to receive and analyze the test results. The server can be any type of processing device and may include, but is not limited to, conventional personal computers, desktop devices, portable devices, microprocessor-based computers, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and / or personal mobile computing devices.
[0024] The memory test device 1 has a built-in self-test circuit (BIST) and can be a device designed to drive test programs sent from ATE 2. The test program can consist of commands for performing test operations in the memory test device 1. The memory test device 1 can receive stimulus signals, perform tests on the memory device 20, and output the test results to ATE 2. According to some embodiments, the stimulus signals may include test commands and parity information. According to some embodiments, the stimulus signals may also include address information, and according to other embodiments, they may include data.
[0025] Reference Figure 2 The BIST module 10 may include a test interface 100, a command FSM module 200, a direct access controller 300, and a multiplexer 400.
[0026] Test interface 100 electrically connects ATE 2 to memory test apparatus 1 to receive excitation signals and output response signals. According to some embodiments, test interface 100 may be formed of multiple conductive patterns, and according to various embodiments, test interface 100 may include input / output test signal lines, clock signal line TCLK, and power lines.
[0027] According to some embodiments, the stimulus signal sent from ATE 2 may include a test command EN from memory device 20. The test command EN may include a test command to perform a test operation. According to some embodiments, the test command may include a command FSM operation command and a direct access command.
[0028] Additionally, according to some embodiments, the excitation signal may also include address information of the test region specified by ATE 2. In this case, the address information of the test region represents the start address ADD_S and the end address ADD_F. According to some embodiments, the excitation signal may also include data DATA according to a test command. According to an embodiment, the memory testing apparatus 1 can program the data DATA included in the excitation signal into the memory device 20 according to the test command CMD_test. According to another embodiment, the memory testing apparatus 1 uses the data DATA included in the excitation signal as target data, and can compare the target data with the data read from the memory device 20 according to the test command CMD_test.
[0029] According to some embodiments, test interface 100 checks whether the test command CMD_test is an FSM operation command or a direct access command, and can send the test command to the BIST module based on the check result. Specifically, if the test command received by ATE 2 is an FSM operation command, test interface 100 can send the test command to command FSM module 200. In response, test interface 100 can return the test result (i.e., pass / fail) to ATE 2 based on the FSM operation command. However, if the test command received by ATE 2 is a direct access command, test interface 100 can send the test command to direct access controller 300. In this case, according to an embodiment, test interface 100 can return the result of the automatic operation test (i.e., pass / fail) to ATE 2. Alternatively, according to another embodiment, test interface 100 can also return the output data DOUT generated as the result of the automatic operation test to ATE 2.
[0030] The command FSM module 200 can repeatedly execute operations defined as test procedures on the memory device 20. Specifically, since the command FSM module 200 can autonomously generate the address for accessing the memory device 20 during the execution of the test procedure, it can perform test operations without typing in another address. Furthermore, since the command FSM module 200 stores data modes, it can execute tests without separately setting input data for ATE 2. Therefore, when testing using FSM operation commands, since the automated test equipment 2 only checks the test results according to a preset test procedure, it can reduce dependence on the automated test equipment 2 and reduce the number of commands or data to be entered, as well as the test time. In other words, if the command FSM module 200 receives an FSM operation command, it can access the memory device and execute at least one test procedure according to the FSM operation command.
[0031] According to some embodiments, the command FSM module 200 may include a finite state machine (FSM), and the finite state machine may include at least one test procedure. In this specification, a test procedure refers to a set of commands comprising at least two or more operation commands CMD_op.
[0032] A command set is a set of commands that execute a first operation command CMD_op of at least one cell included in the memory device 20, and includes at least one second operation command CMD_op whose execution result is determined as the next operation to be executed. That is, a command set refers to the order of commands determined based on the execution result of the previous command. Figures 8 to 9 The test process will be described in more detail below.
[0033] When the direct access controller 300 receives a direct access command from ATE 2, it can execute automatic operations on the test area specified by ATE 2. In this case, ATE 2 may send the address information or test data of the test area together. The direct access controller 300 may include tests to be executed via commands of a test procedure not set as a finite state machine, or tests of specific areas or suspected defective areas set by ATE 2. Tests of suspected defective areas may include, for example, tests for programming or reading predetermined test data, or tests for reading data programmed in a test area in memory device 20 and comparing that data with target data.
[0034] According to some embodiments, automatic operation testing may include an automatic programming operation that programs the same preset data for each memory cell of the test area, an automatic erasing operation for erasing data in the test area, an automatic reading operation for reading data stored in the memory cells of the test area, and an automatic comparison operation that compares the data read from the memory cells of the test area with the target data received from ATE 2 to output a comparison result.
[0035] As an example, the data being programmed during automatic programming operations may, according to some embodiments, be data received by ATE 2, and according to other embodiments, it may be a data pattern. For instance, according to some embodiments, the target data during automatic comparison operations may be the data DATA received by ATE 2.
[0036] When multiplexer 400 receives operation command CMD_op, access address ADD+, and data DIN from command FSM module 200 or direct access controller 300, multiplexer 400 outputs them to memory device 20. Memory device 20 executes the operation according to operation command CMD_op in the memory cell corresponding to access address ADD+, and returns the execution result to multiplexer 400. In addition to the completion signal, the execution result may also include data DOUT according to operation command CMD_op.
[0037] Reference Figure 3 The memory device 20 includes a test area. In the case of an FSM operation command, according to one embodiment, the test area may be the entire area of the memory device 20, or according to another embodiment, it may be a portion of the memory device 20. In the case of a partial area, the test area may be the region from the start address to the end address set during the testing process of the FSM module 200. The partial area may be the area based on the access cells of the memory device 20.
[0038] In the case of a direct access command, according to some embodiments, the test area may be a portion of the memory device 20. According to one embodiment, the portion may be address information received from ATE 2, i.e., the area from the start address to the end address. According to another embodiment, the portion may include memory cells adjacent to the suspected defective area Y1. According to yet another embodiment, in addition to the access cells of the memory device 20, the portion may be a narrow area, such as a page or block cell.
[0039] The memory device 20 may include a main cell region 21 and an option cell region 25. Typically, data is programmed, read, and erased in the memory cells of the main cell region 21. If any memory cell in the main cell region 21 is defective, it can be replaced with a memory cell in the option cell region 250 for debugging purposes.
[0040] More specifically, the memory device 20 can be erased using memory access units such as memory block cells, programmed on a page-by-page basis, and read on a cell-by-cell basis. Consider a command execution unit where, if any cell in the main cell region 21 is defective, the page or block X1 containing the defective cell may become unavailable due to the defect. In this case, the memory device 20 can be replaced by a page or block X2 in the option cell region instead of the page or block X1 containing the defective cell in the main cell region.
[0041] According to some embodiments, memory device 20 updates the FTL (File Transfer Layer) with the address information replaced by debugging, and BIST module 10 can perform test operations on the memory cells at the replaced addresses. Furthermore, according to some embodiments, BIST module 10 can output test results, including the debugging results and the replaced address information, to ATE 2.
[0042] According to some embodiments, memory device 20 may be a volatile memory element such as SRAM, DRAM, and SDRAM, or a non-volatile memory element such as ROM, PROM, EPROM, EEPROM, NAND flash memory device, NOR flash memory device, resistance-change memory device (RRAM), phase-change memory device (PRAM), magnetoresistive memory device (MRAM), and ferroelectric memory device (FRAM), as well as memory assemblies including them. Similarly, memory device 20 is not limited to memory elements or memory packages, and may be, for example, a memory module, memory card, or memory stick formed by combining memory assemblies.
[0043] Figure 4 It is used for detailed explanation. Figure 2 A block diagram of the command FSM module, and Figure 5 It is used for detailed explanation. Figure 2 A block diagram of the direct access controller. Figure 6 It is used for detailed explanation. Figure 2 Block diagram of a multiplexer. (Refer to...) Figure 4 The command FSM module 200 may include a first address generator 210, operation modules 220, 240 and 250, and a comparison module 230. The first address generator 210 generates access addresses for the security test area.
[0044] According to some embodiments, the first address generator 210 can autonomously generate access addresses by incrementing or decrementing the address index from the start address across the entire region of the memory device 20, up to the end address. At this time, based on the test procedure to be performed by the command FSM module 200, an access address for the option cell region or an access address for the main cell region can be generated.
[0045] According to some embodiments, the first address generator 210 can also generate access addresses for a portion of the test process settings. In this case, the portion of the settings may be at least a part of the main unit region according to one embodiment, and at least a part of the option unit region according to another embodiment.
[0046] Operation modules 220, 240, and 250 can perform programming, reading, or erasing operations on the data in the memory cell corresponding to the access address ADD_gen generated by the first address generator 210, according to the test process. This test process may include at least one set of operation commands as a preset sequence. Figure 8 and Figure 9 A more detailed description is given in the text.
[0047] According to some embodiments, when the read operation module 220 is enabled according to a preset sequence, it can read the data DOUT stored in the memory cell of the test area. The read data can be stored in a test register (not shown). According to some embodiments, when the programming operation module 240 is enabled according to a preset sequence, it can program the data DIN into the memory cell of the test area. At this time, the data DIN to be programmed can be data DATA received from ATE 2 according to one embodiment, or data mode received from ATE 2 according to another embodiment. According to some embodiments, when the erase operation module 250 is enabled according to a preset sequence, it can erase the data in the memory cell of the test area.
[0048] The comparison module 230 compares the data read from the memory cell corresponding to the access address with the target data and outputs the comparison result as a test result. The test register can store the target data and the read data, and the comparison module 230 can compare the two sets of data. If the read data matches the target data, the comparison module 230 can re-enable the read operation module 220 to perform a reread; if the reread data does not match the target data, the comparison module 230 can perform debugging.
[0049] As described above, debugging is performed by replacing a portion of the main cell region X1 with a portion of the option cell region X2 and remapping it, and the remapping information can be stored in the FTL (File Transfer Layer) and test registers of the memory device 20. According to some embodiments, the remapping information may include the debug count and address information of the debugged cell.
[0050] According to an embodiment, the comparison result of the comparison module 230 includes at least one of the following: whether it matches or does not match the target data, whether debugging is performed when it does not match, and the address information of the cell when it does not match. The test register can store the comparison result. That is, ATE 2 can check whether there is a defect in the storage device 2 and the location of the defect based on the comparison result of the comparison module 230.
[0051] As an example, if the debugging exceeds a preset number of times, the comparison module 230 determines that the debugged memory has failed and can output the test results. At this time, the test results may include the address information of the memory cell on which the debugging was performed.
[0052] Reference Figure 5 The direct access controller 300 may include a second address generator 310, an automatic read module 320, an automatic programming / erasing module 330, and an automatic comparison module 340. The second address generator 310 can generate access addresses ADD_gen for memory cells in the test region. According to some embodiments, the access address ADD_gen can be generated based on address information received from ATE 2 by incrementing or decrementing the address index from the start address ADD_S to the end address ADD_F.
[0053] The address information received from ATE 2 may, according to one embodiment, be only the address information of the suspected defective region Y, and according to another embodiment, it may be the address information of a wide region including the suspected defective region Y. Alternatively, according to some embodiments, the access address ADD_gen may be used to set the test region based on the address information of the suspected defective region Y received from ATE 2 by increasing or decreasing the address index to adjacent regions.
[0054] At least one of the automatic read module 320, automatic programming / erasing module 330, and automatic comparison module 340 can be enabled and operated based on the direct access command CMD_test or an enable signal. The automatic read module 320 can read data stored in the memory cell corresponding to the access address. The automatic programming / erasing module 330 can automatically program the same data in the memory cell corresponding to the access address, or can automatically erase the programmed data.
[0055] The automatic comparison module 340 can compare the data read for each memory cell corresponding to the access address with the target data and output the comparison result. As a result of the comparison, if the data is the same as the target data, the automatic comparison module 340 can output "pass", and if the data is different from the target data, the automatic comparison module 340 can output "failure" as a test result to ATE 2 through the test interface 100.
[0056] Reference Figure 6 The multiplexer 400 may include a first multiplexer 410 and a second multiplexer 420. The first multiplexer 410 outputs the operation command CMD_op and access address ADD_gen received from the command FSM module 200 or the direct access controller 300 to the memory device 20, so as to execute an operation according to the operation command CMD_op in the memory cell corresponding to the access address ADD+ of the memory device 20. The second multiplexer 420 outputs and programs the data DIN received from the command FSM module 200 or the direct access controller 300 to the memory device 20, or receives the data DOUT read from the memory device 20 and sends it to the command FSM module 200 or the direct access controller 300.
[0057] Figure 7 This is a flowchart illustrating a test method according to some embodiments of the present invention, and Figure 8 This is a flowchart illustrating a test method according to some embodiments. Figure 9 This is a conceptual diagram used to illustrate the process of a test method according to some embodiments. Figure 10 This is a flowchart illustrating a test method according to some embodiments.
[0058] According to some embodiments of the test method, the memory test apparatus receives a test command from the automatic memory device (S10). The memory test apparatus checks whether the received test command (input command) is an FSM operation command or a direct access command (S20). As an example, if the received test command is an FSM operation command, the memory test apparatus tests the test area according to the FSM operation command (S30, S31).
[0059] Reference Figure 8 The access address for accessing the memory device is generated (S32). The access area according to the FSM operation command may be the entire area of the memory device according to one embodiment, or a portion of the memory device according to another embodiment. According to some embodiments, the access area may be all or part of the main cell area of the memory device, and according to some embodiments, the access area may be all or part of the option cell area of the memory device.
[0060] The memory testing apparatus can execute at least one test procedure to test a test area based on FSM operation commands (S33). According to some embodiments, the FSM operation commands may include a test procedure for an option cell area, a test procedure for a main cell area, and a reserved test procedure for the main cell area. The memory testing apparatus includes a finite state machine, and the finite state machine includes at least one test procedure, and may include at least two or more sets of operation commands to be executed in a preset sequence according to at least one test procedure.
[0061] According to some embodiments, the testing process for the option cell area may include at least one of the following: performing an erase operation for each page or sector in the option cell area, programming the data in the option cell area, and reading the programmed data in the option cell area. Furthermore, the testing process for the option cell area may store the test results in a test register after performing the above operations.
[0062] The testing process for the main cell area according to some embodiments may include at least one of the following: performing an erase operation on each page or sector of the main cell area, programming preset data in the main cell area, reading the programmed data in the main cell area, comparing whether the read data is the same as the target data, and performing tests on the main cell area in data mode or reverse data mode. Furthermore, the testing process for the main cell area may store the test results in a test register.
[0063] According to some embodiments, the retention test procedure for the main cell region is a test command executed after a retention operation of the memory device. More specifically, the retention test procedure may include at least one of the following: reading data from the main cell region, comparing the read data with target data, and performing a test in the main cell region in data mode or reverse data mode. Additionally, the retention test procedure may store the test results in a test register.
[0064] Reference Figure 9 The process will be described in more detail below. As an exemplary embodiment, firstly, a test can be performed on the option cell region while accessing each cell via the access address. For each operation cell (page / sector / piece (Mat)), an erase operation is first performed on at least one cell in the option cell region, and then the operation command to be executed next is determined based on the result of the erase operation.
[0065] If the erase operation passes, the data "00" is programmed into that cell in the option cell region, and the data "FF" is also programmed. As a result of program execution, the data "00" is read from the cell, and the test result based on the program operation and the read operation is stored in the test register as the read execution result. If the read data stored in the test register matches the target data, the cell in the option cell region is considered passed. If all cells in the option cell range are determined to pass, the test is performed by accessing one of the cells in the main cell region via the access address.
[0066] First, for each operation unit (page / sector / slice), an erase operation is performed on at least one cell in the main unit area. Then, the next operation command to be executed is determined based on the erase execution result. If the erase execution passes, the data "00" is programmed into a cell in the option unit area. After program execution, the data "00" is read again from that cell, and the test result based on the read operation is stored in the test register. If the data read and programmed in the test register match "00", an inverted data mode CKBDB test is performed on that cell. The result of the data mode test is stored in the test register.
[0067] When the execution result of the data pattern test stored in the test register is determined to be successful, it is reserved for the main cell area. After performing an erase operation on the reserved main cell area for each operation unit (page / sector / slice), the data "FF" is read, the data pattern test CKBD is executed, and the execution result is stored in the test register. In this way, the operation command to be executed in the next step can be changed differently based on the execution result of the previous operation command, and the memory device can perform tests using a set of operation commands that are recombined differently during the test process without intervention from automated test equipment. However, the scope is not limited to this. Figure 9 The embodiments shown are illustrated, and various test procedures can be modified and applied depending on the design.
[0068] The memory testing apparatus can store temporary test results in a test register according to the testing process (S34). The temporary test results may include whether the test was completed, whether the test passed or failed, and whether a defect exists in a predetermined memory cell. If a defect is suspected in at least one cell of the memory device, the memory testing apparatus can perform debugging (S35). A suspected defect occurs when data read from a predetermined memory cell does not match target data during comparison, and debugging can be performed in such cases.
[0069] As described above, debugging is performed by replacing a portion of the main cell region X1 with a portion of the option cell region X2 and remapping it, and the remapping information can be stored in the FTL (File Transfer Layer) and test register of the memory device. According to some embodiments, the remapping information may include the debug count and address information of the debugged cell. According to embodiments, the temporary test results stored in the test register can be updated with the test results after debugging. The test results to be sent to the automated test equipment may include at least one of the following: matching or not matching with target data, whether debugging is performed when there is a mismatch, and the address information of the cell when there is a mismatch. Therefore, the automated test equipment can easily check the presence / absence of defects in the memory device and the location of the defects according to the test process (S36). As an example, if the received test command is a direct access command, the memory test device tests the test area according to the direct access command (S40, S41).
[0070] Reference Figure 10 An access address for accessing the test area is generated (S42). Based on the address information ADD_S and ADD_F received from the automatic testing equipment, the test area may be a region included in the memory device. According to one embodiment, the test area may be a suspected defect area set by the automatic testing equipment, and according to another embodiment, the test area may be address information of a wide area including the suspected defect area set by the automatic testing equipment.
[0071] The memory testing apparatus can perform tests by automatically operating the test area based on direct access commands (S43). The automatic operations can include automatic programming / erasing operations, automatic reading operations, and automatic comparison operations. The automatic programming / erasing operation can program or erase the stored data for each memory cell corresponding to the access address using the same preset data. The automatic reading operation can read the data stored in the memory cell corresponding to the access address and output it as output data. The automatic comparison operation can compare the data read for each memory cell corresponding to the access address with the received target data and output the comparison result as pass / fail.
[0072] The direct access command may be an operation command that performs one of the automatic operations according to some embodiments, or it may be at least two or more operation commands that determine a sequence in the automatic operations and execute them sequentially. The memory test apparatus may return the test results of performing FSM operation commands or direct access commands on the test area to the automatic test equipment (S50).
[0073] The test result can be whether the received command (input command) passed or failed. According to some embodiments, the test result may include pass / fail and, in the case of failure, the address information of the memory cell that failed. According to some embodiments, the test result may also include output data based on the test operation. Furthermore, according to some embodiments, the test result may also include whether debugging of the debug address information was performed.
[0074] In concluding with this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention. Therefore, the preferred embodiments disclosed herein are for general and descriptive purposes and are not intended to be limiting.
Claims
1. A method for testing a memory device using a memory testing apparatus, comprising: In response to a first test command received by the memory testing device, the memory device is tested using finite state machine (FSM) operation commands; as well as In response to the second test command and address information received by the memory testing device, automatic operation testing is performed on the test area within the memory device. The memory testing device includes a built-in self-test circuit (BIST), which is configured to receive the first test command and the second test command as an FSM operation command and a direct access command, respectively. The BIST includes: The test interface responds to the first test command and the second test command. Command FSM; Direct access to the controller; and A multiplexer is configured to receive signals generated at the output of the command FSM and the output of the direct access controller.
2. The method according to claim 1, wherein, The memory device responds to the signals generated by the multiplexer.
3. The method according to claim 1, wherein, The memory device includes a main cell region and an option cell region; and wherein the FSM operation command includes at least one of the following: a test procedure for the option cell region, a test procedure for the main cell region, and a reservation test procedure for the main cell region.
4. The method according to claim 3, wherein, The command FSM is configured to generate memory address information and at least one data pattern provided to the memory device in response to the FSM operation command.
5. The method according to claim 4, wherein, The testing process for the main cell region includes at least one of the following: Perform an erase operation on at least one page or sector within the main unit area; The preset data is programmed into the main unit area; Read data from the main unit area; The data read from the main unit area is compared with the target data; as well as The main cell region is tested in either data mode or reverse data mode.
6. The method according to claim 4, wherein, The retention test process for the main cell region includes at least one of the following: Read data from the main unit area; The data read from the main unit area is compared with the target data; The main cell region is tested in either data mode or reverse data mode.
7. A memory testing apparatus, comprising: Memory devices; as well as A built-in self-testing BIST module is configured to access the memory device and perform tests therein in response to a test command received from a test apparatus. The BIST module is configured to generate an address for the memory device in response to a finite state machine (FSM) operation command, access the memory device and perform a test process within the memory device when the test command is an FSM operation command, and perform automatic operation tests on the test area of the memory device based on the address information received from the test apparatus when the test command is a direct access command. The BIST module includes: The command FSM module is configured to execute at least one test procedure to access the memory device and perform a test procedure corresponding to the FSM operation command; and The direct access controller is configured to perform the automated operation test according to the direct access command.
8. The memory testing apparatus according to claim 7, wherein, The command FSM module includes: A first address generator is configured to generate an access address for accessing the memory device; The operation module is configured to program, read, and / or erase a preset data pattern on a memory cell corresponding to the access address according to a test procedure corresponding to the FSM operation command; and The comparison module is configured to compare the data read from the memory unit with the target data and output the comparison result as a pass or fail test result.
9. The memory testing apparatus according to claim 8, wherein, When the comparison result is failure, the operation module performs debugging; and wherein, the comparison module compares the data read from the debugged memory unit with the target data, and outputs whether the comparison result is pass or fail as the test result.
10. The memory testing apparatus according to claim 7, wherein, The memory device includes a main cell region and an option cell region; and wherein the command FSM module is configured to perform a test process on the option cell region, a test process on the main cell region, and a reservation test process on the main cell region.
11. The memory testing apparatus according to claim 10, wherein, The test process executes a first operation command on at least one unit included in the memory device, and executes a preset second operation command as the next operation based on the execution result of the at least one unit.
12. The memory testing apparatus according to claim 7, wherein, The received address information includes the start and end addresses of the test area.
13. The memory testing apparatus according to claim 7, wherein, The direct access controller includes: The second address generator generates an access address for the test area based on the received address information; An automatic programming / erasing unit programs or erases the stored data for each memory cell corresponding to the access address using the same preset data. The automatic read unit reads data stored in the memory cell corresponding to the access address; and The automatic comparison unit compares the data read from each memory cell corresponding to the access address with the target data and outputs pass / fail as the comparison result.
14. A memory testing apparatus connected between an automated test setup and a memory device, comprising: The test interface receives test commands from the automated test equipment and returns test results; as well as The built-in self-test BIST module accesses the memory device and performs tests. When the test command is a Finite State Machine (FSM) operation command, the BIST module autonomously generates an address based on the FSM operation command, accesses the memory device, and executes the test process. When the test command is a direct access command, the BIST module performs automatic operation tests on the test area of the memory device based on the received address information.
15. The memory testing apparatus according to claim 14, wherein, The BIST module includes: The command FSM module includes at least one test procedure to access the memory device and execute a test procedure corresponding to the FSM operation command; and The controller is directly accessed, and the automated operation test is performed according to the direct access command.
16. The memory testing apparatus according to claim 15, wherein, The command FSM module includes: The first address generator autonomously generates the access address for accessing the memory device; The operation module programs, reads, and / or erases a preset data pattern on the memory cell corresponding to the access address according to a test process corresponding to the FSM operation command; and The comparison module compares the data read from the memory unit with the target data and outputs the comparison result as a pass or fail test result.
17. The memory testing apparatus according to claim 16, wherein, When the comparison result fails, the operation module performs debugging, and The comparison module compares the data read from the debugged memory unit with the target data and outputs the comparison result as a pass or fail test result.