Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array, including MRAM cells arranged in rows and columns, wherein a first column in the columns includes: a first bottom electrode arranged along the first column; a first magnetic tunnel junction (MTJ) stack located above the first bottom electrode; a first shared electrode located above each first MTJ stack; a second bottom electrode arranged along the first column; a second MTJ stack located above the second bottom electrode; a second shared electrode located above each second MTJ stack; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications, including, for example, radios, televisions, cellular phones, and personal computing devices. One type of semiconductor memory is magnetoresistive random access memory (MRAM), which involves spintronic devices that combine semiconductor technology with magnetic materials and devices. The spin of an electron (via its magnetic moment) is used to indicate the value of a bit. An MRAM cell typically includes a magnetic tunnel junction (MTJ) stack, which includes two ferromagnets separated by a thin insulator. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a magnetoresistive random access memory (MRAM) array, including MRAM cells arranged in rows and columns, wherein a first column of the columns includes: a first bottom electrode arranged along the first column; a first magnetic tunnel junction (MTJ) stack located above the first bottom electrode; a first shared electrode located above each of the first MTJ stacks; a second bottom electrode arranged along the first column; a second MTJ stack located above the second bottom electrode; a second shared electrode located above each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

[0004] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first intermetallic dielectric (IMD) layer over a substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a top electrode layer over the MTJ film stack; patterning the top electrode layer, the MTJ film stack, and the bottom electrode layer to form a first magnetoresistive random access memory (MRAM) cell and a second MRAM cell; forming a spacer around sidewalls of the first MRAM cell and the second MRAM cell; depositing an etch stop layer over an exposed portion of the first IMD layer and the spacer; depositing a second IMD layer over the etch stop layer; exposing portions of the first MRAM cell and the second MRAM cell; and forming a shared electrode on the exposed portions of the first MRAM cell and the second MRAM cell.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a magnetoresistive random access memory (MRAM) cell over a substrate, the MRAM cell comprising: a first bottom electrode over the substrate; a first magnetic tunnel junction (MTJ) stack over the first bottom electrode; a first top electrode over the first MTJ stack; forming a first dielectric layer laterally surrounding the first bottom electrode, the first MTJ stack, and the first top electrode; recessing the first dielectric layer to expose a portion of a sidewall of the first top electrode; forming a protection structure in contact with the exposed portion of the sidewall of the first top electrode; depositing a first intermetallic dielectric (IMD) layer over the MRAM cell; and forming a conductive feature extending through the first IMD layer, the conductive feature in contact with the first top electrode and the protection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a cross-sectional view of an MRAM device according to some embodiments.

[0008] Figure 2 is a block diagram of an MRAM device according to some embodiments.

[0009] Figures 3 to 23 are various views of intermediate stages in the fabrication of an interconnect structure for an MRAM device, according to some embodiments.

[0010] Fig.24 and Fig.25 are various views of an MRAM device according to some embodiments.

[0011] Figures 26 to 40 is a cross-sectional view of an intermediate stage in fabricating an interconnect structure for an MRAM device according to some other embodiments.

[0012] Fig.41 is a cross-sectional view of an MRAM device according to some other embodiments.

[0013] Fig.42 is a cross-sectional view of an MRAM device according to some other embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0016] According to some embodiments, an MRAM array is formed in an interconnect structure, wherein the MRAM array includes a shared electrode for an MTJ stack in the MRAM array. Specifically, the electrode is shared by multiple MTJ stacks along the columns of the MRAM array and is electrically connected to the same bit line. Forming a shared electrode for the MTJ stack helps to reduce the contact resistance with the MTJ stack and reduces the risk of damaging the MTJ stack during the subsequent formation of an overlying metallization layer. According to some other embodiments, a dielectric protection structure is formed around the MRAM cell before forming the overlying metallization layer. The protection structure prevents etching of the MTJ stack during the subsequent formation of the overlying metallization layer. By forming a shared electrode and / or a protection structure, damage to the MRAM cell during processing (particularly when the MRAM array is formed in a higher level of the interconnect structure) can be avoided.

[0017] Figure 15 is a block diagram of an MRAM device 50 according to some embodiments. The MRAM device 50 includes an MRAM array 52, a row decoder 54, and a column decoder 56. The MRAM array 52 includes MRAM cells 58 arranged in rows and columns. The row decoder 54 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, etc. During operation, the row decoder 54 selects a desired MRAM cell 58 in a row by activating a corresponding word line WL of the row of the MRAM array 52. ​​The column decoder 56 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, etc., and may include a writer driver, a sense amplifier, a combination thereof, etc. During operation, the column decoder 56 selects a bit line BL for a desired MRAM cell 58 from a column of the MRAM array 52 in a selected row, and reads data from the selected MRAM cell 58 or writes data to the selected MRAM cell 58 using the bit line BL.

[0018] Figure 2 is a cross-sectional view of an MRAM device 50 according to some embodiments. Figure 2 5 is a simplified diagram, and some features (discussed below) are omitted for clarity. MRAM device 50 includes logic region 50L and memory region 50M. Memory devices (e.g., MRAM) are formed in memory region 50M, and logic devices (e.g., logic circuits) are formed in logic region 50L. For example, MRAM array 52 (see Figure 1 ), and a row decoder 54 and a column decoder 56 may be formed in the logic region 50L (see Figure 1 ). The logic region 50L may occupy most of the area of ​​the MRAM device 50. For example, the logic region 50L may occupy 95% to 99% of the area of ​​the MRAM device 50, and the memory region 50M may occupy the remaining area of ​​the MRAM device 50. The memory region 50M may be disposed at the edge of the logic region 50L, or the logic region 50L may surround the memory region 50M.

[0019] The logic region 50L and the memory region 50M are formed on the same semiconductor substrate 60. The semiconductor substrate 60 may be silicon (doped or undoped), or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 60 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer substrates or gradient substrates.

[0020] Devices 62 are formed at the active surface of semiconductor substrate 60. Devices 62 may be active devices or passive devices. For example, the electrical components may be transistors, diodes, capacitors, resistors, etc. formed by any suitable formation method. Devices 62 are interconnected to form memory devices and logic devices of MRAM device 50. For example, some devices 62 may be access transistors.

[0021] One or more interlayer dielectric (ILD) layers 64 are formed on the semiconductor substrate 60, and conductive features (e.g., contact plugs 66) are formed to be electrically connected to the device 62. The (one or more) ILD layers 64 can be formed of any suitable dielectric material, for example, nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or similar materials. The (one or more) ILD layers can be formed by any acceptable deposition process (e.g., spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or a combination thereof). The conductive features in the (one or more) ILD layers can be formed by any suitable process (e.g., deposition, metal damascene (e.g., single metal damascene, dual metal damascene, etc.), or a combination thereof).

[0022] An interconnect structure 68 is formed over the semiconductor substrate 60. The interconnect structure 68 interconnects the devices 62 to form an integrated circuit in each of the logic region 50L and the memory region 50M. The interconnect structure 68 includes a plurality of metallization layers M1-M6. Although six metallization layers are shown, it should be understood that more or fewer metallization layers may be included. Each of the metallization layers M1-M6 includes a metallization pattern in a dielectric layer. The metallization pattern is electrically coupled to the device 62 of the semiconductor substrate 60 and includes metal lines L1-L6 and metal vias V1-V6 formed in one or more intermetallic dielectric (IMD) layers, respectively. The interconnect structure 68 may be formed by a damascene process (e.g., a single damascene process, a dual damascene process, etc.). In some embodiments, the contact plug 66 is also part of the metallization pattern, for example, part of the lowest layer of the metal via V1. Figure 2 Also marked are some reference numerals which will be further described below.

[0023] An MRAM cell 58 is formed in the interconnect structure 68. The MRAM cell 58 may be formed in any of the metallization layers M1-M6 and is shown as being formed in the middle metallization layer M5. Each MRAM cell 58 includes a conductive via 72, a bottom electrode 74 located on the conductive via 72, an MTJ stack 76 located on the bottom electrode 74, and a top electrode 78 located on the MTJ stack 76. An additional IMD layer 80 may be formed around the MRAM cell 58, wherein the conductive via 72 extends through the IMD layer 80. Spacers 82 may also be formed around the MRAM cell 58. The IMD layer 80 and / or the spacer 82 surround and protect the components of the MRAM cell 58. The resistance of the MTJ stack 76 is programmable and can be set to a high resistance (R ap ) and low resistance (R p ) changes between high resistance (R ap ) can represent values ​​such as a logical “1”, and a low resistance (R p ) may represent a value such as a logical “0.” Thus, a value may be written to the MRAM cell 58 by programming the resistance of the MTJ stack 76 using its corresponding access transistor, and a value may be read from the MRAM cell 58 by measuring the resistance of the MTJ stack 76 using an access transistor.

[0024] MRAM cell 58 is electrically connected to device 62. Conductive via 72 is physically and electrically coupled to an underlying metallization pattern, such as metal line L4 in the example shown. Top electrode 78 is physically and electrically coupled to an overlying metallization pattern, such as metal via V6 in the example shown. MRAM cell 58 is arranged in an MRAM array having rows and columns of memory. The metallization pattern includes access lines (e.g., word lines and bit lines) for the MRAM array. For example, the underlying metallization pattern may include word lines arranged along rows of the MRAM array, and the overlying metallization pattern may include bit lines arranged along columns of the MRAM array.

[0025] Figures 3 to 23 5 are various views of an interconnect structure at intermediate stages of fabricating an MRAM device 50 according to some embodiments. The interconnect structure includes an MRAM array of memory cells. As discussed further below, groups of memory cells along a column of the MRAM array share electrodes, which allows for reduced contact resistance to the memory cells.

[0026] exist Figure 3 In the example, a metallization layer (e.g., M4, see Figure 2 ). The metallization layer includes an IMD layer 102 and a conductive feature 104 (which may correspond to a metal line L4, see Figure 2). The IMD layer 102 is formed on the (one or more) ILD layers 64. The IMD layer 102 can be formed of any suitable dielectric material, for example, a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or the like. The IMD layer 102 can be formed by any acceptable deposition process, for example, spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or a combination thereof. The IMD layer 102 can be a layer formed of a low-k dielectric material having a k value of less than about 3.0. The IMD layer 102 can be a layer formed of an ultra-low-k (ELK) dielectric material having a k value of less than 2.5.

[0027] Conductive feature 104 is formed in IMD layer 102 and is electrically connected to device 62. According to some embodiments, conductive feature 104 includes a diffusion barrier layer and a conductive material located above the diffusion barrier layer. An opening is formed in IMD layer 102 using, for example, an etching process. The opening exposes the underlying conductive feature, for example, the underlying metal via. The diffusion barrier layer may be formed of TaN, Ta, TiN, Ti, CoW, etc., and may be formed in the opening by a deposition process (e.g., atomic layer deposition (ALD)), etc. The conductive material may include copper, aluminum, tungsten, silver, and combinations thereof, etc., and may be formed on the diffusion barrier layer in the opening by an electrochemical plating process, CVD, ALD, PVD, etc., or a combination thereof. In an embodiment, the conductive material is copper, and the diffusion barrier layer is a thin barrier layer that prevents copper from diffusing into IMD layer 102. After forming the diffusion barrier layer and the conductive material, the excess diffusion barrier layer and the conductive material may be removed, for example, by a planarization process (e.g., a chemical mechanical polishing (CMP) process). In some embodiments, conductive feature 104 is a metal line.

[0028] One or more etch stop layers 106 are formed on the conductive features 104 and the IMD layer 102. The etch stop layer(s) 106 may be formed of a dielectric material, such as aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and the like. The etch stop layer(s) 106 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, a spin-on dielectric process, and the like, or a combination thereof. The etch stop layer(s) 106 may also be a composite layer formed of a plurality of dielectric layers. In this embodiment, the etch stop layer(s) 106 include a first etch stop layer 106A and a second etch stop layer 106B located above the first etch stop layer 106A. The first etch stop layer 106A may be formed of a first dielectric material such as silicon carbide, and the second etch stop layer 106B may be formed of a second dielectric material such as aluminum oxide. The silicon carbide layer is used as a bonding layer to improve adhesion between the aluminum oxide layer and the IMD layer 102. The etch stop layer(s) 106 may be formed to have a combined thickness of about To date within the range.

[0029] The IMD layer 108 is formed on the etch stop layer(s) 106. In some embodiments, the IMD layer 108 is formed of tetraethyl orthosilicate (TEOS) oxide (e.g., silicon oxide deposited using, for example, a chemical vapor deposition (CVD) method using TEOS as a precursor). In some embodiments, the IMD layer 108 may be formed using PSG, BSG, BPSG, undoped silicate glass (USG), fluorosilicate glass (FSG), SiOCH, a flowable oxide, a porous oxide, etc., or a combination thereof. For example, the IMD layer 108 may also be formed of a low-k dielectric material having a k value of less than about 3.0. The IMD layer 108 may be formed to a thickness of about To date within the range.

[0030] A conductive via 110 is formed extending through the IMD layer 108 and the (one or more) etch stop layers 106. The conductive via 110 may also be referred to as a bottom via. In some embodiments, the conductive via 110 includes a conductive region 114 and a conductive barrier layer 112 lining the sidewalls and bottom surface of the conductive region 114. The conductive barrier layer 112 may be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, and the like. The conductive region 114 may be formed of a metal such as copper, aluminum, tungsten, cobalt, alloys thereof, and the like. The formation of the conductive via 110 may include: etching the IMD layer 108 and the (one or more) etch stop layers 106 to form a via opening; forming a blanket conductive barrier layer extending into the via opening; depositing a metal material over the blanket conductive barrier layer; and performing a planarization process (e.g., a CMP process or a mechanical grinding process) to remove excess portions of the blanket conductive barrier layer and the metal material.

[0031] One or more bottom electrode layers 116 are formed on the conductive vias 110 and the IMD layer 108. In some embodiments, the bottom electrode layer(s) 116 are formed as a blanket covering layer and may be formed using CVD, physical vapor deposition (PVD), electrochemical plating (ECP), electroless plating, and the like. The bottom electrode layer(s) 116 may be formed of a conductive material such as Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, TiN, TaN, combinations thereof, multilayers thereof, and the like. For example, the bottom electrode layer(s) 116 may include a first bottom electrode layer 116A and a second bottom electrode layer 116B located above the first bottom electrode layer 116A. The first bottom electrode layer 116A may be formed of a first conductive material such as TaN, and the second bottom electrode layer 116B may be formed of a second conductive material such as TiN. The bottom electrode layer 116 may be formed to have a combined thickness of about 100 Å. To date within the range.

[0032] exist Figure 4 In the embodiment, an MTJ film stack 118 is formed on the bottom electrode layer(s) 116. The MTJ film stack 118 is a multi-layer structure including an antiferromagnetic layer 118A, a pinned layer 118B located on the antiferromagnetic layer 118A, a tunnel barrier layer 118C located on the pinned layer 118B, and a free layer 118D located on the tunnel barrier layer 118C. The total thickness of the MTJ film stack 118 is about 1000 Å. to about Each layer of the MTJ film stack 118 may be deposited using one or more deposition methods (eg, CVD, PVD, ALD, combinations thereof, etc.).

[0033] The antiferromagnetic layer 118A may be formed of a metal alloy including manganese (Mn) and one or more other metals (e.g., platinum (Pt), iridium (Ir), rhodium (Rh), nickel (Ni), palladium (Pd), iron (Fe), osmium (Os), etc.). For example, the antiferromagnetic layer 118A may be formed of PtMn, IrMn, RhMn, NiMn, PdPtMn, FeMn, OsMn, etc. The thickness of the antiferromagnetic layer 118A may be about 1000 nm. To date within the range.

[0034] The pinned layer 118B may be formed of a ferromagnetic material having a larger coercivity field than the free layer 118D, such as cobalt iron (CoFe), cobalt iron boron (CoFeB), a combination thereof, etc. The thickness of the pinned layer 118B may be about 1000 nm. to about In some embodiments, the pinned layer 118B has a synthetic ferromagnetic (SFM) structure, in which the coupling between the magnetic layers is ferromagnetic coupling. The pinned layer 118B may also adopt a synthetic antiferromagnetic (SAF) structure, which includes a plurality of magnetic metal layers separated by a plurality of non-magnetic spacer layers. The magnetic metal layer may be formed of Co, Fe, Ni, etc. The non-magnetic spacer layer may be formed of Cu, Ru, Ir, Pt, W, Ta, Mg, etc. For example, the pinned layer 118B may have a Co layer and a repeated (Pt / Co) x Layer, where x represents the number of repetitions, which can be any integer equal to or greater than 1, for example, 20.

[0035] The tunnel barrier layer 118C may be formed of a dielectric material such as MgO, AlO, AlN, combinations thereof, etc. The tunnel barrier layer 118C may have a thickness in a range of about 0.5 nm to about 3 nm. The tunnel barrier layer 118C is thicker than other layers of the MTJ film stack 118 .

[0036] The free layer 118D may be formed of a ferromagnetic material such as CoFe, NiFe, CoFeB, CoFeBW, combinations thereof, and the like. The free layer 118D may also employ a synthetic ferromagnetic structure similar to a SAF structure, in which the thickness of the nonmagnetic spacer layer is adjusted to achieve ferromagnetic coupling between separated magnetic metals, for example, so that the magnetic moments are coupled in the same direction. The magnetic moment of the free layer 118D is programmable, and the resistance of the resulting MTJ stack is therefore programmable. Specifically, based on the programmed magnetic moment of the free layer 118D, a high resistance (R ap ) and low resistance (R p ) between the 100A and 100B, and the resistance of the resulting MTJ stack is changed between the 100A and 100B. In this way, the resulting MTJ stack can also be referred to as a programmable resistance element or a programmable resistor. The thickness of the tunnel barrier layer 118C contributes to the R of the resulting MTJ stack. ap and R p .

[0037] It should be understood that the material and structure of the MTJ film stack 118 can have many variations, which also fall within the scope of the present disclosure. For example, the layers 118A, 118B, 118C, and 118D can be formed in the reverse order of the above order. Therefore, the free layer 118D can be the bottom layer of the MTJ film stack 118, and the antiferromagnetic layer 118A can be the top layer of the MTJ film stack 118.

[0038] The top electrode layer 120 is formed on the MTJ film stack 118. In some embodiments, the top electrode layer 120 is formed as a blanket covering layer and can be formed using CVD, PVD, ECP, electroless plating, etc. The material of the top electrode layer 120 may include metals such as titanium, tantalum, tungsten, aluminum, copper, alloys thereof, etc. For example, the top electrode layer 120 may be formed of TiN, Ta, TaN, Ti, Ru, W, WC, Ru, multilayers thereof, etc. In some embodiments, the top electrode layer 120 is formed of titanium nitride. In some embodiments, the thickness of the top electrode layer 120 is about To date In some embodiments, the thickness of the top electrode layer 120 is greater than the combined thickness of the bottom electrode layer(s) 116. The top electrode layer 120 is used as a hard mask in subsequent patterning of the MTJ film stack 118.

[0039] exist Figure 5In the embodiment of the present invention, one or more masks are formed above the top electrode layer 120. The masks will be used to pattern the various layers simultaneously and form the MRAM cells. In some embodiments, the one or more masks may include one or more hard masks, three-layer masks, combinations thereof, and the like. For example, a hard mask layer 126 may be formed above the top electrode layer 120, and a photosensitive mask 128 may be formed above the hard mask layer 126. In some embodiments, the hard mask layer 126 is formed of an oxide such as titanium oxide, silicon oxide, a combination thereof, and the like. The photosensitive mask 128 may be a photoresist, for example, a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, and the like. The photosensitive mask 128 is formed in the memory region 50M, wherein the pattern of the photosensitive mask 128 corresponds to the pattern of the subsequently formed MRAM cell.

[0040] exist Figure 6 In the embodiment of the present invention, the photosensitive mask 128 is used as an etching mask to etch and pattern the hard mask layer 126. Then, the patterned hard mask layer 126 is used as an etching mask to etch and pattern the top electrode layer 120, the MTJ film stack 118 and the (one or more) bottom electrode layers 116. Patterning may include one or more etching processes, and a groove 130 may be formed in the IMD layer 108. The etching method may include a plasma etching method, such as ion beam etching (IBE). IBE has a high level of precision (e.g., high anisotropy), which may help control the profile of the resulting MRAM cell. Etching may be achieved using glow discharge plasma (GDP), capacitively coupled plasma (CCP), inductively coupled plasma (ICP), etc. The photosensitive mask 128 and the hard mask layer 126 may be consumed in the etching process, or may be removed after the etching process.

[0041] The etching process forms a bottom electrode 132, an MTJ stack 134, and a top electrode 136, which together form an MRAM cell 58. Each MRAM cell 58 includes a bottom electrode 132, an MTJ stack 134, and a top electrode 136. The bottom electrode 132 includes a remaining portion of the bottom electrode layer(s) 116. The MTJ stack 134 includes a remaining portion of the MTJ film stack 118. The top electrode 136 includes a remaining portion of the top electrode layer 120. In some embodiments, the etching process partially etches the IMD layer 108 and the conductive via 110. In such an embodiment, the remaining portion of the IMD layer 108 has a sloped sidewall and has a trapezoidal shape in the cross-section shown. After the etching process, the thickness of the remaining portion of the IMD layer 108 in the logic region 50L may be about 1000 Å. to about The MTJ stack 134 and the bottom electrode 132 also have sloped sidewalls and have a trapezoidal shape in the illustrated cross section.

[0042] exist Figure 7 , spacers 140 are formed on sidewalls of the MRAM cell 58. The spacers 140 surround and protect components of the MRAM cell 58. The spacers 140 may be formed of oxides (e.g., silicon oxide, aluminum oxide, etc.), nitrides (e.g., silicon nitride, aluminum nitride, etc.), carbides (e.g., silicon carbide), combinations thereof (e.g., silicon oxynitride, silicon carbonitride, etc.), multilayers thereof, etc.

[0043] In an embodiment where spacer 140 includes multiple layers, spacer 140 includes passivation layers 142 and 144, and oxide layer 146. As an example of forming spacer 140, passivation layer 142 may be formed to blanket over MRAM cell 58 and blanket over recess 130 (see FIG. Figure 6 ). In some embodiments, the passivation layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, and the like, and may be formed using CVD, plasma enhanced chemical vapor deposition (PECVD), ALD, plasma enhanced atomic layer deposition (PEALD), PVD, combinations thereof, and the like. In some embodiments, the passivation layer 142 may reduce or prevent moisture (e.g., H2O) from diffusing into the MRAM cell 58 during subsequent processing. The passivation layer 142 is then patterned to expose portions of the top electrode 136. In some embodiments, the patterning is a dry etching process, such as an anisotropic etching process. The patterning removes horizontal portions of the passivation layer 142. Subsequently, another passivation layer 144 is formed over the passivation layer 142. In some embodiments, the passivation layer 144 is formed of one of the candidate materials and methods for the passivation layer 142, but is formed of a different material than the passivation layer 142. For example, the passivation layer 142 may be formed of an oxide such as silicon oxide, and the passivation layer 144 may be formed of a nitride such as silicon nitride. An oxide layer 146 is then formed over the passivation layer 144. In some embodiments, the oxide layer 146 may include silicon oxide, etc., and may be formed using CVD, PECVD, ALD, PEALD, combinations thereof, etc. Subsequently, one or more dry etching processes are performed to etch the passivation layer 144 and the oxide layer 146 and expose portions of the top electrode 136. In some embodiments, the one or more dry etching processes are anisotropic etching processes and remove horizontal portions of the oxide layer 146. The remaining portions of the passivation layer 142, the passivation layer 144, and the oxide layer 146 form the spacer 140. After the spacer 140 is patterned, the IMD layer 108 in the logic region 50L is exposed.

[0044] exist Figure 8In the embodiment, an etch stop layer 148 is formed over the spacers 140, the top electrode 136, and the exposed portions of the IMD layer 108. An IMD layer 150 is then formed on the etch stop layer 148. The etch stop layer 148 may be formed of a dielectric material such as aluminum nitride, aluminum oxide, silicon carbide, silicon carbonitride, combinations thereof, multilayers thereof, and the like. In some embodiments, the IMD layer 150 is formed using materials and methods similar to those of the IMD layer 108. In some embodiments, the etch stop layer 148 is formed of aluminum nitride and the IMD layer 150 is formed of silicon oxide. Aluminum nitride and silicon oxide have high selectivity with respect to an etching process (discussed further below) that will be used to pattern the IMD layer 150. The IMD layer 150 is formed to a thickness of about 100 Å. to about Due to pattern loading, the portion of the IMD layer 150 in the memory region 50M may extend higher than the portion of the IMD layer 150 in the logic region 50L. The IMD layer 150 is formed to have a sufficient thickness so that the portion of the IMD layer 150 in the logic region 50L has a greater thickness than the MRAM cell 58.

[0045] exist Fig. 9 In the embodiment of the present invention, a planarization process is performed to planarize the IMD layer 150. The planarization process may be a CMP process, a mechanical grinding process, etc. After the planarization process, the MRAM cell 58 remains buried, and after the planarization process, portions of the IMD layer 150 in the logic region 50L and the memory region 50M share a planar uppermost surface.

[0046] exist Fig.10 In the embodiment, the hard mask 152 is formed on the flat uppermost surface of the IMD layer 150. The hard mask 152 may include a dielectric material (e.g., silicon oxide, silicon nitride, titanium oxide, BSG, BPSG, USG, FSG, SiOCH, a flowable oxide, a porous oxide, etc.); a conductive material (e.g., titanium, tantalum, tungsten, alloys thereof, etc.); a multilayer thereof, etc. For example, the hard mask 152 may include a silicon carbide layer and a titanium nitride layer formed on the silicon carbide layer, wherein the thickness of the titanium nitride layer is about 1000 Å. to about and the thickness of the silicon carbide layer is about to about The silicon carbide layer is used as a glue layer to improve the adhesion between the titanium nitride layer and the IMD layer 150. After forming the mask material of the hard mask 152, a patterning process is performed, wherein the remaining portion of the mask material forms the hard mask 152. The patterning may be a dry etching process (e.g., an anisotropic etching process) using a photoresist as an etching mask. The photoresist may be a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, etc. The resulting hard mask 152 has an opening 154, exposing a lower portion of the IMD layer 150.

[0047] Fig.11 1 is a top view of the MRAM device 50 after forming the hard mask 152. As discussed further below, the hard mask 152 will be used to pattern the openings 156 (see FIG. 12) in the IMD layer 150, exposing the underlying MRAM cells 58. The openings 154 in the hard mask 152 are each disposed along the MRAM array 52 (see FIG. Figure 1 ). In this way, each opening 156 (see FIG. 12 ) subsequently formed in the IMD layer 150 will expose a plurality of MRAM cells 58 along a column of the resulting MRAM array 52.

[0048] Each opening 154 will be used to expose the same number of MRAM cells 58 in the memory region 50M. The openings 154 in the hard mask 152 have uniform dimensions, for example, uniform width W1 and uniform length L1. The width W1 of the opening 154 may be approximately To date and is larger than the diameter D1 of the MRAM cell 58, for example, the diameter of the top electrode 136. The diameter D1 may be about To date The length L1 can be within the range of The opening 154 may be within a range of about 50 μm to about 50 μm and may be large enough to span across several MRAM cells 58. In the illustrated embodiment, the opening 154 completely exposes the MRAM cell 58 in a central region of the opening 154 and partially exposes the MRAM cell 58 in an end region of the opening 154. Specifically, the opening 154 may overlap the MRAM cell 58 at a distance D2 at an end region of the opening 154, and the distance D2 may be less than about

[0049] Fig.11 The cross section AA is taken along the MRAM array 52 (see Figure 1) and in the direction of, for example, a bit line of the MRAM array 52. ​​Cross section BB is perpendicular to cross section AA and is along a row of the MRAM array 52 and in the direction of, for example, a word line of the MRAM array 52. ​​For clarity, subsequent figures refer to these reference cross sections. Specifically, cross section AA shows Fig. 12A , 13A and 14A, and along cross section BB shows Fig. 12B , 13B and 14B.

[0050] exist Fig. 12A and Fig. 12B In the embodiment, the hard mask 152 is used as an etching mask to pattern the IMD layer 150 and the etch stop layer 148. The patterning may include one or more etching processes and form openings 156 in the IMD layer 150 and the etch stop layer 148. As shown, the openings 156 have the same shape as the openings 154 in the hard mask 152 (see Fig.11 ) have substantially the same top-view shape and size (e.g., the same width W1 and the same length L1). Specifically, a first etching process may be performed to form an opening 156 in the IMD layer 150, and a second etching process may be performed to extend the opening 156 through the etch stop layer 148. In some embodiments, the patterning is one or more dry etching processes, for example, one or more anisotropic etching processes. The etch stop layer 148 helps protect the top electrode 136 (and thereby the MTJ stack 134) from over-etching damage during etching of the IMD layer 150. Because the width W1 of the opening 156 is larger than the MRAM cell 58 (see Fig.11 ) has a diameter D1, Fig. 12B The opening 156 in the cross section shown exposes the sidewalls of the top electrode 136. In some embodiments, a residual portion 148R of the etch stop layer 148 may remain between adjacent top electrodes 136. Although the residual portion 148R of the etch stop layer 148 may remain, the top surface of the top electrode 136 is exposed.

[0051] The opening 156 has a plurality of depths measured from the planar uppermost surface of the IMD layer 150. The opening 156 has a depth D3 above the top electrode 136, which may be about To date The opening 156 has a depth D4 above the residual portion 148R of the etch stop layer 148, and the depth D4 may be about To date In this embodiment, the opening 156 does not completely expose the top surface of all top electrodes 136. Instead, some of the top surfaces of the top electrodes 136 are only partially exposed. In other embodiments (discussed further below), the opening 156 completely exposes the top surface of all top electrodes 136.

[0052] exist Fig.13A and Fig. 13B In the embodiment, a common electrode layer 158 is formed on the hard mask 152 and the opening 156 (see Fig. 12A and Fig. 12B ). The common electrode layer 158 may be formed of a conductive material. In some embodiments, in embodiments where the hard mask 152 includes a conductive material, the common electrode layer 158 is used with the top electrode layer 120 (see Figure 4 ) and / or hard mask 152 are formed by similar materials and methods. The common electrode layer 158 may be formed to a thickness of about To date within the range.

[0053] exist Fig.14A and Fig. 14B In the process, a planarization process is performed to planarize the common electrode layer 158 and the IMD layer 150. The planarization process may be a CMP process, a mechanical grinding process, etc. The redundant portion of the common electrode layer 158 outside the opening 156 is removed by the planarization process (see Fig.13A and Fig. 13B ) and hard mask 152. The planarization process forms a common electrode 160, which includes the remaining portion of the common electrode layer 158.

[0054] Fig.15 1 is a top view of the MRAM device 50 after forming the common electrode 160. As shown in the figure, the common electrode 160 has a shape similar to the opening 154 in the hard mask 152 (see FIG. Fig.11 ) have substantially the same top-view shape and size (e.g., the same width W1 and the same length L1). In this embodiment, the common electrode 160 completely overlaps the MRAM cell 58 in the center region of the common electrode 160, but only partially overlaps the MRAM cell 58 in the end region of the common electrode 160.

[0055] exist Fig.16 In the embodiment of the present invention, the IMD layer 150, the etch stop layer 148 and the IMD layer 108 are patterned to expose the (one or more) etch stop layers 106 in the logic region 50L. In some embodiments, the patterning process may include suitable photolithography and etching processes. After the patterning process, the IMD layer 150, the etch stop layer 148 and the portion of the IMD layer 108 in the memory region 50M remain.

[0056] exist Fig.17 In some embodiments, some of the etch stop layer(s) 106 may be optionally removed, such as in embodiments in which the etch stop layer(s) 106 include multiple layers. For example, when the etch stop layer(s) 106 include a first etch stop layer 106A and a second etch stop layer 106B, a portion of the second etch stop layer 106B in the logic region 50L may be removed to expose the first etch stop layer 106A below. The second etch stop layer 106B may be removed using an isotropic wet cleaning process that is selective to the material of the second etch stop layer 106B. The etching process used to remove the second etch stop layer 106B may be different from the etching process used to pattern the IMD layer 150, the etch stop layer 148, and the IMD layer 108 (e.g., different etchants and / or other etching process parameters may be used). In some embodiments, it may be advantageous to use multiple layers of the etch stop layer(s) 106. For example, the etching process(es) used to etch the IMD layer 150, the etch stop layer 148, and the IMD layer 108 (see Fig.16 ) may etch the second etch stop layer 106B more slowly than the first etch stop layer 106A. Similarly, one or more etching processes (see Fig.21 ) The first etch stop layer 106A may be etched slower than the second etch stop layer 106B.

[0057] exist Fig.18 In the embodiment, an IMD layer 162 is formed on the common electrode 160, the IMD layer 150, and the first etch stop layer 106A. In some embodiments, the IMD layer 162 is formed using materials and methods similar to those of the IMD layer 108. The IMD layer 162 may be formed to a thickness of about 100 to about 500 nm. To date Then, an anti-reflection layer 164 is formed on the IMD layer 162. The anti-reflection layer 164 may be a nitrogen-free anti-reflection layer (NFARL) and may be formed of a nitrogen-free dielectric material (eg, silicon oxycarbide). The anti-reflection layer 164 may be formed to a thickness of about To date The anti-reflective layer 164 will be used to protect the memory region 50M during subsequent processing of the logic region 50L.

[0058] exist Fig.19, an opening 166 is formed in the logic region 50L, exposing the conductive features 104 in the logic region 50L. Specifically, the opening 166 is formed to pass through the anti-reflective layer 164, the IMD layer 162, and the first etch stop layer 106A. The opening 166 can be patterned by suitable photolithography and etching processes. Each opening 166 has an upper (e.g., trench) portion in which a conductive line will be formed and a lower (e.g., via) portion in which a conductive via will be formed. In some embodiments, the opening 166 is formed by a via-first process. In other embodiments, the opening 166 is formed by a trench-first process. As discussed further below, before forming the opening 166, an etch-back process may optionally be performed to remove portions of the IMD layer 162 and the anti-reflective layer 164 above the MRAM cell 58.

[0059] exist Fig. 20 , a conductive material 168 is formed in the opening 166. The conductive material 168 may fill the opening 166, and may also be formed over the IMD layer 162 and the anti-reflective layer 164. The conductive material 168 may be copper, aluminum, tungsten, gold, a combination thereof, or the like, and may be formed in the opening 166 by an electrochemical plating process, CVD, ALD, PVD, or the like, or a combination thereof.

[0060] exist Fig.21 In the embodiment of the present invention, a planarization process is performed to remove excess conductive material 168 outside of the opening 166. The planarization process may be a CMP process, a mechanical grinding process, or the like. The planarization process may remove the anti-reflective layer 164 and expose the uppermost surface of the IMD layer 150 and the shared electrode 160. The planarization process forms a conductive feature 170, which includes the remaining portion of the conductive material 168 in the opening 166. The conductive feature 170 includes a conductive via 170V formed in a lower (e.g., via) portion of the opening 166, and a conductive line 170L formed in an upper (e.g., trench) portion of the opening 166. The memory region 50M may be free of the conductive via 170V and the conductive line 170L. Although each conductive via 170V and the corresponding conductive line 170L are shown as separate elements, it should be understood that they may be continuous conductive features, for example, in an embodiment in which they are formed by a dual damascene process. After the planarization process, the top surfaces of the conductive features 170 , the IMD layer 162 , the IMD layer 150 , and the common electrode 160 are planar.

[0061] After the planarization process, the common electrode 160 has several heights measured from the planar uppermost surface of the IMD layer 150. The common electrode 160 has a height H1 above the top electrode 136, which may be about To date The common electrode 160 is located in the residual portion 148R of the etching stop layer 148 (see Fig. 12A ) has a height H2 above, which can be about to about within the range.

[0062] exist Fig. 22 In the embodiment, another metallization layer (e.g., M6, see Figure 2 ). The metallization layer includes one or more etch stop layers 172, IMD layers 174, and conductive features 176. The conductive features include conductive vias 176V (which may correspond to metal vias V6, see Figure 2 ) and conductive line 176L (which may correspond to metal line L6, see Figure 2 ), and is formed in both the logic region 50L and the memory region 50M. In some embodiments, the etch stop layer(s) 172 may be formed using materials and methods similar to the etch stop layer(s) 106. In some embodiments, the IMD layer 174 is formed using materials and methods similar to the IMD layer 162. In some embodiments, the conductive vias 176V and the conductive lines 176L are formed using materials and methods similar to the conductive vias 176V and the conductive lines 176L, respectively. Although each conductive via 176V and the corresponding conductive line 176L are shown as separate elements, it should be understood that they can be continuous conductive features, for example, in an embodiment in which they are formed by a dual damascene process. It is noteworthy that the conductive vias 176V and the conductive lines 176L can be formed of a conductive material different from the shared electrode 160. The selection of various conductive materials allows the contact resistance with the shared electrode 160 to be adjusted. The conductive feature 176 is electrically connected to the memory device (e.g., MRAM) formed in the memory region 50M and the logic device (e.g., logic circuit) formed in the logic region 50L. Specifically, some conductive vias 176V are physically and electrically connected to the shared electrode 160. In some embodiments, the conductive vias 176V and the conductive lines 176L electrically connect the memory devices in the memory region 50M to the logic devices in the logic region 50L. In some embodiments, the conductive features 176 in the logic region 50L and the memory region 50M are formed using the same process. In some embodiments, the conductive features 176 in the logic region 50L and the conductive features 176 in the memory region 50M are formed using different processes. For example, because the shared electrode 160 provides an increased landing area, the conductive features 176 in the memory region 50M can be formed to be larger (e.g., wider) than the conductive features 176 in the logic region 50L, which can help reduce the contact resistance with the MRAM cell 58.

[0063] Fig.23 176L is a top view of the MRAM device 50 after forming the conductive vias 176V and the conductive lines 176L. As shown, the conductive lines 176L include the conductive lines 176L for the MRAM array 52 (see Figure 1 ) bit lines BL. Each bit line BL is electrically connected to a plurality of shared electrodes 160 through a conductive via 176V. Further, each shared electrode 160 is electrically connected to a plurality of MRAM cells 58 (see Fig.15 ). The conductive via 176V has a width W2, which may be about To date The width W1 of the common electrode 160 is greater than the width W2 of the conductive via 176V.

[0064] Embodiments can achieve advantages. The diameter D1 of the MRAM cell 58 (see Fig.11 ) can be small. Specifically, the diameter D1 of the MRAM cell 58 is smaller than the width W2 of the conductive via 176V, especially when at a higher level of the interconnect structure (e.g., Figure 2 When forming the MRAM cell 58 in M5 of . However, the width W1 of the shared electrode 160 is greater than the width W2 of the conductive via 176V. Advantageously, the shared electrode 160 thus provides a landing pad of sufficient size for the conductive via 176V, which can prevent penetration into the underlying layers during the formation of the conductive via 176V. For example, when etching the opening for the conductive via 176V, the top electrode 136 and the MTJ stack 134 can be protected from over-etching damage. In addition, by providing a larger contact area, the contact resistance of the conductive via 176V can be reduced. Finally, as described above, the conductive material selected for the shared electrode 160 can be different from the conductive material of the overlying conductive feature 176, which allows the contact resistance with the shared electrode 160 to be adjusted.

[0065] Fig.24 and Fig.25 are various views of an MRAM device 50 according to some embodiments. Fig.24 With Fig.15 Similar manufacturing stages are shown, and Fig.25 With Fig. 22 Similar manufacturing stages are shown. In this embodiment, the common electrode 160 is formed to have a greater length L1 than the previous embodiment. For example, in this embodiment, the length L1 may be about The common electrode 160 is within a range of about 50 μm. Due to its longer length L1, the common electrode 160 does not partially overlap with the MRAM cell 58 at the end region of the common electrode 160. In contrast, in this embodiment, the common electrode 160 completely overlaps with all the MRAM cells 58 in contact with the common electrode 160. Increasing the contact area can allow the contact resistance with the MRAM cell 58 to be further reduced.

[0066] Figures 26 to 40 5 is a cross-sectional view of an intermediate stage in the fabrication of an interconnect structure of an MRAM device 50 according to some other embodiments. The interconnect structure also includes an MRAM array of memory cells. As discussed further below, a protection structure will be formed around the memory cells of the MRAM array, which helps protect the memory cells during the subsequent formation of overlying metallization layers. Figures 26 to 40 Some of the features shown are Figures 3 to 23 The features shown are similar and therefore will not be described again. Such features are shown using similar reference numerals.

[0067] exist Fig.26 In the example above, we obtain a value similar to that for Figure 6 The intermediate structure described. Then, the passivation layer 202 is formed to blanket over the MRAM cell 58 and blanket over the recess 130 (see Figure 6 ). In some embodiments, the passivation layer 202 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, or the like, and may be formed using CVD, plasma enhanced chemical vapor deposition (PECVD), ALD, plasma enhanced atomic layer deposition (PEALD), PVD, combinations thereof, or the like. In some embodiments, the passivation layer 202 is a nitride, such as silicon nitride. The passivation layer 202 may reduce or prevent moisture (e.g., H2O) from diffusing into the MRAM cell 58 during subsequent processing. The passivation layer 202 is formed to a thickness of about to about Specifically, the passivation layer 202 is formed to have a sufficient thickness to fill the groove 130 and bury the MRAM cell 58 .

[0068] Then, a dielectric layer 204 is formed over the passivation layer 202. In some embodiments, the dielectric layer 204 is formed using materials and methods similar to those of the IMD layer 108. For example, the dielectric layer 204 may be formed of an oxide, such as silicon oxide. The dielectric layer 204 may be formed to a thickness of about 100 Å. to about within the range.

[0069] Then, a planarization stop layer 206 is formed on the dielectric layer 204. The planarization stop layer 206 may be a nitrogen-free layer and may be formed of a nitrogen-free dielectric material. For example, the planarization stop layer 206 may be formed of a doped or undoped oxide (e.g., silicon oxycarbide). The planarization stop layer 206 may be formed to a thickness of about 1000 Å. To date The planarization stop layer 206 will be used to protect the logic region 50L during subsequent processing (discussed further below).

[0070] Then, a dielectric layer 208 is formed over the planarization stop layer 206. In some embodiments, the dielectric layer 208 is formed using materials and methods similar to those of the IMD layer 108 and the dielectric layer 204. For example, the dielectric layer 208 may be formed of silicon oxide. The dielectric layer 208 may be formed to a thickness of about To date within the range.

[0071] Then, a coating 210 is formed over the dielectric layer 208. The coating 210 serves as a buffer layer to help reduce topographical changes during a subsequent etch-back process. The coating 210 may be formed using a coating process such as a spin coating process. The coating 210 may be formed from a material that is ashed and fluid, such as a bottom layer of a photoresist. After the spin coating process, the material may be cured. Curing the material hardens the coating 210. In some embodiments, curing the material includes exposing the material to an elevated temperature.

[0072] exist Fig. 27 In the embodiment of the present invention, an etch-back process is performed to remove portions of the coating layer 210, the dielectric layer 208, and the planarization stop layer 206. Specifically, the etch-back process removes portions of the planarization stop layer 206 in the memory region 50M to expose portions of the dielectric layer 204 above the MRAM cell 58. The logic region 50L is covered by the remaining portions of the planarization stop layer 206. The etch-back process may be a dry etching process using a process such as CH x F y , CF4, He, O2, N2, Ar, NF3, SF6, a combination thereof, etc., as the etching gas. The coating layer 210 may be consumed by the etch-back process, or the coating layer 210 may be removed by, for example, a suitable ashing or stripping process after the etch-back process. In some embodiments, some portions of the coating layer 210 remain in the logic region 50L after the etch-back process, and these portions are removed after the etch-back process.

[0073] exist Fig.28In the process, a planarization process is performed to expose the top electrode 136 of the MRAM cell 58. The planarization process may be a CMP process, a mechanical grinding process, or the like. The planarization process removes the remaining portion of the dielectric layer 208 and also removes the portion of the dielectric layer 204 above the MRAM cell 58. The planarization stop layer 206 has a lower removal rate than the dielectric layers 204 and 208 relative to the planarization process. In this way, the planarization process may be performed until the planarization stop layer 206 (and thus the top electrode 136) is exposed. In some embodiments, the uppermost surface of the planarization stop layer 206 is formed to have a sufficient thickness so that it extends above the uppermost surface of the top electrode 136, and the top electrode 136 is exposed by, for example, a dishing that may occur during the planarization process. The exposed portion of the planarization stop layer 206 covers the logic region 50L and may cover a portion of the memory region 50M. Although the planarization process does not remove the planarization stop layer 206, it may reduce the thickness of the planarization stop layer 206. After the planarization process, the thickness T1 of the planarization stop layer 206 may be about To date within the range.

[0074] exist Fig.29 In the embodiment of the present invention, an etch back process 212 is performed to recess the passivation layer 202 and form a groove 214 around the top electrode 136 of the MRAM cell 58. The groove 214 is formed to have a depth D5, which may be about To date The recess 214 exposes the sidewalls of the top electrode 136 but does not expose the sidewalls of the MTJ stack 134. After the etch-back process 212, the sidewalls of the MTJ stack 134 remain covered and protected by the passivation layer 202.

[0075] The etch back process 212 is selective to the material of the passivation layer 202. As described above, in some embodiments, the passivation layer 202 is a nitride, and the dielectric layer 204 and the planarization stop layer 206 are oxides. In such embodiments, the etch back process 212 may etch the material of the passivation layer 202 (e.g., nitride) at a higher rate than the material(s) of the dielectric layer 204 and the planarization stop layer 206 (e.g., oxide). For example, the ratio of the etch rate of the passivation layer 202 to the etch rate of the dielectric layer 204 and the planarization stop layer 206 relative to the etch back process 212 may be in the range of about 3:1 to about 10:1. As examples of the etch back process 212, dielectrics such as HBr, CF4, He, O2, N2, CH x F y, combinations thereof, etc. as etching gases to perform dry etching processes such as IBE, reactive ion etching (RIE), etc. N2, Ar, He, combinations thereof, etc. can be used as carrier gases for etching gases. Etching can be achieved using glow discharge plasma (GDP), capacitively coupled plasma (CCP), inductively coupled plasma (ICP), etc. Etching can be performed at a source power in the range of about 100 watts to about 1500 watts, and can be performed at a bias voltage of up to about 1000 volts. Etching can be performed for a duration in the range of about 7 seconds to about 300 seconds. Performing the etch back process 212 with such parameters allows a high etching selectivity between the material (e.g., nitride) of the passivation layer 202 and the material (e.g., oxide) of the dielectric layer 204 and the planarization stop layer 206.

[0076] Although the etch-back process 212 is selective to the material of the passivation layer 202, some etching of the planarization stop layer 206 may still occur. For example, the etch-back process 212 may reduce the thickness of the planarization stop layer 206 to about To date The new thickness T2 of the planarization stop layer 206 is less than the original thickness T1 of the planarization stop layer 206, but still has sufficient thickness to withstand subsequent processing. In some embodiments, the new thickness T2 of the planarization stop layer 206 is at least half of the original thickness T1 of the planarization stop layer 206.

[0077] exist Fig.30 In the embodiment of the present invention, a protective layer 216 is formed in the recess 214 and on the exposed surfaces of the MRAM cell 58, the dielectric layer 204, and the planarization stop layer 206. The protective layer 216 is formed of a dielectric material such as aluminum nitride, aluminum oxide, silicon carbide, silicon carbonitride, combinations thereof, multilayers thereof, and the like, and is formed by a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), ALD, combinations thereof, and the like. The protective layer 216 is formed of a material having a high selectivity relative to an etching process (discussed further below) that will be used to pattern a subsequently formed metallization layer of the interconnect structure. For example, the protective layer 216 can be a silicon carbide layer, an aluminum oxide layer, or a multilayer including a silicon carbide sublayer and an aluminum oxide sublayer located on the silicon carbide sublayer. After formation, the protective layer 216 surrounds the top electrode 136 of the MRAM cell 58. Advantageously, forming the protective layer 216 in the recess 214 allows the protective layer 216 to be self-aligned with the top electrode 136.

[0078] exist Fig.31 In the embodiment, a planarization process is performed to expose the top electrode 136 of the MRAM cell 58. The planarization process removes the protective layer 216 in the groove 214 (see Fig.29), for example, the portion of the protection layer 216 above the MRAM cell 58, the dielectric layer 204, and the planarization stop layer 206. The planarization process may be a CMP process, a mechanical grinding process, or the like. Relative to the planarization process, the planarization stop layer 206 has a lower removal rate than the protection layer 216. In this way, the planarization process may be performed until the planarization stop layer 206 is exposed. After the planarization process, the top electrode 136 is exposed. The planarization process forms a protection structure 218, which includes a portion of the protection layer 216 remaining in the recess 214 after the planarization process.

[0079] A plurality of planarization processes are performed using the planarization stop layer 206. Specifically, Fig.28 and Fig.31 The planarization processes are performed in two steps, and both stop on the planarization stop layer 206. Performing multiple planarization processes helps reduce uneven topography that may be caused by pattern density variations between the logic region 50L and the memory region 50M, and helps ensure that features in the logic region 50L and the memory region 50M share a flat top surface.

[0080] After the planarization process, the protection structure 218 has a thickness T3, which may be about To date and the top electrode 136 has a thickness T4 which may be in the range of about To date The thickness T3 is less than the thickness T4. Specifically, the thickness T3 of the protection structure 218 is sufficient to ensure that the MRAM cell 58 is protected during subsequent processing, but is small enough to ensure that the sidewalls of the MTJ stack 134 are free of undesirable materials (and thus maintain their desired high resistance (R ap ) and low resistance (R p ) value), for example, residues resulting from a subsequent contact etch process (discussed further below).

[0081] exist Fig.32 In the embodiment of the present invention, the anti-reflective layer 220 is formed on the planar surface of the intermediate structure. Specifically, the anti-reflective layer 220 is formed on the planar surfaces of the protective structure 218, the top electrode 136, the planarization stop layer 206, and the dielectric layer 204. The anti-reflective layer 220 can be a nitrogen-free anti-reflective layer (NFARL) and can be formed of a nitrogen-free dielectric material (e.g., silicon oxycarbide). In some embodiments, the anti-reflective layer 220 is formed of a different material than the protective structure 218. The anti-reflective layer 220 can be formed to a thickness of about 1000 Å. To date During the subsequent processing of the logic region 50L, the anti-reflective layer 220 will be used to protect the memory region 50M.

[0082] exist Fig.33 In the embodiment of the present invention, the intermediate structure is patterned to expose the (one or more) etching stop layers 106 in the logic region 50L. The patterning may include suitable photolithography and etching processes. For example, one or more dry etching processes may be performed using an etching mask 222 to etch the anti-reflective layer 220, the planarization stop layer 206, the dielectric layer 204, the passivation layer 202, and the IMD layer 108. The etching mask 222 may be a photoresist, for example, a single layer of photoresist, a double layer of photoresist, a triple layer of photoresist, etc. In some embodiments, the remaining portion of the planarization stop layer 206 is removed by the (one or more) etching process. In some embodiments (discussed below), portions of the planarization stop layer 206 may be retained after the (one or more) etching process. Portions of the dielectric layer 204 may remain in the memory region 50M after the (one or more) etching process. The etching process(es) form one or more openings 224 that expose the etching stop layer(s) 106, for example, the second etching stop layer 106B in embodiments where the etching stop layer(s) 106 include multiple layers. The etching mask 222 may be consumed by the etching process(es), or the etching mask 222 may be removed after the etching process(es) by, for example, a suitable ashing or stripping process.

[0083] exist Fig.34 224, some of the etch stop layer(s) 106 may optionally be removed, such as in embodiments in which the etch stop layer(s) 106 include multiple layers. For example, when the etch stop layer(s) 106 include a first etch stop layer 106A and a second etch stop layer 106B, a portion of the second etch stop layer 106B in the opening(s) 224 may be removed to expose the first etch stop layer 106A underneath. The second etch stop layer 106B may be removed using an isotropic wet cleaning process that is selective to the material of the second etch stop layer 106B. The etching process used to remove the second etch stop layer 106B may be different from the etching process(es) used to initially form the opening(s) 224 (e.g., different etchants and / or other etching process parameters may be used). In some embodiments, it may be advantageous to use multiple layers of the etch stop layer(s) 106. For example, the etching process(es) used to etch the anti-reflective layer 220, the planarization stop layer 206, the dielectric layer 204, the passivation layer 202, and the IMD layer 108 (see Fig.32) The etching of the second etch stop layer 106B may be slower than that of the first etch stop layer 106A. Similarly, one or more etching processes (see Fig.39 ) The etching of the first etch stop layer 106A can be slower than that of the second etch stop layer 106B.

[0084] exist Fig.35 , an IMD layer 162 is formed in the opening(s) 224 and over the MRAM cell 58 and the protection structure 218, for example, over the anti-reflective layer 220. An anti-reflective layer 164 is then formed over the IMD layer 162. The anti-reflective layer 164 will be used to protect the memory region 50M during subsequent processing of the logic region 50L.

[0085] exist Fig.36 In the embodiment of the present invention, an etch-back process may be optionally performed to remove the portion of the IMD layer 162 and the anti-reflective layer 164 above the MRAM cell 58, thereby exposing the anti-reflective layer 220. Portions of the logic region 50L (e.g., portions located above the conductive features 104) may be covered by the etch mask 226 during the etch-back process. The etch-back process may be a dry etch process using a process such as CH x F y , CF4, He, O2, N2, Ar, NF3, SF6, combinations thereof, and the like are used as etching gases. The etching mask 226 may be consumed by the etch-back process, or the etching mask 226 may be removed by, for example, a suitable ashing or stripping process after the etch-back process. After the etch-back process, the remaining portion of the anti-reflective layer 164 is disposed in the logic region 50L and does not extend into the memory region 50M. In some embodiments, the etch-back process is omitted, and the portions of the IMD layer 162 and the anti-reflective layer 164 above the MRAM cell 58 may be removed during a subsequent planarization process (discussed further below).

[0086] exist Fig.37 In the embodiment, openings 166 are formed in the logic region 50L, thereby exposing the conductive features 104 in the logic region 50L. Specifically, the openings 166 are formed through the anti-reflective layer 164, the IMD layer 162, and any (one or more) etch stop layers 106 (e.g., the first etch stop layer 106A) remaining in the logic region 50L. The openings 166 may be formed using the same method as described above for Fig.19 The processes and materials discussed can be formed by processes and materials similar to those discussed.

[0087] exist Fig.38In the embodiment, the conductive material 168 is formed in the opening 166. The conductive material 168 may overfill the opening 166 and may also be formed on the IMD layer 162 and the anti-reflective layers 164 and 220. The conductive material 168 may be used in the same manner as described above for Fig. 20 The processes and materials discussed can be formed by processes and materials similar to those discussed.

[0088] exist Fig.39 In the process, a planarization process is performed to remove excess conductive material 168 outside of opening 166. The planarization process can be a CMP process, a mechanical grinding process, etc. The planarization process can remove anti-reflective layers 164 and 220 and expose top electrode 136 and protection structure 218. The planarization process forms conductive features 170. After the planarization process, the top surfaces of conductive features 170, IMD layer 162, protection structure 218, dielectric layer 204, and top electrode 136 are flat.

[0089] As mentioned above, Fig.36 The etch-back process shown is optional. The etch-back process can help reduce the uneven topography caused by the pattern density variation between the logic region 50L and the memory region 50M. In some embodiments, the etch-back process is omitted. Fig.36 The etch-back process shown may alternatively be Fig.39 Portions of the IMD layer 162 and the anti-reflective layer 164 over the MRAM cell 58 are removed during the illustrated planarization process.

[0090] exist Fig.40 , forming (one or more) etch stop layers 172, IMD layers 174, and conductive features 176. In the illustrated embodiment, (one or more) etch stop layers 172 include a single etch stop layer 172, such as a silicon nitride layer. Conductive vias 176V in memory region 50M are physically and electrically connected to top electrode 136. MRAM cell 58 can be very small, especially when high density memory is required. For example, the diameter D1 of top electrode 136 can be smaller than the width W2 of conductive via 176V above, especially when at a higher level of the interconnect structure (e.g., Figure 2 When forming the MRAM cell 58 in M5 of FIG. 1 , the conductive via 176V may contact a portion of the protection structure 218 and the top electrode 136.

[0091] In some embodiments, conductive feature 176 is formed using materials and methods similar to conductive feature 170. For example, an opening is formed to expose conductive feature 170 and top electrode 136. The opening is filled with a conductive material, and then a planarization process is performed to form conductive feature 176, which includes the remaining portion of the conductive material in the opening. When forming the opening for conductive feature 176, IMD layer 174 is patterned by a first etching process, and etch stop layer 172 is used to stop the first etching process. The first etching process may include suitable photolithography and etching steps. Then, etch stop layer 172 is opened by a second etching process to expose conductive feature 170 and top electrode 136. The second etching process may include suitable photolithography and etching steps. During the second etching process, protection structure 218 surrounds and protects MRAM cell 58. Protection can be achieved in several ways. Protection structure 218 prevents the second etching process from etching the MTJ stack 134 of MRAM cell 58. Therefore, damage to MRAM cell 58 can be avoided.

[0092] In some embodiments, the protection structure 218 is formed of an etch stop material similar to the etch stop layer 172. The amount of etch stop material protecting the MRAM cell 58 is thus increased, thereby expanding the process window of the second etch process. The likelihood of etching the MTJ stack 134 is thus reduced.

[0093] In some embodiments, the protective structure 218 is formed of an etch stop material different from the etch stop layer 172. Specifically, the second etching process can be selective to the material of the etch stop layer 172. For example, in some embodiments, the protective structure 218 is silicon carbide and / or aluminum oxide, and the etch stop layer 172 is silicon nitride. In such embodiments, the second etching process can etch the material (e.g., silicon nitride) of the etch stop layer 172 at a higher rate than the material (e.g., silicon carbide and / or aluminum oxide) of the etching protective structure 218. For example, relative to the second etching process, the ratio of the etching rate of the etch stop layer 172 to the etching rate of the protective structure 218 can be in the range of about 1 to about 5. As an example of the second etching process, an isotropic wet cleaning process that is selective to the material of the etch stop layer 172 can be performed. Etching can be performed using a solution including water (e.g., deionized water, carbonated deionized water, etc.). Etching can be performed for a duration in the range of about 5 seconds to about 600 seconds. Performing the second etching process with such parameters allows achieving high etching selectivity between the material of the etch stop layer 172 (eg, silicon nitride) and the material of the protection structure 218 (eg, silicon carbide and / or aluminum oxide). Thus, the likelihood of etching the MTJ stack 134 is further reduced.

[0094] Fig.41is a cross-sectional view of an MRAM device 50 according to some other embodiments. Fig.41 An embodiment is shown in which some etching of the protection structure 218 occurs during the formation of the conductive features 176. As shown, the protection structure 218 helps protect the MTJ stack 134 even when partial perforation of the protection structure 218 occurs.

[0095] Fig.42 is a cross-sectional view of an MRAM device 50 according to some other embodiments. In this embodiment, a portion of the planarization stop layer 206 is Fig.33 These remaining portions of the planarization stop layer 206 are disposed between the remaining portions of the dielectric layer 204 and the etch stop layer 172 .

[0096] Embodiments can achieve advantages. Forming the protection structure 218 around the top electrode 136 helps protect the MRAM cell 58 when forming the overlying metallization layer. Specifically, etching of the MTJ stack 134 can be avoided during the formation of the conductive feature 176. The protection structure 218 can protect the top electrode 136 by expanding the process window for forming the conductive feature 176, or acting as an etch stop layer to prevent etching of the MTJ stack 134. Therefore, damage to the MRAM cell 58 can be avoided, thereby improving the manufacturing yield of the resulting device.

[0097] Although embodiments have been described in the context of MRAM cells, it should be understood that similar techniques can be used to form other types of memory cells having programmable resistance elements. For example, similar techniques can be used to form phase change memory (PCRAM) cells, resistive random access memory (RRAM) cells, etc.

[0098] In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, wherein a first column of the columns includes: a first bottom electrode arranged along the first column; a first magnetic tunnel junction (MTJ) stack located above the first bottom electrode; a first shared electrode located above each first MTJ stack; a second bottom electrode arranged along the first column; a second MTJ stack located above the second bottom electrode; a second shared electrode located above each second MTJ stack; and a bit line electrically connected to the first shared electrode and the second shared electrode.

[0099] In some embodiments of the device, the first bottom electrode, the second bottom electrode, the first shared electrode, and the second shared electrode all include titanium nitride, and the bit line includes copper. In some embodiments of the device, the first column also includes: a first top electrode disposed between the first MTJ stack and the first shared electrode; a second top electrode disposed between the second MTJ stack and the second shared electrode; a first conductive via physically and electrically connecting the bit line to the first shared electrode; and a second conductive via physically and electrically connecting the bit line to the second shared electrode, the width of the first conductive via and the second conductive via being greater than the width of each first top electrode and each second top electrode. In some embodiments of the device, the width of the first shared electrode and the second shared electrode is greater than the width of the first top electrode, the second top electrode, the first conductive via, and the second conductive via. In some embodiments of the device, the first shared electrode completely overlaps each first top electrode. In some embodiments of the device, the first shared electrode completely overlaps a first subset of the first top electrodes and partially overlaps a second subset of the first top electrodes. In some embodiments of the device, the first shared electrode and the second shared electrode have the same length along the first column. In some embodiments of the device, each of the rows includes a word line electrically connected to one of the first bottom electrode or the second bottom electrode, and the device further includes: a row decoder electrically connected to the word line of each of the rows; a column decoder electrically connected to the bit line. In some embodiments of the device, the first column further includes: a first spacer laterally surrounding the first bottom electrode and the first MTJ stack; and an etch stop layer extending along a top surface and sidewalls of the first spacer; and a first intermetallic dielectric (IMD) layer located on the etch stop layer, wherein the first shared electrode extends through the first IMD layer and the etch stop layer. In some embodiments of the device, the etch stop layer includes aluminum nitride.

[0100] In an embodiment, a method includes: forming a first intermetal dielectric (IMD) layer over a substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a top electrode layer over the MTJ film stack; patterning the top electrode layer, the MTJ film stack, and the bottom electrode layer to form a first magnetoresistive random access memory (MRAM) cell and a second MRAM cell; forming spacers around sidewalls of the first MRAM cell and the second MRAM cell; depositing an etch stop layer over an exposed portion of the first IMD layer and the spacers; depositing a second IMD layer over the etch stop layer; exposing portions of the first MRAM cell and the second MRAM cell; and forming a shared electrode on the exposed portions of the first MRAM cell and the second MRAM cell.

[0101] In some embodiments of the method, exposing portions of the first MRAM cell and the second MRAM cell includes etching an opening in the second IMD layer, and forming the shared electrode includes: depositing a conductive material in the opening; and planarizing the conductive material to remove a portion of the conductive material outside the opening, the shared electrode including a remaining portion of the conductive material after planarization. In some embodiments, the method further includes: depositing a third IMD layer over the shared electrode and the second IMD layer; planarizing the third IMD layer so that the surfaces of the third IMD layer, the second IMD layer, and the shared electrode are planar; and forming a conductive feature in the third IMD layer. In some embodiments, the method further includes: depositing a fourth IMD layer over the third IMD layer, the second IMD layer, and the shared electrode; forming a conductive via in the fourth IMD layer; and forming a bit line in the fourth IMD layer, the conductive via physically and electrically connecting the bit line to the shared electrode. In some embodiments of the method, exposing portions of the first MRAM cell and the second MRAM cell includes etching an opening in the second IMD layer and the etch stop layer, the opening completely exposing a first top surface of the first MRAM cell and partially exposing a second top surface of the second MRAM cell. In some embodiments of the method, exposing portions of the first and second MRAM cells includes etching openings in the second IMD layer and the etch stop layer that completely expose a first top surface of the first MRAM cell and a second top surface of the second MRAM cell.

[0102] In an embodiment, a method includes: forming a magnetoresistive random access memory (MRAM) cell over a substrate, the MRAM cell including: a first bottom electrode over the substrate; a first magnetic tunnel junction (MTJ) stack over the first bottom electrode; a first top electrode over the first MTJ stack; forming a first dielectric layer laterally surrounding the first bottom electrode, the first MTJ stack, and the first top electrode; recessing the first dielectric layer to expose a portion of a sidewall of the first top electrode; forming a protection structure in contact with the exposed portion of the sidewall of the first top electrode; depositing a first intermetallic dielectric (IMD) layer over the MRAM cell; and forming a conductive feature extending through the first IMD layer, the conductive feature in contact with the first top electrode and the protection structure.

[0103] In some embodiments of the method, recessing the first dielectric layer to form a groove, and forming the protection structure includes: depositing a second dielectric layer in the recess; and planarizing the second dielectric layer to form the protection structure, the surface of the protection structure and the first top electrode being planar. In some embodiments, the method further includes: forming an etch stop layer over the protection structure, the first IMD layer being deposited over the etch stop layer, the etch stop layer and the protection structure comprising different dielectric materials. In some embodiments, the method further includes: forming an etch stop layer over the protection structure, the first IMD layer being deposited over the etch stop layer, the etch stop layer and the protection structure comprising the same dielectric material.

[0104] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0105] Example 1. A semiconductor device comprising: a magnetoresistive random access memory (MRAM) array, comprising MRAM cells arranged in rows and columns, wherein a first column of the columns comprises: a first bottom electrode arranged along the first column; a first magnetic tunnel junction (MTJ) stack located above the first bottom electrode; a first shared electrode located above each of the first MTJ stacks; a second bottom electrode arranged along the first column; a second MTJ stack located above the second bottom electrode; a second shared electrode located above each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

[0106] Example 2. The semiconductor device of Example 1, wherein the first bottom electrode, the second bottom electrode, the first common electrode, and the second common electrode all comprise titanium nitride, and wherein the bit line comprises copper.

[0107] Example 3. A semiconductor device according to Example 1, wherein the first column further includes: a first top electrode, disposed between the first MTJ stack and the first shared electrode; a second top electrode, disposed between the second MTJ stack and the second shared electrode; a first conductive via, physically and electrically connecting the bit line to the first shared electrode; and a second conductive via, physically and electrically connecting the bit line to the second shared electrode, the width of the first conductive via and the second conductive via being greater than the width of each of the first top electrodes and each of the second top electrodes.

[0108] Example 4. The semiconductor device of Example 3, wherein the widths of the first common electrode and the second common electrode are greater than the widths of the first top electrode, the second top electrode, the first conductive via, and the second conductive via.

[0109] Example 5. The semiconductor device of Example 3, wherein the first common electrode completely overlaps each of the first top electrodes.

[0110] Example 6. The semiconductor device of Example 3, wherein the first shared electrode completely overlaps a first subset of the first top electrodes and partially overlaps a second subset of the first top electrodes.

[0111] Example 7. The semiconductor device of Example 1, wherein the first common electrode and the second common electrode have the same length along the first column.

[0112] Example 8. A semiconductor device according to Example 1, wherein each of the rows includes a word line electrically connected to one of the first bottom electrode or the second bottom electrode, and the device further includes: a row decoder electrically connected to the word line of each of the rows; and a column decoder electrically connected to the bit line.

[0113] Example 9. A semiconductor device according to Example 1, wherein the first column further includes: a first spacer laterally surrounding the first bottom electrode and the first MTJ stack; an etch stop layer extending along the top surface and sidewalls of the first spacer; and a first intermetallic dielectric (IMD) layer located on the etch stop layer, wherein the first shared electrode extends through the first IMD layer and the etch stop layer.

[0114] Example 10. The semiconductor device of Example 9, wherein the etch stop layer comprises aluminum nitride.

[0115] Example 11. A method for manufacturing a semiconductor device, comprising: forming a first intermetallic dielectric (IMD) layer over a substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a top electrode layer over the MTJ film stack; patterning the top electrode layer, the MTJ film stack, and the bottom electrode layer to form a first magnetoresistive random access memory (MRAM) cell and a second MRAM cell; forming a spacer around sidewalls of the first MRAM cell and the second MRAM cell; depositing an etch stop layer over an exposed portion of the first IMD layer and the spacer; depositing a second IMD layer over the etch stop layer; exposing portions of the first MRAM cell and the second MRAM cell; and forming a shared electrode on the exposed portions of the first MRAM cell and the second MRAM cell.

[0116] Example 12. A method according to Example 11, wherein exposing the portions of the first MRAM cell and the second MRAM cell includes etching openings in the second IMD layer, and wherein forming the shared electrode includes: depositing a conductive material in the openings; and planarizing the conductive material to remove portions of the conductive material outside the openings, the shared electrode including a remaining portion of the conductive material after the planarization.

[0117] Example 13. The method according to Example 11 also includes: depositing a third IMD layer over the shared electrode and the second IMD layer; planarizing the third IMD layer so that the surfaces of the third IMD layer, the second IMD layer and the shared electrode are flat; and forming conductive features in the third IMD layer.

[0118] Example 14. The method according to Example 13 further includes: depositing a fourth IMD layer over the third IMD layer, the second IMD layer and the shared electrode; forming a conductive via in the fourth IMD layer; and forming a bit line in the fourth IMD layer, the conductive via physically and electrically connecting the bit line to the shared electrode.

[0119] Example 15. The method of Example 11, wherein exposing the portions of the first MRAM cell and the second MRAM cell comprises etching openings in the second IMD layer and the etch stop layer, the openings completely exposing a first top surface of the first MRAM cell and partially exposing a second top surface of the second MRAM cell.

[0120] Example 16. The method of Example 11, wherein exposing the portions of the first MRAM cell and the second MRAM cell comprises etching openings in the second IMD layer and the etch stop layer, the openings completely exposing a first top surface of the first MRAM cell and a second top surface of the second MRAM cell.

[0121] Example 17. A method for manufacturing a semiconductor device, comprising: forming a magnetoresistive random access memory (MRAM) cell above a substrate, the MRAM cell comprising: a first bottom electrode located above the substrate; a first magnetic tunnel junction (MTJ) stack located above the first bottom electrode; a first top electrode located above the first MTJ stack; forming a first dielectric layer laterally surrounding the first bottom electrode, the first MTJ stack and the first top electrode; recessing the first dielectric layer to expose a portion of a sidewall of the first top electrode; forming a protection structure in contact with the exposed portion of the sidewall of the first top electrode; depositing a first intermetallic dielectric (IMD) layer above the MRAM cell; and forming a conductive feature extending through the first IMD layer, the conductive feature in contact with the first top electrode and the protection structure.

[0122] Example 18. A method according to Example 17, wherein the first dielectric layer is recessed to form a groove, and wherein forming the protective structure includes: depositing a second dielectric layer in the groove; and planarizing the second dielectric layer to form the protective structure, and the surfaces of the protective structure and the first top electrode are flat.

[0123] Example 19. The method of Example 17, further comprising: forming an etch stop layer over the protection structure, the first IMD layer being deposited over the etch stop layer, the etch stop layer and the protection structure comprising a same dielectric material.

[0124] Example 20. The method according to Example 17 further includes: forming an etch stop layer on the protection structure, the first IMD layer is deposited on the etch stop layer, the etch stop layer includes silicon nitride, and the protection structure includes silicon carbide or aluminum oxide.

Claims

1. A semiconductor device, comprising: A magnetoresistive random access memory (MRAM) array comprises MRAM cells arranged in rows and columns, wherein a first column of the columns comprises: a first bottom electrode arranged along the first column; A first magnetic tunnel junction MTJ stack is located on the first bottom electrode; a first common electrode disposed on each of the first MTJ stacks; a second bottom electrode arranged along the first column; a second MTJ stack located on the second bottom electrode; A second common electrode located on each of the second MTJ stacks; and A bit line is electrically connected to the first common electrode and the second common electrode.

2. The semiconductor device according to claim 1, wherein The first bottom electrode, the second bottom electrode, the first common electrode, and the second common electrode all include titanium nitride, and wherein the bit line includes copper.

3. The semiconductor device according to claim 1, wherein The first column also includes: a first top electrode disposed between the first MTJ stack and the first common electrode; a second top electrode disposed between the second MTJ stack and the second common electrode; a first conductive via physically and electrically connecting the bit line to the first common electrode; and A second conductive via physically and electrically connects the bit line to the second common electrode, wherein the width of the first conductive via and the second conductive via are greater than the width of each of the first top electrodes and each of the second top electrodes.

4. The semiconductor device according to claim 3, wherein: Widths of the first common electrode and the second common electrode are greater than widths of the first top electrode, the second top electrode, the first conductive via, and the second conductive via.

5. The semiconductor device according to claim 3, wherein: The first common electrode completely overlaps with each of the first top electrodes.

6. The semiconductor device according to claim 3, wherein: The first shared electrode completely overlaps a first subset of the first top electrodes and partially overlaps a second subset of the first top electrodes.

7. The semiconductor device according to claim 1, wherein The first common electrode and the second common electrode have the same length along the first column.

8. The semiconductor device according to claim 1, wherein Each of the rows comprises a word line electrically connected to one of the first bottom electrode or the second bottom electrode, and the device further comprises: a row decoder electrically connected to the word line of each of the rows; and A column decoder is electrically connected to the bit lines.

9. The semiconductor device according to claim 1, wherein: The first column also includes: a first spacer laterally surrounding the first bottom electrode and the first MTJ stack; an etch stop layer extending along a top surface and sidewalls of the first spacer; and A first intermetal dielectric (IMD) layer is located on the etch stop layer, wherein the first common electrode extends through the first IMD layer and the etch stop layer.

10. The semiconductor device according to claim 9, wherein The etch stop layer includes aluminum nitride.

11. A method for manufacturing a semiconductor device, comprising: forming a first intermetal dielectric (IMD) layer on the substrate; forming a bottom electrode layer on the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack on the bottom electrode layer; forming a top electrode layer over the MTJ film stack; patterning the top electrode layer, the MTJ film stack, and the bottom electrode layer to form a first magnetoresistive random access memory (MRAM) cell and a second MRAM cell; forming spacers around sidewalls of the first MRAM cell and the second MRAM cell; depositing an etch stop layer over the exposed portions of the first IMD layer and the spacers; depositing a second IMD layer over the etch stop layer; exposing portions of the first MRAM cell and the second MRAM cell; as well as forming a common electrode on the exposed portions of the first MRAM cell and the second MRAM cell, depositing a third IMD layer on the second IMD layer and the common electrode; A bit line is formed in the third IMD layer, the bit line being electrically connected to the common electrode.

12. The method according to claim 11, wherein: Exposing the portions of the first MRAM cell and the second MRAM cell includes etching openings in the second IMD layer, and wherein forming the shared electrode includes: depositing a conductive material in the opening; and The conductive material is planarized to remove a portion of the conductive material outside the opening, and the common electrode includes a remaining portion of the conductive material after the planarization.

13. The method according to claim 11, further comprising: depositing a fourth IMD layer on the common electrode and the second IMD layer; Planarizing the fourth IMD layer so that surfaces of the fourth IMD layer, the second IMD layer and the common electrode are flat; as well as forming a conductive feature in the fourth IMD layer, The third IMD layer further extends on the fourth IMD layer.

14. The method according to claim 13, further comprising: A conductive via is formed in the third IMD layer, the conductive via physically and electrically connecting the bit line to the common electrode.

15. The method according to claim 11, wherein: Exposing the portions of the first and second MRAM cells includes etching openings in the second IMD layer and the etch stop layer, the openings completely exposing a first top surface of the first MRAM cell and partially exposing a second top surface of the second MRAM cell.

16. The method according to claim 11, wherein: Exposing the portions of the first and second MRAM cells includes etching openings in the second IMD layer and the etch stop layer, the openings completely exposing a first top surface of the first and second top surfaces of the second MRAM cells.

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