Device including a threshold voltage compensated sense amplifier and method for compensating the same

Abstract

The present invention discloses an apparatus including a threshold voltage compensated sense amplifier and a method for compensating the apparatus. An example apparatus includes first and second pull-up transistors coupled to a first power supply node, and first and second pull-down transistors coupled to a second power supply node. A first isolation transistor is coupled to the gate of the second pull-down transistor and to a first sense node to which the first pull-up transistor and the first pull-down transistor are also coupled. A second isolation transistor is coupled to the gate of the first pull-down transistor and to a second sense node to which the second pull-up transistor and the second pull-down transistor are also coupled. An equalization transistor is coupled to the gates of the first and second pull-down transistors, and a precharge transistor is coupled to the second power supply node and to the gate of the first or second pull-down transistor.

Description

Technical Field

[0001] The present application relates to memory devices, and in particular, to memory devices including threshold voltage compensated sense amplifiers. Background Art

[0002] The memory device is structured to have one or more memory cell arrays at least logically arranged in rows and columns. Each memory cell stores data as an electric charge for access by a digit line associated with the memory cell. When a charged memory cell is accessed, the memory cell causes a positive voltage change on the associated digit line, and an accessed memory cell without a charge causes a negative voltage change on the associated digit line. A sense amplifier can sense and amplify the voltage change on the digit line to indicate the value of the data state stored in the memory cell.

[0003] Conventional sense amplifiers are typically coupled to a pair of complementary digit lines connected to a large number of memory cells (not shown). As is known in the art, when a memory cell is accessed, a row of memory cells is activated, and a sense amplifier is used to amplify the data state of the corresponding activated column of memory cells by coupling each of the digit lines of the selected column to a voltage source so that the digit lines have complementary logic levels.

[0004] When a memory cell is accessed, the voltage of one of the digit lines increases or decreases slightly, depending on whether the memory cell coupled to the digit line is charged, which creates a voltage difference between the digit lines. When the voltage of one digit line increases or decreases slightly, the other digit line does not serve as a reference for the sensing operation. Due to the voltage difference, the corresponding transistor is enabled, thereby coupling the slightly higher voltage digit line to the supply voltage and coupling the other digit line to the reference voltage (e.g., ground) to further drive each of the digit lines in the opposite direction and amplify the selected digit line signal.

[0005] The digit lines are precharged to a precharge voltage (e.g., one-half of the supply voltage) during a precharge period so that the voltage difference can be accurately sensed and amplified during a subsequent sensing operation. However, due to threshold voltage mismatches of transistor components, the digit lines may become unbalanced before a voltage change on one of the digit lines is sensed and amplified. Such threshold voltage mismatches may cause the sense amplifier to erroneously amplify the input signal in the wrong direction. Therefore, a sense amplifier design that reduces threshold voltage mismatches is needed. Summary of the invention

[0006] Aspects of the present disclosure are directed to a device comprising: a first pull-up transistor coupled to a first power supply node; a second pull-up transistor coupled to the first power supply node; a first pull-down transistor coupled to a second power supply node; a second pull-down transistor coupled to the second power supply node; a first isolation transistor coupled to a first sense node to which the first pull-up transistor and the first pull-down transistor are also coupled, and the first isolation transistor is further coupled to a gate of the second pull-down transistor; a second isolation transistor coupled to a second sense node to which the second pull-up transistor and the second pull-down transistor are also coupled, and the second isolation transistor is further coupled to a gate of the first pull-down transistor; an equalization transistor coupled to the gates of the first and second pull-down transistors; and a precharge transistor coupled to the second power supply node and further coupled to the gate of the first or second pull-down transistor.

[0007] Another aspect of the disclosure is directed to a device comprising: a first pull-up transistor coupled to a first power supply node; a second pull-up transistor coupled to the first power supply node; a first pull-down transistor coupled to the second power supply node and having a gate coupled to a first sense node; a second pull-down transistor coupled to the second power supply node and having a gate coupled to a second sense node; a first isolation transistor coupled to the first pull-up transistor and further coupled to the first pull-down transistor at a first gut node; a second isolation transistor coupled to the second pull-up transistor and further coupled to the second pull-down transistor at a second gut node; a first equalization transistor coupled to the first gut node and the first sense node; a second equalization transistor coupled to the second gut node and the second sense node; a third isolation transistor coupled to the second sense node and the first gut node; and a fourth isolation transistor coupled to the first sense node and the second gut node.

[0008] Another aspect of the present disclosure is directed to a method including: precharging and equalizing first and second sense nodes of a sense amplifier; isolating the first and second sense nodes of the sense amplifier; and increasing a supply voltage provided to a supply node to which gates and sources of first and second pull-down transistors are coupled to provide corresponding voltages at the first and second sense nodes for use in compensating threshold voltages of the first and second pull-down transistors.

[0009] Yet another aspect of the present disclosure is directed to a method, comprising: sharing voltages of first and second sense nodes to precharge the first and second sense nodes; isolating the first and second sense nodes; and reducing a power supply voltage provided to a power supply node to cause the first and second sense nodes to discharge to corresponding sense node voltages through corresponding diode-coupled pull-down transistors, thereby providing threshold voltage compensation for the pull-down transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 is a schematic diagram of a portion of a memory including a sense amplifier and a pair of complementary digit lines according to an embodiment of the present disclosure.

[0012] Figure 3 is a schematic diagram of a sense amplifier according to an embodiment of the present disclosure.

[0013] Figure 4 is a schematic diagram of a voltage circuit according to an embodiment of the present disclosure.

[0014] Figure 5 is a timing diagram of various signals during sense amplifier operation according to an embodiment of the present disclosure.

[0015] Figure 6 is a schematic diagram of a sense amplifier according to an embodiment of the present disclosure.

[0016] Figure 7 is a diagram showing the layout of a portion of a peripheral area and a memory sub-array area of ​​a memory according to an embodiment of the present disclosure.

[0017] Figure 8 is a schematic diagram of a sense amplifier according to an embodiment of the present disclosure.

[0018] Fig. 9 is a timing diagram of various signals during sense amplifier operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Certain details are set forth below to provide a full understanding of the examples of the present disclosure. However, it will be appreciated by those skilled in the art that the examples of the present disclosure may be practiced without these specific details. In addition, the specific examples of the present disclosure described herein should not be construed as limiting the scope of the present disclosure to these specific examples. In other cases, well-known circuits, control signals, timing protocols, and software operations have not yet been shown in detail to avoid unnecessary confusion of the present disclosure. In addition, terms such as "couples and coupled" mean that two components may be electrically coupled directly or indirectly. Indirect coupling may imply that two components are coupled through one or more intermediate components.

[0020] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that illustrate specific aspects and embodiments of the present disclosure with the aid of drawings. The detailed description contains sufficient details to enable those skilled in the art to practice the embodiments of the present disclosure. Other embodiments may be utilized without departing from the scope of the present disclosure, and structural, logical, and electrical changes may be made. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0021] Figure 1 1 is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a clock input circuit 105, an internal clock generator 107, a timing generator 109, an address command input circuit 115, an address decoder 120, a command decoder 125, a plurality of row (e.g., first access line) decoders 130, a memory cell array 145 including a sense amplifier 150 and a transfer gate 195, a plurality of column (e.g., second access line) decoders 140, a plurality of read / write amplifiers 165, an input / output (I / O) circuit 170, and a voltage generator 190.

[0022] The semiconductor device 100 may include a plurality of external terminals, including a command / address terminal CA, clock terminals CK_t and CK_c, data terminals DQ, DQS and DM, and power supply terminals VDD, VSS, VDDQ and VSSQ. In some examples, the terminals and signal lines associated with the command / address terminal CA may include a first terminal and a signal line set configured to receive a command signal, and a separate second terminal and a signal line set configured to receive an address signal. In other examples, the terminals and signal lines associated with the command / address terminal CA may include a shared terminal and a signal line configured to receive both a command signal and an address signal. The semiconductor device may be mounted on a substrate such as a memory module substrate, a mainboard, or the like.

[0023] The memory cell array 145 includes a plurality of banks BANK0-N, where N is a positive integer, such as 3, 7, 15, 31, etc. Each bank BANK0-N may include a plurality of word lines WL, a plurality of digit lines DL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of digit lines DL and DLb. The selection of the word lines WL of each bank BANK0-N is performed by a corresponding row decoder 130 and the selection of the digit lines DL and DLb is performed by a corresponding column decoder 140. The digit lines DL and DLb are coupled to corresponding sense amplifiers in a plurality of sense amplifiers SAMP 150. The plurality of sense amplifiers 150 are coupled to at least one corresponding local I / O line pair LIOT / B, which is further coupled to a corresponding main I / O line pair MIOT / B in at least two main I / O line pairs MIOT / B via a transfer gate TG 195 acting as a switch. Sense amplifier 150 and transfer gate TG 195 may operate based on control signals from decoder circuitry, which may include command decoder 120, row decoder 130, column decoder 140, any control circuitry of memory cell array 145 of bank BANK0-N, or any combination thereof.

[0024] In some examples, the plurality of sense amplifiers 150 may include threshold voltage compensation circuitry that compensates for threshold voltage differences between components of the sense amplifiers 150. As circuit components become smaller, clock speeds become faster, and voltage / power consumption requirements decrease, small performance differences between circuit components of the sense amplifiers 150 (e.g., due to process, voltage, and temperature (PVT) variations) may reduce the operational reliability of the semiconductor device 100. To mitigate the effects of these differences, compensation for some of these threshold voltage vth differences may include biasing digit lines DL and DLb coupled to the sense amplifiers 150 using internal nodes of the sense amplifiers 150, which are configured to provide sensed data to an output, before activating the sense amplifiers 150 to sense data. The biasing of the digit lines DL and DLb may be based on a threshold difference between at least two circuit components (e.g., transistors) of the sense amplifiers 150. Compensating for threshold voltage vth differences between circuit components within the sense amplifiers 150 may improve reliability.

[0025] The command / address input circuit 115 may receive an address signal and a bank address signal from the outside at a command / address terminal and transmit the address signal and the bank address signal to the address decoder 120. The address decoder 120 may decode the address signal received from the command / address input circuit 115 and provide a row address signal XADD to the row decoder 130 and a column address signal YADD to the column decoder 140. The address decoder 120 may also receive a bank address signal and provide a bank address signal BADD to the row decoder 130 and the column decoder 140.

[0026] The command / address input circuit 115 may receive a command signal from the outside (e.g., the memory controller 105 at the command / address terminal) and provide the command signal to the command decoder 125. The command decoder 125 may decode the command signal and generate various internal commands and control signals. The internal command and control signals may be used to control the operation and timing of various circuits of the semiconductor device 100. For example, the internal command signal may include row and column command signals (e.g., read commands or write commands) to control the circuit to perform access operations on selected word lines and digital lines. Example control signals may include internal control signals for controlling the timing of voltage circuits to provide different voltages during the operation of various circuits (e.g., during voltage threshold compensation of the sense amplifier 150).

[0027] When an activation command is issued and the activation command is supplied to the row address in time, and a read command is supplied to the column address in time, read data is read from the memory cell specified by the row address and the column address in the memory cell array 145. The read / write amplifier 165 can receive the read data DQ and provide the read data DQ to the IO circuit 170. The IO circuit 170 can provide the read data DQ to the outside through the data terminals DQ, DQS and DM together with the data strobe signal at DQS and the data mask signal at DM. Similarly, when an activation command is issued and the activation command is supplied to the row address in time, and a write command is supplied to the column address in time, the write data supplied to the data terminals DQ, DQS, DM is written to the memory cell array 145 together with the data strobe signal at DQS and the data mask signal at DM via the read / write amplifier 165. Therefore, the write data can be written into the memory cell specified by the row address and the column address.

[0028] Turning to the explanation of the external terminals included in the semiconductor device 100, the clock terminals CK_t and CK_c can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to the clock input circuit 105. The clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. The clock input circuit 105 can provide the internal clock signal ICLK to the internal clock generator 107. The internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and the clock start signal CKE from the address / command input circuit 115. Although not limited to this, a DLL circuit can be used as the internal clock generator 107. The internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to the IO circuit 170 and the timing generator 109. The IO circuit 170 can use the phase-controlled internal clock signal LCLK as a timing signal for determining the output timing of the read data. The timing generator 109 can receive the internal clock signal ICLK and generate various internal clock signals.

[0029] The power supply terminal can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to the voltage generator circuit 190. The voltage generator circuit 190 can generate various internal voltages VPP, VBLP, VCMP, VARY, VPERI, etc. based on the power supply voltages VDD and VSS. The internal voltage VPP is mainly used in the row decoder 130, the internal voltages VBLP, VCMP and VARY are mainly used in the sense amplifier 150 included in the memory cell array 145, and the internal voltage VPERI is used in many other circuit blocks. The IO circuit 170 can receive power supply voltages VDD and VSSQ. For example, the power supply voltages VDDQ and VSSQ can be voltages that are respectively the same as the power supply voltages VDD and VSS. However, dedicated power supply voltages VDDQ and VSSQ can be used for the IO circuit 170.

[0030] Figure 2 2 is a schematic diagram of a portion of a memory 200 including a sense amplifier 210 and a pair of complementary digit lines DL220 and DLb221 according to an embodiment of the present disclosure. Figure 2As shown in FIG, sense amplifier 210 is coupled to the pair of true and complementary digital (or bit) lines DL 220 and DLb 221 at sense nodes 230 and 231, respectively. Memory cells 240(0)-(N) can be selectively coupled to digital line DL 220 through corresponding access devices (e.g., transistors) 250(0)-(N), and memory cells 241(0)-(N) can be selectively coupled to digital line DLb 221 through corresponding access devices (e.g., transistors) 251(0)-(N). Word lines WL 260(0)-(N) can control which of the memory cells 240(0)-(N) is coupled to digital line DL 220 by controlling corresponding access devices 250(0)-(N). Similarly, word lines WL 261(0)-(N) can control which of memory cells 241(0)-(N) is coupled to digit line DLb 221 by controlling corresponding access devices 251(0)-(N). Sense amplifier 210 can be controlled via control signals 270 received through decoder circuitry, such as a command decoder (e.g., Figure 1 command decoder 125), a row decoder (e.g., Figure 1 130), a column decoder (e.g., Figure 1 Column decoder 140) memory array control circuitry (e.g., Figure 1 Any one of the control circuit system of the memory cell array 145 of the memory bank BANK0-N) or any combination thereof.

[0031] In some examples, the memory 200 can operate in a common phase or mode. A first phase (e.g., a precharge phase) can be initiated in response to a precharge command. During the precharge phase, word lines WL 260 (0)-(N) and 261 (0)-(N) can be set to an inactive state, and in response, all access devices 250 (0)-(N) and 251 (0)-(N) can be disabled. In addition, digital lines DL 220 and DLb 221 and internal nodes of sense amplifier 210 configured to provide sensed data states to outputs can be precharged to a precharge voltage before transitioning to a subsequent phase.

[0032] In some examples, the sense amplifier 210 includes threshold voltage compensation circuitry that compensates for threshold voltage mismatches between components of the sense amplifier 210 during a threshold voltage compensation phase. To perform threshold voltage compensation, the sense amplifier 210 may precharge or bias the digit lines DL 220 and DLb 221 during the threshold voltage compensation phase so that a voltage difference between the digit lines DL 220 and DLb 221 is substantially equal to a threshold voltage difference between at least two circuit components of the sense amplifier 210. In some examples, the threshold voltage difference may be based on a threshold voltage of a transistor of the sense amplifier 210. Compensation for threshold voltage vth differences between circuit components within the sense amplifier 210 may improve reliability.

[0033] The third phase is a digital line sampling phase. During the sampling phase, the word lines WL of the word lines WL 260 (0)-(N) and 261 (0)-(N) may be set to an active state, and in response, the access devices of the access devices 250 (0)-(N) and 251 (0)-(N) may be enabled to couple the corresponding memory cells of the memory cells 240 (0)-(N) and 241 (0)-(N) to one of the digital lines DL 220 and DLb 221. The fourth phase may be a sense amplifier activation phase. The sense amplifier 210 may be activated to perform a sensing operation of sensing the data state of the activated memory cell. That is, during the sensing operation, the sense amplifier 210 senses and amplifies the data state stored by the activated memory cell to drive one of the digital lines DL 220 or DLb 221 to a high or low voltage level corresponding to the sensed data state and drive the other of the digital lines DL 220 and DLb 221 to a complementary voltage level during the sensing operation. After the sensing operation, the circuitry of memory 200 may remain in the active phase or may transition back to the precharge phase in response to a precharge command.

[0034] Similarly, when being accessed, the memory cells of the memory cells 241(0)-(N) are coupled to the digit line DLb 221 through the corresponding access devices 251(0)-(N) in response to the corresponding word lines 261(0)-(N) becoming active. The sense amplifier 210 senses and amplifies the data state stored by the memory cell to drive the digit line DLb 221 to a high or low voltage level corresponding to the sensed data state. During the sensing operation, the other digit line DL 220 is driven to a complementary voltage level (e.g., a high voltage level complementary to the low voltage level and a low voltage level complementary to the high voltage level).

[0035] During the threshold voltage compensation operation, the sense nodes 230 and 231 of the sense amplifier 210 may be isolated from each other in response to the control signal 270 (e.g., from the decoder circuit). In some examples, during the threshold voltage compensation stage, the control signal 270 may configure the sense amplifier 210 to isolate the sense nodes 230 and 231. For example, during the precharge stage, the sense nodes 230 and 231 of the sense amplifier 210 may be coupled to each other and coupled to the precharge voltage to be precharged to the precharge voltage. After the sense nodes 230 and 231 of the sense amplifier 210 are precharged, the control signal 270 may configure the sense amplifier 210 to isolate the sense nodes 230 and 231 from each other. A voltage difference may then be generated at the sense nodes 230 and 231 to provide threshold voltage compensation.

[0036] Figure 3 is a schematic diagram of a sense amplifier 300 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the sense amplifier 300 may be included in Figure 1 The sense amplifier 150 and / or Figure 2 In one or more of the sense amplifiers 210.

[0037] Sense amplifier 300 includes pull-up transistors 310 and 312 having drains coupled to nodes 346 and 348, respectively. Nodes 346 and 348 may be referred to as sense nodes. Sources of pull-up transistors 310 and 312 are coupled to a power supply that provides a power supply voltage ACT at a power supply node 355. Gates of pull-up transistors 310 and 312 are coupled to wiring nodes 336 and 332, respectively. Sense amplifier further includes pull-down transistors 320 and 322. Pull-down transistor 320 has a source coupled to a power supply that provides a power supply voltage RNL at a power supply node 350 and a drain coupled to sense node 346. Pull-down transistor 322 has a source coupled to power supply node 350 and a drain coupled to sense node 348. Gates of pull-down transistors 320 and 322 are coupled to wiring nodes 336 and 332, respectively.

[0038] In addition, sense amplifier 300 includes isolation (ISO) transistors 314 and 316. The source of ISO transistor 314 is coupled to wiring node 332 and its drain is coupled to sense node 346. The source of ISO transistor 316 is coupled to sense node 348 and its drain is coupled to wiring node 336. Sense amplifier 300 additionally includes equalization transistor 324 and precharge transistor 326, which are activated at their gates by active control signal EQ (e.g., active high logic level). Equalization transistor 324 is coupled across the gates of pull-down transistors 320 and 322. Precharge transistor 326 is coupled to power supply node 350 and the gates of pull-down transistors 322 and 320 (e.g., active high logic level). Figure 3 320 is shown as being coupled to the gate of pull-down transistor 322).

[0039] In some embodiments of the present disclosure, digit line DL is coupled to sensing node 346 and digit line DLb is coupled to sensing node 348. The digit line DL may represent Figure 2 The digit line DL 220 and the digit line DLb may represent the digit line DLb 221 .

[0040] exist Figure 3 In the embodiment of the present invention, pull-up transistors 310 and 312 are shown as p-type field effect transistors (PFETs), and pull-down transistors 320 and 322, isolation transistors 314 and 316, equalization transistor 324, and precharge transistor 326 are shown as n-type field effect transistors (NFETs). However, one or more of the transistors may be changed to a different type, a different transistor, or a different circuit without departing from the scope of the present disclosure.

[0041] As will be described below, sense amplifier 300 can provide threshold voltage compensation. For example, sense amplifier 300 can provide threshold voltage compensation for the threshold voltages of pull-down transistors 320 and 322. Sense amplifier 300 can have advantages over conventional sense amplifiers in providing threshold voltage compensation. For example, sense amplifier 300 can include fewer circuit components (e.g., transistors) than other sense amplifier designs of this type. Therefore, sense amplifier 300, as well as other sense amplifiers according to embodiments of the present disclosure, can provide a more compact circuit design and have lower circuit complexity.

[0042] refer to Figure 5 An example operation of the sense amplifier 300 according to an embodiment of the present disclosure is described. Figure 5 is a timing diagram of various signals during operation of a sense amplifier according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 3 The sense amplifier 300 may be based on Figure 5 Refer to Figure 3 The sense amplifier is described Figure 5 In example operation, however, the sense amplifier 300 or Figure 5 Instance operations are not subject to this restriction.

[0043] In an example operation, it is assumed that pull-down transistor 322 has a threshold voltage (vth+Δvth) that is different from the threshold voltage (vth) of pull-down transistor 320. Therefore, the threshold voltage of pull-down transistor 322 deviates from the threshold voltage of pull-down transistor 320 by Δvth. Figure 5 Example operation of sense amplifier 300 designed to compensate for the threshold voltage difference of pull-down transistors 322 and 320 is shown.

[0044] refer to Figure 5 After time T0, the power supply node 355 and the power supply node 350 are provided with a precharge voltage (e.g., 0.35V) by the power supplies ACT and RNL, respectively. The control signal EQ is also active (e.g., an active high logic level, such as 1.4V) to activate the equalization transistor 324 and activate the precharge transistor 326. Therefore, the connection node 332 at the gates of the pull-up transistor 312 and the pull-down transistor 322 and the connection node 336 at the gates of the pull-up transistor 310 and the pull-down transistor 320 are coupled together through the active equalization transistor 324, and are provided with a precharge voltage from the power supply node 350 through the active precharge transistor 326.

[0045] Also at time T0, control signal ISO signal is active (e.g., active high logic level, e.g., 1.2V) to activate isolation transistors 316 and 314 and couple wiring node 336 to sensing node 348 (and digit line DLb) and couple wiring node 332 to sensing node 346 (and digit line DL). Thus, sensing nodes 346 and 348 (and digit lines DL and DLb) are also provided with a precharge voltage from power supply node 350.

[0046] Prior to time T1 , control signal ISO becomes inactive (eg, an inactive low logic level, such as 0V), deactivating isolation transistors 316 and 314 and thereby isolating wiring nodes 332 and 336 from sensing nodes 346 and 348 , respectively.

[0047] The operation between time T0 and T1 may be referred to as a precharge phase.During the precharge phase of sense nodes 346 and 348, digit lines DL and DLb are equalized, set to a precharge voltage, and isolated at the precharge voltage.

[0048] After time T1, the power supply voltage RNL provided to the power supply node 350 changes to a compensation voltage (e.g., 0.65V), and the power supply voltage ACT provided to the power supply node 355 continues to be the precharge voltage. The equalization transistor 324 and the precharge transistor 326 remain activated to provide the compensation voltage to the connection node 332 at the gates of the pull-up transistor 312 and the pull-down transistor 322 and to provide the compensation voltage to the connection node 336 at the gates of the pull-up transistor 310 and the pull-down transistor 320. The source nodes of the pull-down transistors 322 and 320 are also provided with the compensation voltage from the power supply node 350.

[0049] By setting the gate and source nodes of the pull-down transistors 322 and 320 at the compensation voltage, the pull-down transistors 322 and 320 are effectively diode-coupled. Thus, a voltage of (PRE-vth_A) is set at the sense node 348 (the drain of the pull-down transistor 322), and a voltage of (PRE-vth_B) is set at the sense node 346 (the drain of the pull-down transistor 320), where PRE is a precharge voltage (e.g., 0.65V), vth_A is the threshold voltage of the pull-down transistor 322, and vth_B is the threshold voltage of the pull-down transistor 320.

[0050] In the present example, as previously described, it is assumed that the threshold voltage of the pull-down transistor 322 is Δvth greater than the threshold voltage of the pull-down transistor 320. That is, where the threshold voltage of the pull-down transistor 320 is vth, the threshold voltage of the pull-down transistor 322 is vth+Δvth. The resulting voltage at the sense node 346 (and the digital line DL) is (PRE-vth) and the resulting voltage at the sense node 348 (and the digital line DLb) is (PRE-vth-Δvth). The voltage difference between the sense nodes 346 and 348 compensates for the threshold voltage difference between the pull-down transistors 322 and 320.

[0051] Prior to time T2 , control signal EQ becomes inactive (eg, an inactive low logic level, such as 0 V), deactivating equalization transistor 324 and precharge transistor 326 , and thereby isolating wiring nodes 332 and 336 .

[0052] The operation between time T1 and T2 may be referred to as a threshold voltage compensation (vtc) phase. During the threshold voltage compensation phase, the sense node (and digit line) is set at a corresponding compensation voltage to compensate for the threshold voltage difference between pull-down transistors 322 and 320.

[0053] After time T2, access line WL may be activated (e.g., changed to an activated (high) voltage level) to couple the memory cell to the digit line. The memory cell may change the voltage of the digit line to which it is coupled. In the present example, it is assumed that activation of access line WL couples the memory cell to digit line DL (and to sense node 346). It is further assumed that the memory cell stores a high cell state, which causes the voltage of digit line DL to increase (e.g., by a voltage Δsign) when coupled to digit line DL.

[0054] Prior to time T3, control signal ISO becomes active, activating isolation transistors 316 and 314. Activated isolation transistor 316 couples sense node 348 (and digit line DLb) to wiring node 336 at the gates of pull-up transistor 310 and pull-down transistor 320. Activated isolation transistor 314 couples sense node 346 (and digit line DL) to wiring node 332 at the gates of pull-up transistor 312 and pull-down transistor 322. Thus, the voltage of digit line DLb (PRE-vth-Δvth) is provided to wiring node 336 and the voltage of digit line DL (PRE-vth+Δsign) is provided to wiring node 332.

[0055] The operation between times T2 and T3 may be referred to as a digit line sampling phase.During the digit line sampling phase, the memory cell is coupled to one of the digit lines, and the digit line is coupled to the gates of the corresponding pull-up and pull-down transistors.

[0056] After time T3, the power supply voltage RNL provided to the power supply node 350 changes to a low activation voltage (e.g., 0V), and the power supply voltage ACT provided to the power supply node 355 changes to a high activation voltage (e.g., 1.0V) to "activate" the sense amplifier. The corresponding voltages at the power supply nodes 355 and 350 cause the voltage difference between the digit lines DL and DLb to be amplified by driving the sense node and the digit line to opposite voltage levels (e.g., a high voltage and a low activation voltage) based on the voltage difference between the digit lines DL and DLb. The wiring nodes 332 and 336 may also be driven to opposite voltage levels.

[0057] In this example, as the memory cell increases the voltage of the digit line DL, the pull-down transistor 322 is activated to a greater extent than the pull-down transistor 320. Therefore, the digit line DLb (and the wiring node 336) begins to pull down to the low activation voltage provided to the power supply node 350, which in turn begins to activate the pull-up transistor 310 to pull up the wiring node 332 and further activate the pull-down transistor 322. Through the positive feedback loop of the pull-down transistor 322 and the pull-up transistor 310, the digit line DLb (and the sense node 348 and the wiring node 336) is driven to the low activation voltage and the digit line DL (and the sense node 346 and the wiring node 332) is driven to the high activation voltage. Prior to time T4, the access line WL becomes inactive (e.g., changes to an inactive (low) voltage level) to isolate the memory cell from the digit line DL.

[0058] The operation between time T3 and T4 may be referred to as a sense amplifier activation phase. During the sense amplifier activation phase, the sense amplifier is activated by providing a high activation voltage and a low activation voltage to the sense amplifier, and the voltage difference between the digit lines DL and DLb is amplified by driving the digit lines DL and DLb to opposite activation voltages based on the voltage difference between the digit lines DL and DLb (e.g., caused by coupling of a memory cell to one of the digit lines).

[0059] After time T4, as previously described, the sense amplifier can be prepared for another sensing operation by precharging the digit lines DL and DLb. For example, the control signal EQ becomes active and activates the equalization transistor 324 and the precharge transistor 326. In addition, after time T4, the power supply voltages ACT and RNL provided to the power supply node 355 and the power supply node 350, respectively, are changed to the precharge voltage. Therefore, the digit lines DL and DLb are equalized by the active equalization transistor 324 and set to the precharge voltage by the active precharge transistor 326. The sense amplifier 300 is placed in the same precharge state as previously described at time T0 and is ready for another access operation.

[0060] exist Figure 5 In the example of FIG. 1 , the power supply voltages ACT and RNL and the control signals EQ and ISO are shown as having specific timing relative to other voltages and control signals. However, embodiments of the present disclosure include different timings than those in the reference Figure 5 Other voltages and signal timings than those described. Therefore, the scope of the present disclosure is not limited to Figure 5 specific instance of .

[0061] The voltage circuit can be provided as a reference Figure 5 The power supply voltages provided to the power supply nodes ACT and RNL as described may be provided, for example, by a command decoder (e.g., in some embodiments of the present disclosure, Figure 1 The internal signal control voltage circuit of the command decoder 125).

[0062] Figure 4 4 is a schematic diagram of a voltage circuit 400 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the voltage circuit 400 can be used to provide power supply voltages ACT and RNL to power supply nodes 355 and 350. For example, as shown in FIG. Figure 5 As described in the example operation of , the voltage circuit 400 can provide the supply voltages ACT and RNL to the supply nodes 355 and 350 .

[0063] The voltage circuit 400 includes a transistor 412 that provides a power supply voltage Vary to a power output node 436 when activated, and a transistor 422 that provides a power supply voltage Vblp to the power output node 436 when activated. The power output node 436 can be coupled to the power supply node 355, for example, to provide the power supply voltage Vary and / or Vblp as the power supply voltage ACT. The voltage circuit 400 further includes a transistor 418 that provides a power supply voltage GND (e.g., ground) to the power output node 434 when activated, and a transistor 424 that provides a power supply voltage Vcmp to the power output node 434 when activated. The power output node 434 can be coupled to the power supply node 350, for example, to provide the power supply voltage GND and / or Vcmp as the power supply voltage RNL. The transistor 415 couples the power output nodes 434 and 436 together when activated. The transistors of the voltage circuit 400 can be controlled by an internal control signal to provide different power supply voltages.

[0064] In some embodiments of the present disclosure, the power supply voltage Vary may be 1.0V, the power supply voltage Vblp may be 0.35V, the power supply voltage Vcmp may be 0.65V, and / or the power supply GND may be 0.0V.

[0065] In operation, transistor 415 of voltage circuit 400 may be activated to couple power output nodes 434 and 436 together to provide the same power supply voltage, and transistor 422 may be activated so that the power supply voltage Vblp is provided to both power output nodes 434 and 436. For example, during a precharge phase of the sense amplifier, voltage circuit 400 may be configured to provide the Vblp voltage as the power supply voltages ACT and RNL to power supply nodes 355 and 350 coupled to power output nodes 436 and 434.

[0066] In addition, transistor 415 can be deactivated and transistor 424 can be activated so that power output node 434 provides power supply voltage Vcmp and power supply node 436 continues to provide power supply voltage Vblp. For example, during the threshold voltage compensation phase and / or during the sampling phase of the sense amplifier, voltage circuit 400 can be configured to provide the Vblp voltage as power supply voltage ACT to power supply node 355 coupled to power output node 436 and provide the Vcmp voltage as power supply voltage RNL to power supply node 350 coupled to power output node 434.

[0067] In addition, transistors 422 and 424 may be deactivated and transistors 412 and 418 may be activated so that power output node 436 provides power supply voltage Vary and power supply node 434 provides power supply voltage GND. For example, during a sense amplifier activation phase of the sense amplifier (which may include a pull-down and / or pull-up sense amplifier activation phase in some embodiments of the present disclosure), voltage circuit 400 may be configured to provide the Vary voltage as power supply voltage ACT to power supply node 355 coupled to power output node 436 for use as a high activation voltage, and to provide the GND voltage as power supply voltage RNL to power supply node 350 coupled to power output node 434 for use as a low activation voltage.

[0068] Figure 6 is a schematic diagram of a sense amplifier 600 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the sense amplifier 600 may be included in Figure 1 The sense amplifier 150 and / or Figure 2 In one or more of the sense amplifiers 210.

[0069] Sense amplifier 600 includes pull-up transistors 610 and 612 having drains coupled to nodes 646 and 648, respectively. Nodes 646 and 648 may be referred to as sense nodes. The sources of pull-up transistors 610 and 612 are coupled to a power supply that provides a power supply voltage ACT at a power supply node 655. The gates of pull-up transistors 610 and 612 are coupled to sense nodes 648 and 646, respectively. The sense amplifier further includes pull-down transistors 620 and 622. The source of pull-down transistor 620 is coupled to a power supply that provides a power supply voltage RNL at a power supply node 650 and the drain is coupled to sense node 646. The source of pull-down transistor 622 is coupled to power supply node 650 and the drain is coupled to sense node 648. In addition, the gate of pull-down transistor 620 is coupled to sense node 648 through isolation transistor 616, and the gate of pull-down transistor 622 is coupled to sense node 646 through isolation transistor 614.

[0070] Sense amplifier 600 further includes an equalization transistor 624 and a precharge transistor 626, which are activated at their gates by an active control signal EQ (e.g., a high active logic level). Equalization transistor 624 is coupled across the gates of pull-down transistors 620 and 622. Precharge transistor 626 is coupled to power supply node 650 and gates of pull-down transistors 622 and 620 (e.g., at Figure 6 622 as coupled to the gate of pull-down transistor 622).

[0071] In some embodiments of the present disclosure, digit line DL is coupled to sensing node 646 and digit line DLb is coupled to sensing node 648. The digit line DL may represent Figure 2 digit line DL 220 and digit line DLb may represent digit line DLb 221.

[0072] exist Figure 6 In the embodiment of the present invention, the pull-up transistors 610 and 612 are shown as p-type field effect transistors (PFETs), and the pull-down transistors 620 and 622, the isolation transistors 614 and 616, the equalization transistor 624, and the precharge transistor 626 are shown as n-type field effect transistors (NFETs). However, one or more of the transistors may be changed to a different type, a different transistor, or a different circuit without departing from the scope of the present disclosure.

[0073] and Figure 3 In contrast to sense amplifier 300, sense amplifier 600 includes pull-up transistors 610 and 612 having gates that are not coupled to wiring nodes 636 and 632, but instead are coupled to sense nodes 648 and 646. The alternative configuration of sense amplifier 600 may provide a different topology of the sense amplifier and may be more suitable for some designs.

[0074] In some embodiments of the present disclosure, the sense amplifier 600 may be similar to the reference Figure 5 In addition, in some embodiments of the present disclosure, the power supply voltages ACT and RNL may be Figure 4 The voltage circuit 400 provides.

[0075] Figure 7 7 is a diagram showing a layout of a portion of a peripheral area 710 and a memory sub-array area 720 of a memory according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the memory sub-array area 720 may be included in a memory cell array (e.g., included in Figure 1 ) and the peripheral region 710 may be disposed adjacent to the memory sub-array region and / or disposed between the memory sub-array regions.

[0076] The peripheral region 710 includes a sub-word line driver (SWD) region 730. The SWD region 730 may include a sub-word line driver circuit that selectively drives the sub-word lines of the memory sub-array region 720 to activate the selected memory cells for access. The peripheral region 710 may further include a sense amplifier (SA) region 740 in which a sense amplifier (e.g., sense amplifier 300 in some embodiments of the present disclosure) may be included.

[0077] The micro gap region 735 included in the peripheral region 710 may have a size based on the SWD height of the SWD region 730 and the SA height of the SA region 740. The micro gap region 735 may include a circuit used when operating a sub-word driver of the SWD region 730 and / or operating a sense amplifier of the SA region 740. For example, the micro gap region 735 may include a voltage circuit that provides various voltages for operating the sense amplifier of the SA region 740. In some embodiments of the present disclosure, Figure 4 One or more voltage circuits 400 are included in the micro-gap region 735.

[0078] In instances where the size of the micro-gap region 735 is relatively compact, some circuits including, for example, voltage circuits may become challenging. The voltage circuits may have relatively large sizes due to the need for sufficient drivability of the respective voltages.

[0079] Figure 8 is a schematic diagram of a sense amplifier 800 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the sense amplifier 800 may be included in Figure 1 The sense amplifier 150 and / or Figure 2 In one or more of the sense amplifiers 210.

[0080] Sense amplifier 800 includes pull-up transistors 810 and 812 having drains coupled to nodes 836 and 832, respectively, through isolation transistors 814 and 816. Isolation transistors 814 and 816 are activated by an active (e.g., active logic low) control signal ISO2. Sense amplifier 800 further includes pull-down transistors 820 and 822 having drains coupled to nodes 836 and 832, respectively. For convenience, nodes 836 and 832 may be referred to as "wiring nodes" in a non-limiting manner. Gates of pull-up transistors 810 and 812 are coupled to wiring nodes 832 and 836, respectively. Sources of pull-up transistors 810 and 812 are coupled to a power supply node 855 provided with a power supply voltage (e.g., Vary), and sources of pull-down transistors 820 and 822 are coupled to a power supply node 850 provided with a power supply voltage RNL.

[0081] Wiring node 836 is coupled to sensing node 846 through isolation transistor 825, and wiring node 832 is coupled to sensing node 848 through isolation transistor 827. Isolation transistors 825 and 827 are activated by an active (e.g., active high logic level) control signal ISO. Digital line DL is coupled to sensing node 846 and digital line DLb is coupled to sensing node 848. In some embodiments of the present disclosure, digital line DL may represent Figure 2 The digit line DL 220 and the digit line DLb may represent the digit line DLb 221 .

[0082] Sense amplifier 800 additionally includes equalizing transistors 824 and 826. Equalizing transistor 824 is coupled to wiring node 836 and sensing node 848, and equalizing transistor 826 is coupled to wiring node 832 and sensing node 846. Equalizing transistors 824 and 826 are activated by an active control signal BLECP (eg, an active high logic level).

[0083] exist Figure 8 , pull transistors 810 and 812 and isolation transistors 814 and 816 are shown as p-type field effect transistors (PFETs), and pull-down transistors 820 and 822, isolation transistors 825 and 827, and equalization transistors 824 and 826 are shown as n-type field effect transistors (NFETs). However, one or more of the transistors may be changed to a different type, a different transistor, a different circuit without departing from the scope of the present disclosure.

[0084] As will be described below, the sense amplifier 800 can provide threshold voltage compensation. The sense amplifier 800 can be advantageous in providing threshold voltage compensation compared to conventional sense amplifiers. For example, the sense amplifier 800 can provide a constant power supply voltage (e.g., Vary) instead of a power supply voltage ACT that changes during operation of the sense amplifier and can be provided by a voltage circuit. Therefore, the sense amplifier 800 and other sense amplifiers according to embodiments of the present disclosure can operate without requiring a voltage circuit to provide various high activation voltages (e.g., the power supply voltage ACT), such as a voltage circuit that is typically included in a peripheral region (e.g., a microgap region). Therefore, the size of the voltage circuit can be reduced by eliminating the circuit necessary to provide the high activation voltage and retaining the circuit for providing the low activation voltage (e.g., the power supply voltage RNL).

[0085] refer to Fig. 9 An example operation of the sense amplifier 800 according to an embodiment of the present disclosure is described. Fig. 9 is a timing diagram of various signals during operation of a sense amplifier according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 8 The sense amplifier 800 may be based on Fig. 9 Refer to Figure 8 The sense amplifier is described Fig. 9 In example operation, however, the sense amplifier 800 or Fig. 9 Instance operations are not subject to this restriction.

[0086] After time T0, a precharge voltage is provided for power supply node 850, and a power supply voltage Vary is provided for power supply node 855. In some embodiments of the present disclosure, the power supply voltage Vary is a constant voltage. The control signal ISO is active (e.g., active high logic level) to activate isolation transistors 825 and 827, and the control signal ISO2 is inactive (e.g., inactive high logic level) to deactivate isolation transistors 814 and 816. The control signal BLECP is also active (e.g., active high logic level) to activate equalization transistors 824 and 826.

[0087] Therefore, the sensing nodes 846 and 848 (and the digit lines DL and DLb) are coupled together through the activated isolation transistors 825 and 827 and the activated equalization transistors 824 and 826 to equalize the voltages at the sensing nodes 846 and 848 and on the digit lines DL and DLb. The equalized voltage is also provided to the wiring nodes 832 and 836 through the activated isolation transistors 826 and 824. In some embodiments of the present disclosure, the equalized voltage may be about one-half the voltage of the power supply voltage Vary (e.g., about 0.53 V).

[0088] In some embodiments of the present disclosure, the pre-charge voltage provided to the power supply node 850 may be 0.5V, the power supply voltage Vary may be 1.0V, the active control signal ISO voltage may be 1.6V, the inactive control signal ISO2 may be 1.0V, and / or the active control signal BLECP may be 1.2V.

[0089] The operation between times T0 and T1 may be referred to as a pre-charge phase.During the pre-charge phase, sense nodes 846 and 848 (and digit lines DL and DLb) are equalized and set to an equalized voltage.

[0090] After time T1, the power supply voltage RNL provided to the power supply node 850 switches to a low level active voltage (e.g., ground, 0V). Also after time T1, the control signal ISO becomes inactive (e.g., an inactive low logic level) to deactivate the isolation transistors 825 and 827. Thus, the sense nodes 846 and 848 (and the digit lines DL and DLb) are isolated from each other. The sense node 846 and the digit line DL remain at an equilibrated voltage shared with the wiring node 832, and the sense node 848 and the digit line DLb remain at an equilibrated voltage shared with the wiring node 836.

[0091] With equalizing transistors 824 and 826 still activated, pull-down transistors 822 and 820 are effectively diode-coupled (e.g., gate coupled to drain). Thus, the drains of pull-down transistors 822 and 820 are set to voltages based on respective threshold voltages vth_A and vth_B. Additionally, the voltage vth_A at the drain of pull-down transistor 822 is provided to sense node 846 and digit line DL via active equalizing transistor 826, and the voltage vth_B at the drain of pull-down transistor 820 is provided to sense node 848 and digit line DLb via active equalizing transistor 824.

[0092] In this example, it is assumed that the threshold voltage vth_A of the pull-down transistor 822 is greater than the threshold voltage vth_B of the pull-down transistor 820 by Δvth. That is, in the case where the threshold voltage of the pull-down transistor 820 is vth, the threshold voltage of the pull-down transistor 822 is (vth+Δvth). The resulting voltage at the sensing node 846 and the digital line DL is (vth+Δvth) and the resulting voltage at the sensing node 848 and the digital line DLb is (vth). The voltage difference Δvth between the sensing nodes 846 and 848 (and the digital lines DL and DLb) compensates for the difference between the threshold voltages of the pull-down transistors 822 and 820.

[0093] Prior to time T2, control signal BLECP becomes inactive (e.g., inactive low logic level, 0V) to deactivate balancing transistors 826 and 824. With balancing transistors 826 and 824 deactivated, sense nodes 846 and 848 (and digit lines DL and DLb) are isolated and maintain respective voltages (vth+Δvth) and (vth).

[0094] The operation between time T1 and T2 may be referred to as a threshold voltage compensation (vtc) phase. During the threshold voltage compensation phase, sense nodes 846 and 848 and digit lines DL and DLb are set at corresponding compensation voltages to compensate for the threshold voltage difference between pull-down transistors 822 and 820.

[0095] After time T2, the power supply voltage RNL provided to the power supply node 850 is changed to the precharge voltage. Also after time T2, the WL access line can be activated (e.g., changed to an activated (high) voltage level) to couple the memory cell to the digit line. The memory cell can change the voltage of the digit line to which it is coupled (e.g., the voltage Vsig). In this example, it is assumed that the activation of the access line WL couples the memory cell to the digit line DL. It is further assumed that the memory cell stores a high cell state Vsig, which causes the voltage of the digit line DL and the sense node 846 to increase when coupled to the digit line DL.

[0096] The operation between times T2 and T3 may be referred to as a memory cell sampling phase. During the memory cell sampling phase, the memory cell is coupled to one of the digit lines and the voltage of the digit line to which the memory cell is coupled may be changed based on the data state stored by the memory cell.

[0097] After time T3, control signal ISO becomes active to activate isolation transistors 827 and 825 and provide the voltages at digital lines DLb and DL to wiring nodes 832 and 836, respectively. Also after time T3, power supply voltage RNL provided to power supply node 850 changes to a low-level activation voltage to activate the pull-down sense amplifiers of pull-down transistors 822 and 820.

[0098] The low level activation voltage at power supply node 850 causes the voltage difference (e.g., Vsig+Δvth) between digit lines DL and DLb to begin to be amplified by driving the lower voltage digit line toward the low level activation voltage. In this example, with digit line DLb having a lower voltage than digit line DL, digit line DLb is driven toward the low level activation voltage by activating isolation transistor 827 and pull-down transistor 822. Due to the higher voltage of digit line DL provided to the gate of pull-down transistor 822, pull-down transistor 822 is more conductive than pull-down transistor 820.

[0099] Also with isolation transistors 827 and 825 activated, connection node 832 is provided with the voltage of digit line DLb and connection node 836 is provided with the voltage of digit line DL. Thus, the gates of pull-up transistors 812 and 810 coupled to connection nodes 836 and 832 are all provided with the voltages of digit lines DL and DLb, respectively.

[0100] The operation between time T3 and T4 may be referred to as a pull-down sense amplifier activation phase. During the pull-down sense amplifier activation phase, the voltage difference between digit lines DL and DLb begins to be amplified by beginning to drive one of the digit lines toward a low level activation voltage.

[0101] After time T4, control signal ISO2 becomes active (e.g., an active low logic level) to activate isolation transistors 816 and 814 to couple wiring nodes 832 and 836 to the drains of pull-up transistors 812 and 810, respectively. Access line WL may also become inactive (e.g., changed to an inactive (low) voltage level) to isolate the memory cell from digit line DL.

[0102] As previously described, the gate of pull-up transistor 812 is provided with the voltage of sense node 846 and digit line DL, and the gate of pull-up transistor 810 is provided with the voltage of sense node 848 and digit line DLb. In the case where the voltage of digit line DLb is lower than the voltage of digit line DL from the pull-down sense amplifier activation phase, pull-up transistor 810 is activated to a greater extent than pull-up transistor 812. Therefore, wiring node 836 is initially driven to power supply voltage Vary by pull-up transistor 810, which causes the voltage of digit line DL to also increase. The increased voltage of wiring node 836 further activates pull-down transistor 822 to continue driving digit line DLb toward the low level activation voltage provided to power supply node 850.

[0103] The positive feedback loop of activated pull-down transistor 822 and activated pull-up transistor 810 drives digit line DLb (and sense node 848 and wiring node 832) fully to the low level activation voltage and drives digit line DL (and sense node 846 and wiring node 836) fully to the supply voltage Vary.

[0104] The operation between time T4 and T5 may be referred to as a pull-up sense amplifier activation phase. During the pull-up sense amplifier activation phase, the voltage difference between the digit lines DL and DLb from the pull-down sense amplifier activation phase is further amplified by fully driving the digit lines DL and DLb to opposite voltage levels (e.g., the power supply voltage Vary and the low-level activation voltage) based on the voltage difference.

[0105] After time T5, for example, as previously described with reference to the precharge phase between time T0 and T1, the digit lines DL and DLb may be precharged. The power supply voltage provided to the power supply node 850 is changed to the precharge voltage, and the isolation transistors 816 and 814 are deactivated by the control signal ISO2 becoming inactive. In addition, the equalization transistors 826 and 824 are activated by the control signal BLECP becoming active. Therefore, as previously described, the sense nodes 846 and 848 and the digit lines DL and DLb are coupled together through the (already) activated isolation transistors 827 and 825 and the equalization transistors 826 and 824 to equalize the voltages on the sense nodes 846 and 848 and the digit lines DL and DLb. The equalized voltage is also provided to the wiring nodes 832 and 836 by the activated isolation transistors 827 and 825.

[0106] It should be understood from the foregoing that although specific embodiments of the present disclosure have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to any of the specific embodiments described herein.

Claims

1. A device comprising: a first pull-up transistor coupled to a first power supply node; a second pull-up transistor coupled to the first power supply node; a first pull-down transistor coupled to a second power supply node; a second pull-down transistor coupled to the second power supply node; a first isolation transistor coupled to a first sense node to which the first pull-up transistor and the first pull-down transistor are also coupled, and the first isolation transistor is further coupled to a gate of the second pull-down transistor; a second isolation transistor coupled to a second sense node to which the second pull-up transistor and the second pull-down transistor are also coupled, and the second isolation transistor is further coupled to a gate of the first pull-down transistor; an equalization transistor coupled to the gates of the first and second pull-down transistors; and A precharge transistor is coupled to the second power supply node and further coupled to the gate of the first or second pull-down transistor. 2 . The apparatus of claim 1 , wherein the first isolation transistor is further coupled to a gate of the second pull-up transistor and the second isolation transistor is further coupled to a gate of the first pull-up transistor. 3 . The apparatus of claim 1 , wherein a gate of the first pull-up transistor is coupled to the second sense node and the gate of the second pull-up transistor is coupled to the first sense node. 4 . The apparatus of claim 1 , wherein the first sense node is configured to be coupled to a first digit line and the second sense node is configured to be coupled to a second digit line. 5 . The apparatus of claim 1 , wherein the first and second pull-up transistors comprise p-type transistors and the first and second pull-down transistors comprise n-type transistors.

6. The apparatus of claim 1 , wherein the first and second pull-up transistors, the first and second pull-down transistors, the first and second isolation transistors, the equalization transistor, and the pre-charge transistor are included in a sense amplifier, and wherein a first power supply node is configured to receive a first power supply voltage and the second power supply node is configured to receive a second power supply voltage, and the first and second power supply voltages change during operation of the sense amplifier.

7. The apparatus of claim 1 , wherein the equalization transistor and the precharge transistor are configured to be activated, the first and second isolation transistors are configured to be deactivated, and the second power supply node is configured to receive a higher power supply voltage than the first power supply node, all during a threshold voltage compensation phase.

8. A device comprising: a first pull-up transistor coupled to a first power supply node; a second pull-up transistor coupled to the first power supply node; a first pull-down transistor coupled to the second power supply node and having a gate coupled to the first sense node; a second pull-down transistor coupled to the second power supply node and having a gate coupled to a second sense node; a first isolation transistor coupled to the first pull-up transistor and further coupled to the first pull-down transistor at a first wiring node; a second isolation transistor coupled to the second pull-up transistor and further coupled to the second pull-down transistor at a second wiring node; a first balancing transistor coupled to the first wiring node and the first sensing node; a second equalization transistor coupled to the second wiring node and the second sensing node; a third isolation transistor coupled to the second sensing node and the first wiring node; and a fourth isolation transistor coupled to the first sensing node and the second wiring node, Wherein the first and second isolation transistors are configured to be activated in response to an active first activation signal and the third and fourth isolation transistors are configured to be activated in response to an active second activation signal.

9. The apparatus of claim 8, wherein a gate of the first pull-up transistor is coupled to the second wiring node and a gate of the second pull-up transistor is coupled to the first wiring node.

10. The apparatus of claim 8, wherein the first and second equalization transistors are activated in response to an activation equalization control signal.

11. The apparatus of claim 8, wherein the first and second pull-up transistors, the first and second pull-down transistors, the first, second, third, and fourth isolation transistors, and the first and second equalization transistors are included in a sense amplifier circuit, and wherein a constant supply voltage is provided to the first power supply node during operation of the transistors.

12. The apparatus of claim 8, wherein the first and second pull-up transistors and the first and second isolation transistors comprise p-type transistors, and wherein the first and second pull-down transistors, the first and second equalization transistors, and the third and fourth isolation transistors comprise n-type transistors.

13. The apparatus of claim 8, wherein the first and second sense nodes are configured to be precharged to a voltage based on sharing opposite supply voltages between the first and second sense nodes.

14. An apparatus comprising: a first pull-up transistor coupled to a first power supply node; a second pull-up transistor coupled to the first power supply node; a first pull-down transistor coupled to the second power supply node and having a gate coupled to the first sense node; a second pull-down transistor coupled to the second power supply node and having a gate coupled to a second sense node; a first isolation transistor coupled to the first pull-up transistor and further coupled to the first pull-down transistor at a first wiring node; a second isolation transistor coupled to the second pull-up transistor and further coupled to the second pull-down transistor at a second wiring node; a first balancing transistor coupled to the first wiring node and the first sensing node; a second equalization transistor coupled to the second wiring node and the second sensing node; a third isolation transistor coupled to the second sensing node and the first wiring node; and a fourth isolation transistor coupled to the first sensing node and the second wiring node, The first and second isolation transistors are deactivated in response to an inactive first activation signal and the third and fourth isolation transistors are deactivated in response to an inactive second activation signal, and the power supply voltage provided to the second power supply node changes during a threshold voltage compensation phase.

15. A method comprising: precharging and equalizing first and second sense nodes of a sense amplifier; isolating the first and second sense nodes of the sense amplifier; and A supply voltage provided to a supply node to which gates and sources of first and second pull-down transistors are coupled is increased to provide corresponding voltages at the first and second sense nodes for use in compensating threshold voltages of the first and second pull-down transistors.

16. The method of claim 15, further comprising isolating the gates of the first and second pull-down transistors. 17 . The method of claim 15 , wherein precharging the first and second sense nodes of the sense amplifier comprises precharging the first and second sense nodes to a precharge voltage provided to the power supply node.

18. A method comprising: sharing voltages of first and second sense nodes to precharge the first and second sense nodes by activating first and second isolation transistors in response to an active first activation signal; isolating the first and second sense nodes by deactivating the first and second isolation transistors in response to an inactive first activation signal; A supply voltage provided to a power supply node is reduced to cause the first and second sense nodes to discharge to respective sense node voltages through respective diode-coupled pull-down transistors, thereby providing threshold voltage compensation for the pull-down transistors.

19. The method of claim 18, further comprising isolating the first and second sense nodes from a drain of the pull-down transistor.

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