Storage Devices

Abstract

A memory cell comprises: a bit line and a plate line, which are spaced apart from each other and oriented vertically in a first direction; a transistor, which comprises an active layer, which is laterally oriented in a second direction crossing the bit line; a capacitor, which is laterally oriented in the second direction between the active layer and the plate line; and a word line, which is laterally oriented in a third direction crossing the bit line and the active layer, wherein the word line is embedded in the active layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0020244, filed on February 19, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a three-dimensional memory device having improved integration. Background Art

[0004] Since the integration of two-dimensional or planar semiconductor devices is mainly determined by the area occupied by the unit memory cell, the integration is greatly affected by the level of fine pattern formation technology. The miniaturization of patterns requires very expensive equipment. Therefore, although the integration of two-dimensional (2D) semiconductor devices is increasing, the degree to which the integration can be improved is limited. Therefore, a three-dimensional memory device is proposed, which has a memory cell arranged in three dimensions. Summary of the invention

[0005] According to one embodiment of the present invention, a memory cell includes: a bit line and a plate line, which are spaced apart from each other and vertically oriented in a first direction; a transistor, which includes an active layer, which is laterally oriented in a second direction to intersect the bit line; a capacitor, which is laterally oriented in the second direction between the active layer and the plate line; and a word line, which is laterally oriented in a third direction to intersect the bit line and the active layer, wherein the word line is embedded in the active layer.

[0006] According to another embodiment of the present invention, a memory device includes: a memory cell array, which includes a plurality of memory cells arranged vertically in a first direction, wherein each of the memory cells includes: a bit line and a plate line, which are spaced apart from each other and oriented vertically in the first direction; a transistor, which includes an active layer, which is laterally oriented in a second direction to intersect with the bit line, wherein the transistor includes a first active barrel, a second active barrel and a pair of plate portions, which are laterally oriented between the first active barrel and the second active barrel; a word line, which is laterally oriented in a third direction while penetrating between the pair of plate portions of the active layer; and a capacitor, which is laterally oriented in the second direction between the active layer and the plate line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 The structure of a memory device according to an embodiment of the present invention is schematically shown.

[0008] Figure 2Ais a perspective view showing a storage device.

[0009] Figure 2B is a plan view showing a single storage unit.

[0010] Figure 2C is along Figure 2B A cross-sectional view taken along line AA' is shown.

[0011] Figure 3A and Figure 3B Shows Figure 2B The active layer is shown.

[0012] Figure 4 It is shown Figure 2B A perspective view of the word line shown.

[0013] Figure 5 It is shown Figure 2B A perspective view of the capacitor and plate lines shown.

[0014] Figure 6 is a perspective view showing a mirror-type memory device that shares a plate line.

[0015] Figure 7 is a perspective view showing a mirror type memory device that shares a bit line.

[0016] Fig. 8A and Figure 8B is a plan view showing a memory cell according to another embodiment of the present invention.

[0017] 9A to 9C A memory cell according to another embodiment of the present invention is shown.

[0018] Fig. 10A and Fig. 10B A memory cell according to another embodiment of the present invention is shown.

[0019] Fig.11A and Fig. 11B A memory cell according to another embodiment of the present invention is shown.

[0020] Fig.12 FIG. 1 is a plan view schematically showing the structure of a memory device according to another embodiment of the present invention.

[0021] Fig.13A It is shown Fig.12 A perspective view of a portion of a single storage unit is shown in FIG.

[0022] Fig. 13B It is shown Fig.13A A perspective view of the active layer shown in FIG.

[0023] Fig. 13C is along Fig. 13BA cross-sectional view taken along line AA' is shown.

[0024] Fig.13D is a perspective view showing the word line in detail.

[0025] Fig.14 is a cross-sectional view schematically showing a structure of a memory device according to another embodiment of the present invention.

[0026] Fig.15A It is shown Fig.14 A perspective view of a portion of a single storage unit is shown in FIG.

[0027] Fig. 15B It is shown Fig.15A A perspective view of the active layer shown in FIG.

[0028] Fig. 15C is along Fig. 15B A cross-sectional view taken along line AA' is shown.

[0029] Fig.15D is a perspective view showing the word line in detail.

[0030] Fig.16A and Fig. 16B is a perspective view showing a memory device according to another embodiment of the present invention.

[0031] Fig.17 is a perspective view showing a capacitor according to another embodiment of the present invention. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, in the various drawings and embodiments of the present invention, the same reference numerals refer to the same parts.

[0033] The drawings are not necessarily drawn to scale, and in some cases, the proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0034] It will be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0035] In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0036] Embodiments of the present invention are directed to a three-dimensional memory device with improved integration.

[0037] A memory device according to an embodiment of the present invention may include a lateral active layer, a single word line WL, a vertical bit line BL, and a lateral capacitor.

[0038] Figure 1 The structure of a memory device according to an embodiment of the present invention is schematically shown. Figure 2A It is shown Figure 1 A perspective view of a memory device is shown. Figure 2B It is shown Figure 2A Floor plan of a single storage unit shown. Figure 2C is along Figure 2B A cross-sectional view taken along line AA' is shown. Figure 3A and Figure 3B Shows Figure 2B The active layer is shown. Figure 4 It is shown Figure 2B A perspective view of the word line shown. Figure 5 It is shown Figure 2B A perspective view of the capacitor and plate lines shown.

[0039] refer to Figure 1 , the memory device 100 may include a base substrate LS, and a memory cell array MCA may be formed above the base substrate LS. The memory cell array MCA may be arranged vertically VA from the base substrate LS in a first direction D1. The memory cell array MCA may include a plurality of memory cells MC, and each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. In each memory cell MC, the bit line BL, the transistor TR, the capacitor CAP, and the plate line PL may be positioned in a lateral arrangement LA in a second direction D2. Each memory cell MC may further include a word line WL, and the word line WL may extend in a third direction D3. The memory cell array MCA may include a DRAM memory cell array.

[0040] The base substrate LS may be a material suitable for semiconductor processing. The base substrate LS may include at least one of a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed above the base substrate LS. The base substrate LS may include a semiconductor substrate. The base substrate LS may be formed of a silicon-containing material. The base substrate LS may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer. The base substrate LS may include other semiconductor materials, such as germanium. The base substrate LS may include a III / V semiconductor substrate (e.g., a compound semiconductor substrate, such as GaAs). The base substrate LS may include a silicon-on-insulator (SOI) substrate.

[0041] According to another embodiment of the present invention, the base substrate LS may include a peripheral circuit unit PC. The peripheral circuit unit PC may include a plurality of control circuits to control the memory cell array MCA. At least one control circuit in the peripheral circuit unit PC may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuit unit PC may include an address decoder circuit, a read circuit, and a write circuit. At least one control circuit in the peripheral circuit unit PC may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.

[0042] For example, the peripheral circuit unit PC may include a sense amplifier SA, and the sense amplifier SA may be coupled to the multi-level metal wiring MLM.

[0043] Although not shown, the plate line PL may be coupled to another peripheral circuit unit PC, or may be coupled to the base substrate LS through another multi-level metal wiring.

[0044] The memory cell array MCA may include a stack of memory cells MC. The memory cells MC may be vertically stacked in a first direction D1 over a base substrate LS.

[0045] refer to FIG. 2A to FIG. 2C , each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR may include an active layer ACT and a word line WL. The transistor TR may be located between the bit line BL and the capacitor CAP. The transistor TR may be positioned in a lateral arrangement LA parallel to the surface of the base substrate LS in the second direction D2. In short, the transistor TR may be positioned laterally between the bit line BL and the capacitor CAP.

[0046] The bit line BL may extend vertically in a first direction D1 from the base substrate LS. The plane of the base substrate LS may extend in a second direction D2, and the first direction D1 may be perpendicular to the second direction D2. The bit line BL may be oriented vertically relative to the base substrate LS. The bottom of the bit line BL may be coupled to the peripheral circuit unit PC. The bit line BL may have a columnar shape. The bit line BL may be referred to as a vertically oriented bit line or a columnar bit line. The bit line BL may include a conductive material. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Vertically stacked memory cells MC may share a bit line BL. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon doped with N-type impurities or titanium nitride (TiN). The bit line BL may include a stack of titanium nitride and tungsten (TiN / W). The bit line BL may further include an ohmic contact layer, such as a metal silicide.

[0047] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend in a third direction D3, and the active layer ACT may extend in a second direction D2. The third direction D3 may be a direction perpendicular to the first direction D1. The active layer ACT may be arranged laterally with respect to the bit line BL. The word line WL may have a shape that penetrates the active layer ACT. The word line WL may be an embedded word line positioned inside the active layer ACT.

[0048] refer to Figure 3A and Figure 3B , the active layer ACT may have a tube shape with a three-dimensional structure of a through portion TH. For example, it may have a three-dimensional structure having a portion extending in the second direction D2 and a portion extending in the third direction D3. The through portion TH of the active layer ACT may extend in the third direction D3, and the word line WL may be formed inside the through portion TH in the third direction D3. The active layer ACT may include a pair of first side walls SW1 and a pair of second side walls SW2. The pair of first side walls SW1 may extend parallel to each other in the second direction D2. The pair of second side walls SW2 may extend parallel to each other in the first direction D1. The through portion TH may be defined by the inside of the active layer ACT based on a combination of the first side wall SW1 and the second side wall SW2, and the through portion TH may extend in the third direction D3. The gate dielectric layer GD may be formed on the surface of the through portion TH. The pair of second side walls SW2 may be vertical side walls, and the pair of first side walls SW1 may be horizontal side walls.

[0049] The active layer ACT may include a semiconductor material such as polysilicon. The active layer ACT may include a first source / drain region SD1, a second source / drain region SD2, and a pair of channel regions CH between the first source / drain region SD1 and the second source / drain region SD2. The channel region CH may be formed inside the first side wall SW1. The channel region CH may be in the shape of a plate extending in the second direction D2, and the first source / drain region SD1 and the second source / drain region SD2 may be vertical side walls extending in the first direction D1. The first source / drain region SD1 and the second source / drain region SD2 may be formed in the second side wall SW2. The active layer ACT may include doped polysilicon, non-doped polysilicon, or amorphous silicon. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type impurities or P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with impurities of the same conductivity type. The first source / drain region SD1 and the second source / drain region SD2 may contain at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), or a combination thereof. In some embodiments of the present invention, the channel region CH may be doped with conductive impurities. According to another embodiment of the present invention, the first source / drain region SD1 and the second source / drain region SD2 may not be formed in the second side wall SW2, but may be formed above the second side wall SW2.

[0050] The word line WL may operate in close proximity to the channel region CH. The word line WL may include a metal, a metal mixture, a metal alloy, or a semiconductor material. In this embodiment of the present invention as described above, a gate dielectric layer GD may be formed between the word line WL and the channel region CH. The gate dielectric layer GD may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The gate dielectric layer GD may conformally cover the through portion TH of the active layer ACT.

[0051] refer to Figure 4 , the word line WL may include a pair of first side walls G1 and a pair of second side walls G2. The pair of first side walls G1 may extend in parallel with each other in the second direction D2. The pair of second side walls G2 may extend in parallel with each other in the third direction D3. The first side wall G1 and the second side wall G2 may be surrounded by the through portion TH of the active layer ACT. For example, the through portion TH of the active layer ACT may surround the first side wall G1 and the second side wall G2 of the word line WL.

[0052] Return to reference Figure 2B and Figure 2C, the capacitor CAP may be positioned laterally relative to the active layer ACT. The capacitor CAP may extend laterally in the second direction D2. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged laterally in the second direction D2. The storage node SN may have a laterally oriented cylinder shape, and the plate node PN may extend toward the inside and outside of the storage node SN. The dielectric layer DE may be positioned to surround the inner wall of the storage node SN and partially surround the outer wall of the storage node SN and thereby also partially surround the plate node PN. The plate node PN may be coupled to the plate line PL. The plate node PN and the plate line PL may be integrated.

[0053] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer DE may include a high-k material having a dielectric constant of about 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed by a composite layer having two or more layers of the above-mentioned high-k materials.

[0054] The dielectric layer DE may be formed of an oxide based on zirconium (Zr). The dielectric layer DE may be a laminated structure having zirconium oxide (ZrO2). The laminated structure having zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) laminate or a ZAZ (ZrO2 / Al2O3 / ZrO2) laminate. The ZA laminate may have a structure in which aluminum oxide (Al2O3) is laminated on zirconium oxide (ZrO2). The ZAZ laminate may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are sequentially laminated. The ZA laminate and the ZAZ laminate may be referred to as layers based on zirconium oxide (ZrO2). According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may be a laminated structure having hafnium oxide (HfO2). The stacked structure with hafnium oxide (HfO2) may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are sequentially stacked. The HA stack and the HAH stack may be referred to as hafnium oxide (HfO2)-based layers. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, the band gap of aluminum oxide (Al2O3) may be larger than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) may be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material having a bandgap larger than that of the high-k material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may include silicon oxide (SiO2) as another high-bandgap material. The dielectric layer DE may include a high-bandgap material to suppress current leakage. The high-bandgap material may be very thin. The high-bandgap material may be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure in which high-k materials and high-bandgap materials are alternately stacked. For example, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3). In the above-mentioned stacked structure, aluminum oxide (Al2O3) may be very thin.

[0055] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a laminated structure, or a mixed structure of zirconium oxide, hafnium oxide, and aluminum oxide.

[0056] According to another embodiment of the present invention, an interface control layer for improving current leakage may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium dioxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0057] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacking and tungsten nitride / tungsten (WN / W) stacking. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a stacking of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-fill material filling the inside of a storage node SN, while titanium nitride (TiN) may be used as a plate node of a large-capacity capacitor CAP, and tungsten nitride may be a low-resistance material.

[0058] The storage node SN has a three-dimensional structure, but the storage node SN of the three-dimensional structure may be a lateral three-dimensional structure parallel to the second direction D2. As an example of a three-dimensional structure, the storage node SN may have a cylindrical shape, a columnar shape, or a composite pylinder shape in which the columnar shape and the cylindrical shape are combined.

[0059] refer to Figure 5 , the plate node PN of the capacitor CAP may include an internal node N2 and external nodes N21, N22, N23, and N24. The internal node N2 and the external nodes N21, N22, N23, and N24 may be coupled to each other. The internal node N2 and the external nodes N21, N22, N23, and N24 may be coupled to the plate line PL. The internal node N2 may be located inside the storage node SN. The external nodes N21, N22, N23, and N24 may be located outside the storage node SN. The internal node N2 may be located inside the storage node SN. The external nodes N21, N22, N23, and N24 may be positioned around the cylindrical outer wall of the storage node SN. The external nodes N21, N22, N23, and N24 may be continuous.

[0060] Figure 6 is a perspective view showing a mirror-type memory device that shares a plate line. Figure 7 is a perspective view showing a mirror type memory device that shares a bit line.

[0061] refer to Figure 6 , describes a mirror-type structure 200 of a shared plate line PL. The mirror-type structure 200 may include Figure 2A The memory cell array MCA and the memory cells MC are shown.

[0062] refer to Figure 6 , one memory cell array MCA200 may include two memory cells MC1 and MC2. A plurality of memory cell arrays MCA200 may be vertically stacked in the first direction D1. The memory cell arrays MCA200 may be laterally arranged in the third direction D3.

[0063] The memory cell MC1 may include: a bit line BL1 vertically oriented in a first direction D1 relative to a base substrate LS; a transistor TR1 having an active layer ACT1 coupled to the bit line BL1 and laterally oriented in a second direction D2 crossing the bit line BL1; a capacitor CAP1 coupled to the active layer ACT1 and laterally oriented relative to the active layer ACT1; and a plate line PL coupled to the capacitor CAP1 and vertically oriented in the first direction D1. The transistor TR1 may be laterally oriented in the second direction D2 crossing the bit line BL1 and the active layer ACT1, and may include a word line WL1 embedded in the active layer ACT1. The word line WL1 may penetrate the active layer ACT1 and may extend in a third direction D3, and a gate dielectric layer (not shown) may be formed between the word line WL1 and the active layer ACT1. The bit line BL1 may be coupled to a peripheral circuit unit PC of the base substrate LS.

[0064] The memory cell MC2 may include: a bit line BL2 vertically oriented in a first direction D1 relative to a base substrate LS; a transistor TR2 having an active layer ACT2 coupled to the bit line BL2 and laterally oriented in a second direction D2 crossing the bit line BL2; a capacitor CAP2 coupled to the active layer ACT2 and laterally oriented relative to the active layer ACT2; and a plate line PL coupled to the capacitor CAP2 and vertically oriented in the first direction D1. The transistor TR2 may be laterally oriented in the second direction D2 crossing the bit line BL2 and the active layer ACT2, and may include a word line WL2 embedded in the active layer ACT2. The word line WL2 may penetrate the active layer ACT2 and may extend in a third direction D3, and a gate dielectric layer (not shown) may be formed between the word line WL2 and the active layer ACT2. The bit line BL2 may be coupled to a peripheral circuit unit PC of the base substrate LS.

[0065] The memory cells MC1 and MC2 may share one plate line PL. The plate lines PL may be coupled to each other through a common wiring PLM. The plate line PL may not be coupled to the peripheral circuit unit PC. According to another embodiment of the present invention, a common wiring PLM for coupling the plate line PL may be provided between the peripheral circuit unit PC and the plate line PL. According to another embodiment of the present invention, the plate lines PL may be coupled to each other to have an integrated structure.

[0066] The memory cells MC1 and MC2 may be arranged in a mirror-type structure that shares one plate line PL while being coupled to different bit lines BL1 and BL2. The memory cells MC1 and MC2 of the same level may be arranged laterally in a second direction D2 parallel to the base substrate LS. The memory cell array MCA200 of the same level may be arranged in a third direction D3. The memory cell arrays MCA200 of different levels may be arranged vertically in a first direction D1 perpendicular to the base substrate LS.

[0067] refer to Figure 7 , a mirror-type structure 300 sharing a bit line will be described. The mirror-type structure 300 may include Figure 2A The memory cell array MCA and the memory cells MC are shown.

[0068] refer to Figure 7 , one of the memory cell arrays MCA300 may include two memory cells MC1 and MC2. The memory cell arrays MCA300 may be vertically stacked in the first direction D1. The memory cell arrays MCA300 may be laterally arranged in the third direction D3.

[0069] The memory cell MC1 may include: a bit line BL vertically oriented in a first direction D1 relative to a base substrate LS; a transistor TR1 having an active layer ACT1 coupled to the bit line BL and laterally oriented in a second direction D2 crossing the bit line BL; a capacitor CAP1 coupled to the active layer ACT1 and laterally oriented relative to the active layer ACT1; and a plate line PL1 coupled to the capacitor CAP1 and vertically oriented in the first direction D1. The transistor TR1 may be laterally oriented in the second direction D2 crossing the bit line BL and the active layer ACT1, and may include a word line WL1 embedded in the active layer ACT1. The word line WL1 may penetrate the active layer ACT1 and may extend in a third direction D3, and a gate dielectric layer (not shown) may be formed between the word line WL1 and the active layer ACT1. The bit line BL may be coupled to a peripheral circuit unit PC of the base substrate LS.

[0070] The memory cell MC2 may include: a bit line BL vertically oriented in a first direction D1 relative to a base substrate LS; a transistor TR2 having an active layer ACT2 coupled to the bit line BL2 and laterally oriented in a second direction D2 crossing the bit line BL; a capacitor CAP2 coupled to the active layer ACT2 and laterally oriented relative to the active layer ACT2; and a plate line PL coupled to the capacitor CAP2 and vertically oriented in the first direction D1. The transistor TR2 may be laterally oriented in the second direction D2 crossing the bit line BL and the active layer ACT2, and may include a word line WL2 embedded in the active layer ACT2. The word line WL2 may penetrate the active layer ACT2 and may extend in a third direction D3, and a gate dielectric layer (not shown) may be formed between the word line WL2 and the active layer ACT2. The bit line BL may be coupled to a peripheral circuit unit PC of the base substrate LS.

[0071] The memory cells MC1 and MC2 may share one plate line PL. The plate line PL1 coupled to the memory cell MC1 may be coupled to a common wiring PLM. The plate line PL2 coupled to the memory cell MC2 may be coupled to a common wiring PLM. The plate lines PL1 and PL2 may not be coupled to the peripheral circuit unit PC. According to another embodiment of the present invention, the common wiring PLM coupled to the plate lines PL1 and PL2 may be provided between the peripheral circuit unit PC and the plate lines PL1 and PL2. According to another embodiment of the present invention, the plate lines PL1 and PL2 may be coupled to each other to have an integrated structure.

[0072] The memory cells MC1 and MC2 may be arranged in a mirror-type structure that shares one bit line BL while being coupled to different plate lines PL1 and PL2. The memory cells MC1 and MC2 of the same level may be arranged laterally in a second direction D2 parallel to the base substrate LS. The memory cell array MCA300 of the same level may be arranged in a third direction D3. The memory cell arrays MCA300 of different levels may be arranged vertically in a first direction D1 perpendicular to the base substrate LS.

[0073] According to another embodiment of the present invention, Figure 6 and Figure 7 The illustrated memory devices 200 and 300 may have a mirror type structure 200 sharing a plate line PL and a mirror type structure 300 sharing a bit line BL.

[0074] Fig. 8A and Figure 8B FIG. 1 is a plan view showing a memory cell according to another embodiment of the present invention. Fig. 8A is a plan view showing a storage unit, and Figure 8B It is shown Fig. 8A A plan view of the word line is shown.

[0075] refer to Fig. 8A and Figure 8B , the memory cell 400 may include: a bit line BL, which is vertically oriented in a first direction D1; an active layer ACT, which is coupled to the bit line BL and is laterally oriented in a second direction D2 crossing the bit line BL; a capacitor CAP, which is coupled to the active layer ACT and is laterally oriented relative to the active layer ACT; and a plate line PL, which is coupled to the capacitor CAP and is vertically oriented in the first direction D1. The memory cell 400 may include a word line WL, and the word line WL may be laterally oriented in a third direction D3 crossing the bit line BL and the active layer ACT. The word line WL may be embedded in the active layer ACT. The word line WL may penetrate the active layer ACT and may extend in the third direction D3.

[0076] The active layer ACT may include a protruding edge PE at a portion close to the bit line BL. Due to the protruding edge PE of the active layer ACT, the word line WL may include a protruding side portion WLE close to the bit line BL. The active layer ACT may further include a flat edge FE close to the capacitor CAP.

[0077] 9A to 9C A memory cell 500 according to another embodiment of the present invention is shown. Fig.9A is a plan view of a storage unit according to another embodiment of the present invention, Fig. 9B is a detailed diagram of the bit line, and Fig. 9C is a three-dimensional diagram of a storage unit.

[0078] refer to 9A to 9C , the memory cell 500 may include: a bit line BL, which is vertically oriented in a first direction D1; an active layer ACT, which is coupled to the bit line BL and is laterally oriented in a second direction D2 to intersect the bit line BL; a capacitor CAP, which is coupled to the active layer ACT and is laterally oriented relative to the active layer ACT; and a plate line PL, which is coupled to the capacitor CAP and is vertically oriented in the first direction D1. The memory cell 500 may include a word line WL, which is laterally oriented in a third direction D3 to intersect the bit line BL and the active layer ACT and is embedded in the active layer ACT. The word line WL may penetrate the active layer ACT.

[0079] The active layer ACT may include cut-type edges AE1 and AE2, which provide an opening portion AOP at a portion close to the bit line BL. The embedded side portion BLE of the bit line BL may be located in the opening portion AOP of the active layer ACT. The embedded side portion BLE may be a portion extending laterally from the bit line BL in the second direction D2. The active layer ACT may include a cap-shaped body ACB, and the cap-shaped body ACB may have a shape surrounding a portion of the word line WL. One side of the cap-shaped body ACB may be cut to form an opening portion AOP, and the opening portion AOP may be defined between the cut-type edges AE1 and AE2. Therefore, an open sidewall may be provided by the cut-type edges AE1 and AE2, and the embedded side portion BLE of the bit line BL may extend and be positioned in the deviated sidewall. The cut-type edges AE1 and AE2 of the active layer ACT may be coupled to the embedded side portion BLE of the bit line BL. The other side of the cap-shaped body ACB may include a flat edge FE, and the flat edge FE may be coupled to the capacitor CAP. The bit line BL and the embedded side portion BLE may include a metal-containing material. According to another embodiment of the present invention, the bit line BL may include a metal-containing material, and the embedded side portion BLE of the bit line BL may include polysilicon doped with impurities.

[0080] Fig. 10A and Fig. 10B A storage unit 600 according to another embodiment of the present invention is shown. Fig. 10A is a plan view of the storage unit 600, and Fig. 10B is a cross-sectional view of a word line.

[0081] refer to Fig. 10A and Fig. 10B , the memory cell 600 may include: a bit line BL, which is vertically oriented in a first direction D1; an active layer ACT, which is coupled to the bit line BL and is laterally oriented in a second direction D2 crossing the bit line BL; a capacitor CAP, which is coupled to the active layer ACT and is laterally oriented relative to the active layer ACT; and a plate line PL, which is coupled to the capacitor CAP and is vertically oriented in the first direction D1. The memory cell 600 may include a word line WL, which is laterally oriented in a third direction D3 crossing the bit line BL and the active layer ACT and is embedded in the active layer ACT. The word line WL may penetrate the active layer ACT.

[0082] The active layer ACT may include a body portion ACTB, a protruding edge AE60, and a flat edge FE. The protruding edge AE60 of the active layer ACT may be coupled to the bit line BL, and the flat edge FE of the active layer ACT may be coupled to the capacitor CAP. Each of the protruding edge AE60 and the flat edge FE of the active layer ACT may include a vertical sidewall extending in the first direction D1. According to another embodiment of the present invention, the flat edge FE may include a vertical sidewall, and the protruding edge AE60 may include an opening portion (see Fig.9A The protruding edge AE60 having the opening portion may include: Fig.9A The edges AE1 and AE2 are shown. The length of the main portion ACTB in the third direction D3 may be longer than the length of the protruding edge AE60 in the third direction D3.

[0083] The word line WL may include a line portion WLC and a lateral extension portion WLE. The line portion WLC of the word line WL may penetrate the body portion ACTB of the active layer ACT. The lateral extension portion WLE of the word line WL may be formed in the protruding edge AE60 of the active layer ACT.

[0084] According to another embodiment of the present invention, the protruding edge AE60 of the active layer ACT may have a cylindrical shape having an empty space inside, and the lateral extension portion WLE of the word line WL may extend to the inside of the protruding edge AE60 to be buried. Fig.13A , 13B , 15A and 15B.

[0085] Fig.11A and Fig. 11B A storage unit 610 according to another embodiment of the present invention is shown. Fig.11A is a cross-sectional view of the memory cell 610, and Fig. 11B is a cross-sectional view of a word line.

[0086] refer to Fig.11A and Fig. 11B , the memory cell 610 may include: a bit line BL, which is vertically oriented in a first direction D1; an active layer ACT, which is coupled to the bit line BL and is laterally oriented in a second direction D2 crossing the bit line BL; a capacitor CAP, which is coupled to the active layer ACT and is laterally oriented relative to the active layer ACT; and a plate line PL, which is coupled to the capacitor CAP and is vertically oriented in the first direction D1. The memory cell 610 may include a word line WL, which is laterally oriented in a third direction D3 crossing the bit line BL and the active layer ACT and is embedded in the active layer ACT. The word line WL may penetrate the active layer ACT.

[0087] The active layer ACT may include a body portion ACTB, a first protruding edge AE61, and a second protruding edge AE62. The first protruding edge AE61 of the active layer ACT may be close to the capacitor CAP, and the second protruding edge AE62 of the active layer ACT may be close to the bit line BL. Each of the first protruding edge AE61 and the second protruding edge AE62 of the active layer ACT may include a vertical sidewall extending in the first direction D1. According to another embodiment of the present invention, the first protruding edge AE61 may include a vertical sidewall, and the second protruding edge AE62 may include an opening portion (see Fig.9A AOP in ). Fig.9A As shown, the second protruding edge AE62 having the opening portion may include edges AE1 and AE2. The length of the body portion ACTB in the third direction D3 may be longer than the lengths of the first and second protruding edges AE61 and AE62 in the third direction D3.

[0088] The word line WL may include a line portion WLC, a first lateral extension portion WLE1, and a second lateral extension portion WLE2. The line portion WLC of the word line WL may penetrate the body portion ACTB of the active layer ACT. The first lateral extension portion WLE1 of the word line WL may be formed in the first protruding edge AE61 of the active layer ACT. The second lateral extension portion WLE2 of the word line WL may be formed in the second protruding edge AE62 of the active layer ACT.

[0089] According to another embodiment of the present invention, the first and second protruding edges AE61 and AE62 of the active layer ACT may have a cylindrical shape having an empty space inside, and the first and second lateral extensions WLE1 and WLE2 of the word line WL may extend to the inside of the first and second protruding edges AE61 and AE62 to be buried. Fig.13A , 13B , 15A and 15B.

[0090] Fig.12 is a plan view schematically showing the structure of a memory device 700 according to another embodiment of the present invention.

[0091] refer to Fig.12, the memory device 700 may include a base substrate LS, and a memory cell array MCA may be formed on the base substrate LS. The memory cell array MCA may be arranged vertically VA in a first direction D1 from the base substrate LS. The memory cell array MCA may include a plurality of memory cells MC, and each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. In each memory cell MC, the bit line BL, the transistor TR, the capacitor CAP, and the plate line PL may be positioned in a lateral arrangement LA in a second direction D2. Each memory cell MC may further include a word line WL, and the word line WL may extend in a third direction D3. The memory device 700 is shown as having a mirror-type structure with a shared bit line BL. According to another embodiment of the present invention, the memory device 700 may have a mirror-type structure with a shared plate line PL.

[0092] The base substrate LS may be a material suitable for semiconductor processing. The base substrate LS may include at least one of a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed on the base substrate LS. The base substrate LS may include a semiconductor substrate. The base substrate LS may be formed of a silicon-containing material. The base substrate LS may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The base substrate LS may include other semiconductor materials, such as germanium. The base substrate LS may include a III / V semiconductor substrate, for example, a compound semiconductor substrate, such as GaAs. The base substrate LS may include a silicon-on-insulator (SOI) substrate. According to another embodiment of the present invention, the base substrate LS may include a peripheral circuit unit PC. The peripheral circuit unit PC may include a plurality of control circuits to control the memory cell array MCA. The bit line BL may be coupled to the peripheral circuit unit PC.

[0093] The memory cell array MCA may include a stack of memory cells MC. The memory cells MC may be vertically stacked over the base substrate LS in a first direction D1.

[0094] Each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR may include an active layer ACT and a word line WL. The transistor TR may be located between the bit line BL and the capacitor CAP. The transistor TR may be positioned in a lateral arrangement LA parallel to the surface of the base substrate LS in the second direction D2. In short, the transistor TR may be positioned laterally between the bit line BL and the capacitor CAP.

[0095] The bit line BL may extend vertically in a first direction D1 from the base substrate LS. The plane of the base substrate LS may extend in a second direction D2, and the first direction D1 may be perpendicular to the second direction D2. The bit line BL may be vertically oriented relative to the base substrate LS. The bit line BL may have a columnar shape. The bit line BL may be referred to as a vertically oriented bit line or a columnar bit line. The bit line BL may include a conductive material. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Vertically stacked memory cells MC may share one bit line BL. The bit line BL and the plate line PL may be spaced apart from each other and may be vertically oriented in the first direction D1.

[0096] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend in a third direction D3, and the active layer ACT may extend in a second direction D2. The third direction D3 may be a direction perpendicular to the first direction D1. The active layer ACT may be arranged laterally relative to the bit line BL. The word line WL may have a shape that penetrates the active layer ACT. The word line WL may be an embedded word line embedded inside the active layer ACT. The active layer ACT may have a "C"-shaped tubular structure having a sidewall opened and penetrated by the word line WL. Here, the open sidewall of the active layer ACT may be close to the bit line BL. The active layer ACT may be formed separately based on the memory cell MC.

[0097] The transistor TR may further include a first source / drain region SD1 and a second source / drain region SD2. The first source / drain region SD1 may be located between one side of the active layer ACT and the bit line BL. The second source / drain region SD2 may be located between the other side of the active layer ACT and the capacitor CAP. The first source / drain region SD1 may be coupled to the bit line BL, and the second source / drain region SD2 may be coupled to the capacitor CAP. The first source / drain region SD1 may extend vertically in the first direction D1 while filling one open side of the active layer ACT. The vertically stacked memory cells MC may share the first source / drain region SD1. The second source / drain region SD2 may include a material selectively grown on the other sidewall of the active layer ACT. The second source / drain region SD2 may be formed separately from each other in each memory cell MC. The first source / drain region SD1 and the second source / drain region SD2 may include polysilicon doped with N-type impurities. The first source / drain region SD1 may be formed by deposition of a polysilicon layer and impurity doping. The second source / drain region SD2 may be formed by epitaxial growth of a polysilicon layer and impurity doping. A portion of the first source / drain region SD1 may fill an open sidewall of the active layer ACT. The first source / drain region SD1 may extend vertically in the first direction D1.

[0098] The capacitor CAP may be positioned laterally relative to the transistor TR. The capacitor CAP may extend laterally in the second direction D2. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged laterally in the second direction D2. The storage node SN may have a laterally oriented cylindrical shape, and the plate node PN may be a shape extending to the inside of the cylinder of the storage node SN. The dielectric layer DE may be located inside the storage node SN while surrounding the plate node PN. The plate node PN may be coupled to the plate line PL. The plate node PN and the plate line PL may be integrated. As Figure 5 As shown, the board node PN may include an internal node and a plurality of external nodes.

[0099] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer (DE) may include a high-k material having a dielectric constant of about 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed by a composite layer having two or more layers of the above-mentioned high-k materials.

[0100] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may be a laminated structure having zirconium oxide (ZrO2). The laminated structure having zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) laminate or a ZAZ (ZrO2 / Al2O3 / ZrO2) laminate. The ZA laminate may have a structure in which aluminum oxide (Al2O3) is laminated on zirconium oxide (ZrO2). The ZAZ laminate may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are sequentially laminated. The ZA laminate and the ZAZ laminate may be referred to as layers based on zirconium oxide (ZrO2). According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may be a laminated structure having hafnium oxide (HfO2). The stacked structure with hafnium oxide (HfO2) may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are sequentially stacked. The HA stack and the HAH stack may be referred to as hafnium oxide (HfO2)-based layers. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, the band gap of aluminum oxide (Al2O3) may be larger than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) may be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material having a bandgap larger than that of the high-k material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may include silicon oxide (SiO2) as a high-bandgap material. The dielectric layer DE may include a high-bandgap material to suppress current leakage. The high-bandgap material may be very thin. The high-bandgap material may be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure in which high-k materials and high-bandgap materials are alternately stacked. For example, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3). In the above-mentioned stacked structure, aluminum oxide (Al2O3) may be very thin.

[0101] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a laminated structure, or a mixed structure including zirconium oxide, hafnium oxide, and aluminum oxide.

[0102] According to another embodiment of the present invention, an interface control layer for improving current leakage may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium dioxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0103] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacking, tungsten nitride / tungsten (WN / W) stacking. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stacking. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the cylindrical interior of the storage node SN, and titanium nitride (TiN) may be substantially used as a plate node of the capacitor CAP, and tungsten nitride may be a low resistance material.

[0104] The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon doped with N-type impurities or titanium nitride (TiN). The bit line BL may include a stack of titanium nitride and tungsten (TiN / W). A barrier layer BR such as titanium nitride may be further included between the bit line BL and the first source / drain region SD1. The bit line BL may further include an ohmic contact layer such as a metal silicide.

[0105] Fig.13A It is shown Fig.12 A perspective view of a portion of a single storage unit is shown in FIG. Fig.13A The active layers and word lines are shown in detail. Fig. 13B yes Fig.13A Detail of the active layer shown in , and Fig. 13C is along Fig. 13B A cross-sectional view taken along line AA' is shown. Fig.13D This is a detailed diagram of the character line.

[0106] refer to FIG. 13A to FIG. 13D, the active layer ACT may extend in a second direction D2. The second direction D2 may be perpendicular to the first direction D1. The active layer ACT may be referred to as a transverse active layer. The active layer ACT may include a cylindrical portion CA, a macaroni-shaped portion MA, and a pair of plate portions AC3 and AC4, which are oriented transversely between the cylindrical portion CA and the macaroni-shaped portion MA. The pair of plate portions AC3 and AC4 may be positioned in parallel between the cylindrical portion CA and the macaroni-shaped portion MA.

[0107] The word line WL may include a buried body portion GC disposed between a pair of plate portions AC3 and AC4 to extend in a third direction D3, and the word line WL may include a first buried portion GB1 and a second buried portion GB2 extending from the buried body portion GC. The first buried portion GB1 and the second buried portion GB2 may extend in the second direction D2. The first buried portion GB1 and the second buried portion GB2 may be referred to as a first buried gate electrode and a second buried gate electrode, respectively.

[0108] The cylindrical portion CA and the macaroni-shaped portion MA of the active layer ACT may be spaced apart from each other in the second direction D2. A pair of plate portions AC3 and AC4 may be formed laterally between the cylindrical portion CA and the macaroni-shaped portion MA to extend in the second direction D2. The pair of plate portions AC3 and AC4 may be spaced apart from each other in parallel with the third direction D3.

[0109] The active layer ACT may further include a first concave portion R1 and a second concave portion R2. The first concave portion R1 may be formed in the cylindrical portion CA, and the second concave portion R2 may be formed in the macaroni-shaped portion MA. The first concave portion R1 and the second concave portion R2 may be laterally oriented concave portions, and may have a shape that is concave in the second direction D2. The first concave portion R1 may not penetrate the cylindrical portion CA, while the second concave portion R2 may penetrate the macaroni-shaped portion MA. The cylindrical portion CA may be referred to as a one-side closed-type cylinder, one side of which is closed, and the macaroni-shaped portion MA may be referred to as an open-type cylinder, both sides of which are open.

[0110] The first concave portion R1 may be defined by the interior of the cylindrical portion CA, and the first concave portion R1 may extend in the second direction D2. The first concave portion R1 may not penetrate the cylindrical portion CA. The cylindrical portion CA may include an upper sidewall USW, a lower sidewall LSW, and a vertical edge sidewall VSW. The cylindrical portion CA may also include a vertical sidewall SSW between the upper sidewall USW and the lower sidewall LSW. The vertical edge sidewall VSW of the cylindrical portion CA may be coupled to the second source / drain region (see Fig.12One plate portion AC3 may be coupled to the upper side wall USW of the cylindrical portion CA, and another plate portion AC4 may be coupled to the lower side wall LSW of the cylindrical portion CA.

[0111] The second concave portion R2 may be defined by the inside of the macaroni-shaped portion MA, and the second concave portion R2 may extend in the second direction D2. The second concave portion R2 may penetrate the macaroni-shaped portion MA in the second direction D2. The macaroni-shaped portion MA may further include an upper sidewall USW1, a lower sidewall LSW1, and a vertical sidewall SSW1 between the upper sidewall USW1 and the lower sidewall LSW1. The first source / drain region ( Fig.12 A portion of the plate portion AC1 may fill one end of the second concave portion R2. One plate portion AC3 may be coupled to the upper side wall USW1 of the macaroni-shaped portion MA, and another plate portion AC4 may be coupled to the lower side wall LSW1 of the macaroni-shaped portion MA.

[0112] The buried body portion GC of the word line WL may extend in the third direction D3. The first buried portion GB1 and the second buried portion GB2 may extend in the second direction D2. The first buried portion GB1 and the second buried portion GB2 may be coupled to both sides of the buried body portion GC. The first buried portion GB1 may extend laterally in the second direction D2 from the buried body portion GC. The second buried portion GB2 may extend laterally in the second direction D2 from the buried body portion GC. The lateral length L2 of the second buried portion GB2 in the second direction D2 may be longer than the lateral length L1 of the first buried portion GB1 in the second direction D2.

[0113] The buried body portion GC of the word line WL may have a shape buried between a pair of plate portions AC3 and AC4. The first buried portion GB1 may extend to be positioned inside the first concave portion R1 of the cylindrical portion CA. The first buried portion GB1 may fill the first concave portion R1 of the cylindrical portion CA. The second buried portion GB2 may extend to be positioned inside the second concave portion R2 of the macaroni-shaped portion MA. The second buried portion GB2 may fill the second concave portion R2 of the macaroni-shaped portion MA. One end of the second buried portion GB2 may not be covered by the macaroni-shaped portion MA and may be close to the first source / drain region ( Fig.12 The macaroni-shaped portion MA may have a shape surrounding the second buried portion GB2. For example, the remaining surface of the second buried portion GB2 except for the side surfaces opposite in the second direction D2 may be covered by the macaroni-shaped portion MA.

[0114] The buried channel may be defined by the first buried portion GB1 and the second buried portion GB2 of the word line WL from the inside of the active layer ACT.

[0115] Although not shown, a gate dielectric layer may be formed between the word line WL and the active layer ACT. The gate dielectric layer may be formed between the first buried portion GB1 of the word line WL and the barrel portion CA. The gate dielectric layer may be formed between the second buried portion GB2 of the word line WL and the macaroni-shaped portion MA. The gate dielectric layer may be formed between the buried body portion GC of the word line WL and the plate portions AC3 and AC4. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0116] The active layer ACT may include a semiconductor material such as polysilicon. The active layer ACT may include doped polysilicon, undoped polysilicon or amorphous silicon. The first active cylinder AC1, the second active cylinder AC2 and the plate portions AC3 and AC4 may be doped with N-type impurities or P-type impurities.

[0117] The word line WL may include a metal, a metal mixture, a metal alloy, a semiconductor material, a work function material, a barrier material, or a combination thereof.

[0118] Fig.14 800 is a cross-sectional view schematically showing the structure of a memory device according to another embodiment of the present invention. Except for the active layer, the constituent elements of the memory device 800 may be similar to Fig.12 Components of the memory device 700 are shown.

[0119] refer to Fig.14 , the memory device 800 may include a base substrate LS, and a memory cell array MCA may be formed above the base substrate LS. The memory cell array MCA may be arranged VA vertically relative to the base substrate LS in a first direction D1. The memory cell array MCA may include a plurality of memory cells MC, and each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. In the memory cell MC, the bit line BL, the transistor TR, the capacitor CAP, and the plate line PL may be positioned in a lateral arrangement LA in a second direction D2. Each memory cell MC may further include a word line WL, and the word line WL may extend in a third direction D3. The memory device 800 is shown as having a mirror-type structure sharing a bit line BL. According to another embodiment of the present invention, the memory device 800 may include a mirror-type structure sharing a plate line PL.

[0120] Each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR may include an active layer ACT and a word line WL. The transistor TR may be positioned between the bit line BL and the capacitor CAP. The transistor TR may be positioned in a lateral arrangement LA parallel to the surface of the base substrate LS in the second direction D2. In short, the transistor TR may be positioned laterally between the bit line BL and the capacitor CAP.

[0121] The bit line BL may extend in a first direction D1 from the base substrate LS. The plane of the base substrate LS may extend in a second direction D2, and the first direction D1 may be perpendicular to the second direction D2. The bit line BL may be oriented vertically relative to the base substrate LS. The bit line BL may have a columnar shape. The bit line BL may be referred to as a vertically oriented bit line or a columnar bit line. The bit line BL may include a conductive material. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Vertically stacked memory cells MC may share one bit line BL. The bit line BL and the plate line PL may be spaced apart from each other and may be vertically oriented in the first direction D1. According to another embodiment of the present invention, the base substrate LS may include a peripheral circuit unit PC. The peripheral circuit unit PC may include a plurality of control circuits to control the memory cell array MCA. The bit line BL may be coupled to the peripheral circuit unit PC.

[0122] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend in a third direction D3, and the active layer ACT may extend in a second direction D2. The third direction D3 may be a direction perpendicular to the first direction D1. The active layer ACT may be arranged laterally from the bit line BL. The word line WL may have a shape that penetrates the active layer ACT. The word line WL may be an embedded word line embedded in the active layer ACT. The active layer ACT may have a tubular structure penetrated by the word line WL. Here, the active layer ACT may have a shape that surrounds a portion of the word line WL. The active layer ACT may be formed separately based on each memory cell MC.

[0123] The transistor TR may further include a first source / drain region SD1 and a second source / drain region SD2. The first source / drain region SD1 may be located between one side of the active layer ACT and the bit line BL. The second source / drain region SD2 may be located between the other side of the active layer ACT and the capacitor CAP. The first source / drain region SD1 may be coupled to the bit line BL, and the second source / drain region SD2 may be coupled to the capacitor CAP. The first source / drain region SD1 may include a material selectively grown on one sidewall of the active layer ACT. The second source / drain region SD2 may include a material selectively grown on the other sidewall of the active layer ACT. The first source / drain region SD1 and the second source / drain region SD2 may be formed separately from each other in each memory cell MC. The first source / drain region SD1 and the second source / drain region SD2 may include polysilicon doped with N-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be formed by epitaxial growth of a polysilicon layer and impurity doping.

[0124] The capacitor CAP may be positioned laterally relative to the transistor TR. The capacitor CAP may extend laterally in the second direction D2. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged laterally in the second direction D2. The storage node SN may be a laterally oriented cylindrical shape, and the plate node PN may be a shape extending to the inside of the cylinder of the storage node SN. The dielectric layer DE may be positioned inside the storage node SN while surrounding the plate node PN. The plate node PN may be coupled to the plate line PL. The plate node PN and the plate line PL may be integrated. As Figure 5 As shown, the board node PN may include an internal node and a plurality of external nodes.

[0125] The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon doped with N-type impurities or titanium nitride (TiN). The bit line BL may include a stack of titanium nitride and tungsten (TiN / W). A barrier layer BR such as titanium nitride may be further included between the bit line BL and the first source / drain region SD1. The bit line BL may further include an ohmic contact layer such as a metal silicide.

[0126] Fig.15A It is shown Fig.14 A perspective view of a portion of a storage unit is shown in FIG. Fig.15A The active layers and word lines are shown in detail. Fig. 15B It is shown Fig.15A A perspective view of the active layer shown in FIG. Fig. 15C is along Fig. 15BA cross-sectional view taken along line AA' is shown. Fig.15D is a perspective view showing the word line in detail.

[0127] refer to FIG. 15A to FIG. 15D , the active layer ACT may extend in a second direction D2. The second direction D2 may be perpendicular to the first direction D1. The active layer ACT may be referred to as a transverse active layer. The active layer ACT may include a first active cylinder AC1, a second active cylinder AC2, and a pair of plate portions AC3 and AC4, which are oriented transversely between the first active cylinder AC1 and the second active cylinder AC2. The pair of plate portions AC3 and AC4 may be positioned transversely between the first active cylinder AC1 and the second active cylinder AC2.

[0128] The word line WL may include a buried body portion GC extending in a third direction D3 between a pair of plate portions AC3 and AC4, and may include a first buried portion GB1 and a second buried portion GB2 extending from the buried body portion GC. The first buried portion GB1 and the second buried portion GB2 may extend in the second direction D2. The first buried portion GB1 and the second buried portion GB2 may be referred to as a first buried gate electrode and a second buried gate electrode, respectively.

[0129] The first active cylinder AC1 and the second active cylinder AC2 may be spaced apart from each other in the second direction D2. A pair of plate portions AC3 and AC4 may be formed to be long in the second direction D2, between the first active cylinder AC1 and the second active cylinder AC2. A pair of plate portions AC3 and AC4 may be spaced apart from each other in parallel to the third direction D3.

[0130] The active layer ACT may further include a first concave portion R1 and a second concave portion R2. The first concave portion R1 may be formed inside the first active cylinder AC1, and the second concave portion R2 may be formed inside the second active cylinder AC2. The first concave portion R1 and the second concave portion R2 may be transversely oriented recesses and may have a shape that is recessed in the second direction D2. The first concave portion R1 may not penetrate the first active cylinder AC1, and the second concave portion R2 may not penetrate the second active cylinder AC2.

[0131] The first concave portion R1 may be defined by the inside of the first active cylinder AC1, and the first concave portion R1 may extend in the second direction D2. The first concave portion R1 may not penetrate the first active cylinder AC1. The first active cylinder AC1 may include an upper side wall USW, a lower side wall LSW, and a vertical edge side wall VSW. The first active cylinder AC1 may further include a vertical side wall SSW between the upper side wall USW and the lower side wall LSW. The vertical edge side wall VSW of the first active cylinder AC1 may be coupled to the second source / drain region (see Fig.14 'SD2' in FIG. 1 ). One plate portion AC3 may be coupled to the upper side wall USW of the first active cylinder AC1, and another plate portion AC4 may be coupled to the lower side wall LSW of the first active cylinder AC1.

[0132] The second recessed portion R2 may be defined by the interior of the second active cylinder AC2, and the second recessed portion R2 may extend in the second direction D2. The second recessed portion R2 may not penetrate the second active cylinder AC2. The second active cylinder AC2 may include an upper side wall USW1, a lower side wall LSW1, and a vertical edge side wall VSW1. The second active cylinder AC2 may further include a vertical side wall SSW1 between the upper side wall USW1 and the lower side wall LSW1. The vertical edge side wall VSW1 of the second active cylinder AC2 may be coupled to the first source / drain region (see Fig.14 One plate portion AC3 may be coupled to the upper side wall USW1 of the second active cylinder AC2, and the other plate portion AC4 may be coupled to the lower side wall LSW of the second active cylinder AC2.

[0133] As described above, the active layer ACT may include a first active cylinder AC1, a second active cylinder AC2, and a pair of plate portions AC3 and AC4. The first active cylinder AC1 may be coupled to one side edge of a pair of plate portions AC3 and AC4, and the second active cylinder AC2 may be coupled to the other side edge of a pair of plate portions AC3 and AC4. The first active cylinder AC1 and the second active cylinder AC2 may be parallel to each other in the second direction D2. The first active cylinder AC1 and the second active cylinder AC2 may be symmetrical to each other in the second direction D2. The first concave portion R1 and the second concave portion R2 may be symmetrical to each other. The shape, size, depth, width, and height of the first concave portion R1 and the second concave portion R2 may be the same. The first active cylinder AC1 and the second active cylinder AC2 may have a horizontal cylindrical shape. The first active cylinder AC1 and the second active cylinder AC2 may be referred to as a one-side closed cylinder, one side of which is closed by vertical edge side walls VSW and VSW1, respectively.

[0134] The buried body portion GC of the word line WL may extend long in the third direction D3. The first buried portion GB1 and the second buried portion GB2 may extend in the second direction D2. The first buried portion GB1 and the second buried portion GB2 may be coupled to both sides of the buried body portion GC. The first buried portion GB1 may extend laterally in the second direction D2 from the buried body portion GC. The second buried portion GB2 may extend laterally in the second direction D2 from the buried body portion GC.

[0135] The buried body portion GC of the word line WL may have a shape embedded between a pair of plate portions AC3 and AC4. The first buried portion GB1 may extend to be positioned inside the first concave portion R1 of the first active cylinder AC1. The first buried portion GB1 may fill the first concave portion R1 of the first active cylinder AC1. The second buried portion GB2 may extend to be positioned in the second concave portion R2 of the second active cylinder AC2. The second buried portion GB2 may fill the second concave portion R2 of the second active cylinder AC2. The lateral length L1' of the first buried portion GB1 in the second direction D2 may be the same as the lateral length L2' of the second buried portion GB2 in the second direction D2.

[0136] The buried channel may be defined by the first and second buried portions GB1 and GB2 of the word line WL by the insides of the first and second active cylinders AC1 and AC2.

[0137] Although not shown, a gate dielectric layer may be formed between the word line WL and the active layer ACT. The gate dielectric layer may be formed between the first buried portion GB1 of the word line WL and the first active cylinder AC1. The gate dielectric layer may be formed between the second buried portion GB2 of the word line WL and the second active cylinder AC2. The gate dielectric layer may conformally cover the surface of the first recessed portion R1 of the first active cylinder AC1 and the surface of the second recessed portion R2 of the second active cylinder AC2. The gate dielectric layer may be formed between the buried body portion GC of the word line WL and the plate portions AC3 and AC4. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0138] The active layer ACT may include a semiconductor material such as polysilicon. The active layer ACT may include doped polysilicon, undoped polysilicon or amorphous silicon. The first active cylinder AC1, the second active cylinder AC2 and the plate portions AC3 and AC4 may be doped with N-type impurities or P-type impurities.

[0139] The word line WL may include a metal, a metal mixture, a metal alloy, a semiconductor material, a work function material, a barrier material, or a combination thereof.

[0140] According to another embodiment of the present invention, the first active cylinder AC1 and the second active cylinder AC2 may be asymmetric to each other. For example, the lateral length of the first active cylinder AC1 may be shorter than the lateral length of the second active cylinder AC2. Similarly, the lateral length of the first active cylinder AC1 may be longer than the lateral length of the second active cylinder AC2.

[0141] Fig.16A and 16B is a perspective view showing memory devices 901 and 902 according to another embodiment of the present invention.

[0142] refer to Fig.16A and Fig. 16B , each of the memory devices 901 and 902 may include a peripheral circuit unit 910 and a memory cell array 920. The memory cell array 920 may include at least one memory cell array MCA among the memory cell arrays MCA described in the above embodiments of the present invention. The memory cell array MCA may include a DRAM memory cell array.

[0143] refer to Fig.16A , the memory cell array 920 may be located above the peripheral circuit unit 910. Therefore, the memory device 901 may have a PUC (Peripheral Under Cell) structure.

[0144] refer to Fig. 16B , the memory cell array 920 may be located below the peripheral circuit unit 910. Therefore, the memory device 902 may have a CUP (cell under peripheral circuit unit) structure.

[0145] The peripheral circuit unit 910 may refer to a circuit for driving the memory cell array 920 during a read / write operation. The peripheral circuit unit 910 may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The peripheral circuit unit 910 may include an address decoder circuit, a read circuit, and a write circuit. The peripheral circuit unit 910 may have a structure having a semiconductor substrate 912 and a sense amplifier 913 arranged above the semiconductor substrate 912. The sense amplifier 913 may include a transistor having the semiconductor substrate 912 as a channel, and the transistor may be a planar channel transistor whose channel is parallel to the surface of the semiconductor substrate 912. In addition to the planar channel transistor, the transistor structure in the sense amplifier 913 may include a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET).

[0146] The bit line BL of the memory cell array 920 may be electrically connected to the transistor of the sense amplifier 913. Although not shown, the bit line BL and the transistor of the sense amplifier 913 may be coupled to each other through a multi-level metal wiring MLM. The multi-level metal wiring MLM may be formed by a damascene process.

[0147] Although not shown, according to another embodiment of the present invention, the memory devices 901 and 902 may include a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate. The memory cell array 920 may be formed above the first semiconductor substrate, and the peripheral circuit unit 910 may be formed above the second semiconductor substrate. Each of the first semiconductor substrate and the second semiconductor substrate may include a conductive bonding pad, and the first semiconductor substrate and the second semiconductor substrate may be bonded to each other through the conductive bonding pad. As a result, the memory cell array 920 and the peripheral circuit unit 310 may be electrically connected.

[0148] Fig.17 FIG. 4 is a perspective view showing a capacitor CAP′ according to another embodiment of the present invention.

[0149] refer to Fig.17 , the plate node PN' of the capacitor CAP' may include an internal node N2' and external nodes N21', N22', N23', and N24'.

[0150] The external nodes N21', N22', N23', and N24' may include a first external node N21', a second external node N22', a third external node N23', and a fourth external node N24'. The first external node N21' and the second external node N22' may be located at the upper and lower sides of the storage node SN', and the third external node N23' and the fourth external node N24' may be located at the side of the storage node SN'.

[0151] The first external node N21' and the second external node N22' may have the same lateral length. The third external node N23' and the fourth external node N24' may have the same lateral length. The first external node N21' and the second external node N22' may have shorter lateral lengths than the third external node N23' and the fourth external node N24'.

[0152] Since the third external node N23 ′ and the fourth external node N24 ′ have longer lateral lengths, they may be able to more stably support the storage node SN.

[0153] According to an embodiment of the present invention, the three-dimensional memory device includes a transistor and a capacitor three-dimensionally stacked on a substrate. As a result, the integration degree of the memory device can be improved.

[0154] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A storage unit, comprising: bit lines and plate lines spaced apart from one another and oriented vertically in a first direction; a transistor including an active layer laterally oriented in a second direction across the bit line; a capacitor oriented laterally in the second direction between the active layer and the plate line; and A word line is laterally oriented in a third direction to intersect the bit line and the active layer, wherein the word line is embedded in the active layer and surrounded by the active layer.

2. The storage unit according to claim 1, wherein: The active layer includes a through portion extending in the third direction, and the word line is located in the through portion.

3. The storage unit according to claim 1, wherein: The active layer comprises: a first active barrel coupled to the bit line; a second active cylinder coupled to the capacitor; and A pair of plate portions are oriented transversely between the first active cylinder and the second active cylinder.

4. The storage unit according to claim 3, wherein: The first active cylinder, the second active cylinder, and the pair of plate portions are positioned in a transverse arrangement in the second direction.

5. The storage unit according to claim 3, wherein: The word line comprises: a buried body portion located between the pair of plate portions and extending in the third direction; a first buried portion extending from one side of the buried body portion and buried in the cylindrical interior of the first active cylinder; and A second buried portion extends from the other side of the buried body portion and is buried in the cylindrical interior of the second active cylinder.

6. The storage unit according to claim 3, wherein: The first active cylinder and the second active cylinder are located at the same level and have a laterally oriented cylindrical shape, and they are laterally spaced apart in the second direction.

7. The storage unit according to claim 3, wherein: A lateral length of the first active cylinder in the second direction is different from a lateral length of the second active cylinder in the second direction.

8. The storage unit according to claim 3, wherein: The first active barrel includes a first recess oriented transversely, and The second active barrel includes a second laterally oriented recess, and The transversely oriented first recess and the transversely oriented second recess face each other in the second direction.

9. The storage unit according to claim 1, further comprising: A gate dielectric layer is formed between the word line and the active layer.

10. The storage unit according to claim 1, wherein: The capacitor comprises: a storage node coupled to the transistor; a plate node coupled to the plate line; and a dielectric material between the storage node and the plate node, and The storage node, the dielectric material, and the plate node are positioned in a lateral arrangement in the second direction.

11. The storage unit according to claim 10, wherein: The board nodes include: an interior node oriented transversely from the plate line and extending into the cylindrical interior of the storage node; and A plurality of exterior nodes are oriented transversely from the plate line and surround the cylindrical exterior of the storage node.

12. The storage unit according to claim 11, wherein: The external nodes include: a first external node and a second external node positioned on a cylindrical exterior of the storage node in the first direction; and a third external node and a fourth external node positioned on the cylindrical exterior of the storage node in the third direction, and Transverse lengths of the first outer node and the second outer node are shorter than transverse lengths of the third outer node and the fourth outer node.

13. The storage unit according to claim 12, wherein: The lateral length of the first outer node is the same as the lateral length of the second outer node, and A lateral length of the third outer node is the same as a lateral length of the fourth outer node.

14. The storage unit according to claim 1, further comprising: a first source / drain region formed between the active layer and the bit line; and A second source / drain region is formed between the other side of the active layer and the capacitor.

15. The storage unit according to claim 1, wherein: The active layer comprises: a vertical edge sidewall between the capacitor and the word line; a pair of plate portions extending from upper and lower portions of the vertical edge side walls; and An open sidewall is between the word line and the bit line.

16. The storage unit of claim 15, further comprising: a first source / drain region coupled to the bit line while filling the open sidewalls of the active layer; a second source / drain region selectively grown from the vertical edge sidewalls of the active layer and coupled to the capacitor; and An ohmic contact layer is between the first source / drain region and the bit line.

17. A storage device comprising: a memory cell array comprising a plurality of memory cells arranged vertically in a first direction, Wherein, each of the storage units comprises: bit lines and plate lines spaced apart from one another and oriented vertically in a first direction; a transistor comprising an active layer laterally oriented in a second direction across the bit line, wherein the transistor comprises a first active barrel, a second active barrel, and a pair of plate portions laterally oriented between the first active barrel and the second active barrel; a word line oriented laterally in a third direction while penetrating between the pair of plate portions of the active layer; and A capacitor is oriented laterally in the second direction between the active layer and the plate line.

18. The memory device according to claim 17, wherein: The word line comprises: a buried body portion extending in the third direction while penetrating between the pair of plate portions; a first buried portion extending laterally from one side of the buried body portion in the second direction and buried in the first active cylinder; and A second buried portion extends laterally from the other side of the buried body portion in the second direction and is buried in the second active cylinder.

19. The memory device according to claim 17, further comprising: The peripheral circuit unit is located below the memory cell array and includes at least one control circuit for controlling the memory cell.

20. The memory device according to claim 17, further comprising: The peripheral circuit unit is located above the memory cell array and includes at least one control circuit for controlling the memory cells.

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