Organic Light-Emitting Display Device and Method of Manufacturing the Same

Abstract

An organic light-emitting display device includes: a substrate including a first region and a second region; a first active layer having a source region and a drain region disposed on the substrate in the first region; a first gate electrode disposed on the first active layer; a first source electrode disposed on the first gate electrode, the first source electrode being connected to the source region; a sacrificial layer structure disposed spaced apart from the first source electrode, the sacrificial layer structure having an opening; a protective insulating layer disposed on the first source electrode and the sacrificial layer structure; a first drain electrode disposed on the protective insulating layer, the first drain electrode being connected to the drain region through the opening, the first drain electrode together with the first active layer, the first gate electrode, and the first source electrode being defined as a first transistor; and a sub-pixel structure disposed on the first transistor.

Description

Technical Field

[0001] Embodiments generally relate to an organic light emitting display device and a method of manufacturing an organic light emitting display device. More particularly, embodiments of the inventive concept relate to an organic light emitting display device including transistors of different types from each other and a method of manufacturing an organic light emitting display device including transistors of different types from each other. Background Art

[0002] Flat panel display devices are used as display devices for replacing cathode ray tube display devices due to their light weight and thin characteristics. As a representative example of such flat panel display devices, there are liquid crystal display devices and organic light emitting display devices.

[0003] Recently, organic light emitting display devices including silicon-based semiconductor elements and metal oxide-based semiconductor elements have been developed. In order to drive an organic light emitting display device at high resolution, the organic light emitting display device may include a relatively large number of signal wirings. When the organic light emitting display device includes a relatively large number of signal wirings, the width of the signal wirings is relatively reduced to arrange the signal wirings in a limited space, and the resistance of the signal wirings increases. In addition, when the organic light emitting display device includes a flexible substrate and a thin film encapsulation structure, a part of the organic light emitting display device (e.g., a bending region) may be bent or folded. In a method of manufacturing an organic light emitting display device, an etching process of removing an inorganic insulating layer may be performed in the bending region. However, due to the addition of the etching process, the cost of manufacturing the organic light emitting display device is relatively increased. Summary of the Invention

[0004] Problems to be Solved

[0005] An object of the present invention is to provide an organic light emitting display device including transistors of different types from each other.

[0006] Another object of the present invention is to provide a method of manufacturing an organic light emitting display device including transistors of different types from each other.

[0007] However, the object of the inventive concept is not limited thereto. Thus, the object of the inventive concept may be extended without departing from the spirit and scope of the inventive concept.

[0008] Means for Solving the Problems

[0009] To achieve the above object of the present invention, an organic light emitting display device according to an embodiment of the present invention includes: a substrate including a first region and a second region; a first active layer having a source region and a drain region disposed on the substrate in the first region; a first gate electrode disposed on the first active layer; a first source electrode disposed on the first gate electrode and connected to the source region; a sacrificial layer structure disposed at a distance from the first source electrode and having an opening; a protective insulating layer disposed on the first source electrode and the sacrificial layer structure; a first drain electrode disposed on the protective insulating layer and connected to the drain region through the opening, the first drain electrode, together with the first active layer, the first gate electrode, and the first source electrode, being defined as a first transistor; and a sub-pixel structure disposed on the first transistor.

[0010] In an embodiment, the sacrificial layer structure may be positioned to overlap with the drain region, and the sacrificial layer structure and the first source electrode may be positioned at the same layer.

[0011] In an embodiment, the first drain electrode may be in direct contact with the sacrificial layer structure through the opening.

[0012] In an embodiment, the thickness of the sacrificial layer structure may be the same as the thickness of the first source electrode.

[0013] In an embodiment, the organic light emitting display device may further include: a second gate electrode disposed on the substrate in the second region; a second active layer disposed on the second gate electrode; and a second source electrode and a second drain electrode disposed on two sides of the second active layer, the second source electrode and the second drain electrode, together with the second gate electrode and the second active layer, being defined as a second transistor.

[0014] In an embodiment, the sacrificial layer structure may include: a lower sacrificial layer pattern positioned at the same layer as the second active layer and having a first opening; and an upper sacrificial layer pattern disposed on the lower sacrificial layer pattern and having a second opening overlapping with the first opening, and the first opening and the second opening may correspond to the opening of the sacrificial layer structure.

[0015] In an embodiment, the thickness of the lower sacrificial layer pattern may be the same as the thickness of the second active layer, and the thickness of the upper sacrificial layer pattern may be the same as the thickness of each of the first source electrode, the second source electrode, and the second drain electrode.

[0016] In an embodiment, the thickness of the lower sacrificial layer pattern may be the same as the thickness of the second active layer, and the thickness of the upper sacrificial layer pattern may be less than the thickness of each of the first source electrode, the second source electrode, and the second drain electrode.

[0017] In an embodiment, the sacrificial layer structure may be located on the same layer as the second active layer, and the thickness of the sacrificial layer structure may be the same as the thickness of the second active layer.

[0018] In an embodiment, each of the first source electrode, the second source electrode, and the second drain electrode may have a first thickness, and the first drain electrode may have a second thickness. The second thickness may be greater than the first thickness.

[0019] In an embodiment, the first transistor may have a top-gate structure, and the first active layer may include a silicon-based semiconductor. The second transistor may have a bottom-gate structure, and the second active layer may include a metal-oxide-based semiconductor.

[0020] In an embodiment, the organic light-emitting display device may further include: a gate electrode pattern disposed on the first gate electrode, and the gate electrode pattern may be located on the same layer as the second gate electrode.

[0021] In an embodiment, the substrate may further include: a peripheral region surrounding a display region including the first region and the second region; and a bending region located in one side of the peripheral region.

[0022] In an embodiment, the substrate may have a groove in the bending region.

[0023] To achieve another object of the present invention described above, a method of manufacturing an organic light emitting display device according to an embodiment of the present invention includes: forming a substrate having a light emitting region including a first region and a second region, a peripheral region surrounding the light emitting region, and a bending region positioned in one side of the peripheral region; forming a first active layer having a source region and a drain region on the substrate in the first region; forming a first gate electrode on the first active layer; forming a first contact hole exposing the source region; forming a first source electrode connected to the source region through the first contact hole; forming a sacrificial layer structure overlapping the drain region on the first active layer; forming a protective insulating layer on the first source electrode and the sacrificial layer structure; simultaneously forming i) a second contact hole exposing the drain region of the first active layer such that an opening is formed in the sacrificial layer structure and ii) a third contact hole exposing the bending region of the substrate; forming a first drain electrode connected to the drain region through the second contact hole and the opening; and forming a sub-pixel structure on the first drain electrode.

[0024] In an embodiment, a height of the second contact hole may be less than a height of the third contact hole.

[0025] In an embodiment, the method may further include: forming a buffer layer on the substrate; forming a gate insulating layer on the buffer layer; forming a first insulating intermediate layer on the gate insulating layer; and forming a second insulating intermediate layer on the first insulating intermediate layer. The protective insulating layer may be formed on the second insulating intermediate layer, and the sacrificial layer structure may be formed between the second insulating intermediate layer and the protective insulating layer.

[0026] In an embodiment, the second contact hole may be formed by removing the gate insulating layer, the first insulating intermediate layer, the second insulating intermediate layer, the sacrificial layer structure, and the protective insulating layer positioned to overlap the drain region of the first active layer.

[0027] In an embodiment, the third contact hole may be formed by removing the gate insulating layer, the first insulating intermediate layer, the second insulating intermediate layer, and the protective insulating layer positioned to overlap the bending region of the substrate.

[0028] In an embodiment, when forming the third contact hole, a part of the substrate may be removed.

[0029] Effects of the Invention

[0030] Since the organic light emitting display device according to an embodiment of the present invention includes a sacrificial layer structure, the second contact hole and the third contact hole can be formed simultaneously. Accordingly, in the process for forming the third contact hole, the drain region of the first active layer is not damaged.

[0031] In addition, since the organic light emitting display device includes a first transistor, and the first transistor includes a first drain electrode and a first source electrode disposed at different layers from each other, the first drain electrode can be used as a wiring having a relatively large thickness. Accordingly, the organic light emitting display device can be driven with high resolution.

[0032] In the method of manufacturing an organic light emitting display device according to an embodiment of the present invention, the sacrificial layer structure can relatively delay the time for forming the second contact hole, and can simultaneously form the second contact hole exposing the drain region of the first active layer and the third contact hole exposing the upper surface of the second organic layer positioned in the bending region. Accordingly, the drain region of the first active layer is not damaged. In addition, since the second contact hole and the third contact hole are formed simultaneously, the manufacturing cost can be relatively reduced, and the first drain electrode is not damaged.

[0033] However, the effects of the present invention are not limited thereto. Thus, the effects of the present invention can be extended without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a plan view showing an organic light emitting display device according to an embodiment of the present invention.

[0035] Figure 2 is a view showing Figure 1 an example of the organic light emitting display device.

[0036] Figure 3 is a perspective view for describing Figure 1 the shape in which the organic light emitting display device is bent.

[0037] Figure 4 is a block diagram showing an external device electrically connected to Figure 1 the organic light emitting display device.

[0038] Figure 5 is a circuit diagram showing a sub-pixel circuit and an organic light emitting diode disposed in a sub-pixel region of Figure 1 the organic light emitting display device.

[0039] Figure 6 is a cross-sectional view taken along line I-I' of Figure 1 the organic light emitting display device.

[0040] Figure 7 and Figure 8, Figure 10 , Figure 11 , Figure 13 , Figure 15 , Figure 16 and Figure 17 are cross - sectional views showing a method of manufacturing an organic light - emitting display device according to an embodiment of the present invention, Figure 9 is a plan view showing Figure 8 of the lower sacrificial layer pattern, Figure 12 is a plan view showing Figure 11 of the lower sacrificial layer pattern and the upper sacrificial layer pattern, and Figure 14 is a plan view showing Figure 13 of the sacrificial layer structure.

[0041] Figure 18 is a cross - sectional view showing an organic light - emitting display device according to an embodiment of the present invention.

[0042] Figure 19 is a cross - sectional view showing Figure 18 an example of the organic light - emitting display device.

[0043] Figure 20 , Figure 21 , Figure 23 , Figure 24 , Figure 25 , Figure 27 and Figure 28 are cross - sectional views showing a method of manufacturing an organic light - emitting display device according to an embodiment of the present invention, Figure 22 is a plan view showing Figure 18 of the sacrificial layer structure, and Figure 26 is a plan view showing the sacrificial layer structure in which an opening is formed in Figure 25 .

[0044] Figure 29 , Figure 30 and Figure 31 are cross - sectional views showing a method of manufacturing an organic light - emitting display device according to an embodiment of the present invention.

[0045] Figure 32 is a cross - sectional view showing an organic light - emitting display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] Hereinafter, an organic light - emitting display device according to an embodiment of the present invention and a method of manufacturing an organic light - emitting display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same or similar components.

[0047] Figure 1 is a plan view showing an organic light - emitting display device according to an embodiment of the present invention, andFigure 2 is a plan view showing an example of an organic light-emitting display device Figure 1 . Figure 3 is a perspective view for describing the bent shape of the organic light-emitting display device Figure 1 , and Figure 4 is a block diagram showing an external device electrically connected to the organic light-emitting display device Figure 1 .

[0048] Referring to Figure 1 , Figure 2 , Figure 3 and Figure 4 , the organic light-emitting display device 100 (e.g., the substrate 110 Figure 6 ) may include a display area 10 and a pad area 60. The display area 10 may include a light-emitting area 30 and a peripheral area 40 surrounding the light-emitting area 30. The light-emitting area 30 includes a plurality of sub-pixel circuit areas 20, and the sub-pixel circuit areas 20 may be entirely arranged in the light-emitting area 30. For example, Figure 5 the sub-pixel circuit SPC (e.g., the first transistor 250 Figure 6 and the second transistor 255 Figure 6 ) may be provided in each sub-pixel circuit area 20, and Figure 5 the organic light-emitting diode OLED (e.g., the sub-pixel structure 200 Figure 6 ) may be provided on the sub-pixel circuit SPC. In the display area 10, an image may be displayed through the sub-pixel circuit SPC and the organic light-emitting diode OLED.

[0049] For example, a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit may be provided in the sub-pixel circuit area 20. The first sub-pixel circuit may be connected to a first organic light-emitting diode for emitting red light, the second sub-pixel circuit may be connected to a second organic light-emitting diode for emitting green light, and the third sub-pixel circuit may be connected to a third organic light-emitting diode for emitting blue light.

[0050] In an embodiment, the first organic light-emitting diode may overlap with the first sub-pixel circuit, and the second organic light-emitting diode may overlap with the second sub-pixel circuit. Additionally, the third organic light-emitting diode may overlap with the third sub-pixel circuit. Alternatively, the first organic light-emitting diode may overlap with a part of the first sub-pixel circuit and a part of other sub-pixel circuits different from the first sub-pixel circuit, and the second organic light-emitting diode may overlap with a part of the second sub-pixel circuit and a part of other sub-pixel circuits different from the second sub-pixel circuit. Additionally, the third organic light-emitting diode may overlap with a part of the third sub-pixel circuit and a part of other sub-pixel circuits different from the third sub-pixel circuit. For example, the first to third organic light-emitting diodes may be arranged by using an RGB stripe scheme in which rectangles of the same size are arranged in sequence, an S stripe scheme including a blue organic light-emitting diode having a relatively large area, a WRGB scheme further including a white organic light-emitting diode, a PenTile scheme in which an RG-GB pattern is repeatedly arranged, and the like.

[0051] Additionally, at least one driving transistor, at least one switching transistor, at least one capacitor, etc. may be provided in each sub-pixel circuit region 20. In an embodiment, one driving transistor (e.g., Figure 5 the first transistor TR1) and six switching transistors (e.g., Figure 5 the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7) and one storage capacitor (e.g., Figure 5 the storage capacitor CST) etc. may be provided in each sub-pixel circuit region 20.

[0052] Although each of the display region 10, the peripheral region 40, and the sub-pixel circuit region 20 of the present invention has been described as having a rectangular planar shape, the shape is not limited thereto. For example, each of the display region 10, the peripheral region 40, and the sub-pixel circuit region 20 may have a triangular planar shape, a rhombic planar shape, a polygonal planar shape, a circular planar shape, a track planar shape, or an elliptical planar shape.

[0053] Furthermore, a plurality of wirings may be provided in the peripheral region 40. For example, these wirings may include data signal wirings, gate signal wirings, light emission control signal wirings, gate initialization signal wirings, initialization voltage wirings, power supply voltage wirings, etc. These wirings may extend from the peripheral region 40 to the light-emitting region 30 and may be electrically connected to the sub-pixel circuit and the organic light-emitting diode. Additionally, a gate driver and a data driver etc. may be provided in the peripheral region 40.

[0054] The pad region 60 may be positioned on one side of the display region 10, and the pad region 60 may include a bending region 50 and a pad electrode region 70. Here, the bending region 50 may be positioned in one side of the peripheral region 40. The pad electrode 470 electrically connected to the external device 101 may be disposed in the pad electrode region 70. Additionally, the bending region 50 may be positioned between the display region 10 and the pad electrode region 70, and connection electrodes may be disposed in the bending region 50. For example, the connection electrodes may electrically connect the pad electrode 470 and the sub-pixel circuit SPC. In an embodiment, the organic light-emitting display device 100 may have the same width in the horizontal direction (e.g., the first direction D1 parallel to the upper surface of the organic light-emitting display device 100).

[0055] In other embodiments, as Figure 2 shown, the width of the pad region 60 may be less than the width of the display region 10. For example, in the plan view of the organic light-emitting display device 100, the display region 10 may have a first width extending in a direction (e.g., the first direction D1) parallel to the upper surface of the organic light-emitting display device 100, and the pad region 60 may have a second width extending in the first direction D1 that is less than the first width.

[0056] Although the peripheral region 40 surrounding the light-emitting region 30 is shown as having the same width in Figure 1 it, the configuration of the present invention is not limited thereto. For example, the peripheral region 40 may include a first peripheral region extending in the first direction D1 and a second peripheral region extending in a second direction D2 perpendicular to the first direction D1. In other words, the first peripheral region of the peripheral region 40 may be adjacent to the top of the light-emitting region 30 and the bending region 50, and the second peripheral region of the peripheral region 40 may be positioned in two side portions (e.g., the left and right portions) of the light-emitting region 30. Here, the width of the second peripheral region extending in the first direction D1 may be relatively less than the width of the first peripheral region extending in the second direction D2. When the bending region 50 is bent about an axis along the first direction D1, the pad electrode region 70 may be positioned on the lower surface of the organic light-emitting display device 100 (refer to Figure 3 ). In other words, when the pad electrode region 70 is positioned on the lower surface of the organic light-emitting display device 100, the bending region 50 may have a bent shape.

[0057] The external device 101 may be electrically connected to the organic light emitting display device 100 through a flexible printed circuit board or a printed circuit board. For example, one side of the flexible printed circuit board may be in direct contact with the pad electrode 470, and the opposite side of the flexible printed circuit board may be in direct contact with the external device 101. The external device 101 may provide a data signal, a gate signal, a light emission control signal, a gate initialization signal, an initialization voltage, a power supply voltage, etc. to the organic light emitting display device 100. Additionally, a driver integrated circuit may be mounted in the flexible printed circuit board. In other embodiments, the driver integrated circuit may be mounted in the organic light emitting display device 100 adjacent to the pad electrode 470.

[0058] Figure 5 is a circuit diagram showing the sub-pixel circuit and the organic light emitting diode provided in Figure 1 the sub-pixel region.

[0059] Referring to Figure 5 , a sub-pixel circuit SPC and an organic light emitting diode OLED (e.g., Figure 1 ) may be provided in each of the sub-pixel circuit regions 20 (see Figure 1 ) of the organic light emitting display device 100 (see Figure 6 ), and one sub-pixel circuit SPC may include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, and a seventh transistor TR7, a storage capacitor CST, a wiring for a high power supply voltage ELVDD, a wiring for a low power supply voltage ELVSS, a wiring for an initialization voltage VINT, a wiring for a data signal DATA, a wiring for a gate signal GW, a wiring for a gate initialization signal GI, a wiring for a light emission control signal EM, a wiring for a diode initialization signal GB, etc. As described above, the first transistor TR1 may correspond to a driving transistor, and each of the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 may include a first terminal, a second terminal, a channel, and a gate terminal. In an embodiment, the first terminal may be a source terminal, and the second terminal may be a drain terminal. Alternatively, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

[0060] An organic light-emitting diode (OLED) can output light based on a driving current ID. The organic light-emitting diode (OLED) can include a first terminal and a second terminal. In an embodiment, a low power supply voltage ELVSS can be supplied to the second terminal of the organic light-emitting diode (OLED). For example, the first terminal of the organic light-emitting diode (OLED) can be an anode terminal, and the second terminal of the organic light-emitting diode (OLED) can be a cathode terminal. Alternatively, the first terminal of the organic light-emitting diode (OLED) can be a cathode terminal, and the second terminal of the organic light-emitting diode (OLED) can be an anode terminal. In an embodiment, the anode terminal of the organic light-emitting diode (OLED) can correspond to Figure 6 the lower electrode 290, and the cathode terminal of the organic light-emitting diode (OLED) can correspond to Figure 6 the upper electrode 340.

[0061] A first transistor TR1 (e.g., corresponding to Figure 6 the first transistor 250) can generate the driving current ID. In an embodiment, the first transistor TR1 can operate in the saturation region. In this case, the first transistor TR1 can generate the driving current ID based on the voltage difference between the gate terminal and the source terminal. Additionally, a color gradation can be presented based on the magnitude of the driving current ID supplied to the organic light-emitting diode (OLED). Alternatively, the first transistor TR1 can operate in the linear region. In this case, a color gradation can be presented based on the sum of the times of supplying the driving current to the organic light-emitting diode (OLED) within one frame.

[0062] The gate terminal of a second transistor TR2 can be supplied with a gate signal GW. The first terminal of the second transistor TR2 can be supplied with a data signal DATA. The second terminal of the second transistor TR2 can be connected to the first terminal of the first transistor TR1. For example, the gate signal GW can be provided from a gate driver, and the gate signal GW can be applied to the gate terminal of the second transistor TR2 through a wiring for the gate signal GW. The second transistor TR2 can supply the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the second transistor TR2 can operate in the linear region.

[0063] The gate terminal of the third transistor TR3 may be supplied with a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the third transistor TR3 through a wiring for the gate signal GW. The third transistor TR3 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during an activation period of the gate signal GW. In this case, the third transistor TR3 may operate in a linear region. That is, the third transistor TR3 may connect the first transistor TR1 in a diode manner during the activation period of the gate signal GW. Since the first transistor TR1 is connected in a diode manner, the voltage difference between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1 may be as large as the threshold voltage of the first transistor TR1. Therefore, during the activation period of the gate signal GW, a voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1. That is, the data signal DATA may be compensated by as much as the threshold voltage of the first transistor TR1, and the compensated data signal DATA may be supplied to the gate terminal of the first transistor TR1. Since the threshold voltage compensation is performed, the problem of uneven drive current caused by the threshold voltage deviation of the first transistor TR1 may be solved.

[0064] An input terminal of a wiring for an initialization voltage VINT supplied with the initialization voltage VINT may be connected to the first terminals of a fourth transistor TR4 and a seventh transistor TR7, and an output terminal of the wiring for the initialization voltage VINT may be connected to the second terminal of the fourth transistor TR4 and the first terminal of a storage capacitor CST.

[0065] The gate terminal of the fourth transistor TR4 may be supplied with a gate initialization signal GI. The first terminal of the fourth transistor TR4 may be supplied with the initialization voltage VINT. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1.

[0066] The fourth transistor TR4 may supply an initialization voltage VINT to the gate terminal of the first transistor TR1 during an activation period of the gate initialization signal GI. In this case, the fourth transistor TR4 may operate in the linear region. That is, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1. In other embodiments, the initialization voltage VINT may have a voltage level sufficiently higher than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1.

[0067] In an embodiment, the gate initialization signal GI may be a signal substantially the same as the gate signal GW transmitted one horizontal time before. For example, the gate initialization signal GI supplied to the sub-pixel circuit in the nth row (where n is an integer greater than or equal to 2) among the sub-pixel circuits included in the organic light-emitting display device 100 may be a signal substantially the same as the gate signal GW supplied to the sub-pixel circuit in the (n - 1)th row among the sub-pixel circuits. That is, by supplying the activated gate signal GW to the first sub-pixel circuit in the (n - 1)th row among the sub-pixel circuits SPC, the activated gate initialization signal GI may be supplied to the first sub-pixel circuit in the nth row among the sub-pixel circuits SPC. Accordingly, while the gate terminal of the first transistor TR1 in the sub-pixel circuit in the nth row among the sub-pixel circuits SPC is initialized to the initialization voltage VINT, the data signal DATA may be supplied to the sub-pixel circuit in the (n - 1)th row among the sub-pixel circuits SPC.

[0068] The gate terminal of the fifth transistor TR5 may be supplied with a light emission control signal EM. The first terminal of the fifth transistor TR5 may be connected to a wiring for a high power supply voltage ELVDD. The second terminal of the fifth transistor TR5 may be connected to the first terminal of the first transistor TR1. For example, the light emission control signal EM may be provided from a light emission control driver, and the light emission control signal EM may be applied to the gate terminal of the fifth transistor TR5 through a wiring for the light emission control signal EM. The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during an activation period of the light emission control signal EM. Conversely, the fifth transistor TR5 may cut off the supply of the high power supply voltage ELVDD during a deactivation period of the light emission control signal EM. In this case, the fifth transistor TR5 may operate in the linear region. The fifth transistor TR5 supplies the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the light emission control signal EM, so that the first transistor TR1 may generate a drive current ID. In addition, the fifth transistor TR5 cuts off the supply of the high power supply voltage ELVDD during the deactivation period of the light emission control signal EM, so that the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0069] The gate terminal of the sixth transistor TR6 may be supplied with a light emission control signal EM. The first terminal of the sixth transistor TR6 may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 may be connected to the first terminal of the organic light emitting diode OLED. The sixth transistor TR6 may supply the drive current ID generated by the first transistor TR1 to the organic light emitting diode OLED during an activation period of the light emission control signal EM. In this case, the sixth transistor TR6 may operate in the linear region. That is, the sixth transistor TR6 supplies the drive current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emission control signal EM, so that the organic light emitting diode OLED may output light. In addition, the sixth transistor TR6 electrically isolates the first transistor TR1 from the organic light emitting diode OLED during the deactivation period of the light emission control signal EM, so that the data signal DATA (more precisely, the data signal that has been compensated for the threshold voltage) supplied to the second terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0070] The gate terminal of the seventh transistor TR7 may be supplied with a diode initialization signal GB. The first terminal of the seventh transistor TR7 may be supplied with an initialization voltage VINT. The second terminal of the seventh transistor TR7 may be connected to the first terminal of the organic light-emitting diode OLED. The seventh transistor TR7 may supply the initialization voltage VINT to the first terminal of the organic light-emitting diode OLED during the activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 may operate in the linear region. That is, the seventh transistor TR7 may initialize the first terminal of the organic light-emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0071] Alternatively, the gate initialization signal GI and the diode initialization signal GB may be substantially the same signal. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light-emitting diode OLED may not affect each other. That is, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light-emitting diode OLED may be independent of each other. Therefore, the diode initialization signal GB is not separately generated, so that the economic efficiency of the process can be improved.

[0072] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the wiring for the high power supply voltage ELVDD and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the wiring for the high power supply voltage ELVDD. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the disable period of the gate signal GW. The disable period of the gate signal GW may include the activation period of the light emission control signal EM, and during the activation period of the light emission control signal EM, the drive current ID generated by the first transistor TR1 may be supplied to the organic light-emitting diode OLED. Therefore, the drive current ID generated by the first transistor TR1 may be supplied to the organic light-emitting diode OLED based on the voltage level maintained by the storage capacitor CST.

[0073] Although the sub-pixel circuit SPC of the present invention has been described as including seven transistors and one storage capacitor, the configuration of the present invention is not limited thereto. For example, the sub-pixel circuit SPC may have a configuration including at least one transistor and at least one storage capacitor.

[0074] Figure 6 is a cross-sectional view taken along Figure 1 line I-I' of the organic light-emitting display device.

[0075] Reference Figure 6 , the organic light-emitting display device 100 may include a substrate 110, a buffer layer 115, a first transistor 250, a second transistor 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating intermediate layer 190, a second insulating intermediate layer 195, a sacrificial layer structure 500, a protective insulating layer 400, a first planarization layer 270, signal wirings 350, connection patterns 370, a second planarization layer 275, a sub-pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, etc. Here, the substrate 110 may include a first organic layer 111, a first barrier layer 112, a second organic layer 113, and a second barrier layer 114. Since the organic light-emitting display device 100 includes a display region 10 (see Figure 1 ), and a pad region 60, the display region 10 (see Figure 1 ) includes a light-emitting region 30 and a peripheral region 40, and the pad region 60 includes a bending region 50 and a pad electrode region 70, the substrate 110 may also be divided into the display region 10 (see Figure 1 ) and the pad region 60. The first transistor 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230, and the second transistor 255 may include a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. In addition, the sub-pixel structure 200 may include a lower electrode 290, a light-emitting layer 330, and an upper electrode 340, and the thin film encapsulation structure 450 may include a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453. Further, the sacrificial layer structure 500 may include a lower sacrificial layer pattern 510 and an upper sacrificial layer pattern 520.

[0076] Since the organic light-emitting display device 100 includes a flexible substrate 110 and a thin film encapsulation structure 450, the organic light-emitting display device 100 may be used as a flexible organic light-emitting display device.

[0077] The first organic layer 111 may be provided. The first organic layer 111 may include a flexible organic material. In an embodiment, the first organic layer 111 may include polyimide, etc.

[0078] The first barrier layer 112 may be disposed over the entire first organic layer 111. The first barrier layer 112 may block moisture from permeating through the first organic layer 111. The first barrier layer 112 may include a flexible inorganic material. In an embodiment, the first barrier layer 112 may include silicon oxide, silicon nitride, etc.

[0079] The second organic layer 113 may be disposed on the first barrier layer 112. The second organic layer 113 may be disposed over the entire first barrier layer 112. The second organic layer 113 may include a flexible organic material. In an embodiment, the second organic layer 113 may include polyimide or the like.

[0080] The second barrier layer 114 may be disposed on the second organic layer 113. In an embodiment, the second barrier layer 114 may have an opening exposing the upper surface of the second organic layer 113, and the second organic layer 113 is positioned in the bending region 50. The second barrier layer 114 may block moisture from penetrating through the second organic layer 113. The second barrier layer 114 may include a flexible inorganic material. In an embodiment, the second barrier layer 114 may include silicon oxide, silicon nitride, or the like. Alternatively, no opening is formed in the second barrier layer 114 positioned in the bending region 50, or an opening is formed in both the second organic layer 113 and the second barrier layer 114 positioned in the bending region 50.

[0081] Thus, a substrate 110 may be provided, the substrate 110 including a first organic layer 111, a first barrier layer 112, a second organic layer 113, and a second barrier layer 114. In an embodiment, the substrate 110 may have a first region 11 and a second region 12, and the first region 11 may be positioned adjacent to the second region 12. For example, the first region 11 may be a region where a driving transistor is provided, and the second region 12 may be a region where a switching transistor is provided. In an embodiment, due to the formation of an opening in the second barrier layer 114, the substrate 110 may have a groove in the bending region 50.

[0082] Although the substrate 110 is described as having four layers, the configuration of the present invention is not limited thereto. For example, in other embodiments, the substrate 110 may include a single layer or at least two layers.

[0083] In other embodiments, the substrate 110 may include a transparent or opaque material. For example, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (e.g., an F-doped quartz substrate), a soda-lime glass substrate, a non-alkali glass substrate, or the like.

[0084] The buffer layer 115 may be disposed on the substrate 110. In an embodiment, the buffer layer 115 may be disposed on the substrate 110 in the first region 11 and the second region 12, and extend into the bending region 50, and the buffer layer 115 may have a first opening exposing the upper surface of the substrate 110 (e.g., the upper surface of the second organic layer 113) positioned in the bending region 50. The buffer layer 115 may prevent metal atoms or impurities from diffusing from the substrate 110 into the first transistor 250, the second transistor 255, and the sub-pixel structure 200, and may control the heat transfer rate during the crystallization process for forming the first active layer 130 to obtain a substantially uniform first active layer 130. Additionally, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be provided on the substrate 110, or the buffer layer 115 may not be provided on the substrate 110. For example, the buffer layer 115 may include an organic material or an inorganic material.

[0085] The first active layer 130 may be disposed on the buffer layer 115 in the first region 11. For example, the first active layer 130 may include a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, an organic semiconductor, etc. In an embodiment, the first active layer 130 may include a silicon-based semiconductor and may be formed of amorphous silicon or polycrystalline silicon. In an embodiment, the first active layer 130 may have a source region and a drain region.

[0086] The gate insulating layer 150 may be disposed on the buffer layer 115 and the first active layer 130 in the first region 11 and the second region 12. In an embodiment, the gate insulating layer 150 may cover the first active layer 130 on the substrate 110 in the first region 11 and extend into the bending region 50, and may have a second opening overlapping with the first opening. For example, the gate insulating layer 150 may sufficiently cover the first active layer 130 on the buffer layer 115 and may have a substantially flat upper surface without creating steps around the first active layer 130. Alternatively, the gate insulating layer 150 may cover the first active layer 130 on the buffer layer 115 and may be disposed with a substantially uniform thickness along the contour of the first active layer 130. The gate insulating layer 150 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), silicon carbonitride (SiC x N y ), aluminum oxide (AlO x) Aluminum nitride (AlN x ) Tantalum oxide (TaO x ) Hafnium oxide (HfO x ) Zirconium oxide (ZrO x ) Titanium oxide (TiO x ) etc. Alternatively, the gate insulating layer 150 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0087] The first gate electrode 170 may be disposed in the first region 11 on the gate insulating layer 150. For example, the first gate electrode 170 may be disposed on a portion of the gate insulating layer 150 where the first active layer 130 is located therebelow (e.g., a portion overlapping the channel region of the first active layer 130). The first gate electrode 170 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. Alternatively, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0088] The first insulating interlayer 190 may be disposed on the gate insulating layer 150 and the first gate electrode 170 in the first region 11 and the second region 12. In an embodiment, the first insulating interlayer 190 may cover the first gate electrode 170 on the gate insulating layer 150 in the first region 11 and extend into the bending region 50, and may have a third opening overlapping the first opening and the second opening. For example, the first insulating interlayer 190 may sufficiently cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat upper surface without creating a step around the first gate electrode 170. Alternatively, the first insulating interlayer 190 may cover the first gate electrode 170 on the gate insulating layer 150, and may be provided with a substantially uniform thickness along the contour of the first gate electrode 170. The first insulating interlayer 190 may include a silicon compound, a metal oxide, etc. Alternatively, the first insulating interlayer 190 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0089] The gate electrode pattern 180 may be disposed in the first region 11 on the first insulating interlayer 190. The gate electrode pattern 180 may be disposed on a portion of the first insulating interlayer 190 where the first gate electrode 170 is located therebelow. In another cross-sectional view of the organic light emitting display device 100, the first gate electrode 170 and the gate electrode pattern 180 may be used as Figure 5 the storage capacitor CST. The gate electrode pattern 180 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Alternatively, the gate electrode pattern 180 may have a multilayer structure including a plurality of layers.

[0090] The second gate electrode 175 may be disposed on the first insulating interlayer 190 in the second region 12. In other words, the second gate electrode 175 may be spaced apart from the gate electrode pattern 180. In an embodiment, the second gate electrode 175 and the gate electrode pattern 180 may be located at the same layer and may be formed simultaneously using the same material. The second gate electrode 175 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0091] The second insulating interlayer 195 may be disposed on the gate electrode pattern 180 and the second gate electrode 175 in the first region 11 and the second region 12. In an embodiment, the second insulating interlayer 195 may cover the gate electrode pattern 180 on the first insulating interlayer 190 in the first region 11 and cover the second gate electrode 175 on the first insulating interlayer 190 in the second region 12, and extend into the bending region 50, and the second insulating interlayer 195 may have a fourth opening overlapping with the first opening, the second opening, and the third opening. For example, the second insulating interlayer 195 may sufficiently cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190 and may have a substantially flat upper surface without creating steps around the gate electrode pattern 180 and the second gate electrode 175. Alternatively, the second insulating interlayer 195 may cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190 and may be provided with a substantially uniform thickness along the contours of the gate electrode pattern 180 and the second gate electrode 175. The second insulating interlayer 195 may include a silicon compound, a metal oxide, etc. Alternatively, the second insulating interlayer 195 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0092] The first source electrode 210 may be disposed on the second insulating interlayer 195 in the first region 11. The first source electrode 210 may be connected to the source region of the first active layer 130 through a first contact hole 212, and the first contact hole 212 is formed by removing a first portion of each of the gate insulating layer 150, the first insulating interlayer 190, and the second insulating interlayer 195. The first source electrode 210 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first source electrode 210 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an aluminum alloy, aluminum nitride (AlN x) Silver-containing alloy, tungsten nitride (WN x ) Copper-containing alloy, molybdenum-containing alloy, titanium nitride (TiN x ) Chromium nitride (CrN x ) Tantalum nitride (TaN x ) Strontium ruthenium oxide (SrRu x O y ) Zinc oxide (ZnO x ) Indium tin oxide (ITO), tin oxide (SnO x ) Indium oxide (InO x ) Gallium oxide (GaO x ) Indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0093] In an embodiment, the first source electrode 210 may have a first thickness T1 and may be formed as a single layer. For example, the first source electrode 210 may include Mo. Additionally, the first source electrode 210 may function as an electrode. In other words, since the first source electrode 210 functions as an electrode including Mo, the first source electrode 210 may have a relatively higher specific resistance than the first drain electrode 230, the signal wiring 350, and the connection pattern 370 that function as wirings including Al. In other embodiments, the first source electrode 210 may have a multi-layer structure including multiple layers.

[0094] The second active layer 135 may be disposed on the second insulating intermediate layer 195 in the second region 12. The second active layer 135 may be disposed on a portion of the second insulating intermediate layer 195 where the second gate electrode 175 is positioned thereunder. The second active layer 135 may include a metal oxide semiconductor. In other words, the second active layer 135 may be a semiconductor oxide layer that includes binary compounds (AB x ) ternary compounds (AB x C y ) or quaternary compounds (AB x C y D z ) etc. containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. For example, the second active layer 135 may include zinc oxide (ZnO x ) gallium oxide (GaO x ) titanium oxide (TiO x ) tin oxide (SnO x ) indium oxide (InO x) Indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), tin aluminum zinc oxide (TAZO), indium gallium tin oxide (IGTO), etc.

[0095] The second source electrode 215 and the second drain electrode 235 may be disposed on the second insulating intermediate layer 195 in the second region 12. The second source electrode 215 may cover the first side portion of the second active layer 135, and the second drain electrode 235 may cover the second side portion of the second active layer 135 different from the first side portion. In other words, the second source electrode 215 and the second drain electrode 235 may be disposed on two side portions of the second active layer 135 and may expose a part of the upper surface of the second active layer 135. Each of the second source electrode 215 and the second drain electrode 235 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0096] In an embodiment, the second source electrode 215 and the second drain electrode 235 may have a first thickness T1 and may be formed as a single layer. For example, each of the second source electrode 215 and the second drain electrode 235 may include Mo. Additionally, each of the second source electrode 215 and the second drain electrode 235 may serve as an electrode. In other words, since each of the second source electrode 215 and the second drain electrode 235 serves as an electrode including Mo, each of the second source electrode 215 and the second drain electrode 235 may have a relatively higher specific resistance than the first drain electrode 230 serving as a wiring including Al, the signal wiring 350, and the connection pattern 370. In other embodiments, the second source electrode 215 and the second drain electrode 235 may be integrally formed.

[0097] In an embodiment, the first source electrode 210, the second source electrode 215, and the second drain electrode 235 may be positioned at the same layer and may be formed simultaneously using the same material. In other embodiments, each of the second source electrode 215 and the second drain electrode 235 may have a multilayer structure including multiple layers. Accordingly, a second transistor 255 may be provided, which includes a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. Here, the second transistor 255 may be used as a switching transistor including an oxide-based semiconductor. Additionally, the second transistor 255 may be used as a transistor having a bottom gate structure. For example, the second transistor 255 may be one of the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 shown in Figure 5 .

[0098] A sacrificial layer structure 500 may be provided on the second insulating intermediate layer 195 while being spaced apart from the first source electrode 210. In an embodiment, the sacrificial layer structure 500 may overlap with the drain region of the first active layer 130, and the sacrificial layer structure 500 may be positioned at the same layer (e.g., the second insulating intermediate layer 195) as the first source electrode 210, the second active layer 135, the second source electrode 215, and the second drain electrode 235.

[0099] Additionally, the sacrificial layer structure 500 may have an opening 501 (refer to Figure 14 ). The drain region of the first active layer 130 may be exposed through the opening 501. For example, the opening 501 may be formed in a process for forming the second contact hole 232 such that the first drain electrode 230 is connected to the drain region of the first active layer 130. The sacrificial layer structure 500 may have a hollow rectangular planar shape on the second insulating intermediate layer 195. Alternatively, the shape of the sacrificial layer structure 500 may have a hollow triangular planar shape, a hollow rhombic planar shape, a hollow polygonal planar shape, a hollow circular planar shape, a hollow track-shaped planar shape, or a hollow elliptical planar shape.

[0100] As described above, the sacrificial layer structure 500 may include a lower sacrificial layer pattern 510 and an upper sacrificial layer pattern 520 provided on the lower sacrificial layer pattern 510. On the second insulating intermediate layer 195, the lower sacrificial layer pattern 510 is positioned at the same layer as the second active layer 135. Additionally, the lower sacrificial layer pattern 510 may have a first opening, and the upper sacrificial layer pattern 520 may have a second opening overlapping the first opening. Here, the first opening and the second opening may correspond to the opening 501 of the sacrificial layer structure 500.

[0101] In addition, the thickness of the lower sacrificial layer pattern 510 may be substantially the same as the thickness of the second active layer 135, and the thickness of the upper sacrificial layer pattern 520 may be substantially the same as a first thickness T1 of each of the first source electrode 210, the second source electrode 215, and the second drain electrode 235. That is, the upper sacrificial layer pattern 520 may have the first thickness T1.

[0102] Accordingly, the sacrificial layer structure 500 having the opening 501 positioned on the second insulating interlayer 195 may be disposed to overlap with the drain region of the first active layer 130.

[0103] For example, in a conventional method of manufacturing an organic light emitting display device, after forming the second contact hole 232, a third contact hole 102 may be formed in the bending region 50. In this case, in the process of forming the third contact hole 102, all of the photoresist disposed on the first drain electrode 230 may be removed, such that the first drain electrode 230 may be damaged. Otherwise, when the second contact hole 232 and the third contact hole 102 are formed simultaneously, since the thickness (or height) of the second contact hole 232 and the thickness of the third contact hole 102 are different, the drain region of the first active layer 130 may be damaged. For example, while the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the protective insulating layer 400 are removed to form the second contact hole 232, the second barrier layer 114, the buffer layer 115, the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the protective insulating layer 400 may be removed to form the third contact hole 102. That is, while removing the buffer layer 115 and the second barrier layer 114 positioned in the bending region 50, the drain region of the first active layer 130 may be removed.

[0104] In an embodiment of the present invention, since the organic light emitting display device 100 includes the sacrificial layer structure 500, the second contact hole 232 and the third contact hole 102 may be formed simultaneously in the method of manufacturing the organic light emitting display device 100. For example, the sacrificial layer structure 500 may delay the time for forming the second contact hole 232, and the second contact hole 232 exposing the drain region of the first active layer 130 and the third contact hole 102 exposing the upper surface of the second organic layer 113 positioned in the bending region 50 may be formed simultaneously. Accordingly, the drain region of the first active layer 130 may not be damaged.

[0105] The protective insulating layer 400 may be disposed on the second insulating intermediate layer 195, the first source electrode 210, the sacrificial layer structure 500, the second source electrode 215, and the second drain electrode 235 in the first region 11 and the second region 12. In an embodiment, the protective insulating layer 400 may cover the first source electrode 210, the sacrificial layer structure 500, the second source electrode 215, and the second drain electrode 235 on the second insulating intermediate layer 195 in the first region 11 and the second region 12, and may extend into the bending region 50, and the protective insulating layer 400 may have a fifth opening overlapping with the first opening to the fourth opening. Here, the first opening to the fifth opening may correspond to the third contact hole 102 formed in the bending region 50 on the substrate 110 (refer to Figure 13 ). For example, the protective insulating layer 400 may sufficiently cover the first source electrode 210, the sacrificial layer structure 500, the second source electrode 215, and the second drain electrode 235 on the second insulating intermediate layer 195, and may have a substantially flat upper surface without creating steps around the first source electrode 210, the sacrificial layer structure 500, the second source electrode 215, and the second drain electrode 235. Alternatively, the protective insulating layer 400 may cover the first source electrode 210, the sacrificial layer structure 500, the second source electrode 215, and the second drain electrode 235 on the second insulating intermediate layer 195, and may be provided with a substantially uniform thickness along the contours of the first source electrode 210, the sacrificial layer structure 500, the second source electrode 215, and the second drain electrode 235. The protective insulating layer 400 may include a silicon compound, a metal oxide, etc. Alternatively, the protective insulating layer 400 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0106] The first drain electrode 230 may be disposed on the protective insulating layer 400 in the first region 11. In other words, the first source electrode 210 and the first drain electrode 230 may be disposed at different layers from each other. The first drain electrode 230 may be connected to the drain region of the first active layer 130 through the second contact hole 232, and the second contact hole 232 is formed by removing a second portion of each of the gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, and the protective insulating layer 400. In an embodiment, the second contact hole 232 may pass through the opening 501 of the sacrificial layer structure 500. That is, the first drain electrode 230 may be in direct contact with the sacrificial layer structure 500 through the second contact hole 232. In addition, the first drain electrode 230 may have a second thickness T2 greater than the first thickness T1, and may be formed of multiple layers.

[0107] The first drain electrode 230 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the first drain electrode 230 may have a stacked structure of Ti / Al / Ti. Additionally, the first drain electrode 230 may be used as a wiring. In other words, since the first drain electrode 230 is used as a wiring including Al, the first drain electrode 230 may have a relatively lower specific resistance than the first source electrode 210, the second source electrode 215, and the second drain electrode 235 that are used as electrodes. A high power supply voltage (e.g., corresponding to Figure 5 the high power supply voltage ELVDD) may be applied to the first drain electrode 230 including Mo.

[0108] For example, in order to drive a conventional organic light-emitting display device at a high resolution, the conventional organic light-emitting display device must include a relatively large number of signal wirings. In this case, the signal wirings may be disposed on the second insulating intermediate layer 195. When the conventional organic light-emitting display device includes a relatively large number of signal wirings, the width of each signal wiring will be relatively reduced to arrange the signal wirings in a limited space, and the resistance of the signal wirings will increase. That is to say, an organic light-emitting display device with a high resolution may not be manufactured in a conventional manner.

[0109] In an embodiment of the present invention, the first drain electrode 230 of the first transistor 250 included in the organic light-emitting display device 100 is disposed in a layer different from the first source electrode 210, such that the first drain electrode 230 can be formed as a wiring having a relatively large width and a relatively large thickness. That is to say, the first drain electrode 230 may have a relatively low resistance, and the organic light-emitting display device 100 can form signal wirings on the protective insulating layer 400. Therefore, the organic light-emitting display device 100 has a first transistor 250, and the first transistor 250 includes the first drain electrode 230 having a relatively large width and a relatively large thickness, such that the organic light-emitting display device 100 can be driven at a high resolution.

[0110] Therefore, a first transistor 250 including a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230 may be provided. Here, the first transistor 250 may be used as a driving transistor including a silicon-based semiconductor. Additionally, the first transistor 250 may be used as a transistor having a top-gate structure. For example, the first transistor 250 may correspond to Figure 5 the first transistor TR1 shown in

[0111] Although the organic light emitting display device 100 is described as having a configuration including two transistors (e.g., the first transistor 250 and the second transistor 255), the configuration of the present invention is not limited thereto. For example, the organic light emitting display device 100 may have a configuration including at least two transistors and at least one capacitor.

[0112] The first planarization layer 270 may be disposed on the protective insulating layer 400 and the first drain electrode 230. The first planarization layer 270 may be disposed on the entire protective insulating layer 400. For example, the first planarization layer 270 may be disposed to have a relatively thick thickness to sufficiently cover the first drain electrode 230, and in this case, the first planarization layer 270 may have a substantially flat upper surface. Additionally, a planarization process may be applied to the first planarization layer 270 to achieve the flat upper surface of the first planarization layer 270. In an embodiment, the first planarization layer 270 may fill the first opening to the fifth opening located in the bending region 50. In other words, the first planarization layer 270 may be in direct contact with the upper surface of the second organic layer 113 located in the bending region 50. Alternatively, the first planarization layer 270 may be disposed only in the light emitting region 30 and may not be disposed in the pad region 60. The first planarization layer 270 may include an organic material or an inorganic material. In an embodiment, the first planarization layer 270 may include an organic material. For example, the first planarization layer 270 may include a photoresist, a polyacrylic acid-based resin, a polyimide-based resin, a polyamide-based resin, a silicone-based resin, an acrylic acid-based resin, or an epoxy-based resin, etc.

[0113] The signal wiring 350 and the connection pattern 370 may be disposed on the first planarization layer 270. A data signal (e.g., Figure 5 the data signal DATA shown therein) may be applied to the signal wiring 350, and a high power supply voltage (e.g., Figure 5 the high power supply voltage ELVDD shown therein) may be applied to the connection pattern 370. In other words, the signal wiring 350 may correspond to Figure 5 the wiring for the data signal DATA shown therein, and the connection pattern 370 may correspond to Figure 5 the second terminal of the sixth transistor TR6 shown therein. For example, the signal wiring 350 may transmit the data signal DATA to the second transistor 255, and the data signal DATA transmitted to the second transistor 255 (e.g., the second drain electrode 235 of the second transistor 255) may be applied to the first transistor 250 (e.g., the first gate electrode 170 of the first transistor 250). Additionally, the first drain electrode 230 of the first transistor 250 may transmit the high power supply voltage ELVDD to the connection pattern 370 (e.g., Figure 5the second terminal of the sixth transistor TR6 shown in [Fig.], and the high power supply voltage ELVDD transmitted to the connection pattern 370 may be applied to the lower electrode 290.

[0114] Each of the signal wiring 350 and the connection pattern 370 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, each of the signal wiring 350 and the connection pattern 370 may serve as a wiring, and may have a stacked structure of Ti / Al / Ti.

[0115] The second planarization layer 275 may be disposed on the first planarization layer 270, the signal wiring 350, and the connection pattern 370. The second planarization layer 275 may be disposed on the entire first planarization layer 270. For example, the second planarization layer 275 may be disposed to have a relatively thick thickness to sufficiently cover the signal wiring 350 and the connection pattern 370, and in this case, the second planarization layer 275 may have a substantially flat upper surface. Additionally, a planarization process may be applied to the second planarization layer 275 to achieve such a flat upper surface of the second planarization layer 275. Alternatively, the second planarization layer 275 may be disposed only in the light-emitting region 30 and may not be disposed in the pad region 60. The second planarization layer 275 may include an organic material or an inorganic material. In an embodiment, the second planarization layer 275 may include an organic material.

[0116] The lower electrode 290 may be disposed on the second planarization layer 275. The lower electrode 290 may be connected to the connection pattern 370 through a contact hole formed by removing a part of the second planarization layer 275. The lower electrode 290 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. Alternatively, the lower electrode 290 may have a multilayer structure including multiple layers.

[0117] The pixel defining layer 310 may be disposed on a part of the lower electrode 290 and the second planarization layer 275. The pixel defining layer 310 may cover both sides of the lower electrode 290 and may expose a part of the upper surface of the lower electrode 290. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In an embodiment, the pixel defining layer 310 may include an organic material. Alternatively, the pixel defining layer 310 may be disposed only in the light-emitting region 30 and may not be disposed in the pad region 60.

[0118] The light-emitting layer 330 may be disposed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of light-emitting materials for emitting light of different colors (i.e., red, green, blue, etc.) according to sub-pixels. Alternatively, the light-emitting layer 330 may be formed by laminating a plurality of light-emitting materials for emitting light of different colors such as red, green, or blue to emit white light as a whole. In this case, a color filter (e.g., overlapping with the light-emitting layer 330 on the upper surface of the thin film encapsulation structure 450) may be disposed on the light-emitting layer 330. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin, a color photoresist, etc.

[0119] The upper electrode 340 may be disposed on the pixel defining layer 310 and the light-emitting layer 330. The upper electrode 340 may cover the light-emitting layer 330 and the pixel defining layer 310, and may be completely disposed on the light-emitting layer 330 and the pixel defining layer 310. In an embodiment, a low power supply voltage (e.g., Figure 5 the low power supply voltage ELVSS shown in) may be applied to the upper electrode 340. The upper electrode 340 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multi-layer structure including a plurality of layers. Thus, the sub-pixel structure 200 including the lower electrode 290, the light-emitting layer 330, and the upper electrode 340 may be provided.

[0120] The first thin film encapsulation layer 451 may be disposed on the upper electrode 340 in the light-emitting region 30. In the light-emitting region 30, the first thin film encapsulation layer 451 may cover the upper electrode 340, and may be disposed to have a substantially uniform thickness along the contour of the upper electrode 340. The first thin film encapsulation layer 451 may prevent the sub-pixel structure 200 from being deteriorated due to the penetration of moisture, oxygen, etc. In addition, the first thin film encapsulation layer 451 may be used to protect the sub-pixel structure 200 from the influence of external impact. The first thin film encapsulation layer 451 may include a flexible inorganic material.

[0121] The second thin film encapsulation layer 452 may be disposed on the first thin film encapsulation layer 451 in the light-emitting region 30. The second thin film encapsulation layer 452 may improve the flatness of the organic light-emitting display device 100, and may protect the sub-pixel structure 200. The second thin film encapsulation layer 452 may include a flexible organic material.

[0122] The third thin film encapsulation layer 453 may be disposed on the second thin film encapsulation layer 452 in the light emitting region 30. In the light emitting region 30, the third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 and may be disposed to a substantially uniform thickness along the contour of the second thin film encapsulation layer 452. The third thin film encapsulation layer 453, together with the first thin film encapsulation layer 451, may prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, and the like. In addition, the third thin film encapsulation layer 453 may be used together with the first thin film encapsulation layer 451 and the second thin film encapsulation layer 452 to protect the sub-pixel structure 200 from external impact. The third thin film encapsulation layer 453 may include a flexible inorganic material. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by stacking the first thin film encapsulation layer to the fifth thin film encapsulation layer or a seven-layer structure formed by stacking the first thin film encapsulation layer to the seventh thin film encapsulation layer.

[0123] Thus, a thin film encapsulation structure 450 including a first thin film encapsulation layer 451 , a second thin film encapsulation layer 452 , and a third thin film encapsulation layer 453 may be provided.

[0124] Since the organic light emitting display device 100 according to the embodiment of the present invention includes the sacrificial layer structure 500, the second contact hole 232 and the third contact hole 102 can be formed simultaneously. Therefore, in the process for forming the third contact hole 102, the drain region of the first active layer 130 is not damaged.

[0125] In addition, since the organic light-emitting display device 100 includes the first transistor 250, the first transistor 250 includes the first drain electrode 230 and the first source electrode 210 disposed at different layers from each other, the first drain electrode 230 can be used as a wiring having a relatively large thickness. Therefore, the organic light-emitting display device 100 can be driven with high resolution.

[0126] Figure 7 , Figure 8 , Figure 10 , Figure 11 , Figure 13 , Figure 15 , Figure 16 and Figure 17 is a cross-sectional view showing a method for manufacturing an organic light-emitting display device according to an embodiment of the present invention. Figure 7 , Figure 8 , Figure 10 , Figure 11 , Figure 13 , Figure 15 , Figure 16 and Figure 17 is a cross-sectional view showing a method of manufacturing an organic light emitting display device, and Figure 9 It is shown Figure 8Plan view of the lower sacrificial layer pattern. Additionally, Figure 12 is a plan view showing Figure 11 the lower sacrificial layer pattern and the upper sacrificial layer pattern, and Figure 14 is a plan view showing Figure 13 the sacrificial layer structure.

[0127] Referring to Figure 7 , a rigid glass substrate 105 can be provided. A first organic layer 111 can be formed on the glass substrate 105. The first organic layer 111 can be formed over the entire glass substrate 105 and can be formed using a flexible organic material such as polyimide.

[0128] A first barrier layer 112 can be formed over the entire first organic layer 111. The first barrier layer 112 can block moisture from penetrating through the first organic layer 111. The first barrier layer 112 can be formed using a flexible inorganic material such as silicon oxide, silicon nitride, etc.

[0129] A second organic layer 113 can be formed on the first barrier layer 112. The second organic layer 113 can be formed over the entire first barrier layer 112 and can be formed using a flexible organic material such as polyimide.

[0130] A second barrier layer 114 can be formed over the entire second organic layer 113. The second barrier layer 114 can block moisture from penetrating through the second organic layer 113. The second barrier layer 114 can be formed using a flexible inorganic material such as silicon oxide, silicon nitride, etc.

[0131] Thus, a substrate 110 including the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114 can be formed.

[0132] Since the substrate 110 is thin and flexible, the substrate 110 can be formed on the rigid glass substrate 105 to support the formation of an upper structure (e.g., a first transistor, a second transistor, a sub-pixel structure, a thin film encapsulation structure, etc.). For example, after the upper structure is formed on the substrate 110, the glass substrate 105 can be removed. In other words, due to the flexible physical properties of the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114, it may be difficult to directly form the upper structure on the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114. Considering the above points, the glass substrate 105 is used to form the upper structure, and then the glass substrate 105 is removed so that the first organic layer 111, the first barrier layer 112, the second organic layer 113, and the second barrier layer 114 can be used as the substrate 110.

[0133] A buffer layer 115 may be formed on the substrate 110. In an embodiment, the buffer layer 115 may be formed on the substrate 110 in the first region 11 and the second region 12, and may extend into the bending region 50. That is to say, the buffer layer 115 may be formed on the entire substrate 110. The buffer layer 115 may prevent the diffusion of metal atoms or impurities from the substrate 110, and may control the heat transfer rate during the crystallization process for forming the active layer to obtain a substantially uniform active layer. Additionally, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be provided on the substrate 110, or the buffer layer 115 may not be formed on the substrate 110. For example, the buffer layer 115 may be formed using an organic material or an inorganic material.

[0134] In the first region 11, a first active layer 130 may be formed on the buffer layer 115. For example, the first active layer 130 may include a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, an organic semiconductor, etc. In an embodiment, the first active layer 130 may include a silicon-based semiconductor, and may be formed using amorphous silicon or polycrystalline silicon. In an embodiment, the first active layer 130 may have a source region and a drain region.

[0135] In the first region 11 and the second region 12, a gate insulating layer 150 may be formed on the buffer layer 115 and the first active layer 130. For example, the gate insulating layer 150 may cover the first active layer 130 on the substrate 110 in the first region 11, and may extend into the bending region 50. That is to say, the gate insulating layer 150 may be formed on the entire buffer layer 115. For example, the gate insulating layer 150 may sufficiently cover the first active layer 130 on the buffer layer 115, and may have a substantially flat upper surface without creating steps around the first active layer 130. Alternatively, the gate insulating layer 150 may cover the first active layer 130 on the buffer layer 115, and may be formed to have a substantially uniform thickness along the contour of the first active layer 130. The gate insulating layer 150 may be formed using a silicon compound, a metal oxide, etc. For example, the gate insulating layer 150 may include SiO x , SiN x , SiO x N y , SiO x C y , SiC x N y , AlO x , AlN x , TaO x , HfO x , ZrO x , TiO xetc. Alternatively, the gate insulating layer 150 may have a multilayer structure having a plurality of insulating layers including such different materials.

[0136] In the first region 11, a first gate electrode 170 may be formed on the gate insulating layer 150. For example, the first gate electrode 170 may be formed on a portion of the gate insulating layer 150 where the first active layer 130 is located therebelow (e.g., a portion overlapping with the channel region of the first active layer 130). The first gate electrode 170 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. Alternatively, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0137] In the first region 11 and the second region 12, a first insulating intermediate layer 190 may be formed on the gate insulating layer 150 and the first gate electrode 170. For example, the first insulating intermediate layer 190 may cover the first gate electrode 170 on the gate insulating layer 150 in the first region 11 and may extend into the bending region 50. That is, the first insulating intermediate layer 190 may be formed on the entire gate insulating layer 150. For example, the first insulating intermediate layer 190 may sufficiently cover the first gate electrode 170 on the gate insulating layer 150 and may have a substantially flat upper surface without creating a step around the first gate electrode 170. Alternatively, the first insulating intermediate layer 190 may cover the first gate electrode 170 on the gate insulating layer 150 and may be formed to have a substantially uniform thickness along the contour of the first gate electrode 170. The first insulating intermediate layer 190 may be formed using a silicon compound, a metal oxide, etc. Alternatively, the first insulating intermediate layer 190 may have a multilayer structure having a plurality of insulating layers including different materials from each other.

[0138] In the first region 11, a gate electrode pattern 180 may be formed on the first insulating intermediate layer 190. The gate electrode pattern 180 may be formed on a portion of the first insulating intermediate layer 190 where the first gate electrode 170 is located therebelow. The gate electrode pattern 180 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Alternatively, the gate electrode pattern 180 may have a multilayer structure including a plurality of layers.

[0139] In the second region 12, a second gate electrode 175 may be formed on the first insulating intermediate layer 190. In an embodiment, the second gate electrode 175 and the gate electrode pattern 180 may be located at the same layer and may be formed simultaneously using the same material. The second gate electrode 175 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0140] In the first region 11 and the second region 12, a second insulating intermediate layer 195 may be formed on the gate electrode pattern 180 and the second gate electrode 175. For example, the second insulating intermediate layer 195 may cover the gate electrode pattern 180 on the first insulating intermediate layer 190 in the first region 11 and cover the second gate electrode 175 on the first insulating intermediate layer 190 in the second region 12, and may extend into the bending region 50. That is, the second insulating intermediate layer 195 may be formed on the entire first insulating intermediate layer 190. For example, the second insulating intermediate layer 195 may sufficiently cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating intermediate layer 190, and may have a substantially flat upper surface without creating steps around the gate electrode pattern 180 and the second gate electrode 175. Alternatively, the second insulating intermediate layer 195 may cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating intermediate layer 190, and may be formed to have a substantially uniform thickness along the contours of the gate electrode pattern 180 and the second gate electrode 175. The second insulating intermediate layer 195 may be formed using a silicon compound, a metal oxide, etc. Alternatively, the second insulating intermediate layer 195 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0141] Referring to Figure 8 and Figure 9 , in the second region 12, a second active layer 135 may be formed on the second insulating intermediate layer 195. The second active layer 135 may be formed on a portion of the second insulating intermediate layer 195 under which the second gate electrode 175 is located. The second active layer 135 may be formed using a metal oxide semiconductor. In other words, the second active layer 135 may be a semiconductor oxide layer including a binary compound, a ternary compound, a quaternary compound, etc. containing In, Zn, Ga, Sn, Ti, Al, Hf, Zr, Mg, etc. For example, the second active layer 135 may include ZnO x , GaO x , TiO x , SnO x , InO x , IGO, IZO, ITO, GZO, ZMO, ZTO, ZnZr x O y , IGZO, IZTO, IGHO, TAZO, IGTO, etc.

[0142] The lower sacrificial layer pattern 510 may be formed to be spaced apart from the second active layer 135. The lower sacrificial layer pattern 510 and the second active layer 135 may be positioned at the same layer and may be formed simultaneously using the same material. For example, after forming a preliminary active layer over the entire second insulating interlayer 195, the lower sacrificial layer pattern 510 and the second active layer 135 may be formed to have the same thickness by selectively etching the preliminary active layer.

[0143] Referring Figure 10 , after forming the second active layer 135 and the lower sacrificial layer pattern 510, a first contact hole 212 exposing the source region of the first active layer 130 may be formed by removing a portion of each of the gate insulating layer 150, the first insulating interlayer 190, and the second insulating interlayer 195.

[0144] Referring Figure 11 and Figure 12 , the first source electrode 210 may be connected to the source region of the first active layer 130 through the first contact hole 212. The first source electrode 210 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first source electrode 210 may include Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, an aluminum-containing alloy, AlN x , a silver-containing alloy, WN x , a copper-containing alloy, a molybdenum-containing alloy, TiN x , CrN x , TaN x , SrRu x O y , ZnO x , ITO, SnO x , InO x , GaO x , IZO, etc. These may be used alone or in combination with each other.

[0145] In an embodiment, the first source electrode 210 may have a first thickness T1 and may be formed as a single layer. For example, the first source electrode 210 may be formed using Mo. In other embodiments, the first source electrode 210 may have a multi-layer structure including multiple layers.

[0146] In the second region 12, a second source electrode 215 and a second drain electrode 235 can be formed on the second insulating intermediate layer 195. The second source electrode 215 can cover a first side portion of the second active layer 135, and the second drain electrode 235 can cover a second side portion of the second active layer 135 that is different from the first side portion. In other words, the second source electrode 215 and the second drain electrode 235 can be formed in two side portions of the second active layer 135, and a part of the upper surface of the second active layer 135 can be exposed. Each of the second source electrode 215 and the second drain electrode 235 can be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other.

[0147] In an embodiment, each of the second source electrode 215 and the second drain electrode 235 can have a first thickness T1 and can be formed as a single layer. For example, each of the second source electrode 215 and the second drain electrode 235 can include Mo. In other embodiments, each of the second source electrode 215 and the second drain electrode 235 can have a multi-layer structure including multiple layers.

[0148] Thus, a second transistor 255 including the second active layer 135, the second gate electrode 175, the second source electrode 215, and the second drain electrode 235 can be formed.

[0149] An upper sacrificial layer pattern 520 can be formed on the lower sacrificial layer pattern 510. The upper sacrificial layer pattern 520, the first source electrode 210, and the second source electrode 215 and the second drain electrode 235 can be simultaneously formed on the same layer using the same material. For example, after forming a preliminary electrode layer on the second insulating intermediate layer 195, the second active layer 135, and the lower sacrificial layer pattern 510, the upper sacrificial layer pattern 520, the first source electrode 210, and the second source electrode 215 and the second drain electrode 235 can be formed to have the same thickness by selectively etching the preliminary electrode layer.

[0150] Thus, a sacrificial layer structure 500 including the lower sacrificial layer pattern 510 and the upper sacrificial layer pattern 520 can be formed.

[0151] In the first region 11 and the second region 12, a protective insulating layer 400 can be formed over the second insulating intermediate layer 195, the first source electrode 210, the sacrificial layer structure 500, and the second source electrode 215 and the second drain electrode 235. For example, the protective insulating layer 400 can cover the first source electrode 210 and the sacrificial layer structure 500 over the second insulating intermediate layer 195 in the first region 11 and cover the second source electrode 215 and the second drain electrode 235 over the second insulating intermediate layer 195 in the second region 12, and can extend into the bending region 50. That is to say, the protective insulating layer 400 can be formed over the entire second insulating intermediate layer 195. For example, the protective insulating layer 400 can sufficiently cover the first source electrode 210, the sacrificial layer structure 500, and the second source electrode 215 and the second drain electrode 235 over the second insulating intermediate layer 195, and can have a substantially flat upper surface without creating steps around the first source electrode 210, the sacrificial layer structure 500, and the second source electrode 215 and the second drain electrode 235. Alternatively, the protective insulating layer 400 can cover the first source electrode 210, the sacrificial layer structure 500, and the second source electrode 215 and the second drain electrode 235 over the second insulating intermediate layer 195, and can be formed to have a substantially uniform thickness along the contours of the first source electrode 210, the sacrificial layer structure 500, and the second source electrode 215 and the second drain electrode 235. The protective insulating layer 400 can be formed using a silicon compound, a metal oxide, etc. Alternatively, the protective insulating layer 400 can have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0152] Referring to Figure 13 and 14 , after forming the protective insulating layer 400, a second contact hole 232 exposing the drain region of the first active layer 130 can be formed by removing the gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, the sacrificial layer structure 500, and the protective insulating layer 400 that are positioned to overlap with the drain region of the first active layer 130, and a third contact hole 102 can be formed by removing the second barrier layer 114, the buffer layer 115, the gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, and the protective insulating layer 400 that are positioned to overlap with the bending region 50 of the substrate 110. The third contact hole 102 exposes the upper surface of the second organic layer 113 positioned in the bending region 50. An opening 501 can be formed in the sacrificial layer structure 500 in the process for forming the second contact hole 232, and a groove removing a part of the substrate 110 can be formed in the process for forming the third contact hole 102.

[0153] The gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, the sacrificial layer structure 500, and the protective insulating layer 400 positioned to overlap the drain region of the first active layer 130 can be removed to form a second contact hole 232, and the second barrier layer 114, the buffer layer 115, the gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, and the protective insulating layer 400 positioned to overlap the bent region 50 of the substrate 110 can be removed to form a third contact hole 102. The process for forming the second contact hole 232 and the process for forming the third contact hole 102 can be performed simultaneously. For example, after a photoresist is locally formed on the protective insulating layer 400 (e.g., the photoresist is formed in the remaining portions except for the portions where the second contact hole 232 and the third contact hole 102 are to be formed), a dry etching process can be performed on the entire protective insulating layer 400 by using carbon tetrafluoride (“CF 4 ”) gas, sulfur hexafluoride (“SF 6 ”) gas, and nitrogen trifluoride (NF 3 ) gas. Here, the height of the second contact hole 232 can be less than the height of the third contact hole 102. In other words, the thickness etched during the dry etching process can be different in the second contact hole 232 and the third contact hole 102. However, due to the sacrificial layer structure 500, the time for forming the second contact hole 232 will be relatively delayed, and the second contact hole 232 exposing the drain region of the first active layer 130 and the third contact hole 102 exposing the upper surface of the second organic layer 113 positioned in the bent region 50 can be formed simultaneously. Therefore, the drain region of the first active layer 130 will not be damaged. Additionally, since the second contact hole 232 and the third contact hole 102 are formed simultaneously, the manufacturing cost can be relatively reduced.

[0154] Referring to Figure 15 , the first drain electrode 230 can be connected to the drain region of the first active layer 130 through the second contact hole 232 and the opening 501 of the sacrificial layer structure 500. In an embodiment, the second contact hole 232 can pass through the opening 501 of the sacrificial layer structure 500. That is, the first drain electrode 230 can be in direct contact with the sacrificial layer structure 500 through the second contact hole 232. Additionally, the first drain electrode 230 can have a second thickness T2 greater than the first thickness T1 and can be formed in multiple layers. The first drain electrode 230 can be formed using metals, alloys of metals, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used alone or in combination with each other. In an embodiment, the first drain electrode 230 can have a stacked structure of Ti / Al / Ti.

[0155] Accordingly, a first transistor 250 including a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230 can be formed.

[0156] For example, in a conventional method of manufacturing an organic light emitting display device, after forming the second contact hole 232, a third contact hole 102 can be formed in the bending region 50. In this case, in the process of forming the third contact hole 102, all the photoresist formed on the first drain electrode 230 is removed, which may damage the first drain electrode 230.

[0157] In an embodiment, the second contact hole 232 and the third contact hole 102 are formed simultaneously so that the first drain electrode 230 is not damaged.

[0158] A first planarization layer 270 can be formed on the protective insulating layer 400 and the first drain electrode 230. The first planarization layer 270 can be formed over the entire protective insulating layer 400. For example, the first planarization layer 270 can be formed to a relatively thick thickness to sufficiently cover the first drain electrode 230, and in this case, the first planarization layer 270 can have a substantially flat upper surface. Additionally, a planarization process can be applied to the first planarization layer 270 to achieve the flat upper surface of the first planarization layer 270. In an embodiment, the first planarization layer 270 can fill the third contact hole 102 positioned in the bending region 50. In other words, the first planarization layer 270 can be in direct contact with the upper surface of the second organic layer 113 positioned in the bending region 50. Alternatively, the first planarization layer 270 can be formed only in the light emitting region 30 and may not be formed in the pad region 60. The first planarization layer 270 can be formed using an organic material. For example, the first planarization layer 270 can include photoresist, polyacrylic acid-based resin, polyimide-based resin, polyamide-based resin, silicone-based resin, acrylic-based resin, or epoxy-based resin, etc.

[0159] Referring to Figure 16 , a signal wiring 350 and a connection pattern 370 can be formed on the first planarization layer 270. Each of the signal wiring 350 and the connection pattern 370 can be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, each of the signal wiring 350 and the connection pattern 370 can be formed using the same material simultaneously and can have a stacked structure of Ti / Al / Ti.

[0160] A second planarization layer 275 may be formed on the first planarization layer 270, the signal wiring 350, and the connection pattern 370. The second planarization layer 275 may be formed over the entire first planarization layer 270. For example, the second planarization layer 275 may be formed to have a relatively thick thickness to sufficiently cover the signal wiring 350 and the connection pattern 370, and in this case, the second planarization layer 275 may have a substantially flat upper surface. Additionally, a planarization process may be applied to the second planarization layer 275 to achieve such a flat upper surface of the second planarization layer 275. Alternatively, the second planarization layer 275 may be formed only in the light-emitting region 30 and may not be formed in the pad region 60. The second planarization layer 275 may be formed using an organic material.

[0161] A lower electrode 290 may be formed on the second planarization layer 275. The lower electrode 290 may be connected to the connection pattern 370 through a contact hole formed by removing a portion of the second planarization layer 275. The lower electrode 290 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. Alternatively, the lower electrode 290 may have a multilayer structure including multiple layers.

[0162] A pixel defining layer 310 may be formed on a portion of the lower electrode 290 and the second planarization layer 275. The pixel defining layer 310 may cover both sides of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may be formed using an organic material. Alternatively, the pixel defining layer 310 may be formed only in the light-emitting region 30 and may not be formed in the pad region 60.

[0163] Referring to Figure 17 , a light-emitting layer 330 may be formed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of light-emitting materials for emitting light of different colors (i.e., red, green, blue, etc.) according to sub-pixels. Alternatively, the light-emitting layer 330 may be formed by laminating multiple light-emitting materials for emitting light of different colors such as red, green, or blue to emit white light as a whole. In this case, a color filter may be formed on the light-emitting layer 330. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin, a color photoresist, etc.

[0164] An upper electrode 340 may be formed on the pixel defining layer 310 and the light-emitting layer 330. The upper electrode 340 may cover the light-emitting layer 330 and the pixel defining layer 310, and may be completely formed on the light-emitting layer 330 and the pixel defining layer 310. The upper electrode 340 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers.

[0165] Therefore, a sub-pixel structure 200 including the lower electrode 290, the light-emitting layer 330, and the upper electrode 340 may be formed.

[0166] In the light-emitting region 30, a first thin film encapsulation layer 451 may be formed on the upper electrode 340. The first thin film encapsulation layer 451 may cover the upper electrode 340 in the light-emitting region 30, and may be formed to have a substantially uniform thickness along the contour of the upper electrode 340. The first thin film encapsulation layer 451 may prevent the sub-pixel structure 200 from being deteriorated due to the penetration of moisture, oxygen, etc. In addition, the first thin film encapsulation layer 451 may be used to protect the sub-pixel structure 200 from the influence of external shocks. The first thin film encapsulation layer 451 may be formed using a flexible inorganic material.

[0167] In the light-emitting region 30, a second thin film encapsulation layer 452 may be formed on the first thin film encapsulation layer 451. The second thin film encapsulation layer 452 may improve the flatness of the organic light-emitting display device and may protect the sub-pixel structure 200. The second thin film encapsulation layer 452 may be formed using a flexible organic material.

[0168] In the light-emitting region 30, a third thin film encapsulation layer 453 may be formed on the second thin film encapsulation layer 452. The third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 in the light-emitting region 30, and may be formed to have a substantially uniform thickness along the contour of the second thin film encapsulation layer 452. Together with the first thin film encapsulation layer 451, the third thin film encapsulation layer 453 may prevent the sub-pixel structure 200 from being deteriorated due to the penetration of moisture, oxygen, etc. In addition, the third thin film encapsulation layer 453 may be used together with the first thin film encapsulation layer 451 and the second thin film encapsulation layer 452 to protect the sub-pixel structure 200 from the influence of external shocks. The third thin film encapsulation layer 453 may be formed using a flexible inorganic material. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by laminating the first thin film encapsulation layer to the fifth thin film encapsulation layer, or a seven-layer structure formed by laminating the first thin film encapsulation layer to the seventh thin film encapsulation layer.

[0169] Therefore, a thin film encapsulation structure 450 including the first thin film encapsulation layer 451, the second thin film encapsulation layer 452, and the third thin film encapsulation layer 453 may be formed.

[0170] After forming the thin film encapsulation structure 450, the glass substrate 105 can be removed from the substrate 110. Thus, the organic light emitting display device 100 as shown in Figure 6 can be manufactured.

[0171] In the method of manufacturing an organic light emitting display device according to an embodiment of the present invention, the sacrificial layer structure 500 can relatively delay the time for forming the second contact hole 232, and can simultaneously form the second contact hole 232 exposing the drain region of the first active layer 130 and the third contact hole 102 exposing the upper surface of the second organic layer 113 positioned in the bending region 50. Thus, the drain region of the first active layer 130 will not be damaged. In addition, since the second contact hole 232 and the third contact hole 102 are formed simultaneously, the manufacturing cost can be relatively reduced, and the first drain electrode 230 will not be damaged.

[0172] Figure 18 is a cross-sectional view showing an organic light emitting display device according to an embodiment of the present invention, and Figure 19 is a cross-sectional view showing an example of Figure 18 the organic light emitting display device. Except for the sacrificial layer structure 1500, Figure 18 the organic light emitting display device 700 as shown in Figures 1 to 6 can have a configuration substantially the same as or similar to that of the organic light emitting display device 100 described with reference to Figure 18 . In Figures 1 to 6 , redundant descriptions of elements substantially the same as or similar to the elements described with reference to

[0173] Referring to Figure 18 , the organic light emitting display device 700 can include a substrate 110, a buffer layer 115, a first transistor 250, a second transistor 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating intermediate layer 190, a second insulating intermediate layer 195, a sacrificial layer structure 1500, a protective insulating layer 1400, a first planarization layer 270, a signal wiring 350, a connection pattern 370, a second planarization layer 275, a sub-pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, etc.

[0174] The sacrificial layer structure 1500 can be disposed on the second insulating intermediate layer 195 while being spaced apart from the first source electrode 210. In an embodiment, the sacrificial layer structure 1500 can overlap with the drain region of the first active layer 130, and the sacrificial layer structure 1500 can be positioned on the same layer (e.g., the second insulating intermediate layer 195) as the first source electrode 210, the second active layer 135, the second source electrode 215, and the second drain electrode 235.

[0175] In addition, the sacrificial layer structure 1500 may have an opening 1501 (refer to Figure 26 ). The drain region of the first active layer 130 may be exposed through the opening 1501. For example, the opening 1501 may be formed in the process of forming the second contact hole 232 such that the first drain electrode 230 is connected to the drain region of the first active layer 130. The sacrificial layer structure 1500 may have a hollow rectangular planar shape on the second insulating intermediate layer 195. Alternatively, the shape of the sacrificial layer structure 1500 may have a hollow triangular planar shape, a hollow rhombic planar shape, a hollow polygonal planar shape, a hollow circular planar shape, a hollow track-shaped planar shape, or a hollow elliptical planar shape.

[0176] In addition, the thickness of the sacrificial layer structure 1500 may be substantially the same as the thickness of the second active layer 135.

[0177] The protective insulating layer 1400 may be disposed on the second insulating intermediate layer 195, the first source electrode 210, the sacrificial layer structure 1500, the second source electrode 215, and the second drain electrode 235 in the first region 11 and the second region 12. In an embodiment, the protective insulating layer 1400 may cover the first source electrode 210, the sacrificial layer structure 1500, and the second source electrode 215 and the second drain electrode 235 on the second insulating intermediate layer 195 in the first region 11 and the second region 12, and extend into the bending region 50, and the protective insulating layer 1400 may have a fifth opening overlapping with the first opening to the fourth opening. Here, the first opening to the fifth opening may correspond to the third contact hole 102 formed on the substrate 110 in the bending region 50 (refer to Figure 25 ).

[0178] For example, the protective insulating layer 1400 may sufficiently cover the first source electrode 210, the sacrificial layer structure 1500, and the second source electrode 215 and the second drain electrode 235 on the second insulating intermediate layer 195, and may be disposed with a substantially uniform thickness along the contours of the first source electrode 210, the sacrificial layer structure 1500, the second source electrode 215, and the second drain electrode 235. The protective insulating layer 1400 may include a silicon compound, a metal oxide, etc. Alternatively, the protective insulating layer 1400 may have a multilayer structure having a plurality of insulating layers including different materials from each other.

[0179] In other embodiments, as Figure 19As shown, the sacrificial layer structure 1600 may be disposed on the second insulating intermediate layer 195 and spaced apart from the first source electrode 210 in the second direction D2. In an embodiment, the sacrificial layer structure 1600 may be positioned to overlap with the drain region of the first active layer 130 and may be located on the same layer (e.g., the second insulating intermediate layer 195) as the first source electrode 210, the second active layer 135, the second source electrode 215, and the second drain electrode 235.

[0180] Additionally, the sacrificial layer structure 1600 may have an opening. The drain region of the first active layer 130 may be exposed through the opening. For example, the opening may be formed in the process of forming the second contact hole 232 such that the first drain electrode 230 is connected to the drain region of the first active layer 130. The sacrificial layer structure 1600 may have a hollow rectangular planar shape on the second insulating intermediate layer 195. Alternatively, the shape of the sacrificial layer structure 1600 may have a hollow triangular planar shape, a hollow rhombic planar shape, a hollow polygonal planar shape, a hollow circular planar shape, a hollow track-shaped planar shape, or a hollow elliptical planar shape.

[0181] Furthermore, the thickness of the sacrificial layer structure 1600 may be substantially the same as the thickness of each of the first source electrode 210, the second source electrode 215, and the second drain electrode 235. That is, the thickness of the sacrificial layer structure 1600 may have a first thickness T1.

[0182] The protective insulating layer 1400 may be disposed on the second insulating intermediate layer 195, the first source electrode 210, the sacrificial layer structure 1600, the second source electrode 215, and the second drain electrode 235 in the first region 11 and the second region 12. In an embodiment, the protective insulating layer 1400 may cover the first source electrode 210, the sacrificial layer structure 1600, and the second source electrode 215 and the second drain electrode 235 on the second insulating intermediate layer 195 in the first region 11 and the second region 12, extend into the bending region 50, and the protective insulating layer 1400 may have a fifth opening overlapping with the first through fourth openings. Here, the first through fifth openings may correspond to the third contact hole 102 formed on the substrate 110 in the bending region 50.

[0183] For example, the protective insulating layer 1400 may sufficiently cover the first source electrode 210, the sacrificial layer structure 1600, and the second source electrode 215 and the second drain electrode 235 on the second insulating intermediate layer 195 and may be disposed to have a substantially uniform thickness along the contours of the first source electrode 210, the sacrificial layer structure 1600, and the second source electrode 215 and the second drain electrode 235.

[0184] Figure 20 、Figure 21 , Figure 23 , Figure 24 , Figure 25 , Figure 27 and Figure 28 are cross - sectional views showing a method of manufacturing an organic light - emitting display device according to an embodiment of the present invention. For example, Figure 20 , Figure 21 , Figure 23 , Figure 24 , Figure 25 , Figure 27 and Figure 28 are cross - sectional views showing a method of manufacturing an organic light - emitting display device, and Figure 22 is a plan view showing the sacrificial layer structure 1500 of Figure 18 . In addition, Figure 26 is a plan view showing the sacrificial layer structure 1500 having an opening 1501 formed therein where Figure 25 is formed.

[0185] Referring to Figure 7 and Figure 20 , after forming a buffer layer 115, a first active layer 130, a gate insulating layer 150, a first gate electrode 170, a first insulating intermediate layer 190, a gate electrode pattern 180, a second gate electrode 175, and a second insulating intermediate layer 195 on a substrate 110 (refer to Figure 7 ), a first contact hole 212 exposing the source region of the first active layer 130 is formed by removing a part of each of the gate insulating layer 150, the first insulating intermediate layer 190, and the second insulating intermediate layer 195 that is positioned to overlap with the source region of the first active layer 130, and a preliminary third contact hole 103 exposing the upper surface of the buffer layer 115 positioned in the bent region 50 of the substrate 110 is formed by removing the gate insulating layer 150, the first insulating intermediate layer 190, and the second insulating intermediate layer 195 that are positioned to overlap with the bent region 50 of the substrate 110.

[0186] Referring to Figure 21 and Figure 22 , a second active layer 135 may be formed on the second insulating intermediate layer 195 in a second region 12. The second active layer 135 may be formed on a part of the second insulating intermediate layer 195 under which the second gate electrode 175 is positioned. The second active layer 135 may be formed using a metal oxide semiconductor.

[0187] The sacrificial layer structure 1500 may be formed while being spaced apart from the second active layer 135. The sacrificial layer structure 1500 and the second active layer 135 may be positioned at the same layer and may be formed simultaneously using the same material. For example, after forming a preliminary active layer over the entire second insulating intermediate layer 195, the sacrificial layer structure 1500 and the second active layer 135 may be formed to have the same thickness by selectively etching the preliminary active layer.

[0188] Referring Figure 23 , the first source electrode 210 may be connected to the source region of the first active layer 130 through the first contact hole 212. The first source electrode 210 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the first source electrode 210 may have a first thickness T1 and may be formed as a single layer. For example, the first source electrode 210 may be formed using Mo. In other embodiments, the first source electrode 210 may have a multi-layer structure including a plurality of layers.

[0189] In the second region 12, a second source electrode 215 and a second drain electrode 235 may be formed over the second insulating intermediate layer 195. The second source electrode 215 may cover the first side portion of the second active layer 135, and the second drain electrode 235 may cover the second side portion of the second active layer 135 different from the first side portion. In other words, the second source electrode 215 and the second drain electrode 235 may be formed at two side portions of the second active layer 135 and may expose a part of the upper surface of the second active layer 135. Each of the second source electrode 215 and the second drain electrode 235 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, each of the second source electrode 215 and the second drain electrode 235 may have a first thickness T1 and may be formed as a single layer. For example, each of the second source electrode 215 and the second drain electrode 235 may include Mo. In other embodiments, each of the second source electrode 215 and the second drain electrode 235 may have a multi-layer structure including a plurality of layers.

[0190] The first source electrode 210 and the second source electrode 215 and the second drain electrode 235 may be positioned in the same layer and may be formed simultaneously using the same material. For example, after completely forming a preliminary electrode layer over the second insulating intermediate layer 195, the second active layer 135, and the sacrificial layer structure 1500, the first source electrode 210 and the second source electrode 215 and the second drain electrode 235 may be formed to have the same thickness by selectively etching the preliminary electrode layer.

[0191] Accordingly, a second transistor 255 including a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235 can be formed.

[0192] Referring Figure 24 , in the first region 11 and the second region 12, a protective insulating layer 1400 can be disposed on the second insulating intermediate layer 195, the first source electrode 210, the sacrificial layer structure 1500, the second source electrode 215, and the second drain electrode 235. For example, the protective insulating layer 1400 can cover the first source electrode 210, the sacrificial layer structure 1500, the second source electrode 215, and the second drain electrode 235 on the second insulating intermediate layer 195 in the first region 11 and the second region 12, and extend into the bending region 50, and the protective insulating layer 1400 can fill the preliminary third contact hole 103 located in the bending region 50 of the substrate 110. That is, the protective insulating layer 1400 can be formed over the entire substrate 110.

[0193] For example, the protective insulating layer 1400 can sufficiently cover the first source electrode 210, the sacrificial layer structure 1500, the second source electrode 215, and the second drain electrode 235 on the second insulating intermediate layer 195, and can be formed to have a substantially uniform thickness along the contours of the first source electrode 210, the sacrificial layer structure 1500, the second source electrode 215, and the second drain electrode 235. The protective insulating layer 1400 can be formed using a silicon compound, a metal oxide, etc. Alternatively, the protective insulating layer 1400 can have a multilayer structure having a plurality of insulating layers including different materials from each other.

[0194] Referring Figure 25 and Figure 26 , after forming the protective insulating layer 1400, a second contact hole 232 exposing the drain region of the first active layer 130 can be formed by removing the gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, the sacrificial layer structure 1500, and the protective insulating layer 1400 positioned to overlap with the drain region of the first active layer 130, and a third contact hole 102 exposing the upper surface of the second organic layer 113 positioned in the bending region 50 can be formed by removing the second barrier layer 114, the buffer layer 115, and the protective insulating layer 1400 positioned to overlap with the bending region 50 of the substrate 110. An opening 501 can be formed in the sacrificial layer structure 1500 in the process for forming the second contact hole 232, and a groove removing a part of the substrate 110 can be formed in the process for forming the third contact hole 102.

[0195] The gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, the sacrificial layer structure 1500, and the protective insulating layer 1400 that are positioned to overlap with the drain region of the first active layer 130 may be removed to form a second contact hole 232, and the second barrier layer 114, the buffer layer 115, and the protective insulating layer 1400 that are positioned to overlap with the bent region 50 on the substrate 110 may be removed to form a third contact hole 102. The process for forming the second contact hole 232 and the process for forming the third contact hole 102 may be performed simultaneously. For example, after a photoresist is locally formed on the protective insulating layer 1400, a dry etching process may be performed on the entire protective insulating layer 1400 by using CF 4 gas, SF 6 gas, and NF 3 gas. Here, the height of the second contact hole 232 may be different from the height of the third contact hole 102. In other words, the thickness etched during the dry etching process may be different in the second contact hole 232 and the third contact hole 102. However, due to the sacrificial layer structure 1500, the time for forming the second contact hole 232 may be relatively delayed, and the second contact hole 232 exposing the drain region of the first active layer 130 and the third contact hole 102 exposing the upper surface of the second organic layer 113 positioned in the bent region 50 may be formed simultaneously. Therefore, the drain region of the first active layer 130 is not damaged. In addition, since the second contact hole 232 and the third contact hole 102 are formed simultaneously, the manufacturing cost may be relatively reduced.

[0196] Compared with the dry etching process shown in Figure 13 , although in Figure 25 , the thickness of the insulating layer to be dry-etched in the bent region 50 of the substrate 110 is relatively reduced, when each of the buffer layer 115 and the second barrier layer 114 has a relatively low etching ratio, the sacrificial layer structure 1500 having a relatively reduced thickness may be formed on the second insulating intermediate layer 195.

[0197] Refer to Figure 27, the first drain electrode 230 can be connected to the drain region of the first active layer 130 through the second contact hole 232 and the opening 1501 of the sacrificial layer structure 1500. In an embodiment, the second contact hole 232 can pass through the opening 1501 of the sacrificial layer structure 1500. That is to say, the first drain electrode 230 can be in direct contact with the sacrificial layer structure 1500 through the second contact hole 232. In addition, the first drain electrode 230 can have a second thickness T2 greater than the first thickness T1 and can be formed of multiple layers. The first drain electrode 230 can be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, the first drain electrode 230 can have a stacked structure of Ti / Al / Ti.

[0198] Therefore, a first transistor 250 including the first active layer 130, the first gate electrode 170, the first source electrode 210, and the first drain electrode 230 can be formed.

[0199] A first planarization layer 270 can be formed on the protective insulating layer 1400 and the first drain electrode 230. The first planarization layer 270 can be formed over the entire protective insulating layer 1400. For example, the first planarization layer 270 can be formed to have a relatively thick thickness to sufficiently cover the first drain electrode 230, and in this case, the first planarization layer 270 can have a substantially flat upper surface. In addition, a planarization process can be applied to the first planarization layer 270 to achieve a flat upper surface of the first planarization layer 270. In an embodiment, the first planarization layer 270 can fill the third contact hole 102 positioned in the curved region 50. In other words, the first planarization layer 270 can be in direct contact with the upper surface of the second organic layer 113 positioned in the curved region 50. Alternatively, the first planarization layer 270 can be formed only in the light-emitting region 30 and can not be formed in the pad region 60. The first planarization layer 270 can be formed using an organic material.

[0200] Referring to Figure 28 , a signal wiring 350 and a connection pattern 370 can be formed on the first planarization layer 270. Each of the signal wiring 350 and the connection pattern 370 can be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, each of the signal wiring 350 and the connection pattern 370 can be formed using the same material simultaneously and can have a stacked structure of Ti / Al / Ti.

[0201] A second planarization layer 275 may be formed over the first planarization layer 270, the signal wiring 350, and the connection pattern 370. The second planarization layer 275 may be formed over the entire first planarization layer 270. For example, the second planarization layer 275 may be formed to have a relatively thick thickness to sufficiently cover the signal wiring 350 and the connection pattern 370, and in this case, the second planarization layer 275 may have a substantially flat upper surface. Additionally, a planarization process may be applied to the second planarization layer 275 to achieve such a flat upper surface of the second planarization layer 275. Alternatively, the second planarization layer 275 may be formed only in the light-emitting region 30 and may not be formed in the pad region 60. The second planarization layer 275 may be formed using an organic material.

[0202] A lower electrode 290 may be formed over the second planarization layer 275. The lower electrode 290 may be connected to the connection pattern 370 through a contact hole formed by removing a portion of the second planarization layer 275. The lower electrode 290 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. Alternatively, the lower electrode 290 may have a multi-layer structure including a plurality of layers.

[0203] A pixel defining layer 310 may be formed over a portion of the lower electrode 290 and the second planarization layer 275. The pixel defining layer 310 may cover two sides of the lower electrode 290 and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may be formed using an organic material. Alternatively, the pixel defining layer 310 may be formed only in the light-emitting region 30 and may not be formed in the pad region 60.

[0204] An emission layer 330 may be formed over the lower electrode 290 exposed by the pixel defining layer 310. The emission layer 330 may be formed using at least one of light-emitting materials for emitting light of different colors (i.e., red light, green light, blue light, etc.) according to sub-pixels. Alternatively, the emission layer 330 may be formed by stacking a plurality of light-emitting materials for emitting light of different colors such as red light, green light, or blue light to emit white light as a whole. In this case, a color filter may be formed over the emission layer 330.

[0205] An upper electrode 340 may be formed over the pixel defining layer 310 and the emission layer 330. The upper electrode 340 may cover the emission layer 330 and the pixel defining layer 310 and may be completely formed over the emission layer 330 and the pixel defining layer 310. The upper electrode 340 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multi-layer structure including a plurality of layers.

[0206] Therefore, a sub-pixel structure 200 including a lower electrode 290, a light-emitting layer 330, and an upper electrode 340 can be formed.

[0207] In the light-emitting region 30, a first thin-film encapsulation layer 451 can be formed on the upper electrode 340. The first thin-film encapsulation layer 451 can cover the upper electrode 340 in the light-emitting region 30 and can be formed to have a substantially uniform thickness along the contour of the upper electrode 340. The first thin-film encapsulation layer 451 can be formed using a flexible inorganic material.

[0208] In the light-emitting region 30, a second thin-film encapsulation layer 452 can be formed on the first thin-film encapsulation layer 451. The second thin-film encapsulation layer 452 can be formed using a flexible organic material.

[0209] In the light-emitting region 30, a third thin-film encapsulation layer 453 can be formed on the second thin-film encapsulation layer 452. The third thin-film encapsulation layer 453 can cover the second thin-film encapsulation layer 452 in the light-emitting region 30 and can be formed to have a substantially uniform thickness along the contour of the second thin-film encapsulation layer 452. The third thin-film encapsulation layer 453 can be formed using a flexible inorganic material. Alternatively, the thin-film encapsulation structure 450 can have a five-layer structure formed by laminating the first thin-film encapsulation layer to the fifth thin-film encapsulation layer, or a seven-layer structure formed by laminating the first thin-film encapsulation layer to the seventh thin-film encapsulation layer.

[0210] Therefore, a thin-film encapsulation structure 450 including the first thin-film encapsulation layer 451, the second thin-film encapsulation layer 452, and the third thin-film encapsulation layer 453 can be formed.

[0211] After the thin-film encapsulation structure 450 is formed, the glass substrate 105 can be removed from the substrate 110. Therefore, the organic light-emitting display device 700 shown in Figure 18 can be manufactured.

[0212] Figure 29 , Figure 30 and Figure 31 are cross-sectional views showing a method of manufacturing an organic light-emitting display device according to an embodiment of the present invention.

[0213] Referring to Figure 7 , Figure 20 and Figure 29 , a buffer layer 115, a first active layer 130, a gate insulating layer 150, a first gate electrode 170, a first insulating intermediate layer 190, a gate electrode pattern 180, a second gate electrode 175, and a second insulating intermediate layer 195 are formed on the substrate 110 (refer to Figure 7)After that, a first contact hole 212 exposing the source region of the first active layer 130 is formed by removing a part of each of the gate insulating layer 150, the first insulating intermediate layer 190, and the second insulating intermediate layer 195 positioned to overlap with the source region of the first active layer 130, and a preliminary third contact hole 103 exposing the upper surface of the buffer layer 115 positioned in the bent region 50 of the substrate 110 can be formed by removing the gate insulating layer 150, the first insulating intermediate layer 190, and the second insulating intermediate layer 195 positioned to overlap with the bent region 50 of the substrate 110 (refer to Figure 20 ).

[0214] After the first contact hole 212 and the preliminary third contact hole 103 are formed, the second active layer 135 can be formed on the second insulating intermediate layer 195 in the second region 12. The second active layer 135 can be formed on a portion of the second insulating intermediate layer 195 under which the second gate electrode 175 is positioned. The second active layer 135 can be formed using a metal oxide semiconductor.

[0215] A sacrificial layer structure 1700 can be formed in the preliminary third contact hole 103 formed in the bent region 50 of the substrate 110. The sacrificial layer structure 1700 and the second active layer 135 can be formed of the same material simultaneously. For example, after a preliminary active layer is formed over the entire substrate 110, the sacrificial layer structure 1700 and the second active layer 135 can be formed to have the same thickness by selectively etching the preliminary active layer.

[0216] Refer to Figure 30 , the first source electrode 210 can be connected to the source region of the first active layer 130 through the first contact hole 212. The first source electrode 210 can be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, the first source electrode 210 can have a first thickness T1 and can be formed as a single layer. For example, the first source electrode 210 can be formed using Mo. In other embodiments, the first source electrode 210 can have a multi-layer structure including a plurality of layers.

[0217] In the second region 12, a second source electrode 215 and a second drain electrode 235 can be formed on the second insulating intermediate layer 195. The second source electrode 215 can cover the first side portion of the second active layer 135, and the second drain electrode 235 can cover the second side portion of the second active layer 135 that is different from the first side portion. In other words, the second source electrode 215 and the second drain electrode 235 can be formed in two side portions of the second active layer 135, and a part of the upper surface of the second active layer 135 can be exposed. Each of the second source electrode 215 and the second drain electrode 235 can be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, each of the second source electrode 215 and the second drain electrode 235 can have a first thickness T1 and can be formed as a single layer. For example, each of the second source electrode 215 and the second drain electrode 235 can include Mo. In other embodiments, each of the second source electrode 215 and the second drain electrode 235 can have a multi-layer structure including a plurality of layers.

[0218] The first source electrode 210, the second source electrode 215, and the second drain electrode 235 can be located in the same layer and can be formed simultaneously using the same material. For example, after a preliminary electrode layer is completely formed on the second insulating intermediate layer 195, the second active layer 135, and the sacrificial layer structure 1700, the first source electrode 210, the second source electrode 215, and the second drain electrode 235 can be formed to have the same thickness by selectively etching the preliminary electrode layer.

[0219] Therefore, a second transistor 255 including the second active layer 135, the second gate electrode 175, the second source electrode 215, and the second drain electrode 235 can be formed.

[0220] In the first region 11 and the second region 12, a protective insulating layer 2400 can be provided on the second insulating intermediate layer 195, the first source electrode 210, the second source electrode 215, and the second drain electrode 235. For example, the protective insulating layer 2400 can cover the first source electrode 210, the second source electrode 215, and the second drain electrode 235 on the second insulating intermediate layer 195 in the first region 11 and the second region 12, and extend into the bending region 50, and the protective insulating layer 2400 can cover the sacrificial layer structure 1700 located in the bending region 50 of the substrate 110 and fill the preliminary third contact hole 103 located in the bending region 50 of the substrate 110. That is to say, the protective insulating layer 2400 can be formed on the entire substrate 110.

[0221] For example, the protective insulating layer 2400 may sufficiently cover the first source electrode 210, the second source electrode 215, and the second drain electrode 235, as well as the sacrificial layer structure 1700 on the second insulating intermediate layer 195, and may be formed to have a substantially uniform thickness along the contours of the first source electrode 210, the second source electrode 215, the second drain electrode 235, and the sacrificial layer structure 1700. The protective insulating layer 2400 may be formed using a silicon compound, a metal oxide, etc. Alternatively, the protective insulating layer 2400 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0222] In an embodiment, compared with Figure 24 the protective insulating layer 1400 of Figure 30 the protective insulating layer 2400 may have a relatively thin thickness.

[0223] Referring to Figure 31 , after forming the protective insulating layer 2400, the second contact hole 232 exposing the drain region of the first active layer 130 may be formed by removing the gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, and the protective insulating layer 2400 positioned to overlap the drain region of the first active layer 130, and the third contact hole 102 exposing the upper surface of the second organic layer 113 positioned in the bent region 50 may be formed by removing the second barrier layer 114, the buffer layer 115, the sacrificial layer structure 1700, and the protective insulating layer 2400 positioned to overlap the bent region 50 of the substrate 110. The sacrificial layer structure 1700 may be removed in the process for forming the third contact hole 102, and a groove removing a part of the substrate 110 may be formed. Alternatively, the sacrificial layer structure 1700 is not completely removed, and a part of the sacrificial layer structure 1700 may remain in the third contact hole 102.

[0224] The gate insulating layer 150, the first insulating intermediate layer 190, the second insulating intermediate layer 195, and the protective insulating layer 2400 positioned to overlap with the drain region of the first active layer 130 may be removed to form a second contact hole 232, and the second barrier layer 114, the buffer layer 115, the sacrificial layer structure 1700, and the protective insulating layer 2400 positioned to overlap with the bending region 50 on the substrate 110 may be removed to form a third contact hole 102. The process for forming the second contact hole 232 and the process for forming the third contact hole 102 may be performed simultaneously. Here, the height of the second contact hole 232 may be different from the height of the third contact hole 102. In other words, the thickness etched during the dry etching process may be different in the second contact hole 232 and the third contact hole 102. However, due to the sacrificial layer structure 1700, the time for forming the third contact hole 102 may be relatively delayed, and the second contact hole 232 exposing the drain region of the first active layer 130 and the third contact hole 102 exposing the upper surface of the second organic layer 113 positioned in the bending region 50 may be formed simultaneously. Therefore, the substrate 110 positioned in the bending region 50 will not be over-etched. Additionally, since the second contact hole 232 and the third contact hole 102 are formed simultaneously, the manufacturing cost may be relatively reduced.

[0225] Compared with Figure 25 the dry etching process shown in Figure 31 since the thickness of the protective insulating layer 2400 is relatively reduced in

[0226] Figure 32 FIG. is a cross-sectional view of an organic light-emitting display device according to an embodiment of the present invention. Except for the sacrificial layer structure 1800, Figure 32 the organic light-emitting display device 800 shown in Figures 1 to 6 may have a configuration substantially the same as or similar to that of the organic light-emitting display device 100 described with reference to Figure 32 In Figures 1 to 6 redundant descriptions of elements substantially the same as or similar to the elements described with reference to

[0227] Referring to Figure 32, the organic light-emitting display device 800 may include a substrate 110, a buffer layer 115, a first transistor 250, a second transistor 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating intermediate layer 190, a second insulating intermediate layer 195, a sacrificial layer structure 1800, a protective insulating layer 400, a first planarization layer 270, signal wirings 350, connection patterns 370, a second planarization layer 275, a sub-pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, etc. Here, the sacrificial layer structure 1800 may include a lower sacrificial layer pattern 1510 and an upper sacrificial layer pattern 1520.

[0228] The sacrificial layer structure 1800 may be disposed on the second insulating intermediate layer 195 while being spaced apart from the first source electrode 210. In an embodiment, the sacrificial layer structure 1800 may overlap with the drain region of the first active layer 130, and the sacrificial layer structure 1800 may be positioned at the same layer (e.g., the second insulating intermediate layer 195) as the first source electrode 210, the second active layer 135, the second source electrode 215, and the second drain electrode 235.

[0229] In addition, the sacrificial layer structure 1800 may have an opening. The drain region of the first active layer 130 may be exposed through the opening. For example, the opening may be formed in a process for forming the second contact hole 232 such that the first drain electrode 230 is connected to the drain region of the first active layer 130. The sacrificial layer structure 1800 may have a hollow rectangular planar shape on the second insulating intermediate layer 195. Alternatively, the shape of the sacrificial layer structure 1800 may have a hollow triangular planar shape, a hollow rhombus planar shape, a hollow polygonal planar shape, a hollow circular planar shape, a hollow track-shaped planar shape, or a hollow elliptical planar shape.

[0230] As described above, the sacrificial layer structure 1800 may be positioned at the same layer as the second active layer 135 on the second insulating intermediate layer 195, and may include a lower sacrificial layer pattern 1510 having a first opening and an upper sacrificial layer pattern 1520 disposed on the lower sacrificial layer pattern 1510 and having a second opening overlapping with the first opening. Here, the first opening and the second opening may correspond to the opening of the sacrificial layer structure 1800.

[0231] In addition, the thickness of the lower sacrificial layer pattern 1510 may be substantially the same as the thickness of the second active layer 135, and the thickness of the upper sacrificial layer pattern 1520 may be less than a first thickness T1 of each of the first source electrode 210, the second source electrode 215, and the second drain electrode 215. For example, in the method of manufacturing the organic light-emitting display device 800, after the preliminary electrode layer is completely formed on the second insulating intermediate layer 195, the second active layer 135, and the lower sacrificial layer pattern 1510, the preliminary electrode layer may be selectively etched using a patterned photoresist, and the upper sacrificial layer pattern 1520, the first source electrode 210, and the second source electrode 215 and the second drain electrode 235 may be formed to have different thicknesses. In other words, when the etching process is performed after forming a photoresist having a relatively small thickness on the portion where the upper sacrificial layer pattern 1520 is to be formed, the lower sacrificial layer pattern 1510 may be formed to be less than the first thickness T1. That is, even if the thicknesses of the buffer layer 115 and the second barrier layer 114 are changed and the formation time of the third contact hole 102 is changed, the formation time of the second contact hole 232 can be easily adjusted by adjusting the thickness of the lower sacrificial layer pattern 1510. Accordingly, the second contact hole 232 and the third contact hole 102 may be formed simultaneously without damaging the drain region of the first active layer 130.

[0232] The foregoing is illustrative of the embodiments and is not to be construed as limiting the embodiments. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it will be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the particular embodiments disclosed, and that modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

[0233] Industrial Applicability

[0234] The present invention may be applied to various electronic devices including organic light-emitting display devices. For example, the present invention may be applied to many electronic devices such as vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, and the like.

[0235] Explanation of Reference Signs

[0236] 10: Display area 11: First area

[0237] 12: Second area 20: Sub-pixel circuit area

[0238] 30: Light-emitting region 40: Peripheral region

[0239] 50: Bending region 60: Pad region

[0240] 70: Pad electrode region

[0241] 100, 700, 800: Organic light-emitting display device

[0242] 101: External device 110: Substrate

[0243] 102: Third contact hole 103: Preliminary third contact hole

[0244] 111: First organic layer 112: First barrier layer

[0245] 113: Second organic layer 114: Second barrier layer

[0246] 115: Buffer layer 130: First active layer

[0247] 135: Second active layer 150: Gate insulating layer

[0248] 170: First gate electrode 175: Second gate electrode

[0249] 180: Gate electrode pattern 190: First insulating intermediate layer

[0250] 195: Second insulating intermediate layer 200: Sub-pixel structure

[0251] 210: First source electrode 212: First contact hole

[0252] 232: Second contact hole 215: Second source electrode

[0253] 230: First drain electrode 235: Second drain electrode

[0254] 250: First transistor 255: Second transistor

[0255] 270: First planarization layer 275: Second planarization layer

[0256] 290: Lower electrode 310: Pixel defining layer

[0257] 330: Light-emitting layer 340: Upper electrode

[0258] 350: Signal wiring 370: Connection pattern

[0259] 400, 1400, 2400: Protective insulating layer 450: Thin film encapsulation structure

[0260] 451: First thin film encapsulation layer 452: Second thin film encapsulation layer

[0261] 453: Third thin film encapsulation layer 470: Pad electrode

[0262] 500, 1500, 1600, 1700: Sacrificial layer structure

[0263] 501, 1501: Opening 510, 1510: Lower sacrificial pattern

[0264] 520, 1520: Upper sacrificial pattern

Claims

1. An organic light emitting display device, comprising: a substrate having a light emitting region including a first region and a second region, a peripheral region surrounding the light emitting region, and a curved region positioned in one side of the peripheral region; a first active layer having a source region and a drain region disposed on the substrate in the first region; a first gate electrode disposed on the first active layer; a first source electrode disposed on the first gate electrode, the first source electrode being connected to the source region; a sacrificial layer structure disposed to be spaced apart from the first source electrode, the sacrificial layer structure having an opening; a protective insulating layer disposed on the first source electrode and the sacrificial layer structure; a first drain electrode disposed on the protective insulating layer, the first drain electrode being connected to the drain region through a second contact hole including the opening, the first drain electrode together with the first active layer, the first gate electrode, and the first source electrode being defined as a first transistor; and a sub-pixel structure disposed on the first transistor, wherein a groove exposing the curved region of the substrate is formed without creating a step, and wherein the groove and the second contact hole are formed from the same layer toward the substrate such that a height of the second contact hole is less than a height of the groove.

2. The organic light emitting display device according to claim 1, wherein, the sacrificial layer structure is positioned to overlap with the drain region, and the sacrificial layer structure and the first source electrode are positioned at the same layer.

3. The organic light emitting display device according to claim 1, wherein, the first drain electrode is in direct contact with the sacrificial layer structure through the opening.

4. The organic light emitting display device according to claim 1, wherein, a thickness of the sacrificial layer structure is the same as a thickness of the first source electrode.

5. The organic light emitting display device according to claim 1, further comprising: a second gate electrode disposed on the substrate in the second region; a second active layer disposed on the second gate electrode; and a second source electrode and a second drain electrode disposed in two side portions of the second active layer, the second source electrode and the second drain electrode together with the second gate electrode and the second active layer being defined as a second transistor.

6. The organic light emitting display device according to claim 5, wherein, the sacrificial layer structure includes: a lower sacrificial layer pattern positioned at the same layer as the second active layer, the lower sacrificial layer pattern having a first opening; and an upper sacrificial layer pattern disposed on the lower sacrificial layer pattern, the upper sacrificial layer pattern having a second opening overlapping with the first opening, and Wherein, the first opening and the second opening correspond to the opening of the sacrificial layer structure.

7. The organic light emitting display device according to claim 6, wherein, the thickness of the lower sacrificial layer pattern is the same as the thickness of the second active layer, and the thickness of the upper sacrificial layer pattern is the same as the thickness of each of the first source electrode, the second source electrode, and the second drain electrode.

8. The organic light emitting display device according to claim 6, wherein, the thickness of the lower sacrificial layer pattern is the same as the thickness of the second active layer, and the thickness of the upper sacrificial layer pattern is less than the thickness of each of the first source electrode, the second source electrode, and the second drain electrode.

9. The organic light emitting display device according to claim 5, wherein, the sacrificial layer structure and the second active layer are located on the same layer, and the thickness of the sacrificial layer structure is the same as the thickness of the second active layer.

10. The organic light emitting display device according to claim 5, wherein, each of the first source electrode, the second source electrode, and the second drain electrode has a first thickness, and the first drain electrode has a second thickness, and wherein the second thickness is greater than the first thickness.

11. The organic light emitting display device according to claim 5, wherein, the first transistor has a top-gate structure, and the first active layer includes a silicon-based semiconductor, and wherein the second transistor has a bottom-gate structure, and the second active layer includes a metal-oxide-based semiconductor.

12. The organic light emitting display device according to claim 5, further comprising: a gate electrode pattern disposed on the first gate electrode, wherein the gate electrode pattern and the second gate electrode are located on the same layer.

13. A method of manufacturing an organic light emitting display device, the method comprising: forming a substrate having a light emitting region including a first region and a second region, a peripheral region surrounding the light emitting region, and a bending region located on one side of the peripheral region; forming a first active layer having a source region and a drain region on the substrate in the first region; forming a first gate electrode on the first active layer; forming a first contact hole exposing the source region; forming a first source electrode connected to the source region through the first contact hole; forming a sacrificial layer structure overlapping the drain region on the first active layer; forming a protective insulating layer on the first source electrode and the sacrificial layer structure; simultaneously forming i) a second contact hole exposing the drain region of the first active layer such that an opening is formed in the sacrificial layer structure and ii) a groove exposing the bending region of the substrate; forming a first drain electrode connected to the drain region through the second contact hole and the opening; and forming a sub-pixel structure on the first drain electrode.

14. The method according to claim 13, wherein, the height of the second contact hole is less than the height of the groove.

15. The method according to claim 13, further comprising: forming a buffer layer on the substrate; forming a gate insulating layer on the buffer layer; forming a first insulating intermediate layer on the gate insulating layer; and forming a second insulating intermediate layer on the first insulating intermediate layer, wherein the protective insulating layer is formed on the second insulating intermediate layer, and the sacrificial layer structure is formed between the second insulating intermediate layer and the protective insulating layer.

16. The method according to claim 15, wherein, the second contact hole is formed by removing the gate insulating layer, the first insulating intermediate layer, the second insulating intermediate layer, the sacrificial layer structure, and the protective insulating layer that are positioned to overlap the drain region of the first active layer.

17. The method according to claim 15, wherein, the groove is formed by removing the gate insulating layer, the first insulating intermediate layer, the second insulating intermediate layer, and the protective insulating layer that are positioned to overlap the bent region of the substrate.

18. The method according to claim 17, wherein, when forming the groove, a part of the substrate is removed.

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