Method, device and system for data mapping in wireless communication

Abstract

A method, apparatus, and system for data mapping in wireless communication are disclosed. In one embodiment, a method performed by a wireless communication module is disclosed. The method includes: scheduling data of at least one data radio bearer (DRB) at a first layer; and performing mapping between multiple quality of service (QoS) flows and at least one DRB at a mapping layer, the mapping layer being the first layer or a second layer immediately above the first layer.

Description

Technical Field

[0001] The present disclosure relates generally to wireless communications, and more particularly to methods, apparatus, and systems for data mapping in wireless communications. Background Art

[0002] With the rapid development of technologies such as various industrial chains, the Internet of Things, and artificial intelligence, higher requirements are placed on the new generation of wireless mobile communication technology. The fourth generation (4G) wireless mobile communication technology cannot meet the requirements of large capacity, high speed, and multiple connections. In this context, major communication equipment manufacturers and operators are actively investing in the development of the fifth generation (5G) new radio (NR) wireless communication standard.

[0003] In the 5G NR system, the protocol layer is divided into two parts: the central unit (CU) and the distributed unit (DU). The CU and DU are connected through the F1 interface. The CU side includes the service data adaptation protocol (SDAP) layer and the packet data convergence protocol (PDCP) layer, and the DU side includes the radio link control (RLC) layer, the medium access control (MAC) layer and the physical (PHY) layer. Layer 2 (L2) of the user plane of the NR system includes the SDAP layer, the PDCP layer, the RLC layer and the MAC layer. The SDAP layer is responsible for mapping and demapping the Quality of Service (QoS) flow (which is the data sent by the core network to the access network) to the data radio bearer (DRB) and marking the QoS flow identification (QFI) for each uplink or downlink QoS flow packet. The PDCP layer provides header compression and decompression, encryption and decryption, integrity protection and verification, and sequence maintenance functions. The RLC layer provides segmentation, reassembly, and automatic repeat request (ARQ) services. The MAC layer provides mapping, multiplexing, demultiplexing, scheduling, priority processing, hybrid ARQ (HARQ), cascading, packing, and unpacking services from logical channels to transport channels. This design of the L2 QoS architecture in the NR system is inefficient and difficult to meet QoS performance requirements.

[0004] Therefore, existing systems and methods for data mapping and layer design in wireless communications are not entirely satisfactory. Summary of the invention

[0005] The exemplary embodiments disclosed herein are directed to solving problems related to one or more of the problems presented in the prior art, as well as providing additional features that will become apparent when referring to the following detailed description in conjunction with the accompanying drawings. According to various embodiments, exemplary systems, methods, devices, and computer program products are disclosed herein. However, it should be understood that these embodiments are presented by way of example and not limitation, and it will be apparent to those of ordinary skill in the art who have read this disclosure that various modifications may be made to the disclosed embodiments while remaining within the scope of this disclosure.

[0006] In one embodiment, a method performed by a wireless communication module is disclosed. The method includes: scheduling data of at least one data radio bearer (DRB) at a first layer; and performing mapping between multiple quality of service (QoS) flows and at least one DRB at a mapping layer, the mapping layer being the first layer or a second layer immediately above the first layer.

[0007] In another embodiment, a method performed by a wireless communication device is disclosed. The method includes: obtaining scheduling information of at least one data radio bearer (DRB) at a first layer; and performing mapping between multiple quality of service (QoS) flows and at least one DRB at a mapping layer, the mapping layer being the first layer or a second layer immediately above the first layer.

[0008] In various embodiments, a wireless communication module configured to implement the disclosed methods in some embodiments is disclosed. In another embodiment, a wireless communication device configured to implement the disclosed methods in some embodiments is disclosed. In yet another embodiment, a non-transitory computer-readable medium having computer-executable instructions stored thereon for implementing the disclosed methods in some embodiments is disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The accompanying drawings are provided for illustrative purposes only and only depict exemplary embodiments of the present disclosure to facilitate the reader's understanding of the present disclosure. Therefore, the accompanying drawings should not be considered as limiting the breadth, scope or applicability of the present disclosure. It should be noted that for clarity and ease of description, these drawings are not necessarily drawn to scale.

[0010] Figure 1 An exemplary communication network is shown in which the techniques disclosed herein may be implemented according to an embodiment of the present disclosure.

[0011] Figure 2 An exemplary base station architecture is shown in which the central unit and the distributed units are separated according to some embodiments of the present disclosure.

[0012] Figure 3 A block diagram of a base station (BS) according to some embodiments of the present disclosure is shown.

[0013] Figure 4 A flowchart of a method for data mapping and scheduling performed by a BS according to some embodiments of the present disclosure is shown.

[0014] Figure 5 A block diagram of a user equipment (UE) according to some embodiments of the present disclosure is shown.

[0015] Figure 6 A flowchart of a method for data mapping and scheduling performed by a UE according to some embodiments of the present disclosure is shown.

[0016] Figure 7 An exemplary layer 2 structure for downlink data transmission is shown, wherein a data mapping layer is immediately above a medium access control (MAC) layer, according to some embodiments of the present disclosure.

[0017] Figure 8 An exemplary layer 2 structure for uplink data transmission is shown, wherein the data mapping layer is immediately above the MAC layer, according to some embodiments of the present disclosure.

[0018] Fig. 9 An exemplary layer 2 structure for downlink data transmission is shown, wherein the data mapping layer is the MAC layer, according to some embodiments of the present disclosure.

[0019] Fig.10 An exemplary layer 2 structure for uplink data transmission is shown, wherein the data mapping layer is the MAC layer, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] Various exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings so that those of ordinary skill in the art can make and use the present disclosure. As will be apparent to those of ordinary skill in the art, after reading the present disclosure, various changes or modifications may be made to the examples described herein without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the exemplary embodiments and applications described and illustrated herein. Additionally, the specific order and / or hierarchy of the steps in the methods disclosed herein are merely exemplary methods. Based on design preferences, while remaining within the scope of the present disclosure, the specific order or hierarchy of the steps of the disclosed methods or processes may be rearranged. Therefore, those of ordinary skill in the art will understand that the methods and techniques disclosed herein present various steps or actions in a sample order, and the present disclosure is not limited to the specific order or hierarchy presented, unless otherwise expressly stated.

[0021] A typical wireless communication network includes one or more base stations (generally referred to as "BS"), each providing wireless coverage in a geographical area, and one or more wireless user equipments (generally referred to as "UE") that can transmit and receive data within the wireless coverage. In a wireless communication network, the BS and the UE can communicate with each other via a communication link, for example, via a downlink (DL) radio frame from the BS to the UE or via an uplink (UL) radio frame from the UE to the BS.

[0022] The present teaching discloses a communication system design of layer functions in such a way that both the control plane function and the data mapping function are closely integrated with the transmission scheduling function. In one embodiment, the MAC layer of the protocol stack is responsible for scheduling and connection. The MAC+1 layer (which refers to the layer directly above the MAC layer) is responsible for the mapping between QoS flows and data bearer DRBs. The MAC+2 layer (which refers to the layer immediately above the MAC+1 layer) is responsible for the automatic repeat request (ARQ) function. The MAC+3 layer (which refers to the layer immediately above the MAC+2 layer) is responsible for order maintenance, robust header compression (RoHC), encryption and integrity protection functions.

[0023] In another embodiment, the MAC layer of the protocol stack is responsible for data mapping, scheduling, and cascading functions between QoS flows and data bearer DRBs. The MAC+1 layer is responsible for ARQ functions; the MAC+2 layer is responsible for order preservation, RoHC, encryption, and integrity protection functions. In yet another embodiment, one or more of the functions in the above MAC+2 layer can be moved to the MAC+3 layer.

[0024] The present teachings also disclose a method for layer 2 (L2) QoS mapping, wherein the main services and functions of the MAC layer or MAC+1 layer of the L2 include mapping between QoS flows and DRBs. The MAC layer or MAC+1 layer may also mark a QoS flow ID (QFI) for each DL and UL packet. In one example, the network side controls the MAC layer or MAC+1 layer of the L2 on the network side to configure mapping rules for mapping between QoS flows and radio bearers. In another example, the network side controls the MAC layer or MAC+1 layer of the L2 on the terminal side to configure mapping rules for mapping between QoS flows and radio bearers.

[0025] The network side control plane may send the aggregated DRB QoS profile and / or QoS flow profile to the MAC layer or MAC+1 layer of L2 on the network side for data mapping. The MAC layer or MAC+1 layer of L2 may reject the aggregated DRB QoS profile indicated by the control plane of the base station. The base station control plane may forward the rejection information to the core network. The data processing granularity of the MAC+2 layer and MAC+3 layer on the network side and the terminal side includes but is not limited to QoS flows and protocol data unit (PDU) sessions.

[0026] As used herein, the term "layer" refers to an abstract layer of a layered model (e.g., the open systems interconnection (OSI) model) that divides a communication system into abstract layers. A layer serves the next higher layer above it and enjoys the services provided by the next lower layer below it.

[0027] In various embodiments, the BS may be referred to as a network side node, and may include or be implemented as a next generation node B (gNB), an E-UTRAN node B (eNB), a transmission reception point (TRP), an access point (AP), a donor node (DN), a relay node, a core network (CN) node, a RAN node, a master node, a secondary node, a distributed unit (DU), a centralized unit (CU), etc. The UE in the present disclosure may be referred to as a terminal, and may include or be implemented as a mobile station (MS), a station (STA), etc. The BS and the UE may be described herein as non-limiting examples of "wireless communication nodes" or "wireless communication modules", and the UE may be described herein as non-limiting examples of "wireless communication devices". According to various embodiments of the present disclosure, the BS and the UE may practice the methods disclosed herein, and may be capable of wireless and / or wired communication.

[0028] Figure 1 1 shows an exemplary communication network 100 in which the techniques disclosed herein may be implemented according to an embodiment of the present disclosure. Figure 1 As shown, an exemplary communication network 100 includes a base station (BS) 101 and a plurality of UEs, UE 1 110, UE 2 120 ... UE 3 130, wherein BS 101 can communicate with the UE according to a wireless protocol. BS 101 can transmit downlink data to the UE (e.g., UE 1 110) based on a data mapping function and a scheduling function. These two functions can be tightly integrated in two adjacent layers or in the same layer to improve QoS performance, which is also true for uplink data transmission.

[0029] Figure 2 An exemplary architecture of a base station gNB 200 in which a central unit (CU) 220 and a distributed unit (DU) 210 are separated according to some embodiments of the present disclosure is shown. Figure 2 As shown, CU 220 and DU 210 are connected via an F1 interface. DU 210 includes a PHY layer 212, a MAC layer 214 above the PHY layer 212, and a MAC+1 layer 216 above the MAC layer 214. CU 220 includes a MAC+2 layer 222 above the MAC+1 layer 216, and a MAC+3 layer 224 above the MAC+2 layer 222. Therefore, the MAC+2 layer and the MAC+1 layer are deployed separately. In this case, the control plane function can be deployed in the MAC+1 layer or near the MAC layer. For example, the control plane function is deployed on DU 210. Compared with the existing NR method, the mapping function of QoS flow packets to DRBs is deployed in the MAC+1 layer or the MAC layer, so that both the control plane function and the mapping function can be closely integrated with the MAC layer scheduling function.

[0030] Figure 3 1 shows a block diagram of a base station (BS) 300 according to some embodiments of the present disclosure. BS 300 is an example of a node that can be configured to implement the various methods described herein. Figure 3 As shown, BS 300 includes a housing 340 that contains a system clock 302, a processor 304, a memory 306, a transceiver 310 including a transmitter 312 and a receiver 314, a power module 308, a data scheduler 320, a data mapper 322, a QoS attribute analyzer 324, and a QoS flow identification (ID) determiner 326.

[0031] In the present embodiment, system clock 302 provides timing signals to processor 304 for controlling the timing of all operations of BS 300. Processor 304 controls the overall operation of BS 300 and may include one or more processing circuits or modules, such as a central processing unit (CPU) and / or any combination of a general purpose microprocessor, microcontroller, digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gating logic, discrete hardware components, dedicated hardware finite state machines, or any other suitable circuit, device, and / or structure that can perform calculations or other data manipulations.

[0032] Memory 306 (which may include read-only memory (ROM) and random access memory (RAM)) can provide instructions and data to processor 304. A portion of memory 306 may also include non-volatile random access memory (NVRAM). Processor 304 typically performs logic and arithmetic operations based on program instructions stored in memory 306. Instructions (also referred to as software) stored in memory 306 can be run by processor 304 to perform the methods described herein. Processor 304 and memory 306 together form a processing system that stores and executes software. As used herein, "software" refers to any type of instruction that can configure a machine or device to perform one or more desired functions or processes, whether it refers to software, firmware, middleware, microcode, etc. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable code format). When executed by one or more processors, these instructions cause the processing system to perform the various functions described herein.

[0033] The transceiver 310 including a transmitter 312 and a receiver 314 allows the BS 300 to transmit data to and receive data from a remote device (e.g., another BS or UE). The antenna 350 is typically attached to the housing 340 and electrically coupled to the transceiver 310. In various embodiments, the BS 300 includes (not shown) multiple transmitters, multiple receivers, and multiple transceivers. In one embodiment, the antenna 350 is replaced by a multi-antenna array 350, which can form multiple beams, each of which points to a different direction. The transmitter 312 can be configured to wirelessly transmit packets with different packet types or functions, which are generated by the processor 304. Similarly, the receiver 314 is configured to receive packets with different packet types or functions, and the processor 304 is configured to process packets with multiple different packet types. For example, the processor 304 can be configured to determine the type of packet and process the packet and / or the field of the packet accordingly.

[0034] In a communication system including a BS 300 capable of serving one or more UEs, the BS 300 may transmit downlink data to the UE based on data scheduling. In one embodiment, a data scheduler 320 may schedule data of at least one data radio bearer (DRB) at a first layer (e.g., a media access control (MAC) layer). A data mapper 322 may perform mapping between multiple quality of service (QoS) flows and at least one DRB at a mapping layer, which is a first layer or a second layer immediately above the first layer. For example, the second layer may be a radio link control (RLC) layer. In one embodiment, the first layer and the second layer are implemented at a distributed unit (DU) of a split architecture network; and at least one layer above the second layer is implemented at a central unit (CU) of the split architecture network.

[0035] In one embodiment, the QoS attribute analyzer 324 may obtain QoS attribute information of each QoS flow mapped to at least one DRB at the first layer. The QoS attribute information may include at least one of the following: an aggregated DRB QoS profile, a QoS flow profile, and a QoS requirement of each QoS flow mapped to at least one DRB. The QoS attribute analyzer 324 may send the QoS attribute information to the data scheduler 320, which may schedule data of the at least one DRB based on the QoS attribute information.

[0036] In one embodiment, the data mapper 322 may obtain a mapping rule for mapping between multiple QoS flows and at least one DRB from the control plane at the mapping layer. Based on the mapping rule, the data mapper 322 may map multiple QoS flows to at least one DRB for downlink transmission. The control plane may adjust the mapping rule in real time based on the information obtained from the first layer. The information may be related to resource usage and air interface transmission. For example, the information is related to at least one of: actual air interface transmission efficiency, physical resource utilization, and scheduling efficiency of the first layer.

[0037] In one embodiment, the QoS flow ID determiner 326 can determine and mark an identification (ID) for each of the plurality of QoS flows at a mapping layer. In this example, the processor 304 can process data at a layer above layer 2 at a granularity of at least one of: a QoS flow and a protocol data unit (PDU) session.

[0038] The power module 308 may include a power source (such as one or more batteries) and a power regulator to provide power to the Figure 3 Each of the above modules in provides regulated power. In some embodiments, if BS 300 is coupled to a dedicated external power source (eg, a wall outlet), power module 308 may include a transformer and a power conditioner.

[0039] The various modules discussed above are coupled together via a bus system 330. The bus system 330 may include a data bus and other functions other than the data bus, such as a power bus, a control signal bus, and / or a status signal bus. It should be understood that the modules of the BS 300 may be operably coupled to each other using any suitable technology and medium.

[0040] Despite Figure 3 , but it will be understood by those skilled in the art that one or more of the modules may be combined or implemented together. For example, the processor 304 may implement not only the functions described above with respect to the processor 304, but also the functions described above with respect to the data mapper 322. On the contrary, Figure 3 Each of the modules shown in the figure may be implemented using multiple separate components or elements.

[0041] Figure 4 It is shown that according to some embodiments of the present disclosure, a BS (eg, Figure 3 Flowchart of a method 400 for data mapping and scheduling performed by a BS 300 in the MAC layer. At operation 410, a mapping rule for a mapping layer is obtained from a control plane, the mapping layer being a MAC layer or a layer immediately above the MAC layer. At operation 420, based on the mapping rule, mapping between multiple quality of service (QoS) flows and at least one DRB is performed at the mapping layer. At operation 430, an identifier (ID) is marked for each of the multiple QoS flows at the mapping layer. At operation 440, the BS obtains QoS attribute information of each QoS flow mapped to at least one DRB at the MAC layer. At operation 450, the BS schedules data of at least one DRB for transmission at the MAC layer based on the QoS attribute information. According to different embodiments of the present disclosure, Figure 4 The order of operations shown in may be changed.

[0042] Figure 5 1 is a block diagram of a user equipment (UE) 500 according to some embodiments of the present disclosure. UE 500 is an example of a device that can be configured to implement the various methods described herein. Figure 5 As shown, UE 500 includes a housing 540 that contains a system clock 502, a processor 504, a memory 506, a transceiver 510 including a transmitter 512 and a receiver 514, a power module 508, a data scheduler 520, a data mapper 522, a scheduling configuration analyzer 524, and a QoS flow identification (ID) determiner 526.

[0043] In this embodiment, system clock 502, processor 504, memory 506, transceiver 510, and power module 508 operate similarly to system clock 302, processor 304, memory 306, transceiver 310, and power module 308 in BS 300. Antenna 550 or multiple antenna array 550 is typically attached to housing 540 and electrically coupled to transceiver 510.

[0044] In a communication system, UE 500 may wish to transmit uplink data to a BS based on data scheduling. In one embodiment, a data scheduler 520 may schedule data of at least one data radio bearer (DRB) at a first layer (e.g., a medium access control (MAC) layer). In this example, a data mapper 522 may perform mapping between a plurality of quality of service (QoS) flows and at least one DRB at a mapping layer, which is the first layer or a second layer immediately above the first layer. For example, the second layer may be a radio link control (RLC) layer.

[0045] In one embodiment, the data mapper 522 may obtain a mapping rule from the BS at a mapping layer. Based on the mapping rule, the data mapper 522 may map multiple QoS flows to at least one DRB for data transmission between the BS and the UE 500.

[0046] In one embodiment, the scheduling configuration analyzer 524 may obtain the scheduling configuration from the BS at the first layer. In one example, the scheduling configuration is determined based on the QoS attribute information of each QoS flow to be mapped to at least one DRB. The QoS attribute information includes at least one of the following: an aggregated DRB QoS profile, a QoS flow profile, and a QoS requirement of each QoS flow mapped to at least one DRB. The scheduling configuration analyzer 524 may send the scheduling configuration to the data scheduler 520, which may schedule data of the at least one DRB based on the scheduling configuration.

[0047] In one embodiment, the QoS flow ID determiner 526 can determine and mark an identification (ID) for each of the plurality of QoS flows at a mapping layer. In this example, the processor 504 can process data at a layer above layer 2 at a granularity of at least one of: a QoS flow and a protocol data unit (PDU) session.

[0048] The various modules discussed above are coupled together via a bus system 530. The bus system 530 may include a data bus and other functions other than the data bus, such as a power bus, a control signal bus, and / or a status signal bus. It should be understood that the modules of the UE 500 may be operably coupled to each other using any suitable technology and medium.

[0049] Despite Figure 5 , but it will be understood by those skilled in the art that one or more of the modules may be combined or implemented together. For example, the processor 504 may implement not only the functions described above with respect to the processor 504, but also the functions described above with respect to the data mapper 522. On the contrary, Figure 5 Each of the modules shown in the figure may be implemented using multiple separate components or elements.

[0050] Figure 6 UE (eg, Figure 5 Flowchart of a method 600 for data mapping and scheduling performed by a UE 500 in FIG. 1 . At operation 610, a mapping rule for a mapping layer is obtained from a BS, and the mapping layer is a MAC layer or a layer immediately above the MAC layer. At operation 620, based on the mapping rule, mapping between multiple quality of service (QoS) flows and at least one DRB is performed at the mapping layer. At operation 630, an identifier (ID) is marked for each of the multiple QoS flows at the mapping layer. According to various embodiments of the present disclosure, Figure 6 The order of operations shown in may be changed.

[0051] Now, different embodiments of the present disclosure will be described in detail below. Note that the features of the embodiments and examples in the present disclosure can be combined with each other in any way without conflict.

[0052] In a first embodiment, data transmission is performed, wherein the MAC+1 layer is responsible for mapping functions. In this embodiment, the MAC layer of the protocol stack is responsible for scheduling and concatenation; the MAC+1 layer is responsible for mapping QoS flows to data bearers DRBs; the MAC+2 layer is responsible for automatic repeat request (ARQ) functions; and the MAC+3 layer is responsible for order preservation, robust header compression (RoHC), encryption, and integrity protection (e.g., by a first algorithm for protecting data integrity) functions.

[0053] Figure 7 An exemplary layer 2 structure 700 for downlink data transmission according to the first embodiment is shown, wherein the data mapping layer is immediately above the medium access control (MAC) layer. An exemplary downlink transmission according to the first embodiment may include the following steps.

[0054] In step 1, the MAC+3 layer on the network side receives QoS flow data packets from the core network through the Ng interface. The MAC+3 layer can perform order preservation 710 (e.g., by sequence number (SN) numbering), robust header compression (RoHC) 720, encryption and integrity protection 730, and add subheaders on the data packets in each flow to form MAC+3 PDUs. The MAC+3 layer forwards the MAC+3 PDU to the MAC+2 layer.

[0055] In step 2, the MAC+2 layer on the network side receives the MAC+2 SDU sent from the MAC+3 layer. For each data packet in the flow, the MAC+2 layer adds an SN number to the data packet, performs ARQ 740 on the data packet, and adds a subheader to the data packet to form a MAC+2 PDU. The MAC+2 layer forwards the MAC+2 PDU to the MAC+1 layer.

[0056] In step 3, the MAC+1 layer on the network side receives each QoS flow data packet from the MAC+2 layer. The MAC+1 layer establishes the corresponding DRB according to the QoS requirements based on the control plane configuration on the network side. According to the mapping rules configured by the control plane on the network side, in operation 750, the MAC+1 layer maps the QoS flow 745 to DRBs 762, 764, 766, and marks the QoS flow ID (QFI) on each QoS flow. One or more QoS flows can be mapped to the same DRB. For example, three QoS flows are mapped to DRB 762; two QoS flows are mapped to DRB 766; and one QoS flow is mapped to DRB 764. The MAC+1 layer sends the mapped DRB to the MAC layer through a logical channel.

[0057] In step 4, the MAC layer on the network side obtains data information of each DRB from the logical channel. The MAC layer performs scheduling and / or priority processing 770 based on the QoS flow profile configured by the control plane of the base station and the aggregated DRB QoS profile. Then, the MAC layer performs segmentation and multiplexing 780 and assembles a transport block (TB) for each UE to which the downlink data is sent. According to the scheduling result, the MAC layer also performs HARQ processing 790 for each UE. The MAC layer sends the corresponding TB to the PHY layer.

[0058] In step 5, the PHY layer performs corresponding physical layer processing. Then, the PHY layer transmits downlink data to the terminal through the air interface.

[0059] In step 6, the PHY layer on the terminal side receives the downlink data transmitted by the network side through the air interface and performs PHY layer processing. Then, the PHY layer on the terminal side delivers the processed TB to the MAC layer on the terminal side.

[0060] The MAC layer on the terminal side receives the MAC PDU from the PHY layer and performs demultiplexing, reassembly, and HARQ processing to form the MAC PDU in step 7. The MAC layer transmits the MAC SDU to the MAC+1 layer through the logical channel.

[0061] In step 8, the MAC+1 layer on the terminal side performs DRB to QoS flow demapping for each logical channel DRB according to the QoS mapping rules configured by the network side control plane through radio resource control (RRC) signaling. The MAC+1 layer reads the QFI information of each QoS flow and sends the QoS flow data packet to the MAC+2 layer.

[0062] The MAC+2 layer on the terminal side performs an ARQ process on each QoS flow data packet in step 9. Then, the MAC+2 layer sends the data packet to the MAC+3 layer.

[0063] The MAC+3 layer on the terminal side performs decryption, integrity protection parsing (eg, by a second algorithm opposite to the first algorithm), RoHC, and data reordering on each QoS flow packet at step 10. The MAC+3 layer may then send the data packet to an upper layer.

[0064] When the MAC layer on the network side receives the configuration information of the aggregated DRB QoS profile of the network side control plane, if the MAC layer finds that the required QoS performance cannot be met through scheduling, the MAC layer can reject the configuration of the control plane and request the control plane to reconfigure. After receiving the rejection information, the network side control plane can notify the core network of the rejection information through the Ng interface.

[0065] On the network side, the MAC+2 layer and the MAC+1 layer can be deployed separately. That is, there may be an interface between the MAC+2 layer and the MAC+1 layer. In downlink data processing, the MAC+2 layer data packet must be processed through the interface before being sent to the MAC+1 layer. In this case, the control plane function can be deployed in the MAC+1 layer or near the MAC layer. For example, in Figure 2 In the case of CU-DU separation shown, the control plane function is deployed on the DU side. Compared with the existing NR method, in this embodiment, the mapping function of QoS flow packets to DRBs is deployed in the MAC+1 layer, so that both the control plane function and the mapping function can be closely integrated with the MAC layer scheduling function.

[0066] On the one hand, this combined design can avoid cross-layer interactions caused by the separate deployment of the control plane, mapping layer, and MAC layer in the NR system. This can especially avoid delays and inefficient interactions between the CU and the DU. On the other hand, the control plane can obtain resource usage and air interface transmission information from the MAC layer in a timely manner, including: actual air interface transmission efficiency on the DU side, physical resource utilization, scheduling efficiency of the MAC layer, etc. Based on this information, the mapping rules for mapping QoS flow packets to DRBs can be modified in real time to ensure the rationality of the mapping, thereby largely avoiding the situation where the MAC layer rejects the mapping configuration of the control plane because it cannot meet the QoS requirements. At the same time, the MAC layer can also obtain the QoS attribute information of each flow mapped to the DRB from the control plane in a timely manner, and schedule based on the QoS attribute information to maximize the QoS performance requirements of each flow. As a result, users can get a better performance service experience. In addition, scheduling DRBs at the MAC layer can also be based on the QoS requirements of each flow mapped to the DRB.

[0067] Since the mapping function is deployed at the MAC+1 layer on the network side, the processing granularity of the MAC+2 layer and the MAC+3 layer above the MAC+1 layer can be at the QoS flow or PDU session level, which can be the same on the terminal side.

[0068] Figure 8 An exemplary layer 2 structure 800 for uplink data transmission according to the first embodiment is shown, wherein the data mapping layer is immediately above the MAC layer. An exemplary uplink transmission according to the first embodiment may include the following steps.

[0069] In step 1, the MAC+3 layer on the terminal side receives QoS flow data packets from the upper layer. The MAC+3 layer can perform order preservation 810, robust header compression (RoHC) 820, encryption and integrity protection 830 and / or SN numbering, sub-header processing on the data packets in each flow to form a MAC+3 PDU. The MAC+3 layer forwards the MAC+3 PDU to the MAC+2 layer.

[0070] In step 2, the MAC+2 layer on the terminal side receives the MAC+2 SDU transmitted from the MAC+3 layer. For each data packet in the flow, the MAC+2 layer adds an SN to the data packet, performs ARQ 840 on the data packet, and adds a subheader to the data packet to form a MAC+2 PDU. The MAC+2 layer forwards the MAC+2 PDU to the MAC+1 layer.

[0071] In step 3, the MAC+1 layer on the terminal side receives each QoS flow data packet from the MAC+2 layer. The MAC+1 layer establishes the corresponding DRB. According to the QoS mapping rules configured by the network side control plane via radio resource control (RRC) signaling, at operation 850, the MAC+1 layer maps the QoS flow 845 to DRBs 862, 864, and a QoS flow ID (QFI) may be marked on each QoS flow. One or more QoS flows may be mapped to the same DRB. For example, three QoS flows are mapped to DRB 862; and one QoS flow is mapped to DRB 864. The MAC+1 layer sends the mapped DRB to the MAC layer via a logical channel.

[0072] In step 4, the MAC layer on the terminal side obtains data information of each DRB from the logical channel. The MAC layer performs priority processing 870 on each logical channel data according to the uplink scheduling result of the base station. Then, the MAC layer performs segmentation and multiplexing 880 and assembles a transport block (TB). The MAC layer also performs HARQ processing 890 according to the scheduling result. The MAC layer sends the corresponding TB to the PHY layer.

[0073] In step 5, the PHY layer performs corresponding physical layer processing. Then, the PHY layer transmits the uplink data to the network side through the air interface.

[0074] In step 6, the PHY layer on the network side receives the uplink data sent by the terminal side through the air interface and performs PHY layer processing. Then, the PHY layer on the network side delivers the processed TB to the MAC layer on the network side.

[0075] The MAC layer on the network side receives the MAC PDU from the PHY layer and performs demultiplexing, reassembly, and HARQ processing to form the MAC PDU in step 7. The MAC layer transmits the MAC SDU to the MAC+1 layer through a logical channel.

[0076] The MAC+1 layer on the network side performs DRB to QoS flow demapping for each logical channel DRB in step 8. The MAC+1 layer marks QFI information for each QoS flow and sends the QoS flow data packet to the MAC+2 layer.

[0077] The MAC+2 layer on the network side performs an ARQ process on each QoS flow data packet in step 9. The MAC+2 layer then sends the data packet to the MAC+3 layer.

[0078] The MAC+3 layer on the network side performs decryption, integrity protection parsing, RoHC, and data reordering on each QoS flow packet in step 10. The MAC+3 layer may then send the data packet to the core network.

[0079] On the network side, the MAC+2 layer and the MAC+1 layer can be deployed separately. That is, there may be an interface between the MAC+2 layer and the MAC+1 layer. In uplink data processing, the MAC+2 layer data packet must be processed through the interface before being sent to the MAC+1 layer. In this case, the control plane function can be deployed in the MAC+1 layer or near the MAC layer. For example, in Figure 2 In the case of CU-DU separation shown, the control plane function is deployed on the DU side. Compared with the existing NR method, in this embodiment, the mapping function of QoS flow packets to DRBs is deployed in the MAC+1 layer, so that both the control plane function and the mapping function can be closely integrated with the MAC layer scheduling function. Since the mapping function is deployed at the MAC+1 layer on the terminal side, the processing granularity of the MAC+2 layer and the MAC+3 layer above the MAC+1 layer can be at the QoS flow or PDU session level, which can be the same on the network side.

[0080] In a second embodiment, data transmission is performed, wherein the MAC layer is responsible for mapping functions. In this embodiment, the MAC layer of the protocol stack is responsible for mapping QoS flows to data bearers DRBs, scheduling, and concatenation; the MAC+1 layer is responsible for ARQ functions; and the MAC+2 layer is responsible for order preservation, robust header compression (RoHC), encryption, and integrity protection (e.g., by a first algorithm for protecting data integrity) functions. In another embodiment, one or more of the functions in the above MAC+2 layer may be moved to the MAC+3 layer.

[0081] Fig. 9 An exemplary layer 2 structure 900 for downlink data transmission according to the second embodiment is shown, wherein the data mapping layer is the MAC layer. Compared with the downlink data transmission process in the first embodiment in which the MAC+1 layer is responsible for the mapping function, the difference is that in the second embodiment, the mapping function is performed at the MAC layer. The mapping-related processing is performed at the MAC layer; the mapping function and the scheduling function are performed in the same protocol layer.

[0082] like Fig. 9 As shown, the MAC+2 layer on the network side receives QoS flow data packets from the core network through the Ng interface. The MAC+2 layer can perform order preservation 910 (e.g., by sequence number (SN) numbering), robust header compression (RoHC) 920, encryption and integrity protection 930, and add subheaders to the data packets in each flow to form MAC+2 PDUs. The MAC+2 layer forwards the MAC+2 PDUs to the MAC+1 layer.

[0083] The MAC+1 layer on the network side receives the MAC+2 SDU sent from the MAC+2 layer. For each data packet in the flow, the MAC+1 layer adds an SN number to the data packet, performs ARQ 940 on the data packet, and adds a subheader to the data packet to form a MAC+1 PDU. The MAC+1 layer forwards the MAC+1 PDU to the MAC layer.

[0084] The MAC layer on the network side receives each QoS flow data packet from the MAC+1 layer. The MAC layer establishes a corresponding DRB according to the QoS requirements based on the control plane configuration on the network side. According to the mapping rules configured by the control plane on the network side, at operation 950, the MAC layer maps the QoS flow 945 to DRBs 962, 964, 966, and marks the QoS flow ID (QFI) on each QoS flow. One or more QoS flows can be mapped to the same DRB. For example, three QoS flows are mapped to DRB 962; two QoS flows are mapped to DRB 966; and one QoS flow is mapped to DRB 964. The MAC layer performs scheduling and / or priority processing 970 based on the QoS flow profile and the aggregated DRB QoS profile configured by the control plane of the base station. Then, the MAC layer performs segmentation and multiplexing 980 and assembles a transport block (TB) for each UE to which the downlink data is sent. According to the scheduling result, the MAC layer also performs HARQ processing 990 for each UE. The MAC layer sends the corresponding TB to the PHY layer.

[0085] The PHY layer performs corresponding physical layer processing. Then, the PHY layer transmits downlink data to the terminal through the air interface.

[0086] The PHY layer on the terminal side receives the downlink data sent by the network side through the air interface and performs PHY layer processing. Then, the PHY layer on the terminal side delivers the processed TB to the MAC layer on the terminal side.

[0087] The MAC layer on the terminal side receives the MAC PDU from the PHY layer and performs demultiplexing, reassembly, and HARQ processing to form the MAC PDU. The MAC layer on the terminal side also performs DRB to QoS flow demapping for each logical channel DRB according to the QoS mapping rule configured by the network side control plane through radio resource control (RRC) signaling. The MAC layer reads the QFI information of each QoS flow and sends the QoS flow data packet to the MAC+1 layer.

[0088] The MAC+1 layer on the terminal side performs an ARQ process on each QoS flow data packet. The MAC+1 layer then sends the data packet to the MAC+2 layer.

[0089] The MAC+2 layer on the terminal side performs decryption, integrity protection parsing (eg, by a second algorithm opposite to the first algorithm), RoHC, and data reordering on each QoS flow packet. The MAC+2 layer can then send the data packet to the upper layer.

[0090] Fig.10 An exemplary layer 2 structure 1000 for uplink data transmission according to some embodiments of the present disclosure is shown, wherein the data mapping layer is the MAC layer. Compared with the uplink data transmission process in the first embodiment where the MAC+1 layer is responsible for the mapping function, the difference is that in the second embodiment, the mapping function is performed at the MAC layer. The mapping-related processing is performed at the MAC layer; the mapping function and the scheduling function are performed in the same protocol layer.

[0091] like Fig.10 As shown, the MAC+2 layer on the terminal side receives QoS flow data packets from the upper layer. The MAC+2 layer can perform order preservation 1010, robust header compression (RoHC) 1020, encryption and integrity protection 1030 and / or SN numbering, sub-header processing on the data packets in each flow to form a MAC+2 PDU. The MAC+2 layer forwards the MAC+2 PDU to the MAC+1 layer.

[0092] The MAC+1 layer on the terminal side receives the MAC+2 SDU sent from the MAC+2 layer. For each data packet in the flow, the MAC+1 layer adds an SN to the data packet, performs ARQ 1040 on the data packet, and adds a subheader to the data packet to form a MAC+1 PDU. The MAC+1 layer forwards the MAC+1 PDU to the MAC layer.

[0093] The MAC layer on the terminal side receives each QoS flow data packet from the MAC+1 layer. The MAC layer establishes the corresponding DRB. According to the QoS mapping rules configured by the network side control plane via radio resource control (RRC) signaling, in operation 1050, the MAC layer maps the QoS flow 1045 to DRBs 1062, 1064, and can mark the QoS flow ID (QFI) on each QoS flow. One or more QoS flows can be mapped to the same DRB. For example, three QoS flows are mapped to DRB 1062; and one QoS flow is mapped to DRB 1064. The MAC layer also performs priority processing 1070 on each logical channel data according to the uplink scheduling result of the base station. Then, the MAC layer performs segmentation and multiplexing 1080 and assembles a transport block (TB). The MAC layer also performs HARQ processing 1090 according to the scheduling result. The MAC layer sends the corresponding TB to the PHY layer.

[0094] The PHY layer performs the corresponding physical layer processing. Then, the PHY layer transmits the uplink data to the network side through the air interface.

[0095] The PHY layer on the network side receives the uplink data sent by the terminal side through the air interface and performs PHY layer processing. Then, the PHY layer on the network side delivers the processed TB to the MAC layer on the network side.

[0096] The MAC layer on the network side receives the MAC PDU from the PHY layer and performs demultiplexing, reassembly, and HARQ processing to form the MAC PDU. The MAC layer on the network side also performs DRB to QoS flow demapping for each logical channel DRB. The MAC layer marks the QFI information for each QoS flow and sends the QoS flow data packet to the MAC+1 layer.

[0097] The MAC+1 layer on the network side performs an ARQ process on each QoS flow data packet. The MAC+1 layer then sends the data packet to the MAC+2 layer.

[0098] The MAC+2 layer on the network side performs decryption, integrity protection parsing, RoHC, and data reordering on each QoS flow packet. The MAC+2 layer can then send the data packet to the core network.

[0099] Although various embodiments of the present disclosure have been described above, it should be understood that they are presented only as examples rather than as limitations. Similarly, various figures may depict example architectures or configurations, which are provided to enable those of ordinary skill in the art to understand the exemplary features and functions of the present disclosure. However, it will be understood by these personnel that the present disclosure is not limited to the example architectures or configurations shown, but may be implemented using various alternative architectures and configurations. Additionally, as will be appreciated by those of ordinary skill in the art, one or more features of an embodiment may be combined with one or more features of another embodiment described herein. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments.

[0100] It should also be understood that any reference to an element using designations such as "first," "second," etc. herein generally does not limit the number or order of these elements. Rather, these designations may be used herein as a convenient means of distinguishing between two or more elements or instances of elements. Thus, a reference to a first element and a second element does not mean that only two elements can be used, or that the first element must precede the second element in some manner.

[0101] Additionally, it will be understood by those skilled in the art that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols (e.g., which may be referenced in the above description) may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0102] Those of ordinary skill in the art will further understand that any of the various illustrative logical blocks, modules, processors, devices, circuits, methods, and functions described in conjunction with the various aspects disclosed herein may be implemented by electronic hardware (e.g., digital implementations, analog implementations, or a combination of both), firmware, various forms of programs or design code combined with instructions (which, for convenience, may be referred to herein as "software" or "software modules"), or any combination of these technologies.

[0103] In order to clearly illustrate this interchangeability of hardware, firmware and software, various illustrative components, blocks, modules, circuits and steps have been described above in their functional aspects as a whole. Whether this functionality is implemented as hardware, firmware or software or a combination of these technologies depends on the specific application and the design constraints imposed on the entire system. Skilled technicians can implement the described functionality in various ways for each specific application, but this implementation decision will not lead to departing from the scope of this disclosure. According to various embodiments, processors, devices, components, circuits, structures, machines, modules, etc. can be configured to perform one or more of the functions described herein. The term "configured to" or "configured for" used herein with respect to a specific operation or function refers to a processor, device, component, circuit, structure, machine, module, etc. that is physically constructed, programmed and / or arranged to perform a specific operation or function.

[0104] In addition, it will be understood by those of ordinary skill in the art that the various illustrative logic blocks, modules, devices, components, and circuits described herein may be implemented within or performed by an integrated circuit (IC), which may include a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, or any combination thereof. The logic blocks, modules, and circuits may further include antennas and / or transceivers to communicate with various components within a network or within a device. A general-purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a digital signal processor core, or any other suitable configuration to perform the functions described herein.

[0105] If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium. Therefore, the steps of the method or algorithm disclosed herein can be implemented as software stored on a computer-readable medium. Computer-readable media include both computer storage media and communication media, and the communication media include any medium that can be enabled to transfer a computer program or code from one place to another. The storage medium can be any available medium that a computer can access. As an example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures and can be accessed by a computer.

[0106] In this document, the term "module" as used herein refers to software, firmware, hardware, and any combination of these elements for performing the associated functions described herein. Additionally, for the purpose of discussion, various modules are described as discrete modules; however, as is apparent to those of ordinary skill in the art, according to embodiments of the present disclosure, two or more modules may be combined to form a single module that performs the associated functions.

[0107] Additionally, in the embodiments of the present disclosure, a memory or other storage device and a communication component may be used. It should be understood that, for the sake of clarity, the above description has described the embodiments of the present disclosure with reference to different functional units and processors. However, it is apparent that any suitable functional distribution between different functional units, processing logic elements or domains may be used without departing from the present disclosure. For example, a function shown as being performed by a separate processing logic element or controller may be performed by the same processing logic element or controller. Therefore, references to specific functional units are merely references to suitable means for providing the described functionality, rather than indicating a strict logical or physical structure or organization.

[0108] Various modifications to the embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the broadest scope consistent with the novel features and principles disclosed herein, as set forth in the above claims.

Claims

1. A method performed by a wireless communication module, the method comprising: Scheduling data of at least one data radio bearer (DRB) at the first layer; performing mapping between a plurality of quality of service (QoS) flows and the at least one DRB at a mapping layer, the mapping layer being the first layer or a second layer immediately above the first layer; Processing data at a layer above the second layer at a granularity of at least one of: a QoS flow and a protocol data unit (PDU) session; as well as The first layer is a medium access control MAC layer, and the second layer is a radio link control RLC layer.

2. The method according to claim 1, further comprising: QoS attribute information of each QoS flow mapped to the at least one DRB is obtained at the first layer, wherein data of the at least one DRB is scheduled based on the QoS attribute information.

3. The method according to claim 2, wherein the QoS attribute information comprises at least one of the following: Aggregated DRB QoS profile; QoS flow profiles; and The QoS requirements of each QoS flow mapped to the at least one DRB.

4. The method according to claim 1, further comprising: A mapping rule for mapping between the plurality of QoS flows and the at least one DRB is obtained at the mapping layer from a control plane, wherein the mapping is performed based on the mapping rule.

5. The method according to claim 4, further comprising: The mapping rules are adjusted in real time based on information obtained from the first layer. 6 . The method according to claim 1 , further comprising marking an identification ID for each of the plurality of QoS flows at the mapping layer.

7. The method according to claim 1, wherein: The first layer and the second layer are implemented at a distributed unit DU of a split architecture network; and At least one layer above the second layer is implemented at a central unit CU of the split architecture network.

8. A method performed by a wireless communication device, the method comprising: Obtaining, at a first layer, scheduling information for at least one data radio bearer (DRB); performing mapping between a plurality of quality of service (QoS) flows and the at least one DRB at a mapping layer, the mapping layer being the first layer or a second layer immediately above the first layer; Processing data at a layer above the second layer at a granularity of at least one of: a QoS flow and a protocol data unit (PDU) session; as well as The first layer is a medium access control MAC layer, and the second layer is a radio link control RLC layer.

9. The method according to claim 8, further comprising: A mapping rule is obtained at the mapping layer from a wireless communication module, wherein the mapping is performed based on the mapping rule for data transmission between the wireless communication module and the wireless communication device. 10 . The method according to claim 9 , wherein the mapping rule is adjusted in real time by the wireless communication module based on information obtained from a media access control (MAC) layer of the wireless communication module.

11. The method according to claim 8, further comprising marking an identification ID for each of the plurality of QoS flows at the mapping layer.

12. A wireless communication module, configured to implement the method according to any one of claims 1 to 7.

13. A wireless communication device configured to perform the method according to any one of claims 8 to 11.

14. A non-transitory computer-readable medium having stored thereon computer-executable instructions for performing the method of any one of claims 1 to 11.

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