Testing method for memory device and operating method of testing device

Abstract

A test method for a memory device including a plurality of memory cells includes: generating a first test pattern; performing a first pattern write operation to write the first test pattern into the plurality of memory cells; reading first data from the plurality of memory cells written with the first test pattern; generating a second test pattern based on the first data; and performing a second pattern write operation to write the second test pattern into the plurality of memory cells. The second test pattern is generated so that a write operation for a failed cell in which a write failure occurs among the plurality of memory cells during the second pattern write operation is skipped.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Priority is claimed on Korean Patent Application No. 10-2020-0023607, filed on February 26, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor memory, and more particularly, to a test method for a memory device, an operating method of a test device for testing the memory device, and a memory device including a self-test function. Background Art

[0004] Semiconductor memory devices may be characterized as volatile memory devices (e.g., static random access memory (SRAM) or dynamic random access memory (DRAM)) in which stored data disappears when power is turned off, or as nonvolatile memory devices (e.g., flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)) in which stored data is retained even when power is turned off.

[0005] Due to various factors, a fault may occur in the memory device. A fault that occurs in the process of manufacturing the memory device may be detected in the process of testing the memory device, and the detected fault may be repaired. In this case, various faults of the memory device (such as, for example, a write fault of a memory cell) may occur randomly. Therefore, in the case where a write fault does not occur simultaneously in a plurality of memory cells during the process of testing the memory device, the memory device may be determined to be normal. Therefore, an unexpected fault may occur when the memory device is actually used. Summary of the invention

[0006] Embodiments of the inventive concept provide a test method for a memory device, an operating method of the test device, and a memory device configured to perform a self-test.

[0007] An embodiment of the inventive concept provides a test method for a memory device including a plurality of memory cells, the method comprising: generating a first test pattern; performing a first pattern write operation to write the first test pattern into the plurality of memory cells; reading first data from the plurality of memory cells written with the first test pattern; generating a second test pattern based on the first data; and performing a second pattern write operation to write the second test pattern into the plurality of memory cells. The second test pattern is generated so that failure information is written into a failure cell in which a write failure occurs among the plurality of memory cells.

[0008] Embodiments of the inventive concept also provide an operating method of a test device configured to test a memory device including a plurality of memory cells, the method comprising: generating a first test pattern and performing a first pattern write operation to write the first test pattern into the plurality of memory cells; reading first data from the plurality of memory cells; generating a second test pattern based on the first data and performing a second pattern write operation to write the second test pattern into the plurality of memory cells; reading second data from the plurality of memory cells; and generating a third test pattern based on the second data and performing a third pattern write operation to write the third test pattern into the plurality of memory cells. The second test pattern is generated so that during the second pattern write operation, failure information is written into at least one first failure cell among the plurality of memory cells in which a write failure occurs during the first pattern write operation, and the third test pattern is generated so that during the third pattern write operation, failure information is written into at least one first failure cell and at least one second failure cell among the plurality of memory cells in which a write failure occurs during the second pattern write operation.

[0009] Embodiments of the inventive concept also provide a memory device including a self-test function, the memory device including: a memory cell array including a plurality of memory cells; a driving circuit that performs a write operation and a read operation on the plurality of memory cells; and a built-in self-test (BIST) logic that performs a self-test under the control of an external device. During the self-test, the BIST logic is configured to iteratively perform a pattern write operation on the plurality of memory cells. For each iteration of the pattern write operation, the BIST logic is configured to control the driving circuit to write fault information into a faulty cell in which a write fault occurs among the plurality of memory cells.

[0010] An embodiment of the present invention also provides a memory device, comprising: a memory cell array comprising a plurality of memory cells; a driving circuit configured to perform write operations and read operations on the plurality of memory cells; a test register configured to temporarily store data read from the plurality of memory cells during a test operation of the memory cell array, and to generate a test pattern by combining the data stored therein with a default test pattern; and a control logic circuit configured to iteratively perform write operations on the plurality of memory cells using the test pattern during the test operation.

[0011] Embodiments of the inventive concept also provide a method for manufacturing a memory device, comprising: forming a memory device as part of a wafer including the memory device and at least one other memory device, the memory device including a plurality of memory cells; and testing the memory device. The testing of the memory device includes iteratively performing a pattern write operation on the plurality of memory cells, and writing failure information into a failed memory cell in which a write failure occurs among the plurality of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present inventive concept will become apparent in view of the following detailed description of exemplary embodiments with reference to the accompanying drawings.

[0013] Figure 1 A block diagram of a memory testing system according to an embodiment of the inventive concept is shown.

[0014] Figure 2 Show Figure 1 A block diagram of a memory device.

[0015] Figure 3A Show Figure 2 Schematic diagram of memory cells included in a memory cell array.

[0016] Figure 3B A graph showing the resistance value of the variable resistance element in different states is shown.

[0017] Figure 4 Show Figure 1 Flowchart of the operation of the test apparatus.

[0018] Figure 5 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation.

[0019] Figure 6 Show description according to Figure 5 An illustration of the operation of a flowchart.

[0020] Figure 7 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation.

[0021] Figure 8 Show description according to Figure 7 A table of operations for the flowchart.

[0022] Fig. 9 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation.

[0023] Fig.10 Show description according to Fig. 9 An illustration of the operation of a flowchart.

[0024] Fig.11 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation.

[0025] Fig.12 Show description according to Fig.11 An illustration of the operation of a flowchart.

[0026] Fig.13 A flowchart illustrating an operation of a testing device according to an embodiment of the inventive concept.

[0027] Fig.14 Show description according to Fig.13 An illustration of the operation of a flowchart.

[0028] Fig.15 A block diagram of a memory device according to an embodiment of the inventive concept is shown.

[0029] Fig.16 Show Fig.15 A flow chart of the operation of a memory device.

[0030] Fig.17 Show description according to Fig.16 An illustration of the operation of a flowchart.

[0031] Fig.18A and Fig.18B Diagrams describing a test operation according to an embodiment of the inventive concept are shown.

[0032] Fig.19 An exemplary diagram depicting a repair operation on a memory device is shown.

[0033] Fig. 20 An exemplary diagram describing shielding operations on a memory device is shown.

[0034] Fig.21 A block diagram of a test system according to an embodiment of the inventive concept is shown.

[0035] Fig. 22 A block diagram illustrating a memory system to which a memory device according to an embodiment of the inventive concept can be applied.

[0036] Fig.23 A block diagram of a memory system according to an embodiment of the inventive concept is shown.

[0037] Fig.24 A block diagram of a computing system according to an embodiment of the inventive concept is shown.

[0038] Fig.25 A block diagram of an electronic device according to an embodiment of the inventive concept is shown.

[0039] Fig.26 A block diagram illustrating a data center to which a storage system according to an embodiment of the inventive concept can be applied. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the inventive concept are described in detail and clearly so that a person having ordinary skill in the art can easily implement the inventive concept.

[0041] As traditional in the field of the present invention, the embodiment can be described and illustrated according to the block that performs the described function or multiple functions. These blocks may be referred to as units or modules, etc. in this article, and are physically implemented by analog and / or digital circuits, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc. such as logic gates, and may be optionally driven by firmware and / or software. For example, the circuit may be implemented in one or more semiconductor chips or on substrate supports such as printed circuit boards. The circuit constituting the block may be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the block and a processor that performs other functions of the block. Without departing from the scope of the present invention, each block of the embodiment may be physically separated into two or more interacting and discrete blocks. Similarly, without departing from the scope of the present invention, the block of the embodiment may be physically combined into more complex blocks.

[0042] Figure 1 FIG. 1 is a block diagram of a memory test system according to an embodiment of the inventive concept. Figure 1 , the memory test system 100 may include a test device 110 and a memory device 120. In an exemplary embodiment, the memory test system 100 may be used to detect a failure of the memory device 120 during the process of manufacturing the memory device 120. For example, the memory test system 100 may be used to test and detect a failure of the memory device 120 after the memory device 120 is manufactured and before the memory device 120 is implemented in a system or device.

[0043] The test device 110 may perform a test operation for detecting a fault of the memory device 120. For example, the test device 110 may perform a test operation for determining whether the memory device 120 performs various operations (e.g., write operations and read operations) normally. In the following description of the inventive concept, for further understanding, it is assumed that the test device 110 tests the write operation of the memory device 120. However, the embodiments of the inventive concept should not be limited to the write operation, because operations other than the write operation can be tested. In addition, it is assumed that the memory device 120 is a magnetic random access memory (MRAM). However, the inventive concept is not limited thereto. For example, the test device 110 may be configured to detect various faults occurring in the memory device 120. The memory device 120 may be implemented with various memories such as, for example, SRAM, DRAM, flash memory, PRAM, MRAM, RRAM, and FRAM.

[0044] For the purpose of testing the write operation of the memory device 120, the test device 110 may be configured to control the memory device 120. For example, the test device 110 may generate a test pattern to be written in the memory device 120, and may write the generated test pattern in the memory device 120. The test device 110 may determine the failure bits occurring in the memory device 120 by reading the test pattern written in the memory device 120 and comparing the read test pattern with the original test pattern. When the number of detected failure bits exceeds a reference value, the test device 110 may perform a repair operation or a masking operation on the memory device 120.

[0045] In an exemplary embodiment, the test pattern may be a bit stream required to determine a failure of a write operation of a plurality of memory cells included in the memory device 120. In an exemplary embodiment, the reference value may indicate the number of error bits that may be corrected by an error correction code (ECC) engine or circuit included in the memory device 120 or a memory controller (not shown) configured to control the memory device 120.

[0046] As described above, the test device 110 can detect a fault occurring in the memory device 120 by iteratively performing an operation of writing a test pattern into the memory device 120 and checking the written test pattern. However, a write fault may randomly occur in each memory cell included in the memory device 120. That is, even if there are a plurality of memory cells with a high probability of occurrence of a write fault among the memory cells included in the memory device 120, the probability of a write fault occurring simultaneously in a certain number or more of the memory cells may be relatively low. For example, in a test process, in the case of randomly detecting a memory cell with a high probability of occurrence of a write fault in a plurality of write operations rather than in one write operation, a write fault of the memory device 120 may not be detected. However, in an actual driving environment of the memory device 120 after the test process, a write fault may occur simultaneously in a plurality of memory cells even if the probability is low, thereby reducing the reliability of the memory device 120. That is, a test process of simply iteratively writing a given test pattern may provide low accuracy in detection of a write fault for the memory device 120.

[0047] The test device 110 according to an embodiment of the inventive concept may include a pattern generator 111. The pattern generator 111 may generate a test pattern to be used in a current pattern write operation based on the result of a previous pattern write operation. In this case, the pattern generator 111 may generate a test pattern based on the result of a previous pattern write operation so that a write operation or a rewrite operation for a memory cell determined to be a write failure is skipped or not performed. In this case, since the location of the memory cell where the write failure occurs in each iterative pattern write operation is written or stored in the memory cell of the memory device 120 (i.e., the write failure memory cell), the detection accuracy of the write failure of the memory device 120 can be improved. The operation of the test device 110 and the pattern generator 111 according to an embodiment of the inventive concept will be described more fully below with reference to the accompanying drawings.

[0048] Figure 2 Show Figure 1 A block diagram of a memory device. Figure 2 , the memory device 120 may include a memory cell array 121, an address decoder 122, a write driver / sense amplifier 123, an input / output (I / O) circuit 124, a control logic circuit 125, and a repair logic (eg, circuit) 126.

[0049] The memory cell array 121 may include a plurality of memory cells MC. The plurality of memory cells MC may be connected to word lines WL, bit lines BL, and source lines SL. In an exemplary embodiment, each of the plurality of memory cells MC may be an MRAM cell, but the inventive concept is not limited thereto, and the memory cells MC may be other types of cells.

[0050] The address decoder 122 may be connected to the memory cell array 121 through the word line WL. The address decoder 122 may receive an address ADDR from the test device 110 (or an external device such as a memory controller (not shown)), and may decode the received address ADDR. The address decoder 122 may control the voltage of the word line WL respectively based on the decoding result. The address decoder 122 may output a column selection signal CS based on the decoding result.

[0051] The write driver / sense amplifier 123 (hereinafter referred to as the "drive circuit") may be connected to the memory cell array 121 through the source line SL and the bit line BL. The drive circuit 123 may select the source line SL and the bit line BL in response to the column select signal CS. Alternatively, the drive circuit 123 may read data stored in a plurality of memory cells MC of the memory cell array 121 by sensing the voltage of the source line SL or the bit line BL.

[0052] The input / output circuit 124 may receive input data DIN from the test device 110 (or an external device such as a memory controller (not shown)), and may transmit the received input data DIN to the drive circuit 123. In an exemplary embodiment, the drive circuit 123 may write the input data DIN into a plurality of memory cells MC of the memory cell array 121 by controlling the voltages of the source line SL and the bit line BL based on the input data DIN. The input / output circuit 124 may receive output data DOUT from the drive circuit 123, and may transmit the received output data DOUT to the test device 110 (e.g., an external device such as a memory controller).

[0053] In an exemplary embodiment, while the test device 110 performs a test operation, input data DIN may indicate a test pattern to be written in memory cells MC of the memory cell array 121 , and output data DOUT may indicate data read from the memory cells MC to which the test pattern is written.

[0054] The control logic circuit 125 may receive a command CMD or a control signal CTRL from the test device 110 (e.g., a memory controller), and may control the operation of the memory device 120 in response to the received signal. For example, the control logic circuit 125 may control the driver circuit 123 so that the driver circuit 123 operates as a write driver during a write operation of the memory device 120, and the driver circuit 123 operates as a sense amplifier during a read operation of the memory device 120.

[0055] The repair logic 126 may be configured to perform a repair operation on the failed memory cell MC under the control of the test device 110. For example, the repair logic 126 may be configured to replace a specific word line (e.g., a word line connected to the failed cell) with any other word line (e.g., a spare word line) under the control of the test device 110.

[0056] Figure 3A and Figure 3B Is a description Figure 2 1 is a diagram of a memory cell included in a memory cell array of FIG. 1. In the following, to help description and further understanding, an embodiment of the inventive concept will be described based on a write operation of the memory device 120. Figure 3A An exemplary structure of a memory cell MC is described, but the inventive concept is not limited thereto, as other types of memory cells may be used. Figure 3B , the horizontal axis represents the resistance of the variable resistance element MTJ of the memory cell MC, and the vertical axis represents the probability.

[0057] Reference Figure 2 , Figure 3A and Figure 3B, the memory cell MC may include a variable resistance element MTJ and a selection transistor SEL. The variable resistance element MTJ may be implemented using a magnetic tunnel junction. The variable resistance element MTJ may be connected between the bit line BL and the selection transistor SEL. The selection transistor SEL may be connected between the variable resistance element MTJ and the source line SL, and may operate in response to the voltage of the word line WL.

[0058] In an exemplary embodiment, the memory device 120 may write data into the memory cell MC by adjusting the resistance value of the memory cell MC. Figure 3A As shown, the variable resistance element MTJ may include a free layer FRL, a barrier layer BRL, and a fixed layer FXL. The barrier layer BRL may be between the free layer FRL and the fixed layer FXL, the free layer FRL may be connected to the bit line BL, and the fixed layer FXL may be connected to the selection transistor SEL. The magnetization direction of the fixed layer FXL may be fixed to a specific direction, and the magnetization direction of the free layer FRL may be changed according to specific conditions (e.g., the direction of the write current). In an exemplary embodiment, the variable resistance element MTJ may also include an antiferromagnetic layer for fixing the magnetization direction of the fixed layer FXL.

[0059] In an exemplary embodiment, the free layer FRL may include a material having a variable magnetization direction. The magnetization direction of the free layer FRL may be changed by an electric or magnetic factor provided from the outside or inside of the memory cell MC. The free layer FRL may include a ferromagnetic material including at least one of cobalt (Co), iron (Fe), and nickel (Ni). For example, the free layer FRL may include a material selected from FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO 2 、MnOFe 2 O 3 ,FeOFe 2 O 3 、NiOFe 2 O 3 、CuOFe 2 O3、MgOFe 2 O 3 , EuO and Y 3 Fe 5 O 12 However, the present inventive concept is not limited to the above-mentioned ferromagnetic materials, and other suitable ferromagnetic materials may be used.

[0060] In an exemplary embodiment, the thickness of the barrier layer BRL may be less than the spin diffusion distance. The barrier layer BRL may include a non-magnetic material. For example, the barrier layer BRL may include at least one selected from an oxide of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium-zinc (Mg-Zn), and a nitride of titanium (Ti) and vanadium (V). However, the inventive concept is not limited thereto, and other suitable non-magnetic materials may be used.

[0061] In an exemplary embodiment, the fixed layer FXL may have a magnetization direction fixed by an antiferromagnetic layer. The fixed layer FXL may include a ferromagnetic material. For example, the fixed layer FXL may include a material selected from CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO 2 、MnOFe 2 O 3 ,FeOFe 2 O 3 、NiOFe 2 O 3 、CuOFe 2 O 3 MgOFe 2 O 3 , EuO and Y 3 Fe 5 O 12 In an exemplary embodiment, the antiferromagnetic layer may include an antiferromagnetic material. For example, the antiferromagnetic layer may include a material selected from PtMn, IrMn, MnO, MnS, MnTe, MnF 2 、FeCl 2 ,FeO,CoCl 2 、CoO、NiCl 2 At least one of NiO and Cr. However, the inventive concept is not limited thereto, and other suitable antiferromagnetic materials may be used. The above-mentioned structure, material or components of the variable resistance element MTJ are exemplary, and the inventive concept is not limited thereto.

[0062] like Figure 3A As shown, the magnetization direction of the free layer FRL can be changed according to the direction of the current Iap or Ip flowing through the variable resistance element MTJ. When the selection transistor SEL is turned on by the voltage of the word line WL, the current Iap or Ip can be generated by controlling the voltage of the bit line BL and the source line SL.

[0063] Figure 3A The antiparallel current Iap shown may flow from the source line SL toward the bit line BL. When the antiparallel current Iap flows through the variable resistance element MTJ, the magnetization direction of the free layer FRL may be opposite to the magnetization direction of the fixed layer FXL, which is called an "antiparallel state". On the contrary, Figure 3AThe parallel current Ip shown may flow from the bit line BL to the source line SL. When the parallel current Ip flows through the variable resistance element MTJ, the magnetization direction of the free layer FRL may be the same as the magnetization direction of the fixed layer FXL, which is called a "parallel state".

[0064] like Figure 3B As shown, when the variable resistance element MTJ is in an anti-parallel state, the variable resistance element MTJ may have an anti-parallel resistance value Rap. When the variable resistance element MTJ is in a parallel state, the variable resistance element MTJ may have a parallel resistance value Rp. That is, data may be stored in the memory cell MC according to the resistance value of the variable resistance element MTJ, and the data (e.g., bit "1" or bit "0") stored in the memory cell MC may be read by reading the resistance value of the variable resistance element MTJ.

[0065] In an exemplary embodiment, due to PVT (process, voltage and temperature) changes of the memory cell MC, the variable resistance element MTJ or any other structure or due to various factors, data may not be written normally into the memory cell MC. For example, when the bit "1" is written into the memory cell MC, it can be controlled so that the anti-parallel current Iap flows through the variable resistance element MTJ of the memory cell MC. However, due to various factors of the memory cell MC, the anti-parallel current Iap of sufficient size may not flow through the variable resistance element MTJ. On the other hand, even if the anti-parallel current Iap of sufficient size flows through the variable resistance element MTJ, the resistance of the variable resistance element MTJ may not be set to the anti-parallel resistance Rap. In these cases, the data read from the memory cell MC may be bit "0". Similarly, when the bit "0" is written into the memory cell MC, the variable resistance element MTJ may not have a parallel resistance Rp due to various factors of the memory cell MC. That is, the write failure of the memory cell MC may occur randomly.

[0066] Figure 1 The test device 110 may iteratively perform an operation of detecting a failed cell in the memory cell MC by iteratively performing an operation of writing and checking a test pattern for the memory cell MC, and may perform a repair operation or a masking operation according to the number of failed cells detected. The operation of the test device 110 will be described more fully below.

[0067] Figure 4 Show Figure 1 Flow chart of the operation of the test device. Figure 1 and Figure 4In operation S10, the test device 110 iteratively performs a pattern write operation on the memory device 120. For example, for the purpose of detecting a write failure of the memory device 120, the test device 110 may perform a pattern write operation. In an exemplary embodiment, a test pattern used in a current pattern write operation may be generated based on a result of a previous pattern write operation. That is, a test pattern used in a current pattern write operation may be generated based on a result of a previous pattern write operation so that a write operation or a rewrite operation on a failed cell is skipped. Operation S10 will be described more fully below with reference to the accompanying drawings.

[0068] In operation S11, the test device 110 detects fault information from the memory device 120. For example, while the pattern write operation is iteratively performed in operation S10, when the rewrite operation of a specific memory cell determined to be a faulty cell at least once is skipped, information indicating that the specific memory cell is a faulty cell (i.e., fault information) may be maintained at the specific memory cell itself. In other words, in a test operation to determine whether a bit "1" is normally written in a memory cell MC, in the case where the pattern write operation is iteratively performed in operation S10, data read from a specific memory cell to which the bit "1" is not normally written in at least one iterative operation may be a bit "0". That is, information indicating that the specific memory cell is a faulty cell (i.e., fault information) may be detected from the memory cell MC itself. In this case, a separate ECC operation or a separate storage space for storing faulty cell information may not be required.

[0069] In operation S12, the test device 110 performs a repair operation or a shielding operation on the memory device 120 based on the failure information. For example, in a case where the number of failed cells determined for each specific unit (e.g., ECC block unit or data word unit) based on the failure information from the memory device 120 exceeds a reference value, the test device 110 may perform a repair operation or a shielding operation on the memory device 120. Figures 19 to 20 The manner in which a repair operation or a masking operation may be performed on the memory device 120 is more fully described.

[0070] Figure 5 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation. Figure 6 Show description according to Figure 5 1. For convenience of description, it is assumed that a pattern write operation is performed on eight memory cells MC1 to MC8 connected to a specific word line (e.g., the first word line WL1) of the memory device 120. However, the inventive concept is not limited thereto. For example, one pattern write operation may be performed in units of a plurality of memory cells or a plurality of word lines.

[0071] Hereinafter, in order to provide a clear description of an embodiment of the inventive concept, it is assumed that the test device 110 tests whether the variable resistance element MTJ of each memory cell MC is normally switched from a parallel state to an antiparallel state (i.e., whether the bit "1" is normally written into each memory cell MC). That is, the initial test pattern (e.g., a default pattern) generated by the test device 110 may be a bit stream consisting of a bit "1". After the test pattern is written into the memory cell MC, in the case where a bit "0" is read from a specific memory cell in the memory cell MC, the specific memory cell may be a faulty cell. However, the inventive concept is not limited thereto. For example, the initial test pattern may be implemented in various forms according to the test type or scheme (e.g., a bit stream or a random pattern consisting of a bit "0"). In an exemplary embodiment, the size or length of the test pattern may be predetermined (or may be set to a fixed size or length). The given size or length may be a unit of an error correction operation performed by an error correction code (ECC) engine (e.g., a data word or an ECC block). Alternatively, the given size or length may be a word line unit.

[0072] Hereinafter, for convenience of description, the terms "test pattern", "pattern" and "data" may be used interchangeably. These terms may have the same meaning or different meanings according to the context of the embodiment, and the meaning of each term may be understood according to the context of the embodiment to be described.

[0073] Hereinafter, in order to provide a clear understanding of the inventive concept, an embodiment in which a write operation or a rewrite operation to a faulty cell is skipped will be described. However, the inventive concept is not limited thereto. For example, the rewrite operation to a specific memory cell being skipped may mean skipping the operation of writing an expected test pattern. Alternatively, the rewrite operation to a specific memory cell being skipped may mean skipping the operation of intentionally writing fault information into a specific memory cell. For example, in the case where the data read by the test operation associated with the test pattern [11111111] is [11110111], the next test pattern may be set to [1111X111] (or [11110111]). In this case, the memory cell corresponding to the bit value "1" may store information for testing whether the bit "1" is normally written, and the memory cell corresponding to the bit value "0" or the bit value "X" may be configured to store the fault information generated thereby. That is, as described above, the rewrite operation to a specific memory cell (i.e., the faulty cell) being skipped may mean intentionally writing the fault information occurring at the specific memory cell into the specific memory cell itself.

[0074] As described above, in order to maintain the failure information at a specific memory cell (i.e., a failure cell), a test pattern may be generated so that a rewrite operation on the specific memory cell is skipped or the failure information is intentionally written into the specific memory cell. That is, the reference mark "X" described in the following embodiments or drawings may indicate failure information about the corresponding memory cell, and the bit value corresponding to the reference mark "X" (i.e., failure information) may be written into the memory cell corresponding to the reference mark "X".

[0075] Reference Figure 1 , Figure 4 , Figure 5 and Figure 6 , in operation S101, the variable "k" is set to "1". In an exemplary embodiment, the variable "k" may be used to describe or indicate an iteration of a pattern write operation, and it may be understood that the inventive concept is not limited thereto.

[0076] In operation S102, the test device 110 generates a k-th pattern. For example, since the variable "k" is "1", in operation S102, the pattern generator 111 of the test device 110 may generate a first pattern (i.e., a default pattern). In this case, as described above, since the test device 110 tests whether the memory cells MC1 to MC8 of the memory device 120 normally store the bit "1", the first pattern (i.e., the default pattern) may have a value of [11111111].

[0077] In operation S111, the test device 110 performs a k-th pattern write operation on the memory device 120. For example, the test device 110 may write the first pattern thus generated (i.e., the default pattern [11111111]) into the memory cells MC1 to MC8 of the memory device 120. In an exemplary embodiment, the test device 110 writing the pattern into the memory cells MC1 to MC8 may include: sending the pattern and a write command to the memory device 120 at the test device 110; and writing the pattern into the memory cells MC1 to MC8 at the memory device 120 in response to the write command.

[0078] In detail, Figure 6 As shown, the test device 110 may write the first pattern PT1 [11111111] into the memory cells MC1 to MC8 connected to the first word line WL1 of the memory device 120. In this case, the memory cells MC1 to MC8 may be written by referring to Figures 2 to 3BThe described write operation (e.g., providing an anti-parallel current Iap to each of the memory cells MC1 to MC8) stores the first pattern PT1 [11111111]. After the first pattern PT1 is written into the memory cells MC1 to MC8, the variable resistance element MTJ of the fifth memory cell MC5 may be in a parallel state, and the remaining memory cells MC1 to MC4 and MC6 to MC8 may be in an anti-parallel state. That is, a write failure "F" may occur at the fifth memory cell MC5, while the remaining memory cells MC1 to MC4 and MC6 to MC8 may store a bit "1" normally.

[0079] Thereafter, in operation S112, the test device 110 performs a read operation on the memory device 120. For example, the test device 110 may read data written in the memory cells MC1 to MC8 in which the first pattern PT1 is written. Figure 6 As shown, the first pattern PT1 [11111111] may be written into the memory cells MC1 to MC8, and then data may be read from the memory cells MC1 to MC8. In this case, since a write failure occurs at the fifth memory cell MC5, the read data may be [11110111].

[0080] Thereafter, in operation S113, it is determined whether the variable "k" is equal to a maximum value. When the variable "k" is not equal to the maximum value (No in operation S113), thereafter in operation S114, the variable "k" is increased by up to "1". Thereafter, in operation S115, the test device 110 generates a k-th pattern based on the read data. In this case, the k-th pattern may be generated so that the rewrite operation on the failed cell is not performed or is skipped. For example, Figure 6 As shown, the pattern generator 111 of the test device 110 may generate a second pattern PT2 based on the read data (e.g., [11110111]). Here, the second pattern PT2 may be [1111X111]. In an exemplary embodiment, the reference mark "X" is used to emphasize that the rewrite operation of the corresponding memory cell is skipped, but the present inventive concept is not limited thereto. Figure 6 In the embodiment of the present invention, the reference mark "X" may be replaced by a bit "0". That is, since a write failure occurs at the fifth memory cell MC5 in the previous pattern write operation (i.e., since the fifth memory cell MC5 is a failed cell), the second pattern PT2 [1111X111] may be generated so that the rewrite operation on the fifth memory cell MC5 is not performed or is skipped.

[0081] Afterwards, the testing device 110 performs operation S111. For example, Figure 6As shown, the test device 110 may write the second pattern PT2 into the memory cells MC1 to MC8 connected to the first word line WL1. In this case, since the memory cells MC1 to MC8 are in a state of storing the value [11110111] and are currently testing whether the bit "1" is normally written, the write-back operation may be first performed on the memory cells MC1 to MC8 so that the memory cells MC1 to MC8 store the bit "0", and then the second pattern PT2 [1111X111] may be written into the memory cells MC1 to MC8. In an exemplary embodiment, the write-back operation may indicate an operation of writing an inversion pattern corresponding to an inversion version of a default pattern (for example, when the default pattern is [11111111], the inversion pattern is [00000000]) into the memory cells MC1 to MC8. In this case, since the bit value of the second pattern PT2 corresponding to the fifth memory cell MC5 is "X", the write-back operation, the write operation, or the rewrite operation on the fifth memory cell MC5 may be skipped. That is, in the case where the second pattern PT2 is written into the memory cells MC1 to MC8, the write operation or rewrite operation of the memory cell (e.g., the fifth memory cell MC5) determined to be a failed cell in the previous pattern write operation may be skipped. In this case, the fifth memory cell MC5 may maintain a parallel state (i.e., a state corresponding to bit "0"). In other words, the fifth memory cell MC5 itself may be in a state of storing failure information indicating a failed cell.

[0082] In an exemplary embodiment, in the operation of writing the second pattern PT2, such a situation may occur that, for example, a write failure "F" occurs at the third memory cell MC3. In this case, as described above, the third memory cell MC3 may maintain a parallel state (i.e., a state corresponding to bit "0"). As a result, after the second pattern PT2 is completely written, the data read from the memory cells MC1 to MC8 may be [11010111]. Although not shown in the figure, the third pattern to be used in the next pattern write operation may be [11X1X111]. In the case where the third pattern is written into the memory cells MC1 to MC8, the write operation of the third memory cell MC3 and the fifth memory cell MC5 determined as failed cells in the previous pattern write operation may be skipped.

[0083] When the determination result of operation S113 indicates that the variable "k" is equal to the maximum value (ie, in the case where the pattern writing operation is completely iterated a given number of times), the test device 110 may perform operation S11 and possibly operation S12 (refer to Figure 4 ).

[0084] That is, in the case where the above-mentioned pattern write operation is completely iterated, the bit value read from the memory cell determined as a failed cell at least once may be a bit "0". In this case, the test device 110 may compare the number of 0s (i.e., the number of failed cells) with a reference value for each given unit (e.g., an ECC block unit or a data word unit), and may perform a repair operation or a masking operation on the memory device 120 when the number of 0s (i.e., the number of failed cells) exceeds the reference value.

[0085] As described above, the test device 110 may generate a test pattern to be used in the current pattern write operation based on the result of the previous pattern write operation. In this case, the test pattern may be generated so that a write operation or a rewrite operation on a memory cell that was determined to be a failed cell at least once in the previous pattern write operation is not performed or is skipped. In this case, in the iterative pattern write operation, the memory cell that was determined to be a failed cell at least once may maintain a failed state or may be in a state of storing failure information. Therefore, since a memory cell with a high probability of occurrence of a write failure is detected in a specific unit through the iteration of the above-mentioned pattern write operation, the reliability of the test operation for detecting a write failure of the memory device 120 may be improved.

[0086] Figure 7 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation. Figure 8 Show description according to Figure 7 Below, for ease of illustration and for convenience of description, an embodiment of the inventive concept will be described based on a pattern PT used in a test process of the test device 110 and data read from the memory device 120. However, the inventive concept is not limited thereto. Figure 6 As described above, it can be understood that the pattern PT is generated by the test device 110 , and the test device 110 writes the generated pattern PT into the memory device 120 and reads data from the memory device 120 .

[0087] Reference Figure 1 , Figure 4 , Figure 7 and Figure 8 , the testing device 110 performs operations S101, S102, S121, and S122. Figure 5 Operation S101 and operation S102 are described, and operation S121 and operation S122 are similar to Figure 5 Therefore, additional description will be omitted to avoid redundancy.

[0088] In operation S123, the test device 110 stores the data read by operation S122. Thereafter, the test device 110 performs operations S124 and S125, and operations S124 and S125 are respectively similar to Figure 5 Therefore, additional description will be omitted to avoid redundancy.

[0089] In operation S126, the test device 110 generates a kth pattern based on the stored data. In this case, the kth pattern may be generated so that the rewrite operation on the specific failed cell is skipped. Thereafter, the test device 110 performs operation S121. That is, the test device 110 may iteratively perform the pattern write operation up to a given number of times.

[0090] In an exemplary embodiment, a specific failed cell may indicate a memory cell that is determined to be a failed cell a given number of times while the pattern write operation is iteratively performed. Figure 8 As shown, in the first pattern write operation, the test device 110 may generate [11111111] as the first pattern (i.e., the default pattern), and may write the first pattern [11111111] into the memory cells MC1 to MC8. Thereafter, the test device 110 may read data from the memory cells MC1 to MC8. In this case, the read data may be [11110111]. The read data being [11110111] may mean that a write failure occurs at the fifth memory cell MC5 among the memory cells MC1 to MC8. The test device 110 may store the data [11110111] read as a result of the first pattern write operation in a separate storage circuit. For example, in some embodiments, the test device 110 stores the data read as a result of the first pattern write operation in a separate storage circuit in the test device 110.

[0091] Thereafter, in the second pattern write operation, the test device 110 may generate [11111111] as the second pattern based on the stored data (i.e., [11110111]). The second pattern [11111111] thus generated may be written into the memory cells MC1 to MC8. Thereafter, the test device 110 may read data from the memory cells MC1 to MC8. In this case, the read data may be [11111101]. The read data being [11111101] may mean that a write failure occurs at the seventh memory cell MC7 among the memory cells MC1 to MC8. The data [11111101] read as a result of the second pattern write operation may be stored in a separate storage circuit.

[0092] Thereafter, in the third pattern write operation, the test device 110 may generate [11111111] as the third pattern based on the stored data (i.e., [11110111] and [11111101]). The third pattern [11111111] thus generated may be written into the memory cells MC1 to MC8. Thereafter, the test device 110 may read data from the memory cells MC1 to MC8. In this case, the read data may be [11110111]. The read data being [11110111] may mean that a write failure occurs at the fifth memory cell MC5 among the memory cells MC1 to MC8. The data [11110111] read as a result of the third pattern write operation may be stored in a separate storage circuit.

[0093] Thereafter, in a fourth pattern write operation, the test device 110 may generate [1111X111] as a fourth pattern based on the stored data (i.e., [11110111], [11111101], and [11110111]). For example, the test device 110 may check that a write failure occurred twice at the fifth memory cell MC5 in a previous pattern write operation based on the stored data. In this case, the test device 110 may generate a fourth pattern (i.e., [1111X111]) so that a write operation to the fifth memory cell MC5 is skipped in a next pattern write operation. As described above, a reference mark or bit value corresponding to "X" may be used to emphasize that a write operation to the corresponding memory cell is skipped and may be replaced by a value of a bit "0".

[0094] The test device 110 may write the fourth pattern (i.e., [1111X111]) into the memory cells MC1 to MC8. In this case, the write operation to the fifth memory cell MC5 corresponding to "X" may be skipped. Afterwards, the test device 110 may read data from the memory cells MC1 to MC8. The read data may be [11110110]. The reason why the value corresponding to the fifth memory cell MC5 is bit "0" is that the write operation to the fifth memory cell MC5 is skipped, and the value corresponding to the eighth memory cell MC8 is bit "0" may indicate that a write failure occurs at the eighth memory cell MC8. This may be checked by comparing the written fourth pattern with the read data. The read data [11110110] may be stored in a separate storage circuit.

[0095] Thereafter, in the fifth pattern write operation, the test device 110 may generate [1111X111] as the fifth pattern based on the stored data (i.e., [11110111], [11111101], [11110111], and [11110110]), and may write the fifth pattern thus generated into the memory cells MC1 to MC8. Thereafter, the test device 110 may read data from the memory cells MC1 to MC8, and the read data may be [11110101]. The meaning of each bit of the read data is described above, and therefore, additional description will be omitted to avoid redundancy.

[0096] Thereafter, in the sixth pattern write operation, the test device 110 may generate [1111X1X1] as the sixth pattern based on the stored data (i.e., [11110111], [11111101], [11110111], [11110110], and [11110101]). In this case, as described above, the reason why the bit values ​​corresponding to the fifth memory cell MC5 and the seventh memory cell MC7, respectively, are "X" is that a write failure occurs twice or more at each of the fifth memory cell MC5 and the seventh memory cell MC7 in the previous pattern write operation, and is to skip the write operation to the fifth memory cell MC5 and the seventh memory cell MC7. The test device 110 may write the sixth pattern into the memory cells MC1 to MC8. Thereafter, the test device 110 may read data from the memory cells MC1 to MC8, and the read data may be [11110100]. The meaning of each bit of the read data is described above, and therefore, additional description will be omitted to avoid redundancy.

[0097] As described above, the test device 110 may generate a test pattern for a current pattern write operation based on the result of a previous pattern write operation. In detail, the test device 110 may generate a pattern to be used in the current pattern write operation based on the result of a previous pattern write operation, so that the write operation to the memory cell where the write failure occurs up to a threshold number of times or more may be skipped. In an exemplary embodiment, the threshold number of times for determining the memory cell to be skipped for the write operation may be determined based on various conditions. For example, the threshold number of times may be determined based on at least one of the number of iterations of the pattern write operation, the error correction capability of the ECC engine, the size of the ECC block, the size of the data word, and the number of memory cells connected to one word line.

[0098] Although not shown in the figure, the test device 110 may generate a pattern to be used in the current pattern write operation based on the results belonging to a specific range among the results of the previous pattern write operation. For example, it is assumed that the test device 110 iteratively performs the pattern write operation "n" times on the memory cells MC1 to MC8. In this case, the test device 110 may generate a pattern for the kth pattern write operation based on the results of the i-th pattern write operation to the (k-1)th pattern write operation. That is, in the case of generating a pattern to be used in the current pattern write operation, the test device 110 may generate a pattern based on the results belonging to a specific period among the results of the previous pattern write operation.

[0099] Although not shown in the figure, the test device 110 may generate a pattern based on the result of the previous pattern write operation so that the write operation to the memory cell where the write failure occurs continuously (e.g., successively) a given number of times is skipped. That is, the continuous occurrence of the write failure at a specific memory cell for a given number of times may mean that the probability of the write failure occurring at the specific memory cell is very high. Therefore, the test device 110 may allow the specific memory cell to maintain the failure information during the iterative pattern write operation by skipping the write operation to the specific memory cell where the probability of the write failure occurring is high.

[0100] Fig. 9 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation. Fig.10 It is described based on Fig. 9 For simplicity of illustration and for convenience of description, additional and / or repeated descriptions associated with the above-mentioned components will be omitted to avoid redundancy.

[0101] Reference Figure 1 , Figure 4 , Fig. 9 and Fig.10 , the testing device 110 performs operations S101, S102, and S131 to S134. Figure 5 Operation S101 and operation S102 are described, and operations S131 to S134 are similar to Figure 5 Therefore, additional description will be omitted to avoid redundancy.

[0102] In operation S135, the test device 110 performs a pre-read operation on the memory device 120. For example, the pre-read operation in operation S135 may be characterized as a pre-read operation performed before the subsequent k-th pattern write operation in operation S131. For example, the read operation in operation S132 may be a post-read operation performed immediately after the pattern write operation is completed, and the read operation in operation S135 may be a pre-read operation after a given time has elapsed from the time when the pattern write operation is completed. In an exemplary embodiment, the read results in operation S132 and operation S135 may be temporarily stored in a separate storage circuit.

[0103] In operation S136, the test device 110 may generate a kth pattern based on the read data of the post-read operation and the pre-read operation. In this case, the kth pattern may be generated so that a rewrite operation on a failed cell is skipped.

[0104] For example, Fig.10 As shown, in the first pattern write operation, the test device 110 may generate [11111111] as the first pattern (i.e., the default pattern). The test device 110 may write the first pattern [11111111] into the memory cells MC1 to MC8 of the memory device 120, and then may immediately read data from the memory cells MC1 to MC8 (i.e., a read-after operation). In this case, the read data may be [11110111], which may mean that a write failure occurs at the fifth memory cell MC5.

[0105] Afterwards, in the second pattern write operation, the test device 110 may read data from the memory cells MC1 to MC8 before generating the second pattern (i.e., a pre-read operation). In this case, the read data of the second pattern write operation (i.e., pre-read data) may be [11110110], which may mean that a write failure occurs at the fifth memory cell MC5 and the eighth memory cell MC8. In an exemplary embodiment, a write failure detected from the data read through the post-read operation may mean a write failure that occurs during or immediately after the write operation (e.g., an immediate write failure). In contrast, a write failure detected from the data read through the pre-read operation may mean a write failure that does not occur during or immediately after the write operation, but occurs over time (e.g., a delayed write failure). That is, by reading the data through the post-read operation in the first pattern write operation, it may be checked that an immediate write failure occurs at the fifth memory cell MC5, and by reading the data through the pre-read operation in the second pattern write operation, it may be checked that a delayed write failure occurs at the eighth memory cell MC8.

[0106] Then, the test device 110 may generate [1111X11X] as the second pattern based on the result of the post-read operation in the previous pattern write operation (e.g., [11110111]) and the result of the pre-read operation in the current pattern write operation (e.g., [11110110]). In this case, the second pattern [1111X11X] may be set so that the rewrite operation of the fifth memory cell MC5 and the eighth memory cell MC8 in which the write failure occurs is skipped. The test device 110 may write the second pattern [1111X11X] into the memory cells MC1 to MC8, and may perform the post-read operation on the memory cells MC1 to MC8 to read the data [11110110].

[0107] Afterwards, as in the above description, the test device 110 may perform a third pattern write operation. For example, the test device 110 may perform a pre-read operation on the memory cells MC1 to MC8 to read data [11010110] for the third pattern write operation. In this case, the data [11010110] may mean that a delayed write failure occurs at the third memory cell MC3. As in the above description, the test device 110 may generate a third pattern [11X1X11X] so that the rewrite operation on the third memory cell MC3, the fifth memory cell MC5, and the eighth memory cell MC8 is skipped, and the generated pattern may be written into the memory cells MC1 to MC8. Afterwards, the test device 110 may perform a post-read operation on the memory cells MC1 to MC8 to read data [10010110]. The data [10010110] may mean that an immediate write failure occurs at the second memory cell MC2.

[0108] Although not shown in the figure, when the above-mentioned pattern write operation is iteratively performed, the test device 110 can detect memory cells in which various types of write failures (for example, immediate write failures and delayed write failures) occur, and can skip the rewrite operation of the memory cells in which the write failures occur in the pattern write operation.

[0109] Fig.11 Shown with Figure 4 Operation S10 corresponds to a flow chart of an iterative pattern write operation. Fig.12 Show description according to Fig.11 For simplicity of illustration and for convenience of description, additional and repeated descriptions associated with the above-mentioned components will be omitted to avoid redundancy.

[0110] Reference Figure 1 , Figure 4 , Fig.11 and Fig.12 , the testing device 110 may perform operations S101, S102, and operations S141 to S147. Figure 5Operation S101 and operation S102 are described, except that Fig.11 In addition to storing the read results in operations S143 and S147, operations S141 to S147 are similar to Figure 5 Therefore, additional description will be omitted to avoid redundancy.

[0111] In operation S148, the test device 110 generates a first sub-pattern based on the stored result of the post-read operation, and generates a second sub-pattern based on the stored results of the post-read operation and the pre-read operation. Thereafter, in operation S149, the test device 110 generates a k-th pattern based on the first sub-pattern and the second sub-pattern. Thereafter, the test device 110 may proceed to operation S141.

[0112] In an exemplary embodiment, when a pattern is generated, different conditions may be applied according to the type of write failure through operations S148 and S149. Fig.12 As shown, in the first pattern write operation, the test device 110 may generate [11111111] as the first pattern (i.e., the default pattern), and may write the first pattern [11111111] into the memory cells MC1 to MC8. Thereafter, the test device 110 may perform a post-read operation on the memory cells MC1 to MC8 to read the data [11110111]. The meaning of each bit of the read data is similar to that described above, and therefore, additional description will be omitted to avoid redundancy.

[0113] Thereafter, in the second pattern write operation, the test device 110 may perform a pre-read operation on the memory cells MC1 to MC8 to read the data [1110110]. The test device 110 may generate [1111X111] as the first sub-pattern based on the result of the previous post-read operation (e.g., [11110111]) (i.e., the post-read result in the first pattern write operation). In this case, the first sub-pattern [1111X111] may be the same as or similar to the result of the previous post-read operation. That is, in the first sub-pattern, the bit value corresponding to the failed cell may be set to a reference mark "X" based on the result of the previous post-read operation. In an exemplary embodiment, in the first sub-pattern, the memory cell corresponding to the reference mark "X" may be a memory cell corresponding to an immediate write failure or a memory cell whose rewrite operation is skipped in the previous pattern write operation.

[0114] The test device 110 may generate a second sub-pattern based on the result of the post-read operation in the previous pattern write operation and the result of the pre-read operation in the current pattern write operation. For example, in the second pattern write operation, the result of the post-read operation in the previous pattern write operation (i.e., the first pattern write operation) may be [11110111], and the result of the pre-read operation in the current pattern write operation (i.e., the second pattern write operation) may be [11110110]. The second sub-pattern may be generated by performing a logic operation (e.g., XNOR or XOR) on the above two results. In the above example, the second sub-pattern [1111111X] may be generated. This may mean that a delayed write failure occurs at the eighth memory cell MC8.

[0115] The test device 110 may generate a pattern to be used in the current pattern write operation based on the first sub-pattern and the second sub-pattern. For example, as described above, the first sub-pattern may include information about a memory cell corresponding to an immediate write failure or a memory cell in which a rewrite operation is skipped, and the second sub-pattern may include information about a memory cell corresponding to a delayed write failure. The test device 110 may apply a relatively small first reference value for an immediate write failure, and may apply a relatively large second reference value for a delayed write failure.

[0116] For the convenience of description, Fig.12 In the embodiment of , it is assumed that the first reference value is "1" and the second reference value is "2". In the second pattern write operation, the first sub-pattern may include information about the fifth memory cell MC5 where an immediate write failure occurs, and the second sub-pattern may include information about the eighth memory cell MC8 where a delayed write failure occurs. In this case, the test device 110 may generate a test pattern [1111X111] so that the rewrite operation of the fifth memory cell MC5 where an immediate write failure occurs is skipped. The second pattern [1111X111] may be written into the memory cells MC1 to MC8, and the data read from the memory cells MC1 to MC8 by the read-after operation may be [11100111].

[0117] Afterwards, in the third pattern write operation, the data read by the pre-read operation may be [11100110]. In this case, as in the above description, the first sub-pattern may be [111XX111], and the second sub-pattern may be [1111111X]. In this case, it may be checked by the first sub-pattern whether an immediate write failure occurs at the fourth memory cell MC4 and the fifth memory cell MC5, or the fourth memory cell MC4 and the fifth memory cell MC5 are memory cells in which the rewrite operation is skipped (i.e., a write failure occurs). It may be checked by the second sub-pattern whether a write failure that is delayed twice occurs at the eighth memory cell MC8. In this case, the test device 110 may generate a third pattern [111XX111X] so that the rewrite operations of the fourth memory cell MC4, the fifth memory cell MC5, and the eighth memory cell MC8 are skipped. The third pattern thus generated may be written into the memory cells MC1 to MC8, and data [11100110] may be read from the memory cells MC1 to MC8 by the post-read operation.

[0118] Afterwards, in the fourth pattern write operation, the result of the pre-read operation may be [11000110], the first sub-pattern may be [111XX11X], the second sub-pattern may be [11X11111], the fourth pattern may be [111XX11X], and the data corresponding to the result of the post-read operation may be [11100110]. The technical meanings of each bit value and each pattern are similar to those described above, and therefore, additional descriptions will be omitted to avoid redundancy.

[0119] The embodiment in which the test device 110 iteratively performs the pattern write operation for a given number of times is described above, but the inventive concept is not limited thereto. For example, although not shown in the figure, when the number of memory cells determined as failed cells exceeds a reference value while the test device 110 iteratively performs the pattern write operation, the test device 110 may stop the remaining pattern write operations and may perform a repair operation or a masking operation on the memory device 120.

[0120] As described above, the test device 110 may determine a failed cell based on a condition that may vary according to the type of write failure (e.g., a reference value associated with the number of occurrences may vary) during iterative writing of the test pattern. In this case, the test device 110 may generate a test pattern so that a rewrite operation on a memory cell determined to be a failed cell is skipped.

[0121] Fig.13 A flowchart illustrating an operation of a testing device according to an embodiment of the inventive concept. Fig.14 Show description according to Fig.13 For convenience of description, additional and repeated descriptions associated with the above components will be omitted to avoid redundancy. Figure 1 , Fig.13 and Fig.14 , in operation S210 , the test device 110 iteratively performs a pattern writing operation on the memory device 120 and an operation of storing a location of a failed cell.

[0122] In operation S220 , the test device 110 performs a repair operation or a masking operation on the memory device 120 based on location information about the failed cell.

[0123] For example, Fig.14 As shown, the test device 110 may write a default pattern (e.g., [11111111]) into the memory cells MC1 to MC8 by a first default pattern write operation. In this case, a write failure may occur at the fifth memory cell MC5. The test device 110 may store information indicating that a write failure has occurred at the fifth memory cell MC5. For example, the test device 110 may store information indicating that a write failure has occurred at the fifth memory cell MC5 by marking the fifth bit B5 of the bitmap BM. Thereafter, the test device 110 may write a default pattern (e.g., [11111111]) into the memory cells MC1 to MC8 by a second default pattern write operation. In this case, a write failure may occur at the third memory cell MC3. The test device 110 may store information indicating that a write failure has occurred at the third memory cell MC3 by marking the third bit B3 of the bitmap BM. For example, in some embodiments, the test device 110 stores the bitmap BM in a separate storage circuit in the test device 110.

[0124] As described above, the test device 110 may store position information about the failed cells in a separate bitmap BM. In this case, even if the failed cells do not occur simultaneously, the detection accuracy of the write failure may be improved because the positions of the failed cells occurring in the iteration of the pattern write operation are accumulated.

[0125] Fig.15 FIG. 1 is a block diagram of a memory device according to an embodiment of the inventive concept. Fig.15 , the memory device 220 may include a memory cell array 221, an address decoder 222, a write driver / sense amplifier 223, an input / output (I / O) circuit 224, a control logic circuit 225, and a repair logic (e.g., circuit) 226. The input / output circuit 224 may include a test register 227. Figure 2 The memory cell array 221, the address decoder 222, the write driver / sense amplifier 223, the input / output circuit 224, the control logic circuit 225, and the repair logic 226 are described, and therefore, additional and repeated descriptions will be omitted to avoid redundancy.

[0126] Reference Figures 1 to 14 The embodiment in which the test device 110 generates a pattern or a test pattern so that the rewrite operation on the failed cell is skipped is described. However, the inventive concept is not limited thereto. For example, the operation of generating a pattern so that the rewrite operation on the failed cell is skipped may be performed by the memory device 220.

[0127] For example, the test register 227 may be configured to temporarily store data read from the memory cell array 221 during a test operation of the memory device 220. The memory device 220 may be configured to temporarily store data read from the memory cell array 221 by Figure 1 ) is combined with the data stored in the test register 227 to generate a pattern. In this case, the pattern can be generated so that the rewrite operation of the failed cell is skipped. The following will describe the manner in which the memory device 220 can generate a pattern using the test register 227 with reference to the accompanying drawings.

[0128] Fig.16 Show Fig.15 A flow chart of the operation of a memory device. Fig.17 Show description according to Fig.16 An illustration of the operation of a flowchart.

[0129] Reference Figure 1 as well as Figures 15 to 17 In operation S310, the memory device 220 receives a default pattern from the test device 110. In an exemplary embodiment, the default pattern may be set differently according to a test target or scheme of the test device 110. For example, as described above, the pattern for determining whether a bit "1" is normally stored in a memory cell may be a bit stream consisting of bits "1" (i.e., all 1 bits). For example, the default pattern may be received from the test device 110 (see Figure 1 ) or a memory controller external to the memory device 220 receives the default pattern.

[0130] In operation S320, the memory device 220 generates a test pattern based on the default pattern and the test register 227. For example, the memory device 220 may iteratively perform a pattern write operation under the control of the test device 110. In this case, the test register 227 may be configured to store the result of the previous pattern write operation (i.e., data including information about the failed cell). The memory device 220 may generate a test pattern by combining the result of the previous pattern write operation stored in the test register 227 with the default pattern. In this case, the test pattern may be generated so that the rewrite operation on the failed cell is skipped. For example, the control logic circuit 225 may control the drive circuit 223 and the input / output circuit 224 including the test register 227 to generate a test pattern and perform a rewrite operation.

[0131] In operation S330, the memory device 220 performs a write operation based on the test pattern. In an exemplary embodiment, since the test pattern generated in operation S320 is set such that a rewrite operation on a failed cell is skipped, a rewrite operation on a failed cell may be skipped during the write operation in operation S330.

[0132] In operation S340, the memory device 220 performs a read operation and stores a result of the read operation in the test register 227. In an exemplary embodiment, the result of the read operation stored in the test register 227 may include information about a failed cell occurring in the write operation and the previous write operation in operation S330. The result of the read operation stored in the test register 227 may be used to generate a test pattern for the next pattern write operation.

[0133] For example, Fig.17 As shown, in operation ①, the memory device 220 writes a default pattern (e.g., [11111111]) into the memory cells MC1 to MC8 connected to the first word line WL1. For example, a write failure may occur at the fifth memory cell MC5. In this case, the data read from the memory cells MC1 to MC8 may be [11110111]. Thereafter, in operation ②, the memory device 220 stores the data read from the memory device 220 (i.e., [11110111]) in the test register 227.

[0134] Thereafter, in operation ③, the memory device 220 receives a default pattern (i.e., [11111111]) from the test device 110. Thereafter, in operation ④, the memory device 220 generates a test pattern based on the received default pattern (i.e., [11111111]) and the data stored in the test register 227. In this case, since the data stored in the test register 227 indicates that a write failure occurs at the fifth memory cell MC5, the test pattern may be generated so that the rewrite operation on the fifth memory cell MC5 is skipped. That is, the test pattern thus generated may be [1111X111].

[0135] Thereafter, in operation ⑤, the memory device 220 writes the test pattern into the memory cells MC1 to MC8. In this case, since the test pattern is generated so that the rewrite operation on the fifth memory cell MC5 is skipped, during the write operation ⑤, the rewrite operation or the write operation on the fifth memory cell MC5 (i.e., the failed cell) can be skipped.

[0136] As described above, the memory device 220 according to an embodiment of the inventive concept may separately store information about a failed cell using the test register 227 , and the memory device 220 may generate a test pattern using the test register 227 so that a rewrite operation on the failed cell is skipped.

[0137] In an exemplary embodiment, the test register 227 may be a dedicated storage circuit for generating a test pattern at the memory device 220. Alternatively, although not shown in the figure, the test register 227 may be a register for reading / writing, which is included in the input / output circuit 224 for performing a read operation or a write operation at the memory device 220.

[0138] Fig.18A and Fig.18B A diagram describing a test operation according to an embodiment of the present invention is shown. For ease of description, it is assumed that the test operation is performed in units of word lines of a memory device. In addition, for simplicity, Fig.18A and Fig.18B Only word lines of the memory device are shown in FIG. However, the inventive concept is not limited thereto.

[0139] Reference Figure 1 , Fig.18A and Fig.18B , the test device 110 may perform a test operation on the memory cells connected to the first to third word lines WL1 to WL3 of the memory device 120. In this case, Fig.18A As shown, the test device 110 performs a pattern write operation on the first word line WL1 for a given number of times (①). In an exemplary embodiment, the test device 110 may perform a pattern write operation on the first word line WL1 for a given number of times (①). Figures 1 to 17 A method of operation is described to perform iterations of a pattern write operation.

[0140] Afterwards, the test device 110 checks the faulty cells associated with the first word line WL1 (②). For example, in a case where the iteration of the pattern write operation associated with the first word line WL1 is completed, the faulty cells among the memory cells connected to the first word line WL1 may be in a state of storing a value different from the value of the default pattern. The test device 110 may read data from the memory cells connected to the first word line WL1, and may determine the number of faulty cells based on the number of cells having values ​​different from the default pattern. In an exemplary embodiment, when the number of faulty cells exceeds a reference value, the test device 110 may perform a repair operation or a shielding operation on the memory device 120.

[0141] Afterwards, the test device 110 iteratively performs a pattern write operation associated with the second word line WL2 (③). Afterwards, the test device 110 checks the faulty cell associated with the second word line WL2 (④). Afterwards, the test device 110 iteratively performs a pattern write operation associated with the third word line WL3 (⑤). Afterwards, the test device 110 checks the faulty cell associated with the third word line WL3 (⑥).

[0142] Alternatively, if Fig.18B As shown, the test device 110 may sequentially perform iterations of the pattern write operation for the first word line WL1 to the third word line WL3 (①→②→③). Thereafter, the test device 110 may sequentially perform a failed cell check for the first word line WL1 to the third word line WL3 (④→⑤→⑥). The above order of the test operation is exemplary, and the inventive concept is not limited thereto.

[0143] Fig.19 An exemplary diagram describing a repair operation on a memory device is shown. Figure 1 , Figure 2 and Fig.19 , when referring to Figures 1 to 18B The described test operation determines that when the number of failed cells in a given unit exceeds a reference value, the test device 110 may perform a repair operation on the memory device 120 .

[0144] For example, the memory cell array 121 of the memory device 120 may include a normal area and a spare area. The normal area may include a plurality of word lines WL1 to WLn, and the spare area may include a plurality of spare word lines RWL1 to RWLm. Hereinafter, for the purpose of illustration and for providing a clear description of the inventive concept only, an embodiment in which n=4 and m=3 will be described. However, the inventive concept is not limited thereto, and any number of word lines WL and spare word lines RWL may be included in the normal area and the spare area, respectively.

[0145] The test device 110 may perform a test operation on a normal area. In this case, the number of failed cells in the memory cells connected to the second word line WL2 may exceed a reference value. In this case, the test device 110 may replace the second word line WL2 with one (e.g., RWL1) of the spare word lines RWL1 to RWLm of the spare area. In an exemplary embodiment, replacing a word line may mean that when an address of a specific word line is applied, a spare word line is accessed instead of the specific word line. The word line replacement may be performed by the repair logic 126. That is, the test device 110 may set the repair logic 126 of the memory device 120 so that a word line (e.g., WL2) in which a number of failed cells equal to or greater than a reference value is detected is replaced with a spare word line (e.g., RWL1) of the spare area.

[0146] Fig. 20An exemplary diagram describing a shielding operation on a memory device is shown. Figure 1 , Figure 2 and Fig. 20 , the memory device 120 may be formed on the semiconductor wafer WF. That is, the semiconductor wafer WF may include a plurality of semiconductor chips CHIP, and each of the plurality of semiconductor chips CHIP may be the memory device 120 .

[0147] The test device 110 can be based on the reference Figures 1 to 18B The described operation method performs a test operation on a plurality of semiconductor chips CHIP included in a semiconductor wafer WF. In this case, in the case where a faulty cell detected from a specific semiconductor chip among the plurality of semiconductor chips CHIP cannot be repaired by a repair operation, the specific semiconductor chip may be shielded so that the specific semiconductor chip is not used. In an exemplary embodiment, the case where the detected faulty cell cannot be repaired by a repair operation may include at least one of various conditions such as a case where the number of word lines connected to the faulty cells whose number is equal to or greater than a reference value is greater than the number of spare word lines, a case where the faulty cells appear in the form of columns, and a case where the number of faulty cells is equal to or greater than a specific proportion of all memory cells.

[0148] Fig.21 FIG. 1 is a block diagram of a test system according to an embodiment of the present invention. Fig.21 , the test system 300 may include a test device 310 and a memory device 320. The test device 310 and the memory device 320 may be based on a reference Figures 1 to 20 Describes the test method to operate.

[0149] The test device 310 may include an ECC engine ECC1 configured to correct errors in data read from the memory device 320. Alternatively, the memory device 320 may include an ECC engine ECC2 configured to correct errors in data read from the memory cell. Figures 1 to 20 The reference value of the number of failed cells described may correspond to the error correction capability of the above-mentioned ECC engines ECC1 and ECC2. Alternatively, instead of determining the number of failed cells, the test device 310 may perform a repair operation or a masking operation according to whether an error of the read data is correctable by using the ECC engines ECC1 and ECC2.

[0150] Fig. 22 A block diagram of a memory system to which a memory device according to an embodiment of the inventive concept can be applied is shown. Fig. 22, the memory system 1000 may include a memory controller 1100 and a memory device 1200. The memory controller 1100 may store data in the memory device 1200 or may read data stored in the memory device 1200. The memory device 1200 may operate under the control of the memory controller 1100.

[0151] The memory controller 1100 may include an ECC engine ECCa configured to correct errors of data read from the memory device 1200. Alternatively, the memory device 1200 may include an ECC engine ECCb configured to correct errors of data read from the memory cell. Figures 1 to 20 The described reference value of the number of failed cells may correspond to the error correction capabilities of the above-mentioned ECC engines ECCa and ECCb.

[0152] Fig.23 FIG. 1 is a block diagram of a memory system according to an embodiment of the inventive concept. Fig.23 , the memory system 2000 may include a memory controller 2100 and a memory device 2200. Fig. 22 The memory controller 2100 and the memory device 2200 are described, and thus, additional description will be omitted to avoid redundancy.

[0153] The memory device 2200 may include a built-in self-test logic (BIST) 2210. The built-in self-test logic (eg, circuit) 2210 may be configured to perform a self-test on the memory device 2200. In an exemplary embodiment, the built-in self-test logic 2210 may be based on a reference Figures 1 to 19 The memory device 2200 may be tested by the test operation described above. That is, the built-in self-test logic 2210 may iteratively perform pattern write operations on memory cells, and may generate a test pattern so that a rewrite operation on a failed cell is skipped while the pattern write operation is iteratively performed. The built-in self-test logic 2210 may perform a repair operation based on the result of the iterative pattern write operation.

[0154] To perform the above operations, the built-in self-test logic 2210 may be configured to control the reference Figure 2 For example, the built-in self-test logic 2210 can generate a test pattern and can control the driving circuit 123 (see Figure 2 ), so that the generated test pattern is written into the memory cell. The built-in self-test logic 2210 may allow the driver circuit 123 to read data from the memory cell. The built-in self-test logic 2210 may generate another test pattern based on the read data, and may control the driver circuit 123 so that the generated test pattern is written into the memory cell.

[0155] In an exemplary embodiment, instead of generating a test pattern based on the result of a previous pattern write operation, the built-in self-test logic 2210 may control the driving circuit 123 so that a rewrite operation on a failed cell is skipped. For example, in a pattern write operation, the built-in self-test logic 2210 may deactivate a write driver connected to a failed cell among write drivers included in the driving circuit 123 so that a rewrite operation on the failed cell is not performed. In an exemplary embodiment, in a pattern write operation, the built-in self-test logic 2210 may control a write driver included in the driving circuit 123 so that a write driver connected to a failed cell among write drivers writes failure information into the failed cell.

[0156] Fig.24 FIG. 1 is a block diagram of a computing system according to an embodiment of the inventive concept. Fig.24 , the computing system 3000 may include a central processing unit (CPU) 3100, a memory module (DIMM) 3210, and a memory device 3220. The memory module 3210 may be provided in the form of a dual in-line memory module (DIMM). The memory device 3220 may be a reference Figures 1 to 23 One of the memory devices described.

[0157] In an exemplary embodiment, the memory module 3210 may be configured to perform a cache function or a buffer function of the central processing unit 3100. In an exemplary embodiment, the memory device 3220 may be used as a non-volatile memory or storage configured to store data under the control of the central processing unit 3100. In an exemplary embodiment, the memory device 3220 may be an MRAM device or a 3D-Xpoint TM Memory.

[0158] The memory module 3210 can communicate with the central processing unit 3100 through the first interface IF1. The memory device 3220 can communicate with the central processing unit 3100 through the second interface IF2. In an exemplary embodiment, the first interface IF1 and the second interface IF2 can be interfaces of the same type, or can be interfaces defined by the same standard. Alternatively, the first interface IF1 and the second interface IF2 can be interfaces of different types. In an exemplary embodiment, the first interface IF1 can be a DDR interface, and the second interface IF2 can be a modified DDR interface (e.g., a DDR-T interface). However, the inventive concept is not limited thereto.

[0159] Fig.25 FIG. 1 is a block diagram of an electronic device according to an embodiment of the inventive concept. Fig.25, the electronic device 4000 may include a main processor 4100, a touch panel 4200, a touch driver integration (TDI) circuit 4202, a display panel 4300, a display driver integration (DDI) circuit 4302, a system memory 4400, a storage device 4500, an audio processor 4600, a communication block 4700, and an image processor 4800. In an exemplary embodiment, the electronic device 4000 may be one of various electronic devices such as, for example, a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smart phone, a tablet computer, a laptop computer, and a wearable device.

[0160] The main processor 4100 may control the overall operation of the electronic device 4000. The main processor 4100 may control / manage the operations of the components of the electronic device 4000. The main processor 4100 may process various operations for the purpose of operating the electronic device 4000. The touch panel 4200 may be configured to sense a touch input from a user under the control of the touch driver integrated circuit 4202. The display panel 4300 may be configured to display image information under the control of the display driver integrated circuit 4302.

[0161] The system memory 4400 may store data used for the operation of the electronic device 4000. For example, the system memory 4400 may include a volatile memory such as, for example, a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM) and / or a non-volatile memory such as, for example, a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM). The storage device 4500 may store data regardless of whether power is supplied. For example, the storage device 4500 may include at least one of various non-volatile memories such as, for example, a flash memory, a PRAM, an MRAM, a ReRAM, and a FRAM. For example, the storage device 4500 may include an embedded memory and / or a removable memory of the electronic device 4000. In an exemplary embodiment, the system memory 4400 or the storage device 4500 may include a reference Figures 1 to 24 The memory device described or based on the reference Figures 1 to 24 A method of operating a memory device under test is described.

[0162] The audio processor 4600 may process an audio signal by using an audio signal processor 4610. The audio processor 4600 may receive an audio input through a microphone 4620, or may provide an audio output through a speaker 4630. The communication block 4700 may exchange signals with an external device / system through an antenna 4710. The transceiver 4720 and the modulator / demodulator (MODEM) 4730 of the communication block 4700 may process signals exchanged with an external device / system in accordance with at least one of various wireless communication protocols, such as Long Term Evolution (LTE). TM ), World Interoperability for Microwave Access (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID), etc. The image processor 4800 may receive light through a lens 4810. An image device 4820 and an image signal processor (ISP) 4830 included in the image processor 4800 may generate image information about an external object based on the received light.

[0163] Fig.26 A block diagram of a data center to which a storage system according to an embodiment of the inventive concept can be applied is shown. Fig.26 , the data center 5000 may include a plurality of computing nodes (or servers) 5100 to 5400. The plurality of computing nodes 5100 to 5400 may communicate with each other via a network NT. In an exemplary embodiment, the network NT may be a storage-specific network such as a storage area network (SAN), or may be the Internet such as TCP / IP. In an exemplary embodiment, the network NT may include a Fibrechannel SM , iSCSI protocol, FCoE, NAS and NVMe-oF.

[0164] The plurality of computing nodes 5100 to 5400 may include processors 5110 , 5210 , 5310 , and 5410 , memories 5120 , 5220 , 5320 , and 5420 , storage devices 5130 , 5230 , 5330 , and 5430 , and interface circuits 5140 , 5240 , 5340 , and 5440 , respectively.

[0165] For example, the first computing node 5100 may include a first processor 5110, a first memory 5120, a first storage device 5130, and a first interface circuit 5140. In an exemplary embodiment, the first processor 5110 may be implemented with a single core or multiple cores. The first memory 5120 may include, for example, DRAM, SDRAM, SRAM, 3D XPoint TMThe first memory 5120 may be a memory of a memory, such as a memory, MRAM, PRAM, FeRAM, or ReRAM. The first memory 5120 may be used as a system memory, a working memory, or a buffer memory of the first computing node 5100. The first storage device 5130 may be a high-capacity storage medium such as a hard disk drive (HDD) or a solid-state drive (SSD). The first interface circuit 5140 may be a network interface controller (NIC) configured to support communication via the network NT.

[0166] In an exemplary embodiment, the first processor 5110 of the first computing node 5100 may be configured to access the first memory 5120 based on a given memory interface. Alternatively, in an embodiment of a shared memory architecture, the first processor 5110 of the first computing node 5100 may be configured to access the memories 5220, 5320, and 5420 of the remaining computing nodes 5200, 5300, and 5400 via a network NT. The interface circuit 5140 may include a network switch (not shown) configured to control or support access to the shared memory (i.e., the memory of any other computing node).

[0167] In an exemplary embodiment, the first processor 5110 of the first computing node 5100 may be configured to access the first storage device 5130 based on a given storage interface. Alternatively, the first processor 5110 of the first computing node 5100 may be configured to access the storage devices 5230, 5330, and 5430 of the remaining computing nodes 5200, 5300, and 5400 via the network NT. The interface circuit 5140 may include a network switch (not shown) configured to control or support access to the storage device of any other computing node. In an exemplary embodiment, the storage devices 5130 to 5430 respectively included in the plurality of computing nodes 5100 to 5140 may constitute a RAID volume. The operations of the second computing node 5200 to the fourth computing node 5400 may be similar to the operations of the first computing node 5100 described above, and therefore, additional descriptions will be omitted to avoid redundancy.

[0168] In an exemplary embodiment, various applications may be executed in the data center 5000. These applications may be configured to execute instructions for data movement or replication between the computing nodes 5100 to 5400, or may be configured to execute instructions for combining, processing, or reproducing various information present on the computing nodes 5100 to 5400. In an exemplary embodiment, the application may be executed by one of the plurality of computing nodes 5100 to 5400 included in the data center 5000, or the application may be distributed among the plurality of computing nodes 5100 to 5400 and executed.

[0169] In an exemplary embodiment, data center 5000 may be used for high performance computing (HPC) (e.g., finance, petroleum, material science, weather forecasting), enterprise applications (e.g., scale-out databases), big data applications (e.g., NoSQL databases or in-memory replication).

[0170] In an exemplary embodiment, at least one of the plurality of computing nodes 5100 to 5400 may be an application server. The application server may be configured to execute an application configured to perform various operations at the data center 5000. At least one of the plurality of computing nodes 5100 to 5400 may be a storage server. The storage server may be configured to store data generated or managed at the data center 5000.

[0171] In an exemplary embodiment, the plurality of computing nodes 5100 to 5400 included in the data center 5000 or a portion thereof may exist in the same place or in places physically separated from each other, and may communicate with each other via a network NT based on wireless communication or wired communication. In an exemplary embodiment, the plurality of computing nodes 5100 to 5400 included in the data center 5000 may be implemented by the same memory technology, or may be implemented by different memory technologies.

[0172] Although not shown in the figure, at least a portion of the plurality of computing nodes 5100 to 5400 of the data center 5000 may communicate with an external client node (not shown) via the network NT or via any other communication interface (not shown). At least a portion of the plurality of computing nodes 5100 to 5400 may automatically process a request (e.g., data storage or data transfer) according to a request of an external client node, or may process a request at any other computing node.

[0173] In the exemplary embodiment, the number of computing nodes 5100 to 5400 included in the data center 5000 is exemplary, and the inventive concept is not limited thereto. In addition, in each computing node, the number of processors, the number of memories, and the number of storage devices are exemplary, and the inventive concept is not limited thereto. Fig.26 Features shown.

[0174] In an exemplary embodiment, at least one of the memories 5120 to 5420, the storage devices 5130 to 5430, or the system memories included in the processors 5110 to 5410, respectively included in the plurality of computing nodes 5100 to 5400, may be a reference Figures 1 to 24 The memory device described may include a memory device configured to perform reference Figures 1 to 24 The test operation of the BIST logic described here is either Figures 1 to 24Alternatively, each or at least one of the plurality of computing nodes 5100 to 5400 may include a test device or BIST logic configured to perform a test based on a reference. Figures 1 to 24 The described operation method tests at least one of the memories 5120 to 5420 , the storage devices 5130 to 5430 , and the system memory included in the processors 5110 to 5410 , which are respectively included in the plurality of computing nodes 5100 to 5400 .

[0175] According to an embodiment of the present invention, a write failure of a memory device can be detected by iteratively writing a specific pattern into the memory device. In this case, a specific pattern is generated so that a write operation to a faulty cell determined as a write failure in a previous pattern write operation is skipped. Therefore, since a write operation to a memory cell determined as a faulty cell at least once or more times or a reference number of times or more in an iteration of a pattern write operation is skipped, the faulty cell itself can maintain information about the faulty cell. That is, even if a write failure does not occur simultaneously at a plurality of memory cells in one pattern write operation, a cell with a high probability of a write failure is detected through a plurality of pattern write operations. Therefore, a test method for a memory device with improved reliability, an operating method of a test device for testing a memory device, and a memory device including a self-test function are provided.

[0176] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concepts as set forth in the following claims.

Claims

1. A method for testing a memory device comprising a plurality of memory cells, the method comprising: generating a first test pattern; performing a first pattern write operation of writing the first test pattern into the plurality of memory cells; reading first data from the plurality of memory cells written with the first test pattern; generating a second test pattern based on the first data; as well as performing a second pattern write operation of writing the second test pattern into the plurality of memory cells, The second test pattern is generated so that failure information is written into a failed cell in which a write failure occurs among the plurality of memory cells.

2. The method of claim 1, wherein: The plurality of memory cells are connected to the same word line.

3. The method of claim 1, wherein: Each of the plurality of memory cells includes a variable resistance element including a magnetic tunnel junction having a resistance value that changes according to a direction of a current flowing through the variable resistance element.

4. The method of claim 1, wherein: The first test pattern is a default test pattern, and performing the second pattern write operation includes: performing a write-back operation of writing a first reverse pattern into the plurality of memory cells, the first reverse pattern being an inverted version of the default test pattern; and A rewrite operation of writing the second test pattern into the plurality of memory cells on which the write-back operation has been performed is performed.

5. The method of claim 4, wherein: The fail information is written into the fail cell among the plurality of memory cells during the write-back operation or the rewrite operation.

6. The method of claim 1, wherein: The first test pattern includes data in which all bit values ​​are first values, and The second test pattern includes data in which a bit value corresponding to each of the failed cells is a second value different from the first value, and remaining bit values ​​corresponding to memory cells other than the failed cells among the plurality of memory cells are the first value.

7. The method of claim 1, wherein: The iteration of generating the second test pattern and performing the second pattern write operation is performed a given number of times, and During the iteration, the second test pattern is generated based on the result of a previous pattern write operation so that the fail information is written into the fail cell.

8. The method of claim 7, wherein: The failed cell is a memory cell among the plurality of memory cells in which a write failure occurs at least “n” times in the iteration, where n is a natural number of 2 or more.

9. The method of claim 7, wherein: The failed cell is a memory cell among the plurality of memory cells in which write failures successively occur at least “n” times in the iteration, where n is a natural number of 2 or more.

10. The method of claim 7, further comprising: after the iterations of generating the second test pattern and performing the second pattern write operation are performed the given number of times, reading final data from the plurality of memory cells; determining the number of the failed cells among the plurality of memory cells based on the final data and comparing the number of the failed cells with a reference value; as well as When the number of the failed cells exceeds the reference value, a repair operation or a masking operation is performed on the memory device.

11. The method of claim 10, wherein: The reference value corresponds to an error correction capability of an error correction code engine included in the memory device or a memory controller configured to control the memory device.

12. The method of claim 11, wherein: The number of the plurality of memory cells corresponds to an error correction unit of the error correction code engine.

13. A method of operating a test device configured to test a memory device including a plurality of memory cells, the method comprising: generating a first test pattern and performing a first pattern write operation of writing the first test pattern into the plurality of memory cells; reading first data from the plurality of memory cells; generating a second test pattern based on the first data and performing a second pattern write operation of writing the second test pattern into the plurality of memory cells; reading second data from the plurality of memory cells; as well as generating a third test pattern based on the second data and performing a third pattern write operation of writing the third test pattern into the plurality of memory cells, wherein the second test pattern is generated so that during the second pattern write operation, failure information is written into at least one first failure cell among the plurality of memory cells in which a write failure occurs during the first pattern write operation, and The third test pattern is generated so that the failure information is written into the at least one first failure cell and into at least one second failure cell among the plurality of memory cells in which a write failure occurs during the second pattern write operation during the third pattern write operation.

14. The method of claim 13, wherein: The first test pattern is generated based on a test type associated with the memory device.

15. The method of claim 14, wherein: The test types include: a first test type for testing whether each of the multiple memory cells normally switches from a first state corresponding to a first bit value to a second state corresponding to a second bit value during a write operation, and a second test type for testing whether each of the multiple memory cells normally switches from the second state to the first state.

16. The method of claim 15, wherein: For the first test type: All bit values ​​of the first test pattern are the second bit value; a bit value corresponding to the at least one first failure unit among the bit values ​​of the second test pattern is the first bit value, and the remaining bit values ​​of the second test pattern other than the bit value corresponding to the at least one first failure unit are the second bit values; and bit values ​​of the third test pattern that respectively correspond to the at least one first failure cell and the at least one second failure cell are the first bit values, and remaining bit values ​​of the third test pattern other than the bit values ​​corresponding to the at least one first failure cell and the at least one second failure cell are the second bit values, and Wherein, for the second test type: All bit values ​​of the first test pattern are the first bit values; a bit value corresponding to the at least one first failure unit among the bit values ​​of the second test pattern is the second bit value, and the remaining bit values ​​of the second test pattern other than the bit value corresponding to the at least one first failure unit are the first bit values; and The bit values ​​of the third test pattern that respectively correspond to the at least one first fault unit and the at least one second fault unit are the second bit values, and the remaining bit values ​​of the third test pattern other than the bit values ​​corresponding to the at least one first fault unit and the at least one second fault unit are the first bit values.

17. A memory device including a self-test function, comprising: a memory cell array comprising a plurality of memory cells; a driving circuit configured to perform a write operation and a read operation on the plurality of memory cells; as well as Built-in self-test logic configured to perform self-tests under the control of an external device, wherein, during the self-test, the built-in self-test logic is configured to iteratively perform pattern write operations on the plurality of memory cells, and For each iteration of the pattern write operation, the built-in self-test logic is configured to control the driving circuit to write failure information into a failed cell in which a write failure occurs among the plurality of memory cells.

18. The memory device of claim 17, wherein: Each memory cell of the plurality of memory cells comprises: a select transistor configured to operate in response to a voltage on a word line, wherein one terminal of the select transistor is connected to a source line; and A variable resistance element is connected between the selection transistor and the bit line, wherein the resistance value of the variable resistance element is variable according to the direction of a current flowing through the variable resistance element.

19. The memory device of claim 17, wherein: For each iteration of the pattern write operation, the built-in self-test logic is configured to generate a test pattern and control the drive circuit to write the test pattern into the plurality of memory cells, The test pattern includes the failure information written into the failure unit.

20. The memory device of claim 17, wherein: The driving circuit includes a write driver configured to control a plurality of bit lines and a plurality of source lines connected to the plurality of memory cells, and For each iteration of the pattern write operation, the built-in self-test logic is further configured to disable a write driver among the write drivers corresponding to the failed cell.

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