Semiconductor structure and method for forming the same, and package

Abstract

In an embodiment, a structure includes: a core substrate; a coupled redistribution structure, the redistribution structure includes a plurality of redistribution layers, the plurality of redistribution layers include a dielectric layer and a metallization layer; a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component includes a conductive connector, the conductive connector is bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer seals the first local interconnect component; a first integrated circuit die coupled to the redistribution structure; a second integrated circuit die coupled to the redistribution structure, the interconnect structure of the first local interconnect component electrically couples the first integrated circuit die to the second integrated circuit die; and a set of conductive connectors coupled to a second side of the core substrate. Embodiments of the present application also relate to semiconductor structures, methods of forming the same, and packages.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor structure, a method for forming the same, and a package. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, iterative reduction of the minimum component size can improve the integration density, so that more components can be integrated into a given area. With the growth of the demand for shrinking electronic devices, there has been a demand for smaller and more creative semiconductor die packaging technology. An example of such a packaging system is a stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor structure, including: a core substrate; a redistribution structure coupled to a first side of the core substrate, the redistribution structure including: a plurality of redistribution layers, each of the plurality of redistribution layers including a dielectric layer and a metallization layer; a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure located on the substrate, and a conductive connector, the conductive connector being bonded to the metallization layer of the first redistribution layer through a first solder connector, the metallization layer of the first redistribution layer including a first wire and a first conductive via; and a first bottom filler located in the first redistribution layer, the first bottom filler surrounding the first solder connector; a first integrated circuit die coupled to the redistribution structure, the redistribution structure being interposed between the core substrate and the first integrated circuit die; a second integrated circuit die coupled to the redistribution structure, the redistribution structure being interposed between the core substrate and the second integrated circuit die, the interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die; and a group of conductive connectors coupled to a second side of the core substrate.

[0004] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first redistribution structure above a first carrier substrate, wherein forming the first redistribution structure comprises: forming a first group of conductive lines above the first carrier substrate; forming a first group of conductive vias electrically coupled to the first group of conductive lines above the first group of conductive lines; bonding a first interconnection die to the first group of conductive lines through a first solder region, the first interconnection die comprising a substrate and an interconnection structure located on the substrate, the interconnection structure bonded to the first solder region, the first interconnection die being located between two of the first group of conductive vias; forming a first dielectric layer above the first group of conductive lines, the first group of conductive vias, and the first interconnection die, the first dielectric layer, the first group of conductive vias, and the first interconnection die being electrically coupled to the first group of conductive lines. , the first group of conductive lines and the first interconnect die form a first redistribution layer; and form a second redistribution layer above the first redistribution layer, the second redistribution layer comprising a second dielectric layer, a second group of conductive vias and a second group of conductive lines, at least one of the second group of conductive lines being electrically coupled to at least one of the first group of conductive vias; removing the first carrier substrate; electrically connecting the core substrate to a first side of the first redistribution structure, the second redistribution layer being closer to the first side of the first redistribution layer than the first redistribution layer; and bonding a first integrated circuit die and a second integrated circuit die to a second side of the first redistribution structure, the second side being opposite to the first side, the first integrated circuit die and the second integrated circuit die being electrically coupled to the first interconnect die.

[0005] Some other embodiments of the present application provide a package, comprising: a first redistribution structure, the first redistribution structure comprising: a plurality of redistribution layers, each of the plurality of redistribution layers comprising a metallization pattern and a dielectric layer, the first redistribution layer of the plurality of redistribution layers comprising: a first dielectric layer; a first metallization pattern; a first interconnection die, the first interconnection die comprising a substrate, an interconnection structure located on the substrate, and a die connector located on the interconnection structure, the die connector being bonded to the metallization pattern of the first redistribution layer through a first solder bump, the first metallization pattern comprising a first wire and a first conductive via, the first dielectric layer sealing the first interconnection die; and a first bottom filler located between the first interconnection die and the first metallization pattern, the first bottom filler surrounding the first solder bump; a core substrate coupled to a first side of the first redistribution structure using a first set of conductive connectors, the width of the first redistribution structure being smaller than the width of the core substrate; and an integrated circuit die package coupled to a second side of the first redistribution structure using a second set of conductive connectors, the second side being opposite to the first side. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of a package assembly according to some embodiments is shown.

[0008] Figure 2A and Figure 2B According to some embodiments Figure 1 Detailed view of a section of a cross-sectional view.

[0009] Figure 3 A plan view of a package assembly according to some embodiments is shown.

[0010] Figures 4 to 16 and Figures 19 to 23 Cross-sectional views are shown of intermediate steps during a process of forming a package assembly in accordance with some embodiments.

[0011] Fig.17 A plan view illustrating a layout of a packaging area on a wafer substrate according to some embodiments.

[0012] Fig.18 A plan view illustrating the layout of a packaging area on a panel substrate according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] The embodiments discussed herein can be discussed in a specific context, i.e., a package assembly has one or more integrated circuit dies. In some embodiments, the package assembly is a system on an integrated substrate (SoIS) package. The package assembly includes a local interconnect assembly embedded in a redistribution structure. The embedded local interconnect assembly provides electrical connections between the integrated circuit dies. The embedded local interconnect assembly increases the communication bandwidth between the integrated circuit dies while maintaining low contact resistance and high reliability. In some embodiments, other components (such as integrated regulators, integrated passive devices, static random access memory, etc., or combinations thereof) may also be embedded in a manner similar to the embedded local interconnect assembly. The embodiments disclosed herein can be applied to various systems, such as high performance computing (HPC), edge computing, cloud computing, data centers, networking, and artificial intelligence.

[0016] The redistribution structure is connected to the integrated circuit die and provides electrical connections between the integrated circuit die and the core substrate and / or between the integrated circuit dies. The core substrate is additionally connected to a set of external conductive components. In this way, the integrated circuit die is electrically connected to the core substrate and ultimately to the external conductive components through the core substrate and the redistribution structure.

[0017] According to some embodiments, the redistribution structure, embedded local interconnect components, core substrate, and integrated circuit die may be manufactured and tested separately before assembling the finished package component. This further improves component and board level reliability.

[0018] Due to the increased communication bandwidth between the integrated circuit dies provided by the local interconnect assembly, no interposer is required between the integrated circuit die and the redistribution structure. By removing the need for an interposer, the warpage mismatch between the integrated circuit package (including the integrated circuit die) and the core substrate package (including the core substrate and the redistribution structure) is reduced because the coefficient of thermal expansion (CTE) mismatch between the two packaging structures is reduced.

[0019] According to some embodiments, the conductive connectors for connecting the core substrate to the redistribution structure may take the form of, for example, a ball grid array (BGA). The integration of such conductive connectors may provide flexibility in the placement of semiconductor devices, such as integrated passive devices (IPD) chips, integrated voltage regulators (IVRs), active chips, and other electronic components, to achieve a system-on-chip type package assembly, thereby reducing manufacturing complexity. Such embodiments may also provide greater flexibility for various other packaging configurations.

[0020] Figure 1 A cross-sectional view of a singulated package assembly 100 is shown in accordance with some embodiments. Figure 2A and Figure 2B According to some embodiments Figure 1 Detailed view of a portion of a cross-sectional view of the embodiment of the present invention. The segmented package assembly 100 includes a semiconductor device (e.g., an integrated circuit package 500), a redistribution structure 200 having one or more redistribution layers, a core substrate 300, and an external connector 620, as well as other elements. The integrated circuit package 500 may include one or more dies, such as a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof. In some embodiments, the semiconductor device may be an integrated circuit die.

[0021] The integrated circuit package 500 may include a plurality of integrated circuit dies. As shown, for purposes of illustration, the integrated circuit package 500 includes one or more logic dies 512, one or more memory dies 514, and one or more input / output (I / O) dies 516 ( Figure 1 Not shown, but see Figure 3 ). The integrated circuit die may be formed in one or more wafers, which may include different device regions that are segmented in subsequent steps. The integrated circuit die may be packaged with other similar or different integrated circuit dies using known manufacturing techniques. In some embodiments, the integrated circuit dies 512 and 514 are packaged using the following reference Figure 7 Similar processes and techniques as described are formed.

[0022] In some embodiments, one or more of the integrated circuit dies 512 and 514 may be stacked devices including multiple semiconductor substrates. For example, the memory die 514 may be a memory device including multiple memory dies, such as a hybrid memory multidimensional cube (HMC) module, a high bandwidth memory (HBM) module, etc. In such an embodiment, the memory die 514 includes multiple semiconductor substrates interconnected by through substrate vias (TSVs). Each of the semiconductor substrates may (or may not) have an interconnect structure.

[0023] Dies 512 and 514 have bond pads 518 bonded to conductive connectors 188. In some embodiments, bond pads 518 are made of a conductive material and may be similar to the wires described below (see, eg, wire 110).

[0024] The conductive connectors 188 provide electrical connections between the redistribution structure 200 and the integrated circuit package 500. An underfill 610 may be included to securely bond the integrated circuit package 500 to the redistribution structure 200 and to provide structural support and environmental protection.

[0025] As discussed in more detail below, the redistribution structure 200 provides electrical paths and connections between the integrated circuit package 500 and the core substrate 300 through the conductive connectors 365. In some embodiments, the redistribution structure 200 has one or more redistribution layers including a metallization pattern including, for example, conductive lines 110 and 116 and conductive vias 106 and 112, and dielectric layers 108 and 114 separating adjacent layers of conductive lines 110 and 116.

[0026] As discussed in more detail below, the redistribution structure 200 includes one or more local interconnect components 120. The local interconnect components 120 provide electrical routing and connections between the integrated circuit dies 512 and 514 of the integrated circuit package 500 and may be referred to as interconnect dies 120. The local interconnect components 120 increase the communication bandwidth between the integrated circuit dies 512 and 514 while maintaining low contact resistance and high reliability. Figure 1 as well as Figure 2A and Figure 2B As shown, the local interconnect component 120 is connected to the metallization pattern 116 of the redistribution structure 200 through the conductive connector 136. In some embodiments, the conductive connector 136 is a solder connector 136. The local interconnect component 120 is embedded in the redistribution structure 200, and an underfill 137 is formed around the conductive connector 136 and between the local interconnect component 120 and the dielectric layer 114. In some embodiments, the local interconnect component 120 may include a substrate through-via 123 extending through the local interconnect component 120 to become a connection to the metallization pattern adjacent to the back side of the local interconnect component 120.

[0027] Due to the increased communication bandwidth between the integrated circuit dies provided by the local interconnect assembly, no interposer is required between the integrated circuit die and the redistribution structure. By removing the need for an interposer, the warpage mismatch between the integrated circuit package (including the integrated circuit die) and the core substrate package (including the core substrate and the redistribution structure) is reduced because the coefficient of thermal expansion (CTE) mismatch between the two package structures is reduced.

[0028] exist Figure 2A In the embodiment of FIG. 1 , the dielectric layer 142 extends across the singulated package components 100, while in Figure 2B In FIG. 1 , dielectric layer 142 is only located on local interconnect component 120. In addition, in Figure 2B In the embodiment, dielectric layer 143 laterally surrounds dielectric layer 142. The details of dielectric layers 142 and 143 will be referred to below. Fig.11A and Fig. 11B discuss.

[0029] The redistribution structure 200 can be electrically and mechanically attached to the core substrate 300. The core substrate 300 can include a central core 310 with conductive vias 320 extending through the central core 310, and additional optional redistribution structures 340 along opposite sides of the central core 310. In general, the core substrate 300 provides structural support for the package assembly 100, as well as electrical signal routing between the integrated circuit package 500 and the external connectors 620.

[0030] Figure 3 A plan view of a package assembly according to some embodiments is shown. Figure 3 The illustrated embodiment includes two logic dies 510 and 512, four memory dies 514, two I / O dies 516, and seven local interconnect components 120. In this embodiment, each of the memory dies 514 and the I / O dies 516 is connected to at least one of the logic dies 512 through a corresponding local interconnect component 120. In addition, the two logic dies are connected together through the local interconnect component 120. Other embodiments may include more or fewer logic dies 510 and 512, memory dies 514, I / O dies 516, and local interconnect components 120. In some embodiments, each of the integrated circuit dies is connected to each adjacent integrated circuit die through a local interconnect component.

[0031] Figures 4 to 16 The process of manufacturing a redistribution structure 200 (see FIG. 1 ) according to some embodiments is shown. Fig.16 ) in various intermediate stages. A first packaging area 101A and a second packaging area 101B are shown, wherein each packaging area is eventually separated from the other packaging areas. For ease of explanation, Figures 4 to 16 The description of the individual components is simplified.

[0032] First reference Figure 4 , providing a carrier substrate 102, forming a release layer 104 on the carrier substrate 102, and forming a conductive via 106 over the release layer 104. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that a plurality of redistribution structures may be formed on the carrier substrate 102 at the same time.

[0033] The release layer 104 may be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesiveness when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (UV) glue that loses its adhesiveness when exposed to UV light. The release layer 104 may be dispensed and cured in the form of a liquid, may be a laminated film laminated to the carrier substrate 102, and the like. The top surface of the release layer 104 may be horizontal and substantially planar within process variations.

[0034] exist Figure 4 , a conductive via 106 is formed on the release layer 104. The conductive via 106 can be subsequently exposed by a carrier stripping process and used to provide a connection for the redistribution structure 200. The conductive via 106 forms a metallization pattern for the redistribution layer 90. As an example of forming the conductive via 106, a seed layer (not shown) is formed above the release layer 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer can be, for example, a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD), etc. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. Patterning forms an opening through the photoresist to expose the seed layer, wherein the opening in the photoresist corresponds to the conductive via 106. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the portion below the seed layer forms the conductive via 106. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0035] exist Figure 5In the embodiment, according to some embodiments, a dielectric layer 108 is formed on and around the conductive via 106, and a conductive line 110 is formed on the dielectric layer 108 and the conductive via 106. After formation, the dielectric layer 108 surrounds the conductive via 106. The dielectric layer 108 may provide electrical isolation and environmental protection. The dielectric layer 108 and the metallization pattern including the conductive via 106 form a redistribution layer 90. The dielectric layer 108 may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride such as silicon nitride, etc.; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc.; or a combination thereof. The dielectric layer 108 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The dielectric layer 108 may have a substantially horizontal upper surface within process variations. In some embodiments, the dielectric layer is formed to have a thickness in a range from 2 μm to 50 μm.

[0036] After the dielectric layer 108 is formed, a wire 110 is formed on the dielectric layer 108 and the conductive via 106. As an example of forming the wire 110, a seed layer (not shown) is formed above the dielectric layer 108 and the conductive via 106. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. The seed layer can be, for example, a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD, etc. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. Patterning forms an opening through the photoresist to expose the seed layer, wherein the opening in the photoresist corresponds to the wire 110. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, etc. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the portion below the seed layer forms the wire 110. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0037] exist Figure 6In some embodiments, a conductive via 112 is formed on a conductive line 110, and a dielectric layer 114 is formed on and around the conductive via 112 and the conductive line 110. The conductive line 110 and the conductive via 112 together form a metallization pattern for the redistribution layer 92. The conductive via 112 may be similar to the conductive via 106 described above, and the description is not repeated here. The dielectric layer 114 may be similar to the dielectric layer 108 described above, and the description is not repeated here. The dielectric layer 114 and the metallization pattern (including the conductive via 112 and the conductive line 110) form the redistribution layer 92. In some embodiments, the conductive vias 106 and 112 have a width in a range from 2 μm to 50 μm.

[0038] Further in Figure 6 , a conductive line 116 and a conductive via 118 are formed. A conductive line 116 is formed over the conductive via 112 and connected to the conductive via 112, and a conductive via 118 is formed over the conductive line 116 and connected to the conductive via 116. The conductive line 116 and the conductive via 118 together form a metallization pattern for the redistribution layer 94. The conductive line 116 and the conductive via 118 may be similar to the conductive line 110 and the conductive via 106 described above, and are not repeatedly described here. In some embodiments, the conductive via 118 has a greater height than the conductive vias 106 and 112 because the conductive via 118 serves as a dielectric via adjacent to the subsequently attached local interconnect component 120. In some embodiments, the conductive via 118 has a width in a range from 5 μm to 100 μm.

[0039] Figure 7 A cross-sectional view of a local interconnect component 120 is shown in accordance with some embodiments. The local interconnect component 120 will be embedded in a redistribution structure 200 in subsequent processing.

[0040] The local interconnect component 120 can be formed in a wafer, which may include different device regions that are segmented in subsequent steps to form multiple local interconnect components. The local interconnect component 120 can be processed according to an applicable manufacturing process to form a tube core. For example, the local interconnect component 120 includes a substrate 122, such as an active layer of a doped or undoped silicon or a semiconductor on insulator (SOI) substrate. The substrate 122 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In some embodiments, the substrate 122 can be made of a ceramic material, a polymer film, a magnetic material, etc., or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 122 has an active surface (e.g., at Figure 7 The surface facing upward in the middle), sometimes called the front side, and the passive surface (e.g. Figure 7 The downward-facing surface of the medial aspect of the anterior chamber is sometimes called the dorsal side.

[0041] In some embodiments, the local interconnect component 120 includes active or passive devices. In some embodiments, the local interconnect component 120 may not have active or passive devices and may be used only for the routing of electrical signals. In embodiments including active or passive devices, a device (represented by a transistor) 124 may be formed at the front surface of the substrate 122. The device 124 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, an inductor, etc. An interlayer dielectric (ILD) 126 is located above the front surface of the substrate 122. The ILD 126 surrounds and may cover the device 124. The ILD 126 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0042] Conductive plug 128 extends through ILD 126 to electrically and physically couple device 124. For example, when device 124 is a transistor, conductive plug 128 can couple the gate and source / drain regions of the transistor. Conductive plug 128 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof. Interconnect structure 130 is located above ILD 126 and conductive plug 128. Interconnect structure 130 interconnects device 124 and / or provides electrical routing and connection between die connectors 133. Interconnect structure 130 can be formed by metallization patterns in dielectric layers on ILD 126, for example, using a damascene process. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. In an embodiment including device 124, the metallization pattern of interconnect structure 130 is electrically coupled to device 124 through conductive plug 128. Although the interconnect structure 130 is shown as having only two layers of conductive vias and two layers of conductive wires, in some embodiments, more or fewer layers of conductive vias and conductive wires may be included as needed. For example, because the local interconnect component 120 is used for electrical connection between the dies of the integrated circuit package 500, the interconnect structure 130 of the local interconnect component 120 will generally have more interconnect layers to accommodate the electrical connection.

[0043] In some embodiments, the local interconnect component 120 includes a through hole 123 extending through the substrate 122 and / or the interconnect structure 130 to provide the ability to electrically couple the local interconnect component 120 to adjacent devices (e.g., devices above and below the local interconnect component 120). In some embodiments, the through hole 123 is formed only through the substrate 122 and coupled to the interconnect structure 130, and the conductive components and pads 131 of the interconnect structure 130 can be utilized to couple to other devices. In some embodiments, the through hole 123 is formed through the substrate 122 and the interconnect structure 130, and the pads 131 can be utilized to couple to other devices. The through hole 123 can be formed by patterning the holes in the substrate 122 and / or the interconnect structure 130 and forming a conductive material in the holes. The conductive material can be formed by a similar process as described above and below for the conductive components in the interconnect structure 200, and will not be repeated here.

[0044] The local interconnect assembly 120 also includes pads 131, such as aluminum pads, that make external connections. The pads 131 are located on the active side of the local interconnect assembly 120, such as in and / or on the interconnect structure 130. One or more passivation films 132 are located on the local interconnect assembly 120, such as on portions of the interconnect structure 130 and the pads 131. An opening extends through the passivation film 132 to the pads 131. A die connector 133, such as a conductive post (e.g., formed of a metal such as copper), extends through the opening in the passivation film 132 and is physically and electrically coupled to a corresponding one of the pads 131. The die connector 133 can be formed, for example, by plating. The die connector 133 electrically couples a corresponding integrated circuit of the local interconnect assembly 120.

[0045] Solder areas (e.g., solder balls or solder bumps) may be provided on pads 131. The solder balls may be used to perform chip probe (CP) testing on local interconnect components 120. CP testing may be performed on local interconnect components 120 to determine whether local interconnect components 120 are known good dies (KGDs). Thus, only local interconnect components 120 that are subsequently processed as KGDs are packaged, and dies that fail the CP testing are not packaged. After testing, these solder areas may be removed in subsequent processing steps.

[0046] The dielectric layer 134 may (or may not) be located on the active side of the local interconnect component 120, such as on the passivation film 132 and the die connector 133. The dielectric layer 134 laterally seals the die connector 133, and the dielectric layer 134 is laterally coterminal with the local interconnect component 120. Initially, the dielectric layer 134 may bury the die connector 133, so that the topmost surface of the dielectric layer 134 is located above the topmost surface of the die connector 133. In some embodiments where the solder region is disposed on the die connector 133, the dielectric layer 134 may also bury the solder region.

[0047] The dielectric layer 134 may be a polymer such as PBO, polyimide, BCB, etc.; a nitride such as silicon nitride, etc.; an oxide such as silicon oxide, PSG, BSG, BPSG, etc.; etc. or a combination thereof. The dielectric layer 134 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, during the formation of the local interconnect component 120, the die connector 133 is exposed through the dielectric layer 134. Exposing the die connector 133 may remove any solder area that may be present on the die connector 133. In some embodiments, the die connector 133 has a pitch in a range from 20 μm to 80 μm.

[0048] exist Figure 8 1 , the local interconnect component 120 is bonded to the conductive line 116 of the redistribution structure 200. In some embodiments, the local interconnect component 120 is bonded by a solder region (e.g., a solder ball or solder bump) 136. In some embodiments, an under bump metal (UBM) 135 (sometimes referred to as a pad or pillar 135) is formed on the die connector 133 and the dielectric layer 134 for external connection to the die connector 133. Thus, the UBM 135 is electrically coupled to the die connector 133. The UBM 135 can be formed of the same material as the conductive through-hole die connector 133.

[0049] Further in Figure 8 In the embodiment of the present invention, a solder region 136 (sometimes referred to as a conductive connector 136) is formed on the UBM 135. The solder region 136 allows physical and electrical connection between the local interconnect component 120 and the wire 116. The solder region 136 can be a ball grid array (BGA) connector, a solder ball, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The solder region 136 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the solder region 136 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, a reflow can be performed to shape the material into a desired bump shape.

[0050] The local interconnect component 120 may be attached to the conductive line 116 via the solder region 136. Attaching the local interconnect component 120 may include placing the local interconnect component 120 on the conductive line 116 and reflowing the solder region 136 to physically and electrically couple the local interconnect component 120 and the conductive line 116.

[0051] After bonding the local interconnect component 120, in some embodiments, the pads 135 have a pitch ranging from 20 μm to 80 μm. Furthermore, in some embodiments, the thickness of the pads 135 and the bonded solder regions 136 ranges from 2 μm to 30 μm.

[0052] exist Fig. 9 , an underfill 137 is formed to surround the local interconnect component 120 between the local interconnect component 120 and the redistribution layer 92. The underfill 137 can reduce stress and protect joints caused by reflow of the conductive connector 136. The underfill 137 can be formed by a capillary flow process after attaching the local interconnect component 120, or can be formed by a suitable deposition method.

[0053] exist Fig.10 1 , according to some embodiments, a dielectric layer 140 is formed on and around the conductive vias 118 and the local interconnect components 120. The dielectric layer 140 seals the local interconnect components 120 and the conductive vias 118. The dielectric layer 140, the local interconnect components 120, and the metallization pattern (including the conductive vias 118 and the conductive lines 116) form the redistribution layer 94. The dielectric layer 140 (as well as the dielectric layers of the redistribution layers 154, 158, and 162) may be a different material than the dielectric layers 108 and 114.

[0054] In some embodiments, the dielectric layer 140 may be formed of a prepreg material, an Ajinomoto built-up film (ABF), a resin coated copper (RCC), a molding compound, a polyimide, a photoimageable dielectric (PID), an epoxy resin, etc., and may be applied by compression molding, transfer molding, etc. The sealant may be applied in a liquid or semi-liquid form and subsequently cured. In some embodiments, the dielectric layer 140 is formed over the dielectric layer 114 so that the wires 110, the conductive vias 118, and the local interconnect components are buried or covered, and then a planarization process is performed on the dielectric layer 140 to expose the conductive vias 118 and the back side of the substrate 122 of the local interconnect component 120. The topmost surfaces of the dielectric layer 140, the conductive vias 118, and the substrate 122 of the local interconnect component 120 are substantially horizontal (e.g., planar) within the process variation after the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP). In some embodiments, the dielectric layer 140 may include other materials such as silicon oxide, silicon nitride, etc. After a planarization process (if any), the thickness of the local interconnect component is in the range of 10 μm to 100 μm. In some embodiments, the substrate 122 of the local interconnect component 120 has a thickness in the range of 2 μm to 30 μm. The area in a plan view of the substrate 122 of the local interconnect component 120 can be in the range of 2 mm×3 mm to 50 mm×80 mm.

[0055] The local interconnect component 120 provides electrical connections between subsequently attached integrated circuit dies (e.g., 512 and 514). The embedded local interconnect component 120 increases the communication bandwidth between the integrated circuit dies while maintaining low contact resistance and high reliability. In some embodiments, other components (such as integrated voltage regulators, integrated passive devices, static random access memory, etc. or combinations thereof) may also be embedded in a similar manner to the embedded local interconnect component.

[0056] Fig.11A and Fig. 11B Two embodiments of the formation of dielectric layer 142 are shown. Fig.11A In the embodiment, a dielectric layer 142 is formed on the dielectric layer 140, the local interconnect component 120, and the conductive via 118. Fig. 11B In the embodiment, dielectric layer 142 is formed only on local interconnect component 120, and dielectric layer 143 is formed over dielectric layer 140 and conductive via 118. Fig. 11B In the embodiment, the dielectric layer 143 at least laterally surrounds the dielectric layer 142 . Fig. 11B An embodiment of the present invention can be formed by forming Fig.11A The dielectric layer shown is then removed by, for example, masking and patterning steps to remove portions of the dielectric layer 142 that are not on the local interconnect component 120. Likewise, Fig. 11B Embodiments of the present invention may be implemented by selectively forming the dielectric layer 142 on the local interconnect component 120 by, for example, forming and patterning a mask prior to depositing the dielectric layer 142 .

[0057] Further in Fig.11A , a conductive via 144 is formed in the dielectric layer 142. The conductive via 144 is located above the conductive via 118 and the via 123 in the local interconnect component and is electrically coupled to the conductive via 118 and the via 123 in the local interconnect component. The dielectric layer 142 and the conductive via 144 can be similar to the dielectric layer 108 and the conductive via 106 described above, and will not be repeated here. The dielectric layer 142 and the conductive via 144 form the redistribution layer 95.

[0058] Further in Fig. 11B, conductive vias 144 are formed in dielectric layers 142 and 143. Conductive vias 144 are located above conductive vias 118 and vias 123 in the local interconnect assembly and are electrically coupled to conductive vias 118 and vias 123 in the local interconnect assembly. Dielectric layers 142 and conductive vias 144 may be similar to dielectric layers 108 and conductive vias 106 described above, and are not described again herein. Dielectric layers 142 and conductive vias 144 form redistribution layer 95. Dielectric layer 143 may be similar to dielectric layer 140 described above, and are not described again herein. In some embodiments, dielectric layers 142 and 143 are formed of different materials. In some embodiments, conductive vias 144 in dielectric layer 142 are smaller than conductive vias 144 in dielectric layer 143. For example, when dielectric layer 142 is formed of polyimide and dielectric layer 143 is formed of molding compound, the size of the via opening in dielectric layer 142 may be made smaller than the size of the via opening in dielectric layer 143 .

[0059] Figures 12 to 23 Shows the Fig.11A The subsequent processing of the embodiment of the present invention is also applicable to Fig. 11B Embodiment of the invention.

[0060] exist Fig.12 In the embodiment, a conductive line 146 is formed on the dielectric layer 142 and the conductive via 144 and is connected to the conductive via 118. The conductive line 146 may be similar to the conductive line 110 described above and will not be described again herein.

[0061] exist Fig.13 In the embodiment, conductive vias 148 are formed on conductive lines 146 and extend from conductive lines 146. Conductive vias 148 may be similar to conductive vias 106 described above and are not described again herein. Conductive lines 146 and conductive vias 148 together form a metallization pattern for redistribution layer 150.

[0062] Further in Fig.13In the embodiment, according to some embodiments, a dielectric layer 149 is formed on and around the conductive wire 146 and the conductive via 148. After formation, the dielectric layer 149 surrounds the conductive via 148 and the conductive wire 146. The dielectric layer 149 and the metallization pattern (including the conductive via 148 and the conductive wire 146) form a redistribution layer 150. The dielectric layer 149 can be similar to the dielectric layer 140 described above, and the description is not repeated here. In some embodiments, the dielectric layer 149 is formed above the dielectric layer 142 so that the conductive wire 146 and the conductive via 148 are buried or covered, and then the dielectric layer 149 is subjected to a planarization process to expose the conductive via 148. The topmost surfaces of the dielectric layer 149 and the conductive via 148 are substantially horizontal (e.g., planar) within the process variation after the planarization process. The planarization process can be, for example, CMP. In some embodiments, the dielectric layer 149 can include other materials, such as silicon oxide, silicon nitride, etc.

[0063] exist Fig.14 , the steps and processes of forming the redistribution layer 150 discussed above are repeated to form the additionally shown redistribution layers 154, 158, and 162. In some embodiments, the process of forming the redistribution layer 150 described above may be repeated one or more times to provide additional wiring layers desired for a particular design. For illustrative purposes, eight redistribution layers 90, 92, 94, 95, 150, 154, 158, and 162 are shown. In some embodiments, more or less than eight may be used. The metallization pattern for each redistribution layer 90, 92, 94, 95, 150, 154, 158, and 162 may have separately formed conductive lines and conductive vias (as shown), or each may be a single pattern with line and via portions. In some embodiments, the conductive vias of the redistribution layers 150, 154, 158, and 162 have a width in the range of from 2 μm to 100 μm, such as 30 μm.

[0064] Although the conductive vias in redistribution layers 150, 154, 158, and 162 are shown as having tapered sidewalls, and the conductive vias in redistribution layers 90, 92, and 94 are shown as having non-tapered sidewalls, the sidewalls of the conductive vias in each of redistribution layers 90, 92, 94, 95, 150, 154, 158, and 162 may be tapered, non-tapered, or a combination thereof. In some embodiments, the sidewall profile of the conductive via is controlled to be tapered or non-tapered by controlling the photolithography and etching processes that form the openings in which the conductive vias are formed.

[0065] In some embodiments, a set of additional conductive lines 174 are formed over each conductive via 171 and a portion of the dielectric layer 172 of the uppermost redistribution layer (e.g., redistribution layer 162 in the illustrated embodiment). This set of additional conductive lines 174 provides a larger footprint for connecting the core substrate as discussed below.

[0066] In the case where an encapsulant and subsequent CMP process are used to planarize the redistribution layers 150, 154, 158, and 162, the size and roughness of the associated layers can be well controlled, and greater thicknesses can be more easily established. In some embodiments, the thickness of the redistribution layers 150, 154, 158, and 162 is each between 5 μm and 100 μm. More or fewer redistribution layers may be formed by repeating or omitting the steps and processes discussed above, respectively.

[0067] Although Figures 4 to 14 The formation process of forming the wire and the through hole before the dielectric layer around the wire and the through hole is shown, but other formation processes are also within the scope of the present invention. For example, in other embodiments, the dielectric layer is first formed, and then a metallization pattern (including wire and through hole) is formed. The metallization pattern includes a conductive element extending along the main surface of the dielectric layer and extending through the dielectric layer to be physically and electrically coupled to the conductive layer below. As an example of forming a metallization pattern, an opening is formed through the dielectric layer in the position of the desired through hole, and a seed layer is formed above the dielectric layer and in the opening extending through the dielectric layer. Then, a photoresist is formed and patterned on the seed layer. The patterned formation passes through the opening of the photoresist to expose the seed layer, wherein the pattern of the opening corresponds to the metallization pattern. Then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the part of the seed layer below forms the metallization pattern. The part of the photoresist and the seed layer on which the conductive material is not formed is removed. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet etching or dry etching.The combination of the dielectric layer and the metallization pattern forms a redistribution layer.

[0068] exist Fig.15 In the embodiment, carrier substrate peeling is performed to separate (or "peel off") carrier substrate 102 from dielectric layer 108 and conductive via 106. According to some embodiments, peeling includes projecting light, such as laser or UV light, onto release layer 104 so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. The structure is then flipped over and placed on another carrier substrate 180 and release layer 182.

[0069] If desired, a planarization process may be performed on the dielectric layer 108 and the conductive via 106 (and any remaining release layer 104) to expose the conductive via 106. The topmost surfaces of the dielectric layer 108 and the conductive via 106 are substantially horizontal (e.g., planar) within process variations after the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the conductive via 106 is already exposed, planarization may be omitted. Other processes may be used to achieve similar results. For example, after the stripping process, a dielectric layer or a passivation layer may be formed over the conductive via 106. In this case, the dielectric layer or the passivation layer may be patterned in a subsequent step to expose portions of the conductive via 106.

[0070] exist Fig.16 In the embodiment of the present invention, an under bump metal (UBM) 186 (sometimes referred to as pad 186) is formed for external connection to conductive via 106. UBM 186 has a bump portion located on and extending along the main surface of dielectric layer 108, and may have a through hole portion extending into dielectric layer 108 to physically and electrically couple conductive via 106. Therefore, UBM 186 is electrically coupled to conductive line 110 and local interconnect component 120. UBM 186 may be formed of the same material as conductive via 106. In some embodiments, UBM 186 has a pitch in the range from 20 μm to 80 μm.

[0071] exist Fig.16 In the embodiment of the present invention, a conductive connector 188 is formed on the UBM 186. The conductive connector 188 allows physical and electrical connection to the die or another package structure. The conductive connector 188 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. The conductive connector 188 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 188 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 188 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process.

[0072] The redistribution structure 200 may be larger and include multiple packaging regions, such as a first packaging region 101A and a second packaging region 101B. Fig.17 A redistribution structure 200 is shown in the shape of a circular wafer having multiple packaging regions. In the embodiment shown, four packaging regions 101A, 101B, 101C, and 101D are included on the wafer, allowing four final packaged components to be manufactured on a single wafer and then singulated. In other embodiments, fewer or more packaging regions may be utilized on a single wafer. Subsequent steps in the process use the redistribution structure 200 on the wafer template frame 190 as a basis on which to continue the manufacturing process described in further detail below. As described in further detail below, the individual packaging regions are singulated by sawing along line 402 and around the outer edges of the packaging regions 101A, 101B, 101C, and 101D.

[0073] Fig.18 A manufacturing process using a panel template having multiple packaging areas is shown to manufacture the redistribution structure 200. In the embodiment shown, nine packaging areas 101A to 101I are included on the wafer, allowing nine final packaged components to be manufactured on a single wafer or panel. In other embodiments, fewer or more packaging areas may be utilized on a single wafer or panel. Subsequent steps in the process use the redistribution structure 200 on the panel template frame 190 as a basis on which to continue the manufacturing process described in further detail below. As described in further detail below, the individual packaging areas are separated by sawing along line 402 and around the periphery of the packaging areas 101A to 101I.

[0074] exist Fig.19 In Figure 1 The illustrated integrated circuit package 500 can be attached to the redistribution structure 200 via the conductive connectors 188. The conductive connectors 188 attach the integrated circuit package 500 to the UBM 186 and the redistribution structure 200. Attaching the integrated circuit package 500 can include placing the dies 512 and 514 of the integrated circuit package 500 on the conductive connectors 188; and reflowing the conductive connectors 188 to physically and electrically couple the integrated circuit package 500 and the redistribution structure 200.

[0075] In some embodiments, an underfill 610 is formed around the conductive connectors 188 between the integrated circuit package 500 and the redistribution structure 200. The underfill 610 can reduce stress and protect joints caused by reflow of the conductive connectors 188. The underfill 610 can be formed by a capillary flow process after attaching the integrated circuit package 500, or can be formed by an appropriate deposition method. In some embodiments, a single layer of underfill 610 is formed under multiple adjacent devices, and further subsequent underfill (not shown) or sealant (not shown) can be formed under and / or around additional devices placed on top of the redistribution structure 200.

[0076] exist Fig. 20 In the embodiment, carrier substrate peeling is performed to separate (or "peel") carrier substrate 180 from conductive lines 174 and / or dielectric layer 172. According to some embodiments, peeling includes projecting light such as laser or UV light onto release layer 182 so that release layer 182 decomposes under the heat of the light and carrier substrate 180 can be removed.

[0077] Further in Fig.21 In the embodiment, the singulation process is performed by sawing along the scribe line region (eg, between the first package region 101A and the second package region 101B). The sawing separates the first package region 101A from adjacent package regions including the second package region 101B (shown) to form a plurality of singulated package components 100.

[0078] exist Fig. 22 In FIG. 1 , a core substrate 300 is shown, and in FIG. Fig.23 , bonded to the redistribution structure 200. Using the core substrate 300 has the advantage of enabling the core substrate 300 to be manufactured in a different process. In addition, because the core substrate 300 is formed in a different process, it can be tested individually so that a known good core substrate 300 is used. For example, in some embodiments, the core substrate 300 can be tested, verified and / or inspected individually or in batches before bonding the core substrate 300 to the redistribution structure 200.

[0079] The core substrate 300 may be, for example, an organic substrate, a ceramic substrate, a silicon substrate, etc. The conductive connector 365 is used to attach the core substrate 300 to the redistribution structure 200. Attaching the core substrate 300 may include placing the core substrate 300 on the redistribution structure 200, and reflowing the conductive connector 365 to physically and electrically couple the core substrate 300 and the redistribution structure 200.

[0080] Before being attached to the redistribution structure 200, the core substrate 300 may be processed according to an applicable manufacturing process to form a redistribution structure in the core substrate 300. For example, the core substrate 300 includes a core 310. The core 310 may be formed of one or more layers of glass fiber, resin, filler, prepreg material, epoxy resin, silica filler, Ajinomoto accumulation film (ABF), polyimide, molding compound, other materials and / or combinations thereof. In some embodiments, for example, two layers of material constitute the core 310. The core 310 may be formed of organic and / or inorganic materials. In some embodiments, the core 310 includes one or more passive components (not shown) embedded therein. The core 310 may include other materials or components. The conductive via 320 is formed to extend through the core 310. The conductive via 320 includes a conductive material 320A, such as copper, copper alloy or other conductor, and in some embodiments, may include a barrier layer (not shown), a liner (not shown), a seed layer (not shown) and / or a filling material 320B. Conductive vias 320 provide vertical electrical connections from one side of core 310 to the other side of core 310. For example, some conductive vias 320 are coupled between a conductive component at one side of core 310 and a conductive component at the opposite side of core 310. As an example, holes for conductive vias 320 can be formed using a drilling process, photolithography, laser processing, or other methods, and then the holes of conductive vias 320 are filled or plated with a conductive material. In some embodiments, conductive vias 320 are hollow conductive vias having a center filled with an insulating material. Redistribution structures 340A and 340B are formed on opposite sides of core 310. Redistribution structures 340A and 340B are electrically coupled through conductive vias 320 and fan-in / fan-out electrical signals.

[0081] The redistribution structures 340A and 340B each include a dielectric layer formed of ABF, prepreg material, etc., and a metallization pattern. Each corresponding metallization pattern has a line portion extending on and along the main surface of the corresponding dielectric layer, and has a through-hole portion extending through the corresponding dielectric layer. The redistribution structures 340A and 340B each include an under-bump metallization (UBM) 330A and 330B for external connection, and solder resists 350A and 350B for protecting components of the redistribution structures 340A and 340B. The redistribution structure 340A is formed by passing through the metallization pattern such as Fig.23 The UBM 330A of the conductive connector 365 is shown attached to the redistribution structure 200. Fig. 22 More or fewer dielectric layers and metallization patterns may be formed in the redistribution structures 340A and 340B than shown.

[0082] The core substrate 300 may include active and passive devices (not shown), or may have no active devices, passive devices, or both. A variety of devices may be used, such as transistors, capacitors, resistors, inductors, combinations of these, etc. The devices may be formed using any suitable method.

[0083] The conductive connector 365 can be used to bond the core substrate 300 to a substrate such as Fig.23 The redistribution structure 200 shown. The conductive connector 365 may be first formed on either the core substrate 300 or the redistribution structure 200, and then reflowed to complete the bonding. Fig.23 In the illustrated embodiment, a conductive connector 365 having a spacing between 150 μm and 1000 μm is formed on the UBM 330A of the bottom redistribution structure 340A. The conductive connector 365 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 365 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 365 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow may be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 365 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process.

[0084] exist Fig.23 In the embodiment of the present invention, the core substrate 300 is bonded to the segmented redistribution structure 200. In some embodiments, the core substrate 300 can be placed on the redistribution structure 200 using a pick and place process or another suitable process, and the conductive connectors 365 are bonded by a flip chip bonding process or other suitable bonding process. In some embodiments, the conductive connectors 365 are reflowed to attach the core substrate 300 to the redistribution structure 200 through the metallization pattern 174. The conductive connectors 365 electrically and / or physically couple the core substrate 300 to the redistribution structure 200. In some embodiments, the conductive connectors 365 have a pitch in a range from 20 μm to 500 μm.

[0085] The conductive connector 365 may have epoxy flux (not shown) formed thereon before reflow thereof, and at least some epoxy portion of the epoxy flux remains after attaching the core substrate 300 to the redistribution structure 200 .

[0086] In some embodiments, an underfill 370 is formed to surround the conductive connector 365 between the redistribution structure 200 and the core substrate 300. The underfill 370 can reduce stress and protect the joints caused by the reflow of the conductive connector 365. The underfill 370 can be formed by a capillary flow process after attaching the core substrate 300, or can be formed by a suitable deposition method. In some embodiments, a single layer of underfill 370 is formed, and a further subsequent underfill (not shown) or sealant (not shown) can be formed on top of the core substrate 300.

[0087] On the UBM 330B of the core substrate 300, a Figure 1 The external connector 620 is shown. The external connector 620 can be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, etc. The external connector 620 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the external connector 620 is formed by first forming a layer of reflowable material on the UBM 330B by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the layer of reflowable material is formed on the UBM 330B, reflow can be performed to shape the material into the desired bump shape.

[0088] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of known good dies to increase yield and reduce costs.

[0089] Embodiments can achieve advantages. For example, the local interconnect assembly increases the communication bandwidth between the integrated circuit dies while maintaining low contact resistance and high reliability. In addition, the redistribution structure, embedded local interconnect assembly, core substrate, and integrated circuit die can be individually manufactured and tested before assembling the completed package assembly. This further improves the reliability of the assembly and board level. Because of the increased communication bandwidth between the integrated circuit dies provided by the local interconnect assembly, no interposer is required between the integrated circuit die and the redistribution structure. By removing the need for an interposer, the warpage mismatch between the integrated circuit package (including the integrated circuit die) and the core substrate package (including the core substrate and the redistribution structure) is reduced because the coefficient of thermal expansion (CTE) mismatch between the two package structures is reduced.

[0090] Some embodiments of the present application provide a semiconductor structure, including: a core substrate; a redistribution structure coupled to a first side of the core substrate, the redistribution structure including: a plurality of redistribution layers, each of the plurality of redistribution layers including a dielectric layer and a metallization layer; a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure located on the substrate, and a conductive connector, the conductive connector being bonded to the metallization layer of the first redistribution layer through a first solder connector, the metallization layer of the first redistribution layer including a first wire and a first conductive via; and a first bottom filler located in the first redistribution layer, the first bottom filler surrounding the first solder connector; a first integrated circuit die coupled to the redistribution structure, the redistribution structure being interposed between the core substrate and the first integrated circuit die; a second integrated circuit die coupled to the redistribution structure, the redistribution structure being interposed between the core substrate and the second integrated circuit die, the interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die; and a group of conductive connectors coupled to a second side of the core substrate.

[0091] In some embodiments, the redistribution structure is coupled to the first side of the core substrate using a second solder connector. In some embodiments, the semiconductor structure further comprises: a second bottom filler interposed between the redistribution structure and the core substrate and surrounding the second solder connector. In some embodiments, the second bottom filler extends along the sidewalls of the redistribution structure. In some embodiments, the first bottom filler contacts the first conductive line and the dielectric layer of the first redistribution layer. In some embodiments, the interconnect structure of the first local interconnect component is located on a first side of the substrate of the first local interconnect component, the first side of the first local interconnect component facing the first integrated circuit die. In some embodiments, the first local interconnect component further comprises: a first through-hole extending through the substrate of the first local interconnect component, the first through-hole electrically coupled to the interconnect structure of the first local interconnect component and the metallization layer of the plurality of redistribution layers on a second side of the substrate of the first local interconnect component, the second side being opposite to the first side. In some embodiments, the substrate of the first local interconnect component is a silicon substrate.

[0092] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first redistribution structure above a first carrier substrate, wherein forming the first redistribution structure comprises: forming a first group of conductive lines above the first carrier substrate; forming a first group of conductive vias electrically coupled to the first group of conductive lines above the first group of conductive lines; bonding a first interconnection die to the first group of conductive lines through a first solder region, the first interconnection die comprising a substrate and an interconnection structure located on the substrate, the interconnection structure bonded to the first solder region, the first interconnection die being located between two of the first group of conductive vias; forming a first dielectric layer above the first group of conductive lines, the first group of conductive vias, and the first interconnection die, the first dielectric layer, the first group of conductive vias, and the first interconnection die being electrically coupled to the first group of conductive lines. , the first group of conductive lines and the first interconnect die form a first redistribution layer; and form a second redistribution layer above the first redistribution layer, the second redistribution layer comprising a second dielectric layer, a second group of conductive vias and a second group of conductive lines, at least one of the second group of conductive lines being electrically coupled to at least one of the first group of conductive vias; removing the first carrier substrate; electrically connecting the core substrate to a first side of the first redistribution structure, the second redistribution layer being closer to the first side of the first redistribution layer than the first redistribution layer; and bonding a first integrated circuit die and a second integrated circuit die to a second side of the first redistribution structure, the second side being opposite to the first side, the first integrated circuit die and the second integrated circuit die being electrically coupled to the first interconnect die.

[0093] In some embodiments, the method further comprises: after bonding the first interconnect die to the first group of wires through the first solder region, forming a first underfill around the first solder region between the first interconnect die and the first group of wires. In some embodiments, the method further comprises: after bonding the first integrated circuit die and the second integrated circuit die to the second side of the first redistribution structure, singulating through the first redistribution structure. In some embodiments, bonding the first interconnect die to the first group of wires through the first solder region comprises performing a reflow process to reflow the first solder region. In some embodiments, the method further comprises: forming a third redistribution layer over the first carrier substrate, forming the first redistribution layer over the third redistribution layer, the third redistribution layer comprising a third dielectric layer and a third group of conductive vias, at least one of the third group of conductive vias being electrically coupled to at least one of the first group of wires, the third redistribution layer being located between the first integrated circuit die and the first redistribution layer. In some embodiments, the third dielectric layer is made of a different material than the first dielectric layer. In some embodiments, the method further comprises: forming a second underfill between the first integrated circuit die and the second integrated circuit die and the second side of the first redistribution structure.

[0094] Some other embodiments of the present application provide a package, comprising: a first redistribution structure, the first redistribution structure comprising: a plurality of redistribution layers, each of the plurality of redistribution layers comprising a metallization pattern and a dielectric layer, the first redistribution layer of the plurality of redistribution layers comprising: a first dielectric layer; a first metallization pattern; a first interconnection die, the first interconnection die comprising a substrate, an interconnection structure located on the substrate, and a die connector located on the interconnection structure, the die connector being bonded to the metallization pattern of the first redistribution layer through a first solder bump, the first metallization pattern comprising a first wire and a first conductive via, the first dielectric layer sealing the first interconnection die; and a first bottom filler located between the first interconnection die and the first metallization pattern, the first bottom filler surrounding the first solder bump; a core substrate coupled to a first side of the first redistribution structure using a first set of conductive connectors, the width of the first redistribution structure being smaller than the width of the core substrate; and an integrated circuit die package coupled to a second side of the first redistribution structure using a second set of conductive connectors, the second side being opposite to the first side.

[0095] In some embodiments, the first group of conductive connectors and the second group of conductive connectors each include solder. In some embodiments, the package further includes: a second bottom filler, interposed between the core substrate and the first redistribution structure, and surrounding the second group of conductive connectors. In some embodiments, the first redistribution structure further includes a second redistribution layer, the second redistribution layer is located between the first redistribution layer and the integrated circuit die package, the second redistribution layer includes a second dielectric layer, and the second dielectric layer is a different material from the first dielectric layer. In some embodiments, the first interconnect die further includes: a first through-hole, extending through the substrate of the first interconnect die, the first through-hole electrically coupled to the interconnect structure of the first interconnect die and the metallization pattern of the multiple redistribution layers, the metallization pattern of the multiple redistribution layers is located on the side of the substrate of the first interconnect die opposite to the interconnect structure.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: core substrate; A redistribution structure coupled to the first side of the core substrate, the redistribution structure comprising: a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer; a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising a substrate, a first through hole, an interconnect structure and a conductive connector on the substrate, the conductive connector being bonded to a metallization layer of the first redistribution layer through a first solder connector, the metallization layer of the first redistribution layer comprising a first conductive line and a first conductive through hole, wherein the first through hole extends through the substrate of the first local interconnect component, the first through hole being electrically coupled to the interconnect structure of the first local interconnect component, wherein the first local interconnect component further comprises a first dielectric layer laterally sealing the conductive connector, the first dielectric layer laterally co-terminus with the first local interconnect component; and a first bottom filler disposed in the first redistribution layer, the first bottom filler surrounding the first solder connection; a first integrated circuit die coupled to the redistribution structure, the redistribution structure being interposed between the core substrate and the first integrated circuit die; a second integrated circuit die coupled to the redistribution structure, the redistribution structure being interposed between the core substrate and the second integrated circuit die, the interconnect structure of the first local interconnect assembly electrically coupling the first integrated circuit die to the second integrated circuit die; and A set of conductive connectors is coupled to the second side of the core substrate.

2. The semiconductor structure according to claim 1, wherein: The redistribution structure is coupled to the first side of the core substrate using a second solder connection.

3. The semiconductor structure according to claim 2, further comprising: A second underfill is interposed between the redistribution structure and the core substrate and surrounds the second solder connection.

4. The semiconductor structure according to claim 3, wherein: The second underfill extends along sidewalls of the redistribution structure.

5. The semiconductor structure according to claim 1, wherein: The first underfill contacts the first conductive line and a dielectric layer of the first redistribution layer.

6. The semiconductor structure according to claim 1, wherein: The interconnect structure of the first local interconnect component is located on a first side of the substrate of the first local interconnect component, the first side of the first local interconnect component facing the first integrated circuit die.

7. The semiconductor structure according to claim 6, wherein: The first via is electrically coupled to a metallization layer of the plurality of redistribution layers on a second side of the substrate of the first local interconnect component, the second side being opposite to the first side.

8. The semiconductor structure according to claim 1, wherein: The substrate of the first local interconnect component is a silicon substrate.

9. A method of forming a semiconductor structure, comprising: A first redistribution structure is formed over the first carrier substrate, wherein forming the first redistribution structure comprises: forming a first set of conductive lines over the first carrier substrate; forming a first set of conductive vias over the first set of conductive lines electrically coupled to the first set of conductive lines; bonding a first interconnect die to a first set of conductive lines through a first solder region, the first interconnect die comprising a substrate and an interconnect structure on the substrate, the interconnect structure bonded to the first solder region, the first interconnect die being located between two of the first set of conductive vias; forming a first dielectric layer over the first set of conductive lines, the first set of conductive vias, and the first interconnect die, the first dielectric layer, the first set of conductive vias, the first set of conductive lines, and the first interconnect die forming a first redistribution layer; and forming a second redistribution layer over the first redistribution layer, the second redistribution layer comprising a second dielectric layer, a second set of conductive vias, and a second set of conductive lines, at least one of the second set of conductive lines being electrically coupled to at least one of the first set of conductive vias; removing the first carrier substrate; electrically connecting a core substrate to a first side of the first redistribution structure, the second redistribution layer being closer to the first side of the first redistribution layer than the first redistribution layer; and A first integrated circuit die and a second integrated circuit die are bonded to a second side of the first redistribution structure, the second side being opposite the first side, the first integrated circuit die and the second integrated circuit die being electrically coupled to the first interconnect die.

10. The method according to claim 9, further comprising: After bonding the first interconnect die to the first set of conductive lines through the first solder region, a first underfill is formed between the first interconnect die and the first set of conductive lines around the first solder region.

11. The method according to claim 10, further comprising: Singulating through the first redistribution structure occurs after bonding the first integrated circuit die and the second integrated circuit die to the second side of the first redistribution structure.

12. The method according to claim 9, wherein: Bonding the first interconnect die to the first set of conductive lines through a first solder region includes performing a reflow process to reflow the first solder region.

13. The method according to claim 9, further comprising: A third redistribution layer is formed over the first carrier substrate, the first redistribution layer is formed over the third redistribution layer, the third redistribution layer includes a third dielectric layer and a third group of conductive vias, at least one of the third group of conductive vias is electrically coupled to at least one of the first group of conductive lines, and the third redistribution layer is located between the first integrated circuit die and the first redistribution layer.

14. The method according to claim 13, wherein: The third dielectric layer is made of a material different from that of the first dielectric layer.

15. The method according to claim 9, further comprising: A second underfill is formed between the first integrated circuit die and the second integrated circuit die and the second side of the first redistribution structure.

16. A package comprising: A first redistribution structure, wherein the first redistribution structure comprises: A plurality of redistribution layers, each of the plurality of redistribution layers comprising a metallization pattern and a dielectric layer, a first redistribution layer of the plurality of redistribution layers comprising: a first dielectric layer; a first metallization pattern; a first interconnect die, the first interconnect die comprising a substrate, an interconnect structure on the substrate, and a die connector on the interconnect structure, the die connector being bonded to a metallization pattern of the first redistribution layer through a first solder bump, the first metallization pattern comprising a first conductive line and a first conductive via, the first dielectric layer sealing the first interconnect die; and a first underfill disposed between the first interconnect die and the first metallization pattern, the first underfill surrounding the first solder bump; a core substrate coupled to a first side of the first redistribution structure using a first set of conductive connections, the first redistribution structure having a width less than a width of the core substrate; and An integrated circuit die package is coupled to a second side of the first redistribution structure using a second set of conductive connections, the second side being opposite to the first side, wherein the first interconnect die is embedded in the first redistribution layer, the first interconnect die interconnecting multiple integrated circuit dies in the integrated circuit die package.

17. The package according to claim 16, wherein: The first set of conductive connections and the second set of conductive connections each include solder.

18. The package of claim 16, further comprising: A second underfill is disposed between the core substrate and the first redistribution structure and surrounds the second group of conductive connections.

19. The package according to claim 16, wherein: The first redistribution structure further includes a second redistribution layer located between the first redistribution layer and the integrated circuit die package, the second redistribution layer including a second dielectric layer, the second dielectric layer being a different material from the first dielectric layer.

20. The package of claim 16, wherein: The first interconnect die further comprises: A first through-via extends through the substrate of the first interconnect die, the first through-via being electrically coupled to the interconnect structure of the first interconnect die and to the metallization patterns of the plurality of redistribution layers, the metallization patterns of the plurality of redistribution layers being located on a side of the substrate of the first interconnect die opposite to the interconnect structure.

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