Method of manufacturing a display device

Abstract

A method of manufacturing a display device includes: forming a thin-film transistor on a substrate and forming a planarization layer to cover the thin-film transistor; forming a pixel electrode electrically connected to the thin-film transistor and a pixel defining layer exposing at least a central portion of the pixel electrode on the planarization layer; and defining at least one trench having a closed curve shape at a location corresponding to a second non-display area. When the thin-film transistor is formed, voltage lines are also formed at a location corresponding to a first non-display area. When the at least one trench is formed, a portion of the planarization layer disposed between a pad area and a display area is simultaneously removed, exposing a portion of the voltage lines located between the pad area and the display area.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0024472, filed on February 27, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a method of manufacturing a display device. Background Technology

[0003] With the rapid development of display technologies for visually representing electrical signal information, various display devices with excellent characteristics such as thin profile, light weight, and low power consumption have been developed. Recently, in order to expand the display area on which images are displayed, a display device has been introduced in which physical buttons and the like are removed from the front of the display device, and electronic components such as cameras and sensors are placed within the display area.

[0004] Since organic light-emitting diodes (OLEDs) are self-emitting display devices, they do not require an additional light source. Therefore, OLEDs can be driven with low voltage and can be manufactured to be lightweight and thin. Furthermore, OLEDs possess desirable characteristics such as wide viewing angles, high contrast, and fast response times. However, OLEDs can degrade due to moisture or oxygen, and therefore it is necessary to prevent external moisture or oxygen from penetrating into the OLED. Summary of the Invention

[0005] One or more embodiments include a method of manufacturing a display device by means of which external moisture or oxygen can be effectively prevented from penetrating into the display device.

[0006] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be understood by practice of the embodiments of the present disclosure presented.

[0007] According to one or more embodiments, a method of manufacturing a display device includes a display area, a first non-display area, and a second non-display area. The first non-display area is located around the display area and includes a pad area on one side of the first non-display area. The second non-display area is at least partially surrounded by the display area. The method includes: forming a thin-film transistor on a substrate at a location corresponding to the display area, and forming a planarization layer to cover the thin-film transistor; forming a pixel electrode electrically connected to the thin-film transistor and a pixel defining layer exposing at least a central portion of the pixel electrode on the planarization layer; and defining at least one trench extending from the surface of the substrate in a thickness direction at a location corresponding to the second non-display area, the at least one trench having a closed curve shape. When forming the thin-film transistor, a voltage line for applying voltage to the display device is formed together with the thin-film transistor at a location corresponding to the first non-display area. When forming the at least one trench, a portion of the planarization layer disposed between the pad area and the display area is simultaneously removed, such that a portion of the voltage line between the pad area and the display area is exposed.

[0008] The substrate may have a multilayer structure in which a first base layer, a first barrier layer, a second base layer, and a second barrier layer are sequentially stacked, and at least one groove may be defined as extending from the second barrier layer to at least a portion of the second base layer in the thickness direction of the substrate.

[0009] Prior to the formation of at least one groove, a cover layer may be formed on the entire substrate. The cover layer may be patterned to define openings in the cover layer at the location where at least one groove is to be defined and at the location between the pad area and the display area. The formation of at least one groove and the removal of a portion of the planarization layer disposed between the pad area and the display area are performed via the openings.

[0010] By performing dry etching using a cover layer as a mask, at least one trench can be formed, and a portion of the planarization layer disposed between the pad area and the display area can be removed.

[0011] The capping layer may include at least one of indium tin oxide, indium zinc oxide, tin zinc indium oxide, gallium zinc oxide, and gallium zinc indium oxide.

[0012] When a portion of the planarization layer disposed between the pad area and the display area is removed, a first dam and a levee can be formed around the display area, and voltage lines can be exposed in the adhesion area between the first dam and the levee.

[0013] The method may further include: forming an intermediate layer including an emission layer on a pixel electrode and forming a counter electrode on the intermediate layer; sequentially forming a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer on the counter electrode; and defining a via within a region defined by at least one trench.

[0014] The first inorganic encapsulation layer can directly contact the voltage line and the second inorganic encapsulation layer in the adhesion region.

[0015] At least one slot may include a first slot surrounding a through-hole and a second slot located between the first slot and the through-hole and surrounding the through-hole, an organic encapsulation layer may fill the first slot, and a first inorganic encapsulation layer and a second inorganic encapsulation layer may be in direct contact with each other within the second slot.

[0016] The intermediate layer can be broken by at least one groove and can be formed discontinuously.

[0017] A thin-film transistor may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. A first inorganic insulating layer may be formed between the semiconductor layer and the gate electrode to cover the entire substrate, and a second inorganic insulating layer may be formed between the gate electrode and the source and drain electrodes to cover the entire substrate. In the adhesion region, the first inorganic encapsulation layer may directly contact the second inorganic insulating layer.

[0018] The pixel defining layer can be formed on the planarization layer and disposed between the pad area and the display area, and when at least one slot is formed, the pixel defining layer and the planarization layer can be removed from the adhesion area.

[0019] The voltage lines may include a first voltage line and a second voltage line that apply different voltages to each other. The first voltage line may include a first main voltage line formed between the display area and the pad area to correspond to a first edge of the display area, and a first connection unit extending from the first main voltage line to the pad area. The second voltage line may include a second main voltage line surrounding the remaining edges of the display area other than the first edge, and a second connection unit extending from the second main voltage line to the pad area. The corresponding portions of the first and second connection units between the pad area and the display area may be exposed.

[0020] The voltage line can be a three-layer structure comprising a first metal layer, a second metal layer, and a third metal layer, and the etching rate of the second metal layer can be greater than the etching rate of each of the first and third metal layers. Attached Figure Description

[0021] The above and other aspects, features, and advantages of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0023] Figure 2 yes Figure 1 A schematic plan view of area A;

[0024] Figure 3It is along Figure 2 A cross-sectional view of the display device taken by line I-I';

[0025] Figure 4 yes Figure 1 A schematic plan view of area B;

[0026] Figure 5 yes Figure 4 A schematic plan view of area C;

[0027] Figure 6 It is along Figure 5 A cross-sectional view of region C intercepted by line II-II';

[0028] Figure 7 It is along Figure 5 A cross-sectional view of region C intercepted by line III-III'; and

[0029] Figures 8 to 12 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. Detailed Implementation

[0030] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only with reference to the accompanying drawings to explain aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0031] One or more embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. Unless otherwise specified in the drawing numbers, identical or corresponding parts are given the same reference numerals, and redundant descriptions are omitted.

[0032] It will be understood that while this document may use terms such as "first," "second," etc., to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0033] As used herein, the singular forms “a” and “the (said)” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0034] It will be further understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0035] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be formed directly or indirectly on that other layer, region, or component. That is, for example, intermediate layers, regions, or components may exist.

[0036] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily illustrated for ease of explanation, the embodiments of the present invention described below are not limited thereto.

[0037] When an embodiment can be implemented differently, a particular process can be performed in a sequence different from that described. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0038] It will also be understood that when a layer, region, or component is referred to as "connected" or "coupled" to another layer, region, or component, it may be directly connected or coupled to the other layer, region, or component, or there may be intermediate layers, regions, or components. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or coupled to the other layer, region, or component, or there may be intermediate layers, regions, or components.

[0039] Figure 1 This is a schematic plan view of the display device 10 according to an embodiment.

[0040] refer to Figure 1 According to an embodiment, the display device 10 includes a display area DA for displaying an image, a first non-display area PA1 located outside the display area DA, and a second non-display area PA2 at least partially surrounded by the display area DA. In other words, the display area DA, the first non-display area PA1, and the second non-display area PA2 are defined in a substrate 100.

[0041] The display element is located in the display area DA, and the first non-display area PA1 may include a pad area PADA in which various electronic devices or printed circuit boards (“PCBs”) are electrically attached. A first voltage line 410 and a second voltage line 420 may be located in the first non-display area PA1.

[0042] The second non-display area PA2 may be at least partially surrounded by the display area DA, and at least one through-hole H may be located in the second non-display area PA2. Although in Figure 1The second non-display area PA2 is located within the display area DA, and therefore the display area DA completely surrounds the second non-display area PA2, but embodiments of the invention are not limited thereto. For example, in another embodiment, a portion of the second non-display area PA2 may contact the first non-display area PA1. In yet another embodiment, two or more through-holes H may be provided within the second non-display area PA2.

[0043] The through-hole H can serve as space for additional components that enable the display device 10 to function or for additional components that can add new functions to the display device 10. For example, sensors, light sources, and camera modules can be located in the through-hole H. However, since the through-hole H penetrates vertically through the substrate 100 and the multiple layers stacked on the substrate 100, external moisture or oxygen may penetrate into the inner surface of the display device 10 exposed by the through-hole H. However, according to an embodiment, at least one groove is formed around the through-hole H, thereby effectively preventing moisture penetration.

[0044] Figure 1 This is a plan view of the substrate 100, etc., during the manufacturing process of the display device 10. In the final display device 10 or an electronic device such as a smartphone that includes the display device 10, a portion of the substrate 100 may be bent to minimize the area of ​​the first non-display area PA1, which is recognizable to the user in the plan view. In this case, the substrate 100, etc., is bent such that the pad area PADA is located behind the display area DA, and therefore, the user can recognize that the display area DA occupies most of the display device 10 in the plan view.

[0045] The substrate 100 may comprise a variety of suitable materials having flexible or bendable properties. For example, the substrate 100 may comprise polymeric resins such as polyethersulfone (“PES”), polyacrylate, polyetherimide (“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyphenylene sulfide (“PPS”), polyarylate (“PAR”), polyimide (“PI”), polycarbonate (“PC”), or cellulose acetate propionate (“CAP”). The substrate 100 may have a multilayer structure comprising two layers, each comprising a polymeric resin, and a barrier layer between the two layers comprising an inorganic material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). Various modifications can be made in this manner.

[0046] Figure 2 yes Figure 1 A plan view of region A, and Figure 3 It is along Figure 2 A cross-sectional view of the region A intercepted by line I-I'.

[0047] refer to Figure 2 and Figure 3The first slot G1 and the second slot G2 can be located in the area of ​​the second display area PA2 between the through hole H and the display area DA, and can surround the through hole H. However, embodiments of the invention are not limited to this, and in another embodiment, one slot, or three or more slots, can be provided. In other words, one or more slots can be provided around the through hole H. However, an example of two slots G1 and G2 (i.e., the first slot G1 and the second slot G2) being provided around the through hole H will now be described. Depending on their distance from the through hole H, the two slots G1 and G2 will be referred to as the first slot G1 and the second slot G2. In other words, the slot set to be furthest from the through hole H is referred to as the first slot G1.

[0048] Thin-film transistor 210 and display element are located in display area DA on substrate 100. Figure 3 The illustration shows an organic light-emitting diode 300 as a display element. Additionally, another thin-film transistor (not shown) can be disposed in the first non-display area PA1 of the substrate 100 (see [reference]). Figure 1 (in) . Located in Figure 1 Another thin-film transistor in the first non-display area PA1 may be part of a circuit unit used to control the electrical signals applied to the display area DA.

[0049] The substrate 100 may have a multilayer structure in which a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 are stacked sequentially.

[0050] The first substrate layer 101 and the second substrate layer 103 may include, for example, a transparent glass material containing SiO2 as a main component. However, the materials contained in the first substrate layer 101 and the second substrate layer 103 according to the present invention are not limited thereto, and in another embodiment, the first substrate layer 101 and the second substrate layer 103 may include a transparent plastic material. The plastic material may be polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide, polycarbonate (PC), cellulose triacetate (“TAC”), or cellulose acetate propionate (CAP), etc.

[0051] The first substrate 101 and the second substrate 103 may have the same or different thicknesses. For example, each of the first substrate 101 and the second substrate 103 may include polyimide and may have a thickness of about 3 micrometers (μm) to about 20 μm.

[0052] Each of the first barrier layer 102 and the second barrier layer 104 prevents external foreign matter from penetrating through the substrate 100 into the display device 10, and may include materials such as SiN. x and / or SiOx The inorganic material can be a single layer or multiple layers. For example, the first barrier layer 102 may be a multilayer comprising an amorphous silicon layer and a silicon oxide layer to improve adhesion between adjacent layers, and the second barrier layer 104 may be a silicon oxide layer. Each of the first barrier layer 102 and the second barrier layer 104 may have a spacing of approximately 4000 angstroms. up to approximately The thickness is [not specified], but is not limited to this according to embodiments of the present invention.

[0053] A buffer layer may be further provided on the substrate 100. The buffer layer can planarize the upper surface of the substrate 100 and prevent foreign matter or moisture from penetrating through the substrate 100. For example, the buffer layer may comprise inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride) or organic materials (such as polyimide, polyester, or acrylic acid), or may be a stack of these materials. According to some embodiments, the second barrier layer 104 of the substrate 100 may be part of a buffer layer having a multilayer structure.

[0054] The thin-film transistor 210 on the substrate 100 includes a semiconductor layer 211, a gate electrode 213, a source electrode 215, and a drain electrode 217. When a buffer layer is disposed on the substrate 100, the semiconductor layer 211 may be located on the buffer layer.

[0055] Semiconductor layer 211 may include amorphous silicon, polycrystalline silicon or organic semiconductor materials.

[0056] Gate electrode 213 is disposed above semiconductor layer 211. Source electrode 215 and drain electrode 217 are electrically connected to each other in response to a signal applied to gate electrode 213.

[0057] The gate electrode 213 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer or multi-layer structure. To ensure insulation between the semiconductor layer 211 and the gate electrode 213, a first inorganic insulating layer 120, comprising an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, may be disposed between the semiconductor layer 211 and the gate electrode 213.

[0058] The second inorganic insulating layer 130 may be on the gate electrode 213 and may include inorganic materials such as silicon oxide, silicon nitride or silicon oxynitride and have a single-layer or multi-layer structure.

[0059] Source electrode 215 and drain electrode 217 are located on the second inorganic insulating layer 130. Source electrode 215 and drain electrode 217 can be electrically connected to semiconductor layer 211 via contact holes defined in the second inorganic insulating layer 130 and the first inorganic insulating layer 120. Considering conductivity, etc., each of source electrode 215 and drain electrode 217 can include at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can have a single-layer or multi-layer structure. For example, each of source electrode 215 and drain electrode 217 can be a Ti / Al / Ti trilayer.

[0060] The planarization layer 140 can be on the thin-film transistor 210. For example, when the organic light-emitting diode 300 is as follows: Figure 3 As shown, when positioned higher than the thin-film transistor 210, the planarization layer 140 can cover the thin-film transistor 210 and planarize the unevenness caused by the thin-film transistor 210. The planarization layer 140 may comprise an organic insulating material such as acrylic acid, benzocyclobutene (“BCB”), or hexamethyldisiloxane (“HMDSO”). Although in Figure 3 The planarization layer 140 is a single layer, but various modifications can be made to it. For example, in another embodiment, the planarization layer 140 can be a stack of multiple layers.

[0061] The organic light-emitting diode 300 is located on the planarization layer 140 within the display area DA of the substrate 100. The organic light-emitting diode 300 includes a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 between the pixel electrode 310 and the counter electrode 330, which includes an emission layer.

[0062] The pixel electrode 310 is on the planarization layer 140. An opening that exposes at least one of the source electrode 215 and the drain electrode 217 of the thin-film transistor 210 is defined by the planarization layer 140, and the pixel electrode 310 can be electrically connected to the thin-film transistor 210 by contacting the source electrode 215 or the drain electrode 217 through the opening.

[0063] The pixel electrode 310 can be a transparent (or semi-transparent) electrode or a reflective electrode. When the pixel electrode 310 is a transparent (or semi-transparent) electrode, it can include, for example, indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”). When the pixel electrode 310 is a reflective electrode, it can include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof, and a layer containing ITO, IZO, ZnO, In2O3, IGO, or AZO. Of course, the disclosure of the present invention is not limited thereto, and the pixel electrode 310 can include any of a variety of other materials and can have any of a variety of structures, such as a single-layer structure or a multi-layer structure.

[0064] The pixel defining layer 150 may be on the planarization layer 140. The pixel defining layer 150 defines pixels through openings through which at least the central portion of the pixel electrode 310 is exposed. In such a way... Figure 3 In the case shown, the pixel defining layer 150 prevents arcing at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 disposed above the pixel electrode 310. The pixel defining layer 150 may include an organic insulating material, such as polyimide or HMDSO.

[0065] The intermediate layer 320 of the organic light-emitting diode 300 includes an emission layer. The emission layer may include a low-molecular-weight or high-molecular-weight organic material that emits light of a specific color. The intermediate layer 320 may further include at least one functional layer selected from a hole transport layer (“HTL”), a hole injection layer (“HIL”), an electron transport layer (“ETL”), and an electron injection layer (“EIL”). Such a functional layer may include an organic material. Some of the multiple layers constituting the intermediate layer 320 (e.g., functional layers) may extend integrally over the multiple pixel electrodes 310.

[0066] The counter electrode 330 can be configured to cover the display area DA. The counter electrode 330 can be formed as a single unit constituting a plurality of organic light-emitting diodes 300, and thus can correspond to a plurality of pixel electrodes 310. The counter electrode 330 can be a transparent (or semi-transparent) electrode or a reflective electrode. When the counter electrode 330 is a transparent (or semi-transparent) electrode, it can have a layer comprising a metal with a small work function (e.g., Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or compounds thereof) and a transparent (or semi-transparent) conductive layer comprising, for example, ITO, IZO, ZnO, or In2O3. When the counter electrode 330 is a reflective electrode, it can have a layer comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or compounds thereof. The configuration of the counter electrode 330 according to the present invention and the materials contained in the counter electrode 330 are not limited to those described above, and various modifications can be made to the counter electrode 330.

[0067] The encapsulation layer 500 is located above the counter electrode 330. The encapsulation layer 500 protects the organic light-emitting diode 300 from external moisture or oxygen. For this purpose, the encapsulation layer 500 extends above the display area DA where the organic light-emitting diode 300 is located, and extends into the first non-display area PA1 outside the display area DA. The encapsulation layer 500 may have a multilayer structure. Specifically, as... Figure 3 As shown, the encapsulation layer 500 may include a first inorganic encapsulation layer 510, an organic encapsulation layer 520, and a second inorganic encapsulation layer 530.

[0068] The first inorganic encapsulation layer 510 may include silicon oxide, silicon nitride, and / or silicon oxynitride. Since the first inorganic encapsulation layer 510 is formed along the structure beneath it, the upper surface of the first inorganic encapsulation layer 510 may not be flat, such as… Figure 3 As shown in the image.

[0069] The organic encapsulation layer 520 covers the first inorganic encapsulation layer 510 and has sufficient thickness, and therefore the organic encapsulation layer 520 can have an approximately flat upper surface over the entire display area DA. The organic encapsulation layer 520 may comprise polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyl disiloxane, acrylic resin (e.g., polymethyl methacrylate or polyacrylic acid), or any combination thereof.

[0070] The second inorganic encapsulation layer 530 may cover the organic encapsulation layer 520 and may include silicon oxide, silicon nitride, and / or silicon oxynitride. The second inorganic encapsulation layer 530 may extend beyond the organic encapsulation layer 520 and may contact the first inorganic encapsulation layer 510, so that the organic encapsulation layer 520 may not be exposed to the outside.

[0071] In the second non-display area PA2, the first groove G1 and the second groove G2 surround the through hole H at positions spaced apart from it. The second groove G2 surrounds the through hole H at a position between the first groove G1 and the through hole H.

[0072] Each of the first groove G1 and the second groove G2 may have an undercut structure. For example, each of the first groove G1 and the second groove G2 may extend from the second barrier layer 104 of the substrate 100 in the thickness direction of the substrate 100 to at least a portion of the second base layer 103. As used herein, the term "thickness direction of the substrate" refers to a direction perpendicular to the plane defining the main surface of the substrate (i.e., the plane defined by directions X and Y in the figures), like... Figure 3 The direction Z in the middle.

[0073] In this state, the second barrier layer 104 may include a pair of first tips T1 extending toward each other in the upper opening of the first groove G1 and between the first groove G1 therebetween, and a pair of second tips T2 extending toward each other in the upper opening of the second groove G2 and between the second groove G2 therebetween.

[0074] The first trench G1 and the second trench G2 can be formed by defining openings in the respective portions of the second barrier layer 104 that define the first trench G1 and the second trench G2, and then dry etching through these openings to remove portions of the second substrate layer 103. Thus, portions of the second substrate layer 103 can be removed to define cavities wider than each opening in the second barrier layer 104.

[0075] Therefore, the width of the upper opening of the first groove G1 can be smaller than the width of the bottom of the first groove G1, and the second barrier layer 104 in the upper opening of the first groove G1 can include a pair of first tips T1 facing each other. The first tips T1 can both have a cantilever shape. The width of the first groove G1 is a distance measured in a direction perpendicular to the longitudinal direction of the first groove G1. For example, when the first groove G1 has an annular shape, the width of the first groove G1 is in the radial direction of the annulus. Here, the radial direction is on the main surface plane of the substrate 100, such that the radial direction is perpendicular to the thickness direction of the substrate 100. When a buffer layer is further provided on the substrate 100, the buffer layer can define the first tips T1 together with the second barrier layer 104.

[0076] Similarly, the second barrier layer 104 may include a pair of second tips T2 extending toward each other and surrounding the through hole H in the upper opening of the second groove G2, the second groove G2 being between the pair of second tips T2, and the second groove G2 may have an undercut structure.

[0077] As described above, some of the multiple layers constituting the intermediate layer 320 (e.g., functional layers) can extend over the multiple pixel electrodes 310, thus these layers are formed not only in the display area DA but also in the second non-display area PA2. However, due to the undercut structure formed by the first tip T1 and the second tip T2 respectively, the intermediate layer 320 may not be disposed on the corresponding inner wall surfaces of the openings of the first groove G1 and the second groove G2, but may only be formed on the corresponding local areas of the corresponding bottom surfaces of the first groove G1 and the second groove G2.

[0078] Therefore, the organic layer contained in the intermediate layer 320 is disconnected by the first groove G1 and the second groove G2, and thus external moisture or oxygen can be prevented from penetrating into the display area DA through the through hole H along the organic layer in the intermediate layer 320.

[0079] The encapsulation layer 500 is provided not only in the display area DA where the organic light-emitting diode 300 is located, but also in the second non-display area PA2.

[0080] As described above, due to the undercut structure of the first groove G1 and the second groove G2, the functional layer contained in the intermediate layer 320 is not formed on the corresponding inner wall surface in the upper end of the opening of the first groove G1 and the second groove G2. However, since the first inorganic encapsulation layer 510 of the encapsulation layer 500 is formed conformally by chemical vapor deposition or the like, the first inorganic encapsulation layer 510 can be formed not only on the bottom surface of the first groove G1 and the second groove G2, but also on the inner wall surface in the upper end of the opening of the first groove G1 and the second groove G2, and on the lower surface of the first tip T1 and the second tip T2. Therefore, the first inorganic encapsulation layer 510 can be formed continuously without interruption.

[0081] The organic encapsulation layer 520 can fill the first groove G1. Therefore, when the organic encapsulation layer 520 is formed, the material used to form the organic encapsulation layer 520 can be prevented from flowing to the second groove G2, and thus the area in which the organic encapsulation layer 520 is formed can be limited.

[0082] The second inorganic encapsulation layer 530 can be formed similarly to the first inorganic encapsulation layer 510. Therefore, the second inorganic encapsulation layer 530 and the first inorganic encapsulation layer 510 can contact each other in the second groove G2, and thus can effectively prevent the penetration of external moisture and oxygen.

[0083] Figure 4 yes Figure 1 A plan view of region B. Figure 5 yes Figure 4 A plan view of region C. Figure 6 It is along Figure 5 An example cross-sectional view of the section cut by line II-II', and Figure 7 It is along Figure 5A cross-sectional view of an example section taken from line III-III'.

[0084] refer to Figures 4 to 7 The first voltage line 410 and the second voltage line 420 can be located in the first non-display area PA1 to supply driving power to Figure 3 The organic light-emitting diode 300. For example, the first voltage line 410 can be a driving voltage line, and the second voltage line 420 can be a common voltage line. The second voltage line 420 can be directly connected to... Figure 3 The first voltage line 410 and the second voltage line 420 can be connected to the counter electrode 330 via another line. In the manufacturing process, the first voltage line 410 and the second voltage line 420 can be... Figure 3 The source electrode 215 and Figure 3 The drain electrode 217 is formed simultaneously with the source electrode 215 and the drain electrode 217, and may include the same material as the source electrode 215 and the drain electrode 217. For example, as Figure 7 As shown, the first voltage line 410 and the second voltage line 420 can be a three-layer structure in which a first metal layer M1, a second metal layer M2, and a third metal layer M3 are stacked. The first metal layer M1 and the third metal layer M3 may include Ti, and the second metal layer M2 may include Al.

[0085] The first voltage line 410 can be set Figure 1 The first voltage line 410 may include a first main voltage line 412 configured to correspond to one side of the display area DA and a first connection unit 414. For example, when the display area DA is rectangular, the first main voltage line 412 may be configured to correspond to one edge of the display area DA. The first main voltage line 412 may be parallel to this edge of the display area DA and may have a length equal to or greater than the length of this edge. This edge corresponding to the first main voltage line 412 may be the edge of the display area DA between the display area DA and the pad area PADA. Figure 1 The edge of the pad area PADA is adjacent to.

[0086] The first connection unit 414 can protrude from the first main voltage line 412 and face towards Figure 1 The pad area PADA extends in the direction of the pad and can therefore be connected to the pad cell (not shown).

[0087] The second voltage line 420 may surround the remaining area of ​​the display area DA. The second voltage line 420 may include a second main voltage line 422 surrounding both ends of the first main voltage line 412 and the remaining area of ​​the display area DA, and a second connection unit 424 extending from the second main voltage line 422 and configured to be parallel to the first connection unit 414. The second connection unit 424 may be connected to a pad unit (not shown).

[0088] like Figure 5 As shown, a portion of the planarization layer 140 is removed from the first non-display area PA1. The area of ​​the first non-display area PA1 in which the planarization layer 140 has been removed surrounds the display area DA. Therefore, external moisture can be prevented from penetrating into the display area DA via the planarization layer 140 formed of organic material.

[0089] When the encapsulation layer 500 is formed, or more specifically, when the organic encapsulation layer 520 is formed, the material used to form the organic encapsulation layer 520 needs to be confined to a predetermined area. For this purpose, as... Figure 5 and Figure 6 As shown, the first dam 610 may be located within the first non-display area PA1. The first dam 610 may be located within the first non-display area PA1 to be separated from the planarization layer 140, and may surround the display area DA.

[0090] The first dam, 610, can have a multi-layered structure. For example, as... Figure 6 As shown, the first dam 610 may have a structure in which a lower layer 611 and an upper layer 613 are stacked. For example, the lower layer 611 may be formed using the same material as the material used to form the planarization layer 140, and may be formed simultaneously with the formation of the planarization layer 140, and the upper layer 613 may be formed using the same material as the material used to form the pixel defining layer 150, and may be formed simultaneously with the formation of the pixel defining layer 150.

[0091] The second dam 620 may be further located inside the first dam 610. That is, the second dam 620 may be located between the first dam 610 and the display area DA. The second dam 620 may be formed using the same material as the material used to form the planarization layer 140 or the pixel defining layer 150, and may be formed simultaneously with the formation of the planarization layer 140 or the pixel defining layer 150. The second dam 620 may have a height lower than that of the first dam 610 in the Z direction.

[0092] The first dam 610 and the second dam 620 can surround the display area DA to block the material used to form the organic encapsulation layer 520 from diffusing toward the edge of the substrate 100, thereby limiting the position of the organic encapsulation layer 520 and preventing the formation of the edge tail of the organic encapsulation layer 520.

[0093] Dike 630 may be further located outside the first dam 610. Dike 630 may surround the first dam 610. Figure 1 During the manufacturing of the display device 10, the dike 630 supports are used to form Figure 3 Organic light-emitting diode 300 Figure 3 The middle layer 320 or Figure 3The mask for the counter electrode 330. Simultaneously, the dam 630 can prevent previously formed components from contacting and damaging the mask. For example, the dam 630 can have a structure in which a first layer 631, a second layer 633, and a third layer 635 are stacked. The first layer 631 can be formed using the same material used to form the planarization layer 140 and can be formed simultaneously with the formation of the planarization layer 140, and the second layer 633 can be formed using the same material used to form the pixel defining layer 150 and can be formed simultaneously with the formation of the pixel defining layer 150. The third layer 635 can be formed on the second layer 633 using the same material used to form the second layer 633. For example, the third layer 635 can be formed together with the second layer 633 during the formation of the pixel defining layer 150 using a halftone mask.

[0094] The first dam 610, the second dam 620, and the dike 630 are located in the area of ​​the first non-display zone PA1 where the planarization layer 140 has been removed. In this case, as Figure 6 As shown, the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 can cover the dam 630 and extend to the outside of the dam 630. Therefore, the area between the first dam 610 and the dam 630 can be defined as the adhesion area AA consisting only of the inorganic layers. Since the first inorganic encapsulation layer 510 directly contacts the second inorganic encapsulation layer 530 and another inorganic layer (e.g., the second inorganic insulating layer 130) below the first inorganic encapsulation layer 510 in the adhesion area AA, the bonding strength of the film encapsulation layer 500 can be improved, and thus the penetration of external moisture and oxygen can be prevented more effectively.

[0095] When the planarization layer 140 is removed in the first non-display area PA1, the first voltage line 410 and the second voltage line 420 located below the planarization layer 140 can be partially exposed, and the exposed portions of the first voltage line 410 and the second voltage line 420 can directly contact the first inorganic encapsulation layer 510. Specifically, in the adhesion area AA, such as Figure 7 As shown, the planarization layer 140 is removed and thus the first connection unit 414 and the second connection unit 424 are exposed, and the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 are directly provided on the exposed first connection unit 414 and the second connection unit 424.

[0096] The planarization layer 140 can be patterned by performing wet etching via, for example, a photolithography process. Meanwhile, the first voltage line 410 and the second voltage line 420 exposed to the developer used to etch the planarization layer 140 may be damaged.

[0097] Specifically, when each of the first voltage line 410 and the second voltage line 420 is a three-layer structure comprising a first metal layer M1, a second metal layer M2, and a third metal layer M3, the etching rate of the second metal layer M2, which comprises Al, is greater than the etching rate of each of the first metal layer M1 and the third metal layer M3, which comprises Ti. Therefore, while the planarization layer 140 is removed in the adhesion region AA via wet etching, the second metal layer M2 exposed to the developer is over-etched than the first metal layer M1 and the third metal layer M3, and thus, undercut structures can be formed on the side surfaces of the first connection unit 414 and the second connection unit 424. In this state, when the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 are formed, step coverage may decrease at the side surfaces of the first connection unit 414 and the second connection unit 424, and therefore, damage (such as cracks) may occur in the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530.

[0098] The first voltage line 410 and the second voltage line 420 may also be damaged by the developer between the first dam 610 and the second dam 620, and between the second dam 620 and the display area DA. However, since the organic encapsulation layer 520 is provided on the first inorganic encapsulation layer 510 between the second dam 620 and the display area DA, and the area of ​​the space between the first dam 610 and the second dam 620 is smaller than the area of ​​the adhesion area AA, even if damage to the first voltage line 410 and the second voltage line 420 due to the developer occurs between the first dam 610 and the second dam 620, and between the second dam 620 and the display area DA, the probability of direct damage to the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 is likely to be low. Therefore, it is important to prevent the formation of undercut structures on the corresponding side surfaces of the first connection unit 414 and the second connection unit 424 while the planarization layer 140 is being removed in the adhesion area AA. Reference will now be made to... Figures 8 to 12 Description of manufacturing Figure 1 A method for display device 10 in which the side surfaces of the first connecting unit 414 and the second connecting unit 424 exposed in the adhesion area AA are not damaged.

[0099] Figures 8 to 12 This is a schematic cross-sectional view illustrating a method of manufacturing a display device 10 according to an embodiment. Figures 8 to 12 Each illustration in the diagram Figure 2 The I-I' section and Figure 6 The cross section of region II(2)-II'.

[0100] Now refer to Figures 8 to 12 Together Figure 1The following describes a method for manufacturing a display device 10. As described above, the display device 10 may include a display area DA, a first non-display area PA1 located outside the display area DA, and a second non-display area PA2 at least partially surrounded by the display area DA.

[0101] A method of manufacturing a display device 10 may include: forming a thin-film transistor 210 at a location corresponding to a display area DA on a substrate 100 and forming a planarization layer 140 to cover the thin-film transistor 210; forming a pixel electrode 310 electrically connected to the thin-film transistor 210 and a pixel defining layer 150 at least exposing the center of the pixel electrode 310 on the planarization layer 140; forming at least one trench at a location corresponding to a second non-display area PA2; forming an intermediate layer 320 including an emission layer on the pixel electrode 310 and forming a counter electrode 330 on the intermediate layer 320; forming an encapsulation layer 500 by sequentially stacking a first inorganic encapsulation layer 510, an organic encapsulation layer 520 and a second inorganic encapsulation layer 530 on the counter electrode 330; and defining a via H in the region defined by at least one trench. The structure in which the first trench G1 and the second trench G2 surround the via H will now be described.

[0102] The substrate 100 may have a multilayer structure in which a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 are stacked sequentially.

[0103] The thin-film transistor 210 includes a semiconductor layer 211, a gate electrode 213, a source electrode 215, and a drain electrode 217. Simultaneously, a first inorganic insulating layer 120 between the semiconductor layer 211 and the gate electrode 213, and a second inorganic insulating layer 130 between the gate electrode 213 and the source electrode 215 and the drain electrode 217, can be formed corresponding to the entire substrate 100. In other words, the first inorganic insulating layer 120 and the second inorganic insulating layer 130 can be formed in both the first non-display area PA1 and the second non-display area PA2.

[0104] When the thin-film transistor 210 is formed, the first voltage line 410 and the second voltage line 420 can be formed together in the first non-display area PA1. The first voltage line 410 and the second voltage line 420 can be formed simultaneously when the source electrode 215 and the drain electrode 217 are formed.

[0105] After the planarization layer 140 is formed, at least a portion of the planarization layer 140 corresponding to the second non-display area PA2 can be removed via patterning. Simultaneously, during patterning, at least a portion of the planarization layer 140 between the pad area PADA and the display area DA in the first non-display area PA1 is not removed. Therefore, the first voltage line 410 and the second voltage line 420 covered by the planarization layer 140 between the pad area PADA and the display area DA are not exposed due to the patterning of the planarization layer 140, and thus damage to the first voltage line 410 and the second voltage line 420 can be prevented when the planarization layer 140 is patterned.

[0106] After the pixel defining layer 150 is formed, at least a portion of the pixel defining layer 150 corresponding to the second non-display area PA2 can be removed via patterning. Simultaneously, a portion of the pixel defining layer 150 formed on the planarization layer 140 between the pad area PADA and the display area DA can be patterned to form the first dam 610 and the dike 630. Since the first voltage line 410 and the second voltage line 420 are covered by the planarization layer 140 between the pad area PADA and the display area DA, the first voltage line 410 and the second voltage line 420 are not exposed when the pixel defining layer 150 is patterned. However, embodiments of the invention are not limited thereto, and in another embodiment, a portion of the pixel defining layer 150 located on the planarization layer 140 between the pad area PADA and the display area DA can be removed together with the planarization layer 140.

[0107] like Figure 8 As shown, in the second non-display area PA2, openings OP1 and OP2 can be defined in the portions of the first inorganic insulating layer 120 and the second inorganic insulating layer 130 that define the first groove G1 and the second groove G2.

[0108] Next, refer to Figure 9 A cover layer CR is formed on the entire substrate 100, and then a photosensitive layer PR, including exposed areas EP1, EP2 and EP3 of the cover layer CR, is used to remove the exposed portions of the cover layer CR that correspond to the first groove G1, the second groove G2 and the adhesion area AA, respectively.

[0109] Then, as Figure 10 As shown, the photosensitive layer PR is removed, and then dry etching is performed using the capping layer CR as a mask. Due to the dry etching, the first trench G1 and the second trench G2 can be formed in the second non-display area PA2, and the planarization layer 140 can be removed in the adhesion area AA. Each of the first trench G1 and the second trench G2 can have a closed curve shape.

[0110] Each of the first groove G1 and the second groove G2 extends from the surface of the substrate 100 in the thickness direction of the substrate 100. In this state, a pair of first tips T1 extending toward each other in the upper opening of the first groove G1 and between the first groove G1, and a pair of second tips T2 extending toward each other in the upper opening of the second groove G2 and between the second groove G2, can be formed in the second barrier layer 104.

[0111] By removing the planarization layer 140 between the pad area PADA and the display area DA, a first dam 610 and a dam 630 are formed around the display area DA. Simultaneously, since the planarization layer 140 is removed from the adhesion area AA between the first dam 610 and the dam 630, the side surfaces of the first connection unit 414 and the second connection unit 424 do not have an undercut structure, unlike the case where the first connection unit 414 and the second connection unit 424 are exposed to the developer due to the removal of the planarization layer 140.

[0112] Next, as Figure 11 As shown, after the cover layer CR is removed, the intermediate layer 320 and the counter electrode 330 are formed on the pixel electrode 310, and the encapsulation layer 500 is formed on the counter electrode 330. Then, as... Figure 12 As shown, the through hole H is defined.

[0113] The capping layer (CR) can be removed via wet etching. Simultaneously, by improving the selectivity of the capping layer CR relative to the etchant, the etchant's effect on the capping layer CR during removal can be prevented or minimized. Figure 1 The effect of the display device 10 components. For example, the cover layer CR may include at least one of indium tin oxide, indium zinc oxide, indium tin zinc oxide, zinc gallium oxide, and indium gallium zinc oxide.

[0114] Some of the multiple layers constituting the intermediate layer 320 (e.g., functional layers) can be formed to extend over the entire display area DA. Meanwhile, due to the undercut structure formed by the first tip T1 and the second tip T2 respectively, the intermediate layer 320 may not be formed on the corresponding inner wall surfaces at the upper ends of the openings of the first slot G1 and the second slot G2, and can therefore be formed discontinuously by being interrupted.

[0115] When the first trench G1 is formed to surround the second trench G2, the first trench G1 can be filled with an organic encapsulation layer 520, but the second trench G2 is not filled with an organic encapsulation layer 520. The first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 can be in direct contact with each other in the second trench G2.

[0116] In the adhesion region AA, the first inorganic encapsulation layer 510 can directly contact the second inorganic encapsulation layer 530 and the exposed portions of the first voltage line 410 and the second voltage line 420. More specifically, in the adhesion region AA, the first inorganic encapsulation layer 510 covers the first connection unit 414 and the second connection unit 424. Simultaneously, no undercut structures due to excessive etching are generated on the side surfaces of the first connection unit 414 and the second connection unit 424, and therefore no gaps are formed between the first inorganic encapsulation layer 510 and the first connection unit 414 and the second connection unit 424. Therefore, damage such as cracks can be prevented in the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530.

[0117] The via H can be defined within the region defined by the first trench G1 or the second trench G2. For example, when the first trench G1 is defined around the second trench G2, the via H can be located within the region formed by the second trench G2. The via H can be defined, for example, by irradiating the substrate 100 with a laser to penetrate the substrate 100 from the encapsulation layer 500.

[0118] According to embodiments of this disclosure, by preventing undercut structures from forming on the side surface of the power line exposed between the pad area and the display area, the encapsulation layer is not damaged, and thus external moisture or oxygen can be effectively prevented from penetrating into the display device.

[0119] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. A method of manufacturing a display device, the display device comprising a display area, a first non-display area, and a second non-display area, the first non-display area being located around the display area and including pad areas on one side of the first non-display area, the second non-display area being at least partially surrounded by the display area, the method comprising: Thin-film transistors are formed on the substrate at positions corresponding to the display area, and a planarization layer is formed covering the thin-film transistors; A pixel electrode electrically connected to the thin-film transistor and a pixel defining layer exposing at least a central portion of the pixel electrode are formed on the planarization layer; as well as At least one groove extending from the surface of the substrate in the thickness direction is defined at a position corresponding to the second non-display area, the at least one groove having a closed curve shape. Specifically, when forming the thin-film transistor, a voltage line for applying voltage to the display device is formed together with the thin-film transistor at a position corresponding to the first non-display area, and When the at least one groove is formed, a portion of the planarization layer disposed between the pad area and the display area is simultaneously removed, thereby exposing a portion of the voltage line located between the pad area and the display area.

2. The method according to claim 1, wherein, The substrate has a multilayer structure in which a first base layer, a first barrier layer, a second base layer, and a second barrier layer are sequentially stacked, and The at least one groove is defined as extending from the second barrier layer to at least a portion of the second base layer in the thickness direction of the substrate.

3. The method according to claim 1, wherein, Prior to the formation of the at least one groove, a cover layer is formed on the entire substrate. The cover layer is patterned to define openings in the cover layer at the locations where the at least one slot is to be defined and at the locations between the pad area and the display area, and The formation of the at least one groove and the removal of a portion of the planarization layer disposed between the pad area and the display area are performed via the opening.

4. The method according to claim 3, wherein, By performing dry etching using the overlay layer as a mask, the at least one trench is formed, and the portion of the planarization layer disposed between the pad area and the display area is removed.

5. The method according to claim 3, wherein, The covering layer includes at least one of indium tin oxide, indium zinc oxide, tin zinc indium oxide, gallium zinc oxide, and gallium zinc indium oxide.

6. The method according to claim 1, wherein, When the portion of the planarization layer disposed between the pad area and the display area is removed, a first dam and a levee are formed around the display area, and the voltage lines are exposed in the adhesion area between the first dam and the levee.

7. The method of claim 6, further comprising: An intermediate layer including an emission layer is formed on the pixel electrode, and a counter electrode is formed on the intermediate layer; A first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are sequentially formed on the counter electrode; as well as A through hole is defined within the area defined by the at least one groove.

8. The method according to claim 7, wherein, The first inorganic encapsulation layer directly contacts the voltage line and the second inorganic encapsulation layer in the adhesion region.

9. The method according to claim 7, wherein, The at least one groove includes a first groove surrounding the through hole and a second groove located between the first groove and the through hole and surrounding the through hole. The organic encapsulation layer fills the first groove, and The first inorganic encapsulation layer and the second inorganic encapsulation layer are in direct contact with each other within the second groove.

10. The method according to claim 7, wherein, The intermediate layer is broken by the at least one groove and is formed discontinuously.

11. The method according to claim 7, wherein, The thin-film transistor includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. A first inorganic insulating layer is formed between the semiconductor layer and the gate electrode to cover the entire substrate, and a second inorganic insulating layer is formed between the gate electrode and the source electrode and the drain electrode to cover the entire substrate. The first inorganic encapsulation layer directly contacts the second inorganic insulating layer in the adhesion region.

12. The method according to claim 6, wherein, The pixel defining layer is formed on the planarization layer and disposed between the pad area and the display area, and When the at least one groove is formed, the pixel defining layer and the planarization layer are removed from the adhesion area.

13. The method according to claim 1, wherein, The voltage lines include a first voltage line and a second voltage line that apply different voltages to each other. The first voltage line includes a first main voltage line formed between the display area and the pad area to correspond to a first edge of the display area, and a first connection unit extending from the first main voltage line to the pad area. The second voltage line includes a second main voltage line surrounding the remaining edges of the display area, excluding the first edge, and a second connection unit extending from the second main voltage line to the pad area; and The corresponding portions of the first connection unit and the second connection unit between the pad area and the display area are exposed.

14. The method according to claim 1, wherein, The voltage line is a three-layer structure comprising a first metal layer, a second metal layer, and a third metal layer, wherein the etching rate of the second metal layer is greater than the etching rate of each of the first metal layer and the third metal layer.

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