Array substrate and display device

Abstract

The present application discloses an array substrate and a display device, belonging to the field of display technology. The array substrate includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines located on the base substrate. The data line has a plurality of first extensions and a plurality of second extensions arranged alternately. When the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel is displayed, in each column of sub-pixels, the voltage polarities between the two sub-pixels belonging to two adjacent first pixel areas are opposite, and the voltage polarities of the same sub-pixels in the same frame image can be effectively averaged on a spatial scale, thereby reducing the probability of shaking head lines, thereby effectively improving the display effect of the liquid crystal display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Since the full-screen display device has a high screen-to-body ratio (generally reaching 80% or even above 90%), it can provide a larger display screen without increasing the overall size of the display device.

[0003] Currently, if a full-screen display device is prepared using a liquid crystal display panel, a dual gate technology needs to be used to prepare an array substrate in the liquid crystal display panel.

[0004] However, after the array substrate prepared by the dual-gate line technology is assembled into a liquid crystal display panel, the liquid crystal display panel is very likely to have a shaking head wrinkle phenomenon during display, resulting in a poor display effect of the liquid crystal display panel. Summary of the invention

[0005] The embodiments of the present application provide an array substrate and a display device, which can solve the technical problem that after the existing array substrate prepared by the dual-gate line technology is assembled into a liquid crystal display panel, the display effect of the liquid crystal display panel is poor. The technical solution is as follows:

[0006] In one aspect, an array substrate is provided, comprising:

[0007] substrate substrate;

[0008] A plurality of gate lines and a plurality of data lines located on the substrate, wherein the data lines and the gate lines define a plurality of first pixel regions on the substrate, wherein the plurality of first pixel regions are arranged in a plurality of rows, and two gate lines are arranged between any two adjacent rows of first pixel regions, and the data lines have a plurality of first extensions and a plurality of second extensions arranged alternately, wherein the extension direction of the first extensions intersects with the extension direction of the second extensions, and any two adjacent first extensions in the same data line and the second extension between the two adjacent first extensions constitute a pixel accommodating region, and the pixel accommodating region includes at least one of the first pixel regions;

[0009] Two sub-pixels located in the first pixel region, the two sub-pixels are arranged along the extension direction of the gate line, and the two sub-pixels are respectively connected to the two data lines adjacent to the first pixel region, and each of the sub-pixels is connected to one of the two gate lines adjacent to the sub-pixel;

[0010] Also, there are multiple touch signal lines located on the substrate, the multiple first pixel areas are arranged into multiple columns, each column of the first pixel areas includes two columns of sub-pixels, and the touch signal line is located between two columns of sub-pixels in the same column of the first pixel areas.

[0011] Optionally, the multiple first extension portions and the multiple second extension portions in the same data line constitute a plurality of pixel accommodating areas, each of the pixel accommodating areas has an opening, and the directions of the openings of any two adjacent pixel accommodating areas are opposite.

[0012] Optionally, the pixel accommodating area includes one first pixel area.

[0013] Optionally, an extending direction of the first extending portion is the same as an extending direction of the gate line, an extending direction of the second extending portion is perpendicular to an extending direction of the gate line, and an extending direction of the touch signal line is perpendicular to an extending direction of the gate line.

[0014] Optionally, the data lines and the gate lines further define a plurality of second pixel regions on the base substrate, the plurality of second pixel regions are arranged in two columns, the plurality of columns of the first pixel regions are located between the two columns of the second pixel regions, and the array substrate further includes a sub-pixel located in the second pixel region.

[0015] Optionally, the touch signal line includes: a first touch line segment and a second touch line segment arranged at intervals, the first touch line segment and the second touch line segment are arranged in different layers, adjacent first touch line segments are connected to the second touch line segments, the first touch line segment and the data line are arranged in the same layer, and the orthographic projection of the second touch line segment on the base substrate intersects with the orthographic projection of the data line on the base substrate.

[0016] Optionally, the array substrate further includes: a first insulating layer located between the first touch line segment and the second touch line segment, the first insulating layer having a plurality of first via holes, and adjacent first touch line segments are connected with the second touch line segments through at least one of the first via holes.

[0017] Optionally, the plurality of touch signal lines are arranged in the same layer, and the touch signal lines and the data lines are arranged in different layers.

[0018] Optionally, the array substrate further includes: a plurality of touch electrodes, and the plurality of touch electrodes are connected to the plurality of touch signal lines in a one-to-one correspondence.

[0019] Optionally, the touch electrode and the multiple touch signal lines are arranged in different layers, and the array substrate also includes a second insulating layer located between the touch electrode and the multiple touch signal lines, the second insulating layer has a plurality of second vias, and each of the touch electrodes and the corresponding touch signal lines are connected through at least one of the second vias.

[0020] Optionally, the touch electrodes are reused as common electrodes in the array substrate, and the touch signal lines are reused as common electrode lines in the array substrate.

[0021] Optionally, the touch electrode is a block-shaped electrode, each of the sub-pixels includes a pixel electrode, and the orthographic projection of each of the touch electrodes on the base substrate covers the orthographic projections of multiple pixel electrodes on the base substrate.

[0022] Optionally, a plurality of columns of the first pixel regions correspond one-to-one to the plurality of touch signal lines, and each of the touch signal lines is located between two columns of sub-pixels in a column of the first pixel regions corresponding to the touch signal line.

[0023] Optionally, the array substrate comprises: a first conductive layer, a gate insulating layer, an active layer, a second conductive layer, a pixel electrode layer, a first insulating layer, a third conductive layer, a second insulating layer and a fourth conductive layer which are sequentially stacked away from the base substrate;

[0024] The first conductive layer includes: the gate line and the gate electrode; the second conductive layer includes: the data line, the first touch line segment, the source electrode and the drain electrode; the third conductive layer includes: the second touch line segment; and the fourth conductive layer includes: the touch electrode.

[0025] Optionally, the array substrate comprises: a first conductive layer, a gate insulating layer, an active layer, a second conductive layer, a pixel electrode layer, a first insulating layer, a third conductive layer, a second insulating layer and a fourth conductive layer which are sequentially stacked away from the base substrate;

[0026] The first conductive layer includes: the gate line and the gate electrode; the second conductive layer includes: the data line, the source electrode and the drain electrode; the third conductive layer includes: the touch signal line; and the fourth conductive layer includes: the touch electrode.

[0027] On the other hand, a display device is provided, comprising: any one of the above-mentioned array substrates, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.

[0028] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0029] When the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel is displayed, even for the same seed pixel in each row of the first pixel area, the probability that the voltage polarity between any two adjacent sub-pixels is the same is still nearly 50%, but in each column of sub-pixels, the voltage polarity between two sub-pixels belonging to two adjacent first pixel areas is opposite, which can effectively average the voltage polarity of the same seed pixel in the same frame image on a spatial scale, thereby reducing the probability of shaking head lines, thereby effectively improving the display effect of the liquid crystal display panel. In addition, through multiple touch signal lines, the liquid crystal display panel can have a touch function without the need to separately assemble a touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with a touch function. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 It is a structural schematic diagram of an array substrate prepared by using a double-grid line technology provided by the related technology;

[0032] Figure 2 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0033] Figure 3 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0034] Figure 4 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0035] Figure 5 is a structural schematic diagram of an array substrate provided by another embodiment of the present application;

[0036] Figure 6 This is a schematic structural diagram of another array substrate provided in another embodiment of the application;

[0037] Figure 7 yes Figure 6 A cross-sectional view at A-A';

[0038] Figure 8 yes Figure 5 A cross-sectional view at A-A';

[0039] Fig. 9It is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0041] Please refer to Figure 1 , Figure 1 It is a structural schematic diagram of an array substrate prepared by dual-gate line technology provided by the related art. The array substrate 00 may include: a plurality of data lines 01, a plurality of gate lines 02 and a plurality of sub-pixels 03, wherein the gate lines 02 extend along a first direction x, and the data lines 01 extend along a second direction y. The data lines 01 and the gate lines 02 can define a plurality of pixel regions 00a, and two sub-pixels 03 are arranged in each pixel region 00a along the first direction x. The plurality of pixel regions 00a can be arranged in a plurality of rows along the first direction x, and can also be arranged in a plurality of columns along the second direction y, and each column of pixel regions includes two columns of sub-pixels. Two gate lines 02 are arranged between any two adjacent rows of pixel regions 00a, and one data line 02 is arranged between any two adjacent columns of pixel regions 00a.

[0042] Among them, for two sub-pixels 03 in the same pixel area 00a, the two sub-pixels 03 are respectively connected to two gate lines 02 adjacent to the pixel area 00a, and are also respectively connected to two data lines 01 adjacent to the pixel area 00a. The two sub-pixels 03 are two of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B. The sub-pixels in the same row are periodically arranged in the order of the first sub-pixel R, the second sub-pixel G and the third sub-pixel B, and the sub-pixels in the same column are all the first sub-pixel R, the second sub-pixel G or the third sub-pixel B. For example, assuming that the array substrate 00 is assembled into a liquid crystal display panel, the first sub-pixel R can emit red light, the second sub-pixel G can emit green light, and the third sub-pixel B can emit blue light.

[0043] The reason why the liquid crystal display panel prepared by using the above array substrate 00 is prone to shaking head wrinkles is that: when the liquid crystal display panel displays the picture, it is necessary to ensure that the voltage polarities of any two adjacent data lines in the array substrate 00 are opposite, so the voltage polarities of the two sub-pixels 03 in the same pixel area 00a are opposite, and the voltage polarities of the sub-pixels 03 in the same column are the same. In this way, in space, in each row of pixel areas, the voltage polarities of all first sub-pixels R are arranged in a cyclic arrangement of "+--+", the voltage polarities of all second sub-pixels G are arranged in a cyclic arrangement of "++--", and the voltage polarities of all third sub-pixels B are arranged in a cyclic arrangement of "-++-". For the same sub-pixel in each row of pixel areas, the probability that the voltage polarities between any two adjacent sub-pixels are the same is nearly 50%, and for each column of sub-pixels, the voltage polarity of each sub-pixel is the same, and it is impossible to average the voltage polarities of the same sub-pixel in the same frame of image on a spatial scale, and the light and dark stripes that appear visually also present the undesirable phenomenon of shaking head wrinkles.

[0044] Please refer to Figure 2 , Figure 2 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present application. The array substrate 100 may include: a base substrate 10 , a plurality of gate lines 20 , a plurality of data lines 30 and a plurality of sub-pixels 40 located on the base substrate 10 .

[0045] The gate lines 20 and the data lines 30 can define a plurality of first pixel regions 10a on the base substrate 10. The plurality of first pixel regions 10a can be arranged in a plurality of rows or in a plurality of columns, wherein two gate lines 20 are arranged between any two adjacent rows of first pixel regions.

[0046] The data line 30 has a plurality of first extensions 301 and a plurality of second extensions 302 arranged alternately. The extension direction of the first extension 301 intersects with the extension direction of the second extension 302. Any two adjacent first extensions 301 in the same data line 30 and the second extension 302 between the two adjacent first extensions 301 constitute a pixel accommodating area 303, and the pixel accommodating area 303 includes at least one first pixel region 10a. For example, Figure 2 As shown, Figure 2 The pixel accommodating area 302 includes a first pixel area 10a as an example for schematic description. In other optional implementations, such as Figure 3 As shown, Figure 3 The pixel accommodating area 303 including four first pixel areas 10 a is taken as an example for schematic description.

[0047] Two sub-pixels 40 are arranged in each first pixel region 10a along the extension direction of the gate line 20, and the two sub-pixels 40 are respectively connected to two data lines 30 adjacent to the first pixel region 10a, and each sub-pixel 40 is connected to one gate line 20 of the two gate lines 20 adjacent to the sub-pixel 40.

[0048] In the embodiment of the present application, for two sub-pixels 40 in the same first pixel region 10a, the two sub-pixels 40 are two types of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B. The sub-pixels in the same row are periodically arranged in the order of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B, and the sub-pixels in the same column are the first sub-pixel R, the second sub-pixel G, or the third sub-pixel B. For example, assuming that the array substrate 100 is assembled into a liquid crystal display panel, the first sub-pixel R can emit red light, the second sub-pixel G can emit green light, and the third sub-pixel B can emit blue light.

[0049] In the present application, it is assumed that the array substrate 100 is assembled into a liquid crystal display panel. When the liquid crystal display panel is displayed, any two adjacent data lines 30 in the array substrate 100 need to be loaded with voltages of opposite polarities. In this way, even for the same seed pixel in each row of the first pixel area, the probability that the voltage polarity between any two adjacent sub-pixels is the same is still nearly 50%, but in each column of sub-pixels, the voltage polarity between two sub-pixels belonging to two adjacent first pixel areas 10a is opposite. For example, if the pixel accommodating area 303 includes a first pixel area 10a, the voltage polarity between any two adjacent sub-pixels 40 in each column of sub-pixels is opposite. The voltage polarity of the same seed pixel in the same frame image can be effectively averaged on a spatial scale, thereby reducing the probability of the occurrence of shaking head lines, thereby effectively improving the display effect of the liquid crystal display panel.

[0050] like Figure 2 As shown, the array substrate 100 may further include: a plurality of touch signal lines 50 located on the base substrate 10. Each column of the plurality of first pixel regions includes two columns of sub-pixels, and the touch signal line 50 is located between the two columns of sub-pixels in the same column of the first pixel region. In the present application, the liquid crystal display panel prepared by using the array substrate 100 has a touch function through the plurality of touch signal lines 50 in the array substrate 100. In this way, the liquid crystal display panel can have a touch function without separately assembling a touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with a touch function.

[0051] In summary, the array substrate provided by the embodiment of the present application includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines located on the base substrate. When the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel is displayed, even for the same seed pixel in each row of the first pixel area, the probability that the voltage polarity between any two adjacent sub-pixels is the same is still nearly 50%, but in each column of sub-pixels, the voltage polarity between the two sub-pixels belonging to two adjacent first pixel areas is opposite, which can effectively average the voltage polarity of the same seed pixel in the same frame image on a spatial scale, thereby reducing the probability of the occurrence of shaking head lines, and thus effectively improving the display effect of the liquid crystal display panel. In addition, through the plurality of touch signal lines, the liquid crystal display panel can have a touch function without the need to separately assemble a touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with a touch function.

[0052] In the embodiments of the present application, Figure 4 As shown, Figure 4 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present application. The data line 30 and the gate line 20 can also define a plurality of second pixel areas 10b on the substrate 10. The plurality of second pixel areas 10b are arranged in two columns, and the plurality of columns of first pixel areas are located between the two columns of second pixel areas. A sub-pixel 40 is arranged in each second pixel area 10b, and the sub-pixel 40 is connected to a data line 30, and the sub-pixel 40 is connected to a gate line 20 of two adjacent gate lines 20.

[0053] The plurality of data lines 30 in the array substrate 100 can be divided into a plurality of first data lines 30a and two data lines 30b, wherein the plurality of first data lines 30a are located between the two second data lines 30b. For the plurality of second extensions 302 in the first data line 30a, each second extension 302 can connect two adjacent sub-pixels 40, and the two adjacent sub-pixels 40 are located in two different first pixel regions 10a. For the plurality of second extensions 302 in the second data line 30b, a portion of the second extensions 302 are connected to two adjacent sub-pixels 40, and one of the two adjacent sub-pixels 40 is located in the first pixel region 10a, and the other is located in the second pixel region 10b; the other portion of the second extensions 302 is not connected to the sub-pixel 40, and the second extensions 302 connected to the sub-pixel and the second extensions 302 located in the sub-pixel connection are arranged alternately. In the present application, the length of the first extension 301 in the first data line 30a needs to be greater than the length of the first extension 301 in the second data line 30b. For example, the length of the first extension portion 301 in the first data line 30a is greater than the total width of two adjacent sub-pixels 40; and the length of the first extension portion 301 in the second data line 30b is greater than the width of one sub-pixel 40, but less than the total width of two adjacent sub-pixels 40. It should be noted that the length direction of the first extension portion 301 is parallel to the width direction of the sub-pixel 40.

[0054] In the embodiments of the present application, Figure 5 As shown, Figure 5 : is a structural schematic diagram of an array substrate provided by another embodiment of the present application. A plurality of first extensions 301 and a plurality of second extensions 302 in the same data line 30 can form a plurality of pixel accommodating areas 303. Each pixel accommodating area 303 has an opening 303a, and the directions of the openings 303a of any two adjacent pixel accommodating areas 303 are opposite. For example, the nth data line, the n+1th data line and the bottom n+2nd data line are three adjacent data lines 30. For the pixel accommodating area A1 and the pixel accommodating area A2 formed by the n+1th data line, the opening 303a of the pixel accommodating area A1 faces the nth data line, and the opening 303a of the pixel accommodating area A2 faces the n+2th data line.

[0055] Optionally, the extension direction of the first extension portion 301 in the data line 30 is the same as the extension direction of the gate line 20, and the extension direction of the second extension portion 302 in the data line 30 is perpendicular to the extension direction of the gate line 20. Since the extension direction of the gate line 20 is generally parallel to the row arrangement direction of the plurality of first pixel regions 10a (i.e., the first direction x), and perpendicular to the column arrangement direction of the plurality of first pixel regions 10a (i.e., the second direction y), the first extension portion 301 can extend along the first direction x, and the second extension portion 302 can extend along the second direction y. In the embodiment of the present application, the first extension portion 301 in the data line 30 is located between two gate lines 20 between two adjacent rows of first pixel regions, and the orthographic projection of the second extension portion 302 on the substrate 10 is staggered with the orthographic projection of the gate line 20 on the substrate, so that the parasitic capacitance generated between the data line 30 and the gate line 20 can be effectively reduced.

[0056] Optionally, each sub-pixel 40 may include: a thin film transistor 401 and a pixel electrode 402. The pixel electrode 402 may be an electrode made of a transparent conductive material. The thin film transistor 401 may include: a first electrode, a second electrode and a gate electrode. The first electrode may be connected to the data line 30, the gate electrode may be connected to the gate line 20, and the second electrode may be connected to the pixel electrode 402. The first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode.

[0057] Assume that each pixel accommodating area 303 accommodates a first pixel area 10a, and after the array substrate 100 is assembled to the liquid crystal display panel, if the liquid crystal display panel needs to display, the nth data line periodically drives the two columns of sub-pixels connected to it in the order of the first sub-pixel R, the third sub-pixel B, the first sub-pixel R, and the second sub-pixel G; the n+1th data line periodically drives the two columns of sub-pixels connected to it in the order of the third sub-pixel B, the second sub-pixel G, the first sub-pixel R, and the third sub-pixel B; the n+2th data line periodically drives the two columns of sub-pixels connected to it in the order of the first sub-pixel R, the second sub-pixel G, the third sub-pixel B, and the second sub-pixel G.

[0058] In the embodiment of the present application, there are various structures of the touch signal line 50 in the array substrate 100 . The embodiment of the present application uses the following two possible implementation methods as examples for schematic description.

[0059] In the first possible implementation, Figure 6 As stated, Figure 6This is a schematic diagram of the structure of another array substrate provided by another embodiment of the application. The touch signal line 50 in the array substrate 100 includes: a first touch line segment 501 and a second touch line segment 502 arranged at intervals, the extension direction of the first touch line segment 501 is the same as the extension direction of the second touch line segment 502, and the adjacent first touch line segments 501 and second touch line segments 502 are connected. The first touch line segment 501 is arranged in the same layer as the data line 30, and the orthographic projection of the first touch line segment 501 on the base substrate 10 is staggered from the orthographic projection of the data line 30 on the base substrate 10. Since the orthographic projection of the second touch line segment 502 on the base substrate 10 intersects with the orthographic projection of the data line 30 (the first extension portion 301 in the data line 30) on the base substrate 10, in order to avoid a short circuit between the touch signal line 50 and the data line 30, it is necessary to ensure that the second touch line 502 and the data line 50 are arranged in different layers, that is, the second touch line segment 502 and the first touch line segment 501 are arranged in different layers.

[0060] For examples, please refer to Figure 7 , Figure 7 yes Figure 6 The array substrate 100 may further include: a first insulating layer 60 located between the first touch line segment 501 and the second touch line segment 502. The first insulating layer 60 has a plurality of first via holes 601, and adjacent first touch line segments 501 and second touch line segments 502 are connected via at least one first via hole 601.

[0061] Optionally, the material of the second touch line segment 502 may include a transparent conductive material. In this way, the aperture ratio of each sub-pixel 30 may be increased.

[0062] In a second possible implementation, a plurality of touch signal lines 50 in the array substrate 100 are arranged in the same layer, and the touch signal lines 50 and the data lines 30 are arranged in different layers. Figure 8 As stated, Figure 8 yes Figure 5 Cross-sectional view at A-A'. The array substrate 100 may further include: a first insulating layer 60 located between the touch signal line 50 and the data line 30. Optionally, the material of the touch signal line 50 may include a metal material. Since the touch signal line 50 and the data line 30 are arranged in different layers in the second possible implementation, there is no need to set the first via hole on the first insulating layer 60, so that the aperture ratio of each sub-pixel 30 can be improved. In addition, since the material of the touch signal line 50 in the second possible implementation is a metal material, it has higher conductivity and lower resistivity than transparent conductive materials, which effectively increases the signal amount of the touch signal in the touch signal line 50, thereby improving the touch performance of the array substrate 100.

[0063] Optional, such as Figure 7 and Figure 8 As shown, the array substrate 100 may further include: a plurality of touch electrodes 70. The plurality of touch electrodes 70 are connected one-to-one with the plurality of touch signal lines 50. The touch electrodes 70 may be electrodes made of transparent conductive materials. It should be noted that the touch control method in the array substrate 100 in the present application belongs to self-capacitive touch control, and the relevant touch control principle can refer to the relevant technology, which will not be described in detail here.

[0064] For example, the touch electrode 70 and the multiple touch signal lines 50 are arranged in different layers, and the array substrate 100 can also include a second insulating layer 80 located between the touch electrode 70 and the multiple touch signal lines 50, the second insulating layer 80 has a plurality of second vias 801, and each touch electrode 70 and the corresponding touch signal line 50 are connected through a second via 801.

[0065] Optionally, each touch electrode 70 is a block-shaped electrode, and the orthographic projection of each touch electrode 70 on the base substrate 10 covers the orthographic projections of multiple pixel electrodes 402 on the base substrate 10. For example, assuming that multiple sub-pixels in the array substrate 10 can be evenly divided into k sub-pixel groups, each sub-pixel group includes j×j sub-pixels, then the orthographic projection of each touch electrode 70 on the base substrate covers j×j pixel electrodes 402.

[0066] In the embodiment of the present application, the array substrate 100 may further include: a common electrode and a common electrode line. In order to reduce the complexity of the structure of the array substrate 100, the touch electrode 70 in the array substrate 100 may be reused for the common electrode, and the touch signal line 50 in the array substrate 100 may be reused for the common electrode line. That is, the touch electrode 70 in the array substrate 100 is the same electrode as the common electrode, and the touch signal line 50 is the same signal line as the common electrode line.

[0067] Thus, in a liquid crystal display panel prepared using the array substrate 100, if the liquid crystal display panel is required to display, a common electrode signal needs to be loaded on the touch signal line 50 so that the touch electrode 70 can form a pressure difference with the pixel electrode 402 to polarize the liquid crystal; if the liquid crystal display panel is required to perform touch control, a touch signal needs to be loaded on the touch signal line 50 so that the touch electrode 70 can detect the touch position.

[0068] Optional, such as Figure 5 or Figure 6 As mentioned above, the extending direction of the touch signal line 50 is perpendicular to the extending direction of the gate line 20 , that is, the touch signal line 50 extends along the second direction y.

[0069] Optional, such as Figure 5 or Figure 6As described above, the multiple columns of first pixel regions correspond one-to-one to the multiple touch signal lines 50 , and each touch signal line 50 is located between two columns of sub-pixels in a column of first pixel regions corresponding to the touch signal line 50 .

[0070] For the array substrate 100 in the first possible implementation, that is, Figure 6 The array substrate 100 shown in the figure comprises: a first conductive layer, a gate insulating layer 90, an active layer (not shown in the figure), a second conductive layer, a pixel electrode layer, a first insulating layer 60, a third conductive layer, a second insulating layer 80 and a fourth conductive layer which are sequentially stacked in a direction away from the base substrate 10. The first conductive layer comprises: a gate line 20 and a gate in a thin film transistor 402; the second conductive layer comprises: a data line 30, a first touch line segment 501, and a source and a drain in a thin film transistor 402; the pixel electrode layer comprises: a plurality of pixel electrodes 401; the third conductive layer comprises: a second touch line segment 502; and the fourth conductive layer comprises: a touch electrode 70.

[0071] For the array substrate 100 in the second possible implementation manner, that is, for Figure 5 The array substrate 100 shown in the figure includes: a first conductive layer, a gate insulating layer 90, an active layer (not shown in the figure), a second conductive layer, a pixel electrode layer, a first insulating layer 60, a third conductive layer, a second insulating layer 80 and a fourth conductive layer which are sequentially stacked in a direction away from the base substrate 10. The first conductive layer includes: a gate line 20 and a gate in a thin film transistor 402; the second conductive layer includes: a data line 30 and a source and a drain in a thin film transistor 402; the third conductive layer includes: a touch signal line 50; and the fourth conductive layer includes: a touch electrode 70.

[0072] In summary, the array substrate provided by the embodiment of the present application includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines located on the base substrate. When the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel is displayed, even for the same seed pixel in each row of the first pixel area, the probability that the voltage polarity between any two adjacent sub-pixels is the same is still nearly 50%, but in each column of sub-pixels, the voltage polarity between the two sub-pixels belonging to two adjacent first pixel areas is opposite, which can effectively average the voltage polarity of the same seed pixel in the same frame image on a spatial scale, thereby reducing the probability of the occurrence of shaking head lines, and thus effectively improving the display effect of the liquid crystal display panel. In addition, through the plurality of touch signal lines, the liquid crystal display panel can have a touch function without the need to separately assemble a touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with a touch function.

[0073] The present application also provides a method for manufacturing an array substrate. The method for manufacturing an array substrate is used to manufacture Figure 2 , Figure 3 , Figure 4 , Figure 5 or Figure 6 The array substrate 100 is shown. The manufacturing method of the array substrate 100 may include:

[0074] A plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines are formed on the base substrate.

[0075] Among them, the data lines and the gate lines define a plurality of first pixel areas on the substrate, the plurality of first pixel areas are arranged into a plurality of rows, and two gate lines are arranged between any two adjacent rows of first pixel areas, the data line has a plurality of first extension parts and a plurality of second extension parts arranged alternately, the extension direction of the first extension part intersects with the extension direction of the second extension part, and any two adjacent first extension parts in the same data line and the second extension part between the two adjacent first extension parts constitute a pixel accommodating area, the pixel accommodating area includes at least one first pixel area, and any two adjacent data lines are used to load voltages with opposite polarities; two sub-pixels are arranged in each first pixel area along the extension direction of the gate line, and the two sub-pixels are respectively connected to the two data lines adjacent to the first pixel area, and each sub-pixel is connected to one of the two gate lines adjacent to the sub-pixel; the plurality of first pixel areas are also arranged into a plurality of columns, each column of the first pixel area includes two columns of sub-pixels, and the touch signal line is located between the two columns of sub-pixels in the same column of the first pixel area.

[0076] In summary, the manufacturing method of the array substrate provided in the embodiment of the present application forms a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines on the base substrate. When the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel is displayed, even for the same seed pixel in each row of the first pixel area, the probability that the voltage polarity between any two adjacent sub-pixels is the same is still nearly 50%, but in each column of sub-pixels, the voltage polarity between the two sub-pixels belonging to two adjacent first pixel areas is opposite, which can effectively average the voltage polarity of the same seed pixel in the same frame image on a spatial scale, thereby reducing the probability of the occurrence of shaking head lines, and thus effectively improving the display effect of the liquid crystal display panel. In addition, through the plurality of touch signal lines, the liquid crystal display panel can have a touch function without the need to separately assemble a touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with a touch function.

[0077] Optional, please refer to Fig. 9 , Fig. 9: is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application. The method for manufacturing an array substrate is used to manufacture Figure 5 or Figure 6 The array substrate shown. The array substrate manufacturing method may include:

[0078] Step S1, forming a first conductive layer, a gate insulating layer and an active layer on a substrate.

[0079] Optionally, the material of the first conductive layer may include: a metal material such as metal molybdenum (abbreviated as Mo), metal copper (abbreviated as Cu), metal aluminum (abbreviated as Al) or an alloy. The material of the gate insulating layer may include: silicon dioxide, silicon nitride or a mixed material of silicon dioxide and silicon nitride. The material of the active layer may include: polysilicon.

[0080] For example, first, a first conductive material layer can be formed on the substrate by any of a plurality of methods such as deposition, coating, sputtering, etc., and the first conductive material layer is subjected to a patterning process to form a first conductive layer. The first conductive layer can include: a gate and a gate line.

[0081] Then, a gate insulating layer and an active material layer are sequentially formed on the base substrate formed with the first conductive layer by any one of a plurality of methods such as deposition, coating, sputtering, etc., and a patterning process is performed on the active material layer to form an active layer.

[0082] Step S2: forming a second conductive layer and a pixel electrode layer on the active layer.

[0083] Optionally, the material of the second conductive layer may include: metal materials such as metal Mo, metal copper Cu, metal aluminum Al or alloys, etc. The material of the pixel electrode layer may include: a transparent conductive material, for example, it may be ITO.

[0084] For example, first, a second electrode material layer can be formed on the active layer by any of a plurality of methods such as deposition, coating, sputtering, etc., and the second conductive material layer is subjected to a patterning process to form a second conductive layer. The second conductive layer can include: a source electrode, a drain electrode, and a data line.

[0085] Then, a pixel electrode material layer can be formed on the second conductive layer by any of a plurality of methods such as deposition, coating, sputtering, etc., and the pixel electrode material layer is subjected to a patterning process to form a pixel electrode layer. The pixel electrode layer can include: a pixel electrode.

[0086] Step S3: forming a first insulating layer and a third conductive layer on the pixel electrode layer.

[0087] Optionally, the first insulating layer may also be referred to as a planar layer, and its material may include: acrylic resin or epoxy resin and other materials.

[0088] In one possible implementation, if the manufacturing method of the substrate is used to manufacture Figure 5 In the array substrate shown, the material of the third conductive layer includes: a transparent conductive material, for example, it may be ITO.

[0089] In this case, the second conductive layer formed in step S2 also includes: a first touch line segment. First, a first insulating layer can be formed on the pixel electrode layer by any of a plurality of methods such as deposition, coating, sputtering, etc., and a first insulating layer is patterned to form a first insulating layer with a plurality of first vias.

[0090] Then, a third conductive material layer can be formed on the base substrate formed with the first insulating layer by any of a plurality of methods such as deposition, coating, sputtering, etc., and the third conductive material layer is subjected to a patterning process to form a third conductive layer. The third conductive layer may include: a second touch line segment, and the second touch line segment can be connected to the first touch line segment through at least one first via hole, and the second touch line segment and the first touch line segment can form a touch signal line.

[0091] In another possible implementation, if the manufacturing method of the substrate is used to manufacture Figure 6 For the array substrate shown in the figure, the material of the third conductive layer includes: metal materials such as metal Mo, metal copper Cu, metal aluminum Al or alloys.

[0092] In this case, first, a first insulating layer and a third conductive material layer can be formed on the pixel electrode layer in sequence by any of a plurality of methods such as deposition, coating, sputtering, etc., and the third conductive material layer is subjected to a patterning process to form a third conductive layer. The third conductive layer can include: a touch signal line.

[0093] Step S4, forming a second insulating layer and a fourth conductive layer on the third conductive layer.

[0094] Optionally, the second insulating layer may also be referred to as a flat layer, and its material may include: acrylic resin or epoxy resin, etc. The material of the fourth conductive layer includes: a transparent conductive material, for example, it may be ITO.

[0095] For example, first, a second insulating layer and a fourth conductive material layer can be formed on the third conductive layer in sequence by any of a plurality of methods such as deposition, coating, sputtering, etc., and the fourth conductive material layer is patterned once to form the fourth conductive layer. The third conductive layer can include: a touch electrode.

[0096] It should be noted that each patterning process in the above embodiments may include: photoresist coating, exposure, development, etching and photoresist stripping.

[0097] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific principles of the array substrate described above can refer to the corresponding contents in the aforementioned embodiments of the structure of the array substrate, and will not be repeated here.

[0098] In summary, the manufacturing method of the array substrate provided in the embodiment of the present application forms a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines on the base substrate. When the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel is displayed, even for the same seed pixel in each row of the first pixel area, the probability that the voltage polarity between any two adjacent sub-pixels is the same is still nearly 50%, but in each column of sub-pixels, the voltage polarity between the two sub-pixels belonging to two adjacent first pixel areas is opposite, which can effectively average the voltage polarity of the same seed pixel in the same frame image on a spatial scale, thereby reducing the probability of the occurrence of shaking head lines, and thus effectively improving the display effect of the liquid crystal display panel. In addition, through the plurality of touch signal lines, the liquid crystal display panel can have a touch function without the need to separately assemble a touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with a touch function.

[0099] The embodiment of the present application also provides a display device. The display device may be a liquid crystal display device, which includes a liquid crystal display panel. The liquid crystal display panel may include: Figure 2 , Figure 3 , Figure 4 , Figure 5 or Figure 6 The array substrate, the color filter substrate and the liquid crystal layer located between the array substrate and the color filter substrate are shown.

[0100] The display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator or a wearable device.

[0101] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0102] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0103] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A plurality of gate lines and a plurality of data lines located on the substrate, wherein the data lines and the gate lines define a plurality of first pixel regions on the substrate, wherein the plurality of first pixel regions are arranged in a plurality of rows, and two gate lines are arranged between any two adjacent rows of first pixel regions, and the data lines have a plurality of first extensions and a plurality of second extensions arranged alternately, wherein the extension direction of the first extensions intersects with the extension direction of the second extensions, and any two adjacent first extensions in the same data line and the second extension between the two adjacent first extensions constitute a pixel accommodating region, and the pixel accommodating region includes at least one of the first pixel regions; Two sub-pixels located in the first pixel region, the two sub-pixels are arranged along the extension direction of the gate line, and the two sub-pixels are respectively connected to the two data lines adjacent to the first pixel region, and each of the sub-pixels is connected to one of the two gate lines adjacent to the sub-pixel; and, a plurality of touch signal lines located on the substrate, the plurality of first pixel regions are further arranged in a plurality of columns, each column of the first pixel regions includes two columns of sub-pixels, and the touch signal line is located between two columns of sub-pixels in the same column of the first pixel regions; The touch signal line comprises: a first touch line segment and a second touch line segment arranged at intervals, the first touch line segment and the second touch line segment are arranged in different layers, adjacent first touch line segments are connected to the second touch line segments, the first touch line segment and the data line are arranged in the same layer, and the orthographic projection of the second touch line segment on the base substrate intersects with the orthographic projection of the data line on the base substrate; The array substrate further includes: a first insulating layer located between the first touch line segment and the second touch line segment, the first insulating layer having a plurality of first via holes, and adjacent first touch line segments are connected to the second touch line segments through at least one of the first via holes; The material of the second touch line segment includes a transparent conductive material; in a direction perpendicular to the base substrate, the second touch line segment overlaps with the two gate lines between two adjacent rows of sub-pixels and overlaps with the first extension portion; in a first direction, the width of the second touch line segment is greater than the width of the first touch line segment, and the first direction is the same as the extension direction of the gate line.

2. The array substrate according to claim 1, characterized in that: The plurality of first extension portions and the plurality of second extension portions in the same data line constitute a plurality of pixel accommodating areas, each of the pixel accommodating areas has an opening, and the directions of the openings of any two adjacent pixel accommodating areas are opposite.

3. The array substrate according to claim 1, characterized in that: The pixel accommodating area includes a first pixel region.

4. The array substrate according to claim 1, characterized in that: An extending direction of the first extending portion is the same as an extending direction of the gate line, an extending direction of the second extending portion is perpendicular to an extending direction of the gate line, and an extending direction of the touch signal line is perpendicular to an extending direction of the gate line.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate further includes: a plurality of touch electrodes, and the plurality of touch electrodes are connected to the plurality of touch signal lines in a one-to-one correspondence.

6. The array substrate according to claim 5, characterized in that: The touch electrode and the multiple touch signal lines are arranged in different layers, and the array substrate also includes a second insulating layer located between the touch electrode and the multiple touch signal lines, the second insulating layer has a plurality of second via holes, and each of the touch electrodes and the corresponding touch signal lines are connected through at least one of the second via holes.

7. The array substrate according to claim 6, characterized in that: The touch electrodes are reused as common electrodes in the array substrate, and the touch signal lines are reused as common electrode lines in the array substrate.

8. The array substrate according to claim 6 or 7, characterized in that: The touch control electrode is a block-shaped electrode, each of the sub-pixels includes a pixel electrode, and the orthographic projection of each of the touch control electrodes on the base substrate covers the orthographic projections of multiple pixel electrodes on the base substrate.

9. The array substrate according to any one of claims 1 to 4, characterized in that: A plurality of columns of the first pixel regions correspond one-to-one to the plurality of touch signal lines, and each of the touch signal lines is located between two columns of sub-pixels in a column of the first pixel regions corresponding to the touch signal line.

10. A display device, characterized in that: include: The array substrate, the color filter substrate and the liquid crystal layer located between the array substrate and the color filter substrate as claimed in any one of claims 1 to 9.

Images