Method of manufacturing a bipolar transistor and bipolar transistor obtained by this method

Abstract

Embodiments of the present disclosure relate to a method of manufacturing a bipolar transistor and a bipolar transistor obtained by such a method. A method of manufacturing a bipolar transistor includes forming a stack of a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer on a substrate. An opening is formed in the stack to reach the substrate. An epitaxy process forms a collector of the transistor on the substrate and selectively etches a ring-shaped opening in the third layer. An intrinsic portion of a base is then formed by epitaxy on the collector, the intrinsic portion being separated from the third layer by the ring-shaped opening. A junction between the collector and the intrinsic portion of the base is surrounded by the second layer. An emitter is formed on the intrinsic portion and the third layer is removed. A semiconductor layer is selectively deposited on the second layer and in direct contact with the intrinsic portion to form a non-intrinsic portion of the base.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 2001986, filed on February 28, 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This article relates to methods for manufacturing bipolar transistors and bipolar transistors that can be obtained by such methods. Background Technology

[0004] A bipolar transistor consists of an emitter, a base, and a collector superimposed on a semiconductor substrate.

[0005] The base includes: the so-called intrinsic portion, which is the active region of the transistor, forming a junction with the collector at its lower part and with the emitter at its upper part; and the so-called extrinsic portion, which is an electrically connected region extending laterally relative to the intrinsic base, and the intrinsic portion can be polarized through the extrinsic portion during transistor operation.

[0006] To reduce base-collector capacitance, it is necessary to electrically insulate the collector from the intrinsic portion of the base.

[0007] This insulation can be achieved by means of an air gap surrounding the base-collector junction, which prevents any contact between the base and the collector in the non-intrinsic portion.

[0008] Figure 1 A bipolar transistor formed on a semiconductor substrate 1 is shown. A collector C is partially formed in an electrically insulating layer 11. The upper portion of the collector C, which forms a junction with the intrinsic portion B1 of the base B, is surrounded by an air gap 3'. The intrinsic portion B1 has a T-shape and is connected to the semiconductor layer 13, which forms the extrinsic portion B2 of the base, via a lateral portion B3 formed after portion B1 and having different electrical properties. The air gap 3' is defined by the electrically insulating layer 11, the semiconductor layer 13, and an electrically insulating layer 12 extending below the T-shaped head of the intrinsic portion of the base.

[0009] Methods for forming such air gaps are described by reference to incorporated U.S. Patent Nos. 10,186,605 and 10,224,423.

[0010] However, these methods are particularly complex because the number of steps required to connect the intrinsic portion of the base to the intrinsic portion is large. Furthermore, controlling the air gap size is difficult, which introduces the risk of a short circuit between the extrinsic portion of the base and the collector.

[0011] Therefore, there is still a need to design a method for manufacturing bipolar transistors that can robustly and with the fewest possible steps electrically insulate the intrinsic portion of the base from the collector. Summary of the Invention

[0012] In an embodiment, a method for manufacturing a bipolar transistor including a collector, a base, and an emitter includes: forming a stack on a semiconductor substrate, comprising: a first layer, a second layer, a third layer, and a fourth layer, wherein each of the first to fourth layers is selectively etchable relative to each adjacent layer, and the first, second, and fourth layers are electrically insulating; forming an opening in the stack leading to the semiconductor substrate; forming a collector of the bipolar transistor on the substrate by epitaxy, and forming an annular opening by selective etching in the third layer; forming an intrinsic portion of the base on the collector by epitaxy, the intrinsic portion being separated from the third layer by an air gap formed in the annular opening, a junction between the collector and the intrinsic portion of the base being surrounded by a second layer; forming an emitter on the intrinsic portion of the base; removing the third layer by selective etching; and selectively depositing a semiconductor layer on the second layer, in direct contact with the intrinsic portion of the base, to form an intrinsic portion of the base of the bipolar transistor.

[0013] In this context, the phrase "intrinsic portion of the base" is understood to mean the portion of the bipolar transistor that forms a PN junction with the collector and emitter, respectively. The phrase "intrinsic portion of the base" is understood to mean the region of electrical contact that extends laterally relative to the intrinsic portion of the base, and therefore functions to polarize the base of the bipolar transistor.

[0014] In some embodiments, forming an emitter includes forming an opening in the fourth layer that extends to the intrinsic portion of the base, and non-selectively depositing semiconductor material on the fourth layer and the intrinsic portion of the base.

[0015] In some embodiments, forming the intrinsic portion of the base includes a first stage of laterally growing a semiconductor layer from the edge of the intrinsic portion of the base, followed by a second stage of growing a semiconductor layer from the surface of a second electrically insulating layer in a direction perpendicular to the surface.

[0016] In other embodiments, the intrinsic portion forming the base includes depositing a first semiconductor layer on a second electrically insulating layer, followed by selectively depositing a semiconductor layer on the first semiconductor layer.

[0017] In some embodiments, the first, second, and fourth layers are formed of silicon oxide (SiO2) or silicon nitride (Si3N4) materials.

[0018] Specifically, the first and fourth layers can be silicon oxide layers, and the second layer can be a silicon nitride layer.

[0019] In some embodiments, the third layer is a polycrystalline silicon-germanium layer.

[0020] In some embodiments, the semiconductor layer forming the intrinsic portion of the base is a polycrystalline silicon layer.

[0021] In some embodiments, the intrinsic portion of the base comprises silicon germanium.

[0022] In some embodiments, the third layer and the intrinsic portion of the base are made of silicon germanium, and the germanium content of the third layer is at least 1.5 times higher than the germanium content of the intrinsic portion of the base.

[0023] In some embodiments, the method includes forming a spacer on the intrinsic portion of the base prior to forming the emitter.

[0024] Specifically, forming the spacer may include: depositing a silicon oxide layer on the intrinsic portion of the base; depositing a silicon nitride layer on the silicon oxide layer; and forming openings in the silicon nitride layer and the silicon oxide layer that extend to the intrinsic portion of the base, so as to define the spacer in the silicon oxide layer.

[0025] In one embodiment, a structure includes a bipolar transistor that can be obtained by the method described above.

[0026] The structure includes a bipolar transistor comprising: a collector, a base, and an emitter. The structure includes: a semiconductor substrate; a stack sequentially comprising, from the substrate: a first electrically insulating layer, a second electrically insulating layer made of a material different from that of the first electrically insulating layer, and a semiconductor layer, the stack including a window extending into the substrate; an intrinsic portion of the collector, the base, and the emitter being sequentially stacked on the substrate in the window; a junction between the collector and the intrinsic portion of the base being surrounded by the second electrically insulating layer; and the semiconductor layer forming an intrinsic portion of the base of the bipolar transistor.

[0027] In some embodiments, the second electrical insulating layer is in direct contact with the junction between the intrinsic portions of the collector and the base.

[0028] In some embodiments, the first electrical insulating layer is made of silicon oxide, and the second electrical insulating layer is made of silicon nitride.

[0029] In some embodiments, the semiconductor layer forming the intrinsic portion of the base is made of polycrystalline silicon. Attached Figure Description

[0030] Referring to the accompanying drawings, other features and advantages of these embodiments will become clear in the following detailed description, wherein:

[0031] Figure 1 This is a schematic cross-sectional view of a bipolar transistor including the air gap around the junction between the base and collector.

[0032] Figure 2 This is a schematic cross-sectional view of the stack of layers formed on a substrate;

[0033] Figure 3 After an opening is formed in the stack Figure 2 A schematic cross-sectional view of the structure;

[0034] Figure 4 It refers to the collector of a bipolar transistor formed on a substrate via epitaxy. Figure 3 A schematic cross-sectional view of the structure;

[0035] Figure 5 It is formed by epitaxial growth of the base of a bipolar transistor onto the collector. Figure 4 A schematic cross-sectional view of the structure;

[0036] Figure 6 It is after the deposition of silicon oxide and silicon nitride layers. Figure 5 A schematic cross-sectional view of the structure;

[0037] Figure 7 It occurred after a portion of the silicon nitride layer was etched. Figure 6 A schematic cross-sectional view of the structure;

[0038] Figure 8 This occurs after the opening is formed on the upper surface of the base of the bipolar transistor. Figure 7 A schematic cross-sectional view of the structure;

[0039] Figure 9 This is after removing the silicon nitride pads. Figure 8 A schematic cross-sectional view of the structure;

[0040] Figure 10 This occurs after the deposition of materials that form the emitter and protective layer of a bipolar transistor. Figure 9 A schematic cross-sectional view of the structure;

[0041] Figure 11 This is after defining the emitter of the bipolar transistor. Figure 10 A schematic cross-sectional view of the structure;

[0042] Figure 12 It is after the encapsulation layer around the deposited emitter. Figure 11 A schematic cross-sectional view of the structure;

[0043] Figure 13 It occurred after the localized etching of the encapsulation layer. Figure 12 A schematic cross-sectional view of the structure;

[0044] Figure 14 It is after the polycrystalline silicon germanium layer is removed. Figure 13A schematic cross-sectional view of the structure;

[0045] Figure 15 This occurs after the selective deposition of the semiconductor layer that forms the intrinsic portion of the base of a bipolar transistor. Figure 14 A schematic cross-sectional view of the structure;

[0046] Figure 16A This is a schematic cross-sectional view of the selective deposition step according to the first embodiment; and

[0047] Figure 16B This is a schematic cross-sectional view of the selective deposition step according to the second embodiment.

[0048] For ease of reading, the accompanying drawings are not drawn to scale. Furthermore, the drawings have been simplified to show only the elements necessary for understanding them. Detailed Implementation

[0049] In this document, the terms “lateral,” “lower,” “upper,” “below,” “above,” “upper,” “lower,” etc., are understood in accordance with the orientation of the elements considered in the accompanying drawings.

[0050] refer to Figure 2 A stack 2 of four consecutive (and adjacent) layers is formed on a substrate 1: a first layer 21, a second layer 22 on and in contact with the first layer 21, a third layer 23 on and in contact with the second layer 22, and a fourth layer 24 on and in contact with the third layer 23.

[0051] Substrate 1 is a selectively doped single-crystal semiconductor substrate. For example, substrate 1 can be a single-crystal silicon substrate. As described below, substrate 1 must actually be used as a seed for the epitaxial growth of the collector, base, and emitter of a bipolar transistor.

[0052] The stacked first, second, and fourth layers are electrically insulating. For example, the layers may be formed of silicon oxide (SiO2) or silicon nitride (Si3N4).

[0053] Furthermore, each of layers 21 to 24 can be selectively etched compared to each adjacent layer.

[0054] Therefore, in some embodiments, layers 21 and 24 are silicon oxide layers, and layer 22 is a silicon nitride layer.

[0055] The third layer 23 is advantageously a polycrystalline silicon-germanium layer, which can be selectively etched compared to the materials of layers 22 and 24 and the intrinsic portion of the base to be formed thereafter.

[0056] Of course, these materials are given as examples, and those skilled in the art may choose other materials that meet the above conditions.

[0057] refer to Figure 3 An opening 20 extending to the substrate 1 has been formed in the stack 2 to expose the surface 10 of the substrate 1.

[0058] Such openings can be formed by etching through a mask (not shown), particularly by dry etching. The etching employs a reagent suitable for the composition of the sequentially etched layers 24, 23, 22, and 21. This etching is inherently anisotropic, meaning primarily in the direction of the stacked thickness. The etchant is selected based on the material to be etched, within the range achievable by those skilled in the art, and will not be described in detail herein.

[0059] The opening 20 forms a window in which the collector, base and emitter must be formed from the surface 10 of the substrate 1.

[0060] refer to Figure 4 A selective cyclic epitaxy method has been implemented to grow the collector C of a bipolar transistor while laterally etching layer 23.

[0061] Substrate 1 is single-crystal and serves as a seed for the epitaxial growth of the collector. The collector is formed of a single-crystal semiconductor material with lattice parameters as similar as possible to those of substrate 1 to avoid the formation of crystal defects in the collector. Advantageously, both substrate 1 and collector C are made of single-crystal silicon. Collector C can be doped during or after epitaxy by methods known to those skilled in the art. In the case of an NPN transistor, collector doping can be performed with arsenic or phosphorus, typically at a dose of 10. 18 cm -3 Up to 10 19 cm -3 On the order of magnitude. In the case of PNP transistors, collector doping can be performed using boron or indium, typically with a dose of 10. 18 cm -3 Up to 10 19 cm -3 The magnitude.

[0062] Each selective epitaxial cycle consists of an etching step and a growth step. The growth rate varies depending on the material to be grown. Epitaxial selectivity is achieved through etching, which removes material deposited in areas where growth is less rapid.

[0063] Each selective etching step utilizes an etchant that etches the polycrystalline silicon germanium of layer 23 faster than the silicon of the collector electrode. For example, the etchant may include hydrochloric acid (HCl). Each selective etching step is capable of forming an annular opening 230 extending laterally around opening 20 in layer 23. The width of the opening 230 is on the order of tens of nanometers on each side of opening 20.

[0064] Each selective epitaxial step can preferably grow single-crystal silicon on the surface 10 of substrate 1, the lattice of substrate 1 serving as a seed for growing the collector C.

[0065] The growth of the collector stops when the upper surface of the collector is located between the upper surface of the silicon oxide layer 21 and the upper surface of the silicon nitride layer 22.

[0066] refer to Figure 5 The base of the bipolar transistor (more precisely, the intrinsic portion B1 of the base) continues to grow epitaxially on the collector C. The collector is single-crystal and serves as a seed for the epitaxial growth of the base. The base is formed of a single-crystal semiconductor material with lattice parameters as similar as possible to those of the collector C to avoid the formation of crystal defects in the collector. Advantageously, the substrate 1 and the collector C are made of single-crystal silicon, while the base B1 is made of single-crystal silicon germanium. The germanium content of layer 23 is sufficiently high (e.g., more than 1.5 times higher) compared to the germanium content of the base B1 to ensure selectivity in the etching of layer 23 relative to the base B1, so that the base is not damaged during the etching of layer 23. Figure 14 (The steps are schematically shown in the diagram). The base is doped with a doping type opposite to that of the collector to form a PN junction, which is in lateral contact with the electrically insulating layer 22.

[0067] Because of the annular opening 230 formed in layer 23, the base is uniquely grown from the single-crystal material of the collector, maintaining a certain distance from the polycrystalline material of layer 23. This optimizes the crystal quality of the base. In reality, if the base were in contact with layer 23, the base material would also be deposited on the edge of that layer, which is composed of a different material from the base and is not single-crystal. This would cause crystal defects in the base.

[0068] The growth of the base stops when the upper surface of the base reaches the upper surface of the polycrystalline silicon germanium layer 23.

[0069] At the end of base growth, the annular opening 230 is thus defined by the interior of the base to form an air gap 3. However, it should be noted that this air gap is related to… Figure 1 The air gaps 3' in the bipolar transistors are not in the same location and do not perform the same function. In fact, Figure 1 The air gap 3' of the bipolar transistor is designed to avoid electrical contact between the base-collector junction and the intrinsic portion of the base, while Figure 5The air gap 3 is designed to optimize the crystal quality of the intrinsic portion of the base. As will be seen below, the air gap 3 will disappear in subsequent steps of the method used to manufacture the bipolar transistor, and thus will not exist in the final bipolar transistor.

[0070] refer to Figure 6 ,exist Figure 5 An additional silicon oxide layer and a silicon nitride layer 26 have been deposited on top of the silicon oxide layer 25. These two layers are intended to form the spacers for the emitter that will be formed subsequently. Because the silicon oxide deposition is conformal, a layer of uniform thickness can be formed across the entire exposed surface, allowing for the subsequent acquisition of spacers with optimal shapes.

[0071] refer to Figure 7 The silicon nitride layer 26 has been etched across the entire surface of the structure. At the end of this etching step, only two silicon nitride pads 26a remain in the opening.

[0072] refer to Figure 8 An opening is formed between the pads 26a by removing the oxide layer present between the pads to expose the upper surface of the intrinsic portion B1 of the base.

[0073] refer to Figure 9 The silicon nitride pad 26a has been removed, leaving only two spacers 25a on the intrinsic portion B1 of the base, which are the remnants of the silicon oxide layer 25.

[0074] refer to Figure 10 The deposition of polysilicon intended to form the emitter has been achieved. This deposition is not selective; a polysilicon layer 27 has been deposited simultaneously on the silicon oxide layer 24, the spacer 25a, and the intrinsic portion B1 of the base. Layer 27 is doped with a type opposite to that of the base to form a PN junction between the base and emitter. In the case of an NPN transistor, emitter doping can be performed using arsenic, typically at a dose of 10. 20 Up to 10 21 cm -3 On the order of magnitude. In the case of PNP transistors, emitter doping can be performed using boron, typically with a dose of 10. 20 Up to 10 21 cm -3 The magnitude.

[0075] Layer 27 is then covered by an electrically insulating protective layer 28 (e.g., made of silicon oxide).

[0076] refer to Figure 11 Local etching is performed using a mask (not shown) to define the emitter E in the polysilicon layer 27. In the regions of the structure not covered by the mask, the etching has removed the silicon oxide layer 28, the polysilicon layer 27, and the silicon oxide layer 24.

[0077] An etchant is selected to ensure selective etching of silicon oxide compared to polycrystalline silicon germanium, with the polycrystalline silicon germanium layer 23 serving as an etch stop layer.

[0078] refer to Figure 12 A silicon oxide layer 29 has been deposited to enable the encapsulation of the emitter. The layer 29 is deposited conformally on the polysilicon-germanium layer 23, the silicon oxide layer 28, and the lateral edge of the emitter.

[0079] refer to Figure 13 The silicon oxide layer 29 present on the surface of the silicon germanium layer 23 has been etched. The etching is anisotropic to preserve the upper surface and lateral edges of the silicon oxide package emitter E. The polycrystalline silicon germanium layer 23 serves as an etch stop layer.

[0080] refer to Figure 14 The polycrystalline silicon germanium layer 23 was etched. The etchant was selected to ensure selective etching of the polycrystalline silicon germanium compared to other materials in the structure, particularly the materials of the intrinsic portion B1 of the base and the layer 22.

[0081] The etching exposes the upper part of the lateral edge of the intrinsic portion B1 of the base, where the base-collector junction is surrounded by a silicon nitride layer 22.

[0082] refer to Figure 15 Semiconductor layer 30 has been deposited on silicon nitride layer 22. The semiconductor material of layer 30 is selectively deposited on silicon nitride rather than on silicon oxide. Silicon nitride is not a single-crystal material; the semiconductor material of layer 30 is typically polycrystalline. According to a preferred embodiment, the material of layer 30 is polycrystalline silicon doped with the same type as the base.

[0083] The deposition of layer 30 can stop from the moment the upper surface of the layer reaches the lower surface of the emitter E. Therefore, layer 30 completely fills the stop region under the emitter and makes electrical contact with the upper part of the base B. Thus, layer 30 realizes the function of the intrinsic portion B2 of the base.

[0084] According to the embodiments, such as Figure 16A As shown, the growth of layer 30 can begin from the exposed edge of the intrinsic portion B1 of the base, growing in a direction parallel to the main surface of the structure (indicated by arrow I), and then from the surface of layer 22 of the silicon nitride layer, growing in a direction perpendicular to the surface of layer 22 (indicated by arrow II). For this purpose, selective epitaxy is first implemented so that the material of layer 30 can be uniquely grown from the silicon-germanium intrinsic portion of the base, and then selective epitaxy is performed so that the material of layer 30 can also be grown from the silicon nitride of layer 22.

[0085] according to Figure 16BIn the alternative embodiment shown, the growth of layer 30 can be performed in two steps in a direction perpendicular to the main surface of the structure. In the first step (schematically shown by arrow I), a thin silicon layer can first be deposited on layer 22. In the second step (schematically shown by arrow II), P-doped polysilicon is deposited on the thin silicon layer to form the remainder of layer 30. This pre-deposition of the thin silicon layer can help ensure sufficient selectivity of the polysilicon layer relative to the deposition of the oxide of the packaged emitter. Due to the low silicon layer thickness, the silicon layer deposited in the first step cannot provide electrical functionality. The electrical functionality of the intrinsic portion B2 of the base is ensured by the polysilicon layer deposited in the second step.

[0086] Therefore, due to the prudent selection of materials for the stacks deposited on the substrate in terms of etching and / or deposition selectivity, compared with Figure 1 Compared to methods for manufacturing bipolar transistors, the method described herein has the following advantages. Firstly, the air gap formed around the intrinsic portion of the base improves the crystal quality of the base. Secondly, the electrical insulation of the base-collector junction relative to the extrinsic portion of the base is ensured by an electrically insulating layer (i.e., silicon nitride layer 22 in the embodiment shown in the figure), which is in direct contact with both the base and collector on either side of the junction; thus avoiding difficulties related to air gap control. Finally, the number of implementation steps is reduced, particularly regarding the connection between the intrinsic and extrinsic portions of the base.

[0087] The resulting bipolar transistors are more robust and easier to manufacture on an industrial scale.

[0088] Furthermore, the steps for manufacturing the bipolar transistor are compatible with the steps for manufacturing a CMOS transistor, and the method is applicable to the cointegration of bipolar transistors and CMOS transistors (represented by the term BiCMOS).

Claims

1. A method for manufacturing a bipolar transistor, the bipolar transistor comprising a collector, a base, and an emitter, the method comprising: A stack of adjacent layers is formed on a semiconductor substrate, comprising, successively, a first layer, a second layer, a third layer, and a fourth layer, wherein each of the first layer, the second layer, the third layer, and the fourth layer is selectively etchable compared to each adjacent layer, and the first layer, the second layer, and the fourth layer are electrically insulating. An opening is formed in the stack to reach the semiconductor substrate; An epitaxial process is performed to grow the collector of the bipolar transistor on the semiconductor substrate in the opening, and to etch an annular opening in the third layer in the opening; The intrinsic portion of the base is formed epitaxially on the collector electrode, and the intrinsic portion of the base electrode is separated from the third layer by an air gap formed in the annular opening, wherein the junction between the collector electrode and the intrinsic portion of the base electrode is surrounded by the second layer. The emitter is formed on the intrinsic portion of the base; The third layer was removed by selective etching; and In the region where the third layer is removed and in direct contact with the intrinsic portion of the base, a semiconductor layer is selectively deposited on the second layer to form the extrinsic portion of the base of the bipolar transistor.

2. The method of claim 1, wherein forming the emitter comprises: An opening is formed in the fourth layer that leads to the intrinsic portion of the base; as well as Semiconductor material is non-selectively deposited on the intrinsic portion of the fourth layer and the base.

3. The method of claim 1, wherein the intrinsic portion forming the base comprises: The first stage of laterally growing the semiconductor layer from the edge of the intrinsic portion of the base; The second stage then involves growing the semiconductor layer from the surface of the second layer in a direction perpendicular to the surface.

4. The method of claim 1, wherein the intrinsic portion forming the base comprises: The stage of depositing the first semiconductor layer on the second layer; The semiconductor layer is then selectively deposited on the first semiconductor layer.

5. The method of claim 1, wherein the first layer, the second layer and the fourth layer are formed of a material selected from the group consisting of silicon oxide and silicon nitride.

6. The method of claim 5, wherein the first layer and the fourth layer are made of silicon oxide, and the second layer is made of silicon nitride.

7. The method of claim 1, wherein the third layer is made of polycrystalline silicon germanium.

8. The method of claim 1, wherein the semiconductor layer forming the intrinsic portion of the base is made of polycrystalline silicon.

9. The method of claim 1, wherein the intrinsic portion of the base is made of silicon germanium.

10. The method of claim 9, wherein the third layer is made of polycrystalline silicon germanium, and wherein the germanium content of the third layer is at least 1.5 times higher than the germanium content of the intrinsic portion of the base.

11. The method of claim 1, further comprising forming a spacer on the intrinsic portion of the base prior to forming the emitter.

12. The method of claim 11, wherein forming the spacer comprises: A silicon oxide layer is deposited on the intrinsic portion of the base; A silicon nitride layer is deposited on the silicon oxide layer; as well as An opening is formed in the silicon nitride layer and the silicon oxide layer to reach the intrinsic portion of the base, so as to define the spacer in the silicon oxide layer.

13. A structure including a bipolar transistor, the bipolar transistor including a collector, a base, and an emitter, the structure comprising: Semiconductor substrate; A stack on the semiconductor substrate, the stack sequentially comprising: a first electrically insulating layer; a second electrically insulating layer on and in contact with the first electrically insulating layer, wherein the second electrically insulating layer is made of a material different from that of the first electrically insulating layer; and a semiconductor layer, the stack including a window extending through the stack to reach the semiconductor substrate; The collector, the intrinsic portion of the base, and the emitter are successively stacked on the semiconductor substrate in the window; The junction between the intrinsic portions of the collector and the base is surrounded by the second electrically insulating layer; and The semiconductor layer is in direct contact with the intrinsic portion of the base to form the non-intrinsic portion of the base of the bipolar transistor.

14. The structure of claim 13, wherein the second electrical insulating layer directly contacts the junction between the intrinsic portions of the collector and the base.

15. The structure of claim 13, wherein the first electrical insulating layer is made of silicon oxide and the second electrical insulating layer is made of silicon nitride.

16. The structure of claim 13, wherein the semiconductor layer forming the intrinsic portion of the base is made of polycrystalline silicon.

Images