Semiconductor Package and Method of Manufacturing the Same

Abstract

The present disclosure provides a semiconductor package, the semiconductor package comprising: a first substrate having a first active surface and a first trench recessed from the first active surface; a second substrate having a second trench facing the first trench; and a path cavity defined by the first trench and the second trench. The first trench includes a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package having a path cavity that permits fluid passage therethrough and a method of manufacturing such a semiconductor package. Background Art

[0002] Conventional chip-chip bonding, module-module bonding, chip-wafer bonding, chip-substrate bonding, wafer-wafer bonding require the formation of metal bonds. Certain types of chips or modules, wafers, substrates containing such chips may require low-temperature bonding operations to prevent performance degradation of such chips. In low-temperature bonding operations, electroless Cu-Cu bonding can be an option.

[0003] Current electroless Cu-Cu bonding applies a non-fixed spacer between opposing bonding surfaces to create a path for an electroless plating solution. However, the spacer is a non-fixed structure and thus may affect the flow of the electroless plating solution. Additionally, as the demand for I / O density increases, lateral bridging often occurs in conventional electroless Cu-Cu bonding scenarios. Summary of the Invention

[0004] In some embodiments, the present disclosure provides a semiconductor package including: a first substrate having a first active surface and a first trench recessed from the first active surface; a second substrate having a second trench facing the first trench; and a path cavity defined by the first trench and the second trench. The first trench includes a first metal protrusion and a first insulating protrusion.

[0005] In some embodiments, the present disclosure provides a semiconductor package including: a first substrate having a first active surface and a first trench recessed from the first active surface; a second substrate having a second trench facing the first trench; a first fluid path defined by the first trench and the second trench; and a plurality of conductive elements and a plurality of insulating portions in the first fluid path, and each of the conductive elements is staggered with respect to each of the insulating portions.

[0006] In some embodiments, the present disclosure provides a method of manufacturing a semiconductor package, the method including: providing a first substrate and a second substrate; forming a first metal protrusion on the first substrate; depositing a first dielectric layer on the first substrate; planarizing the first dielectric layer; forming a first trench in the first substrate and exposing the first metal protrusion; and bonding the first substrate and the second substrate by an electroless plating operation. Brief Description of the Drawings

[0007] As will be readily understood in view of the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not necessarily be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be increased or decreased arbitrarily.

[0008] Figure 1A A top view of a first substrate in a semiconductor package according to some embodiments of the present disclosure is shown.

[0009] Figure 1B A top view of a second substrate in a semiconductor package according to some embodiments of the present disclosure is shown.

[0010] Figure 1C A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0011] Figure 1D A top view of a first substrate in a semiconductor package according to some embodiments of the present disclosure is shown.

[0012] Figure 2 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0013] Figure 3 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0014] Figure 4 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0015] Figure 5 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0016] Figure 6 A perspective view of a semiconductor package and a box-to-pin connector before bonding a first substrate and a second substrate opposite the first substrate according to some embodiments of the present disclosure is shown.

[0017] Figure 7 A cross-sectional view of a semiconductor package having a multi-layer stacked structure according to some embodiments of the present disclosure is shown.

[0018] Figures 8A through 8J A cross-sectional view of an intermediate product in various stages of manufacturing a semiconductor package according to some embodiments of the present disclosure is shown.

[0019] Figure 8K A semiconductor package assembled through the structure in Figure 8J is shown in a cross-sectional view according to some embodiments of the present disclosure.

[0020] Figures 9A through 9K Shows a cross-sectional view of an intermediate product in various stages of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0021] Figure 9L Shows a cross-sectional view of a semiconductor package assembled through the structure in Figure 9K according to some embodiments of the present disclosure.

[0022] Figures 10A through 10G Shows a cross-sectional view of an intermediate product in various stages of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0023] Figure 10H Shows a cross-sectional view of a semiconductor package assembled through the structure in Figure 10G according to some embodiments of the present disclosure. Detailed Description

[0024] Throughout the drawings and the detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings.

[0025] Spatial descriptions such as "above", "below", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "higher", "lower", "upper", "above", "below", etc. are specified with respect to the orientation of a certain component or a certain group of components or a certain plane of a component or a group of components for the one or more components, as shown in the relevant drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and the actual implementation of the structures described herein can be arranged in any orientation or manner in space, provided that such an arrangement does not deviate from the advantages of the embodiments of the present disclosure.

[0026] The present disclosure provides a semiconductor package structure having a metal-metal bond (e.g., Cu-Cu bond) formed through an electroless plating operation. The insulating protrusions in the semiconductor package structure provide a fixed configuration for implementing a defined path of the electroless plating solution. The insulating protrusions or insulating portions in the semiconductor package structure are arranged in a staggered manner between adjacent conductive elements (e.g., copper pillars or copper pads), and can prevent adjacent conductive elements from bridging at high I / O counts. The conductive elements mentioned herein include, but are not limited to, copper pillars, copper pads, copper studs, copper protrusions, nickel, gold, palladium, and other suitable conductive materials having variable sizes and geometries known in the art.

[0027] Refer to Figure 1A , Figure 1AShows a top view of a first substrate 10A in a semiconductor package according to some embodiments of the present disclosure. The first substrate 10A includes a substrate body 101 having an active surface 101A, and trenches 101T recessed from the active surface 101A. The active surface 101A is adjacent to the active region of the first substrate 10A and may include a dielectric surface. A connector region 110 having a plurality of conductive connectors, e.g., an I / O region, is positioned in the trenches 101T. As Figure 1A depicted, the trenches 101T may have a narrower width 1001W at the edge of the substrate body 101 or the active surface 101A and a wider width 1003W at the center of the substrate body 101 or the active surface 101A. In some embodiments, the wider width 1003W of the trenches 101T may be closer to the connector region 110 than the edge. The width variation of the trenches 101T can enhance the fluid dynamics and flow rate of a fluid (e.g., electroless plating solution).

[0028] Reference Figure 1B , Figure 1B Shows a top view of a second substrate 10B in a semiconductor package according to some embodiments of the present disclosure. The second substrate 10B includes a substrate body 102 having an active surface 102A, and trenches 102T recessed from the active surface 102A. A connector region 110' having a plurality of conductive connectors, e.g., an I / O region, is positioned in the trenches 102T. As Figure 1B depicted, the trenches 102T may have a narrower width 1001W at the edge of the substrate body 102 or the active surface 102A and a wider width 1003W at the center of the substrate body 102 or the active surface 102A. In some embodiments, the wider width 1003W of the trenches 102T may be closer to the connector region 110' than the edge. The width variation of the trenches 102T can enhance the fluid dynamics and flow rate of a fluid (e.g., electroless plating solution).

[0029] In some embodiments, the active surface 101A of the first substrate 10A is bonded to the active surface 102A of the second substrate 10B and forms the Figure 1C shown semiconductor package. The trenches 101T of the first substrate 10A and the trenches 102T of the second substrate 10B define a path cavity that allows a fluid (e.g., electroless plating solution) to pass through. The path cavity may be referred to as a fluid path in the present disclosure because, in some embodiments, the path cavity is configured as a fluid path during an electroless plating operation.

[0030] Referring to Figure 1C , Figure 1C Shows a cross-sectional view of a semiconductor package 10C according to some embodiments of the present disclosure. The semiconductor package 10C is along Figure 1A andFigure 1B The cross-section taken along the dotted line AA' of Figure 1B . The first substrate 101 is bonded to the second substrate 102 at the first active surface 101A and the second active surface 102A. The active surface 101A is close to the active region of the first substrate 10A and may include a dielectric surface. The active surface 101B is close to the active region of the second substrate 10B and may include a dielectric surface. In addition, the trench 101T and the trench 102T respectively recessed from the first active surface 101A and the second active surface 101B together form a path cavity 107. The semiconductor package 10C includes a plurality of conductive elements (including the metal protrusions 103M, 105M and the electroless plating portion 108) and a plurality of insulating portions (including the insulating protrusions 103I, 105I). The plurality of conductive elements are arranged alternately with respect to the plurality of insulating protrusions in the path cavity 107. At least one metal protrusion 103M and at least one insulating protrusion 103I are positioned in the trench 101T of the first substrate 101. As Figure 1C shown, the metal protrusion 103M is laterally adjacent to two insulating protrusions 103I, thus forming an alternating arrangement between the plurality of metal protrusions 103M and the insulating protrusions 103I.

[0031] Similarly, at least one metal protrusion 105M and at least one insulating protrusion 105I are positioned in the trench 102T of the second substrate 102. As Figure 1C shown, the metal protrusion 105M is laterally adjacent to two insulating protrusions 105I, thus forming an alternating arrangement between the plurality of metal protrusions 105M and the insulating protrusions 105I. The metal protrusion 105M is electrically coupled to the metal protrusion 103M through the electroless plating portion 108. In some embodiments, the electroless plating portion 108 may surround the upper surface and the side surface of each of the metal protrusions 103M and the metal protrusion 105M, and the electroless plating portions 108 at the upper surfaces of the opposite metal protrusions are connected to form an electrical connection. In some embodiments, the upper surface of the insulating protrusion 105I is physically connected to the upper surface of the insulating protrusion 103I. A boundary may be observed at the contact interface of the insulating protrusion 105I and the insulating protrusion 103I.

[0032] In some embodiments, the trench 102T of the first substrate 101 may have a flat bottom, while the trench 102T of the second substrate 102 may have bottoms at different horizontal heights. Depending on the layout and depth of the active regions, some of the semiconductor die in the semiconductor die may allow for deeper trenches towards the passive surface of the substrate, while some of the die in the semiconductor die may only accommodate shallower trenches towards the passive surface of the substrate. The bottom horizontal heights of the trenches 101T and 102T can be adjusted according to the active region arrangements of different semiconductor die. The greater the depth of the horizontal height of the trench bottom towards the passive surface, the greater the volume of fluid can be allowed to pass over the metal protrusions 103M and 105M during the electroless plating operation to facilitate the process, especially when using a high-viscosity fluid.

[0033] Reference Figure 1D , Figure 1D shows a top view of a first substrate in a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the active surface 101A of the substrate body 101 may have more than one trench 101T, 101T', and 101T". Each of the trenches 101T, 101T', and 101T" may include more than one connector region 110A, 110B, and 110C, depending on the various designs of the semiconductor die.

[0034] Figure 2 shows a cross-sectional view of a semiconductor package 20 according to some embodiments of the present disclosure. The semiconductor package 20 is similar to the semiconductor package 10C, except that it has additional conductive pads 201 in the first trench 101T and additional conductive pads 202 in the second trench 102T. In some embodiments, a seed layer 201' may be disposed between the first substrate 101 and the conductive pad 201, and a seed layer 202' may be disposed between the second substrate 102 and the conductive pad 202. Specifically, in some embodiments, the second trench 102T includes a shallower bottom horizontal height 102T1 and a deeper bottom horizontal height 102T2, and the conductive pad 202 is positioned on the shallower bottom horizontal height 102T1, receiving the metal protrusions 205M at both ends. The first trench 101T includes a single bottom horizontal height, and the conductive pad 201 is positioned at the bottom of the first trench 101T, receiving the metal protrusions 203M at both ends. In some embodiments, a seed layer 203' may be disposed between the conductive pad 201 and the metal protrusion 203M, and a seed layer 205' may be disposed between the conductive pad 202 and the metal protrusion 205M. As Figure 2 shown, the conductive pads 201, the metal protrusions 203M, the metal protrusions 205M, the conductive pads 202, etc. form a daisy chain. Such a daisy chain configuration allows for in-situ electrical characterization (e.g., resistance measurement) during the electroless plating operation, thereby detecting the progress of the deposition of the electroless plating portion 208.

[0035] The boundary 1035 between the insulating protrusion 103I and the insulating protrusion 105I can be observed because, before the electroless plating operation, the insulating protrusion 103I and the insulating protrusion 105I form an abutting junction while maintaining a gap, such as less than 5 μm, between the opposite ends of the metal protrusion 203M and the metal protrusion 205M. Therefore, the horizontal height of the boundary is higher than the upper surface of the metal protrusion 203 and lower than the surface of the metal protrusion 205M opposite to the metal protrusion 203M.

[0036] Reference Figure 2 , the metal protrusion 203M in the first trench 101T is spaced apart from the insulating protrusion 103I on the left and right sides. There is a distance L1 between the right side of the metal protrusion 203M and the opposite side of the insulating protrusion 103I, and there is a distance L2 between the left side of the metal protrusion 203M and the opposite side of the insulating protrusion 103I. In some embodiments, the distance L1 is different from the distance L2. For example, the distance L1 can be less than the distance L2. In some embodiments, the electroless plating portion 208 at the right side of the metal protrusion 203M can contact the opposite sidewall of the insulating protrusion 103I on the right side while still being spaced apart from the opposite sidewall of the insulating protrusion 103I on the left side. In a device with a high-density I / O count, the insulating protrusion 103I can act as a spacer to prevent the electroless plating portion 208 of the metal protrusion 203M from bridging to the electroless plating portion 208 of an adjacent metal protrusion 203M.

[0037] Figure 3 A cross-sectional view of a semiconductor package 30 according to some embodiments of the present disclosure is shown. The semiconductor package 30 is similar to the semiconductor package 20, except that the metal protrusion 203M in the trench 101T and the metal protrusion 205M in the trench 102T each have a tapered shape. The metal protrusion 203M has a narrower end proximal to the conductive pad 201 and a wider end distal to the conductive pad 201. In some embodiments, the seed layer 301 serves as a lining for the bottom and sidewall profiles of the tapered metal protrusion 203M and the metal protrusion 205M.

[0038] Figure 4Shows a cross-sectional view of a semiconductor package 40 in accordance with some embodiments of the present disclosure. The semiconductor package 40 is similar to the semiconductor package 10C, except that, similar to the second trench 102T, the first trench 101T includes different horizontal heights. For example, the first trench 101T includes a shallower bottom horizontal height 101T1 and a deeper bottom horizontal height 101T2, and the metal protrusion 203M is positioned on the shallower bottom horizontal height 101T1. Depending on the layout and depth of the active regions, some of the semiconductor dies in the semiconductor die may allow for a deeper recess toward the passive surface of the substrate, while some of the dies in the semiconductor die may only accommodate a shallower recess toward the passive surface of the substrate. The bottom horizontal heights 101T1, 101T2, 102T1, and 102T2 can be adjusted according to the layout of the active regions of different semiconductor dies. The deeper the horizontal height of the bottom of the trench toward the passive surface, the greater the volume of fluid that can pass over the metal protrusions 203M and 205M during the electroless plating operation to facilitate the process, especially when using a high-viscosity fluid.

[0039] Figure 5 Shows a cross-sectional view of a semiconductor package 50 in accordance with some embodiments of the present disclosure. The semiconductor package 50 is similar to the semiconductor package 20, except that a conductive layer 503M is disposed on the insulating protrusion 103I of the first substrate 101, and a conductive layer 505M is disposed on the insulating protrusion 105I of the second substrate 102. Thus, the electroless plating portion 208 electrically connects the metal protrusions 203M, 205M, and the conductive layers 503M, 505M. Different from the semiconductor package 20, the insulating protrusions 103I, 105I of the semiconductor package 50 do not directly contact. The electroless plating operation can be carried out by means of a fixing mechanism that fixes the first substrate 101 and the second substrate 102 at a sufficiently close distance to facilitate the bridging of the electroless plating portion 208 between the metal protrusions 203M, 205M, and the conductive layers 503M, 505M. In some embodiments, it may be necessary to planarize the opposing surfaces of the insulating protrusions 103I, 105I before forming the conductive layers 503M, 505M.

[0040] Figure 6Shows a perspective view of a semiconductor package and a cartridge-pin connector before bonding a first substrate 60A and a second substrate 60B opposite the first substrate 60A. Before forming the electroless plating portion 208, the first substrate 101 and the second substrate 102 are bonded by insulating protrusions 103I, 105I. To enhance the bonding force, fixing elements can be further disposed in both of the trenches 101T, 102T. For example, a cartridge element 603 can be disposed in the first trench 101T, and a pin element 605 can be disposed in the second trench 102T corresponding to the position of the cartridge element 603. Figure 6 The illustrated cartridge element 603 can be of a hollow cylindrical configuration, and the pin element 605 can be of a rod-like configuration that is loosely assembled into the cartridge element 603. Alternatively, the radius of the pin element 605 is less than the radius of the cartridge element 603 to the extent that there can be a gap after assembling the pin element 605 into the cartridge element 603.

[0041] When bonding the first substrate 101 and the second substrate 102, the pin element 605 and the cartridge element 603 are loosely assembled, while the insulating protrusions 103I, 105I are in direct contact and form a molecular-level bond. During the electroless plating operation, the electroless plating portion 208 is deposited between the opposing metal protrusions 203M, 205M and in the gap between the pin element 605 and the cartridge element 603. After completing the electroless plating operation, the cartridge and pin mechanism provides additional mechanical bonding since the electroless plating portion 208 has filled the gap or gap between the cartridge element 605 and the pin element 603.

[0042] Figure 7 Shows a cross-sectional view of a semiconductor package 70 having a multi-layer stacked structure according to some embodiments of the present disclosure. The semiconductor package 70 is similar to the semiconductor package 40, except that a third substrate 701 and a fourth substrate 702 are stacked on top of the first substrate 101 and the second substrate 102. Similarly, the third substrate 701 has a trench 701T recessed from the third active surface 701A, and the fourth substrate 702 has a trench 702T recessed from the fourth active surface 702A. After bonding the third substrate 701 and the fourth substrate 702, the trench 701T and the trench 702T define a second path cavity 207 or a second fluid path. A metal protrusion 303M is disposed in the third trench 701T, and a metal protrusion 305M is disposed in the fourth trench 702T. In some embodiments, the metal protrusion 303M is electrically connected to the metal protrusion 305M through the electroless plating portion 208. In some embodiments, the metal protrusions 303M, 305M are electrically connected to the first substrate 101 and the second substrate 102 through vias 707 in the second substrate 102 or the third substrate 701.

[0043] As Figure 7 shown, in some embodiments, the first substrate 101 may include trenches 101T having various bottom horizontal heights. Depending on the layout and depth of the active regions, some of the semiconductor die in the semiconductor die may allow deeper recesses towards the passive surface of the substrate in a predetermined region, while some of the die in the semiconductor die may only accommodate shallower recesses towards the passive surface of the substrate in other predetermined regions. In some embodiments, the third substrate 701 may include trenches 701T having a single bottom horizontal height.

[0044] Figures 8A through 8J shows a cross-sectional view of an intermediate product in various stages of manufacturing a semiconductor package according to some embodiments of the present disclosure. As Figure 8A shown, a first substrate 101 is provided. The first substrate has an active surface, and a seed layer 800, such as a physical vapor deposition (PVD) Ti / Cu layer, is formed over the active surface. In Figure 8B , a conductive pad 201 is formed over the active surface of the first substrate 101 through a lithography operation, such as a patterned photoresist 801 is formed before electrochemically depositing copper. In Figure 8C , the photoresist 801 is removed, thereby exposing the seed layer 800 not covered by the conductive pad 201. In Figure 8D , the exposed seed layer 800 is removed, and a patterned photoresist 802 is formed over the active surface and the conductive pad 201, as Figure 8E shown. A seed layer 803 or a PVD Ti / Cu layer is formed on the conductive pad 201 not covered by the patterned photoresist 802 and on the upper surface of the patterned photoresist 802.

[0045] In Figure 8F , a pair of metal protrusions 203M are formed at both ends of the conductive pad 201 through electrochemically depositing copper, that is, in the openings of the patterned photoresist 802. In Figure 8G , the patterned photoresist 802 and the seed layer 803 are removed through a lift-off operation. In Figure 8H , a dielectric layer 103I' is formed over the active surface of the substrate 101, the conductive pad 201, and the pair of metal protrusions 203M. In some embodiments, the dielectric layer 103I' is deposited through a silicon oxide chemical vapor deposition (CVD) operation. The upper surface of the dielectric layer 103I' should cover the upper surface of the pair of metal protrusions 203M. In Figure 8I , a planarization operation (e.g., chemical mechanical polishing (CMP)) is performed to planarize and remove a portion of the dielectric layer 103I' to the extent that the upper surface of the pair of metal protrusions 203M is still covered by a thin dielectric layer. In Figure 8JIn [the figure], trenches 101T are formed in the first substrate 101 and the dielectric layer 103I' through a dry etching operation. The upper surface and the side surfaces of the pair of metal protrusions 203M are exposed to the trenches 101T after the dry etching operation. The metal protrusions 203M and the insulating protrusions 103I are arranged alternately. Note that after the dry etching operation, the upper surface of the insulating protrusion 103I is higher than the upper surface of the metal protrusion 203M.

[0046] Figure 8K A cross-sectional view of a semiconductor package assembled from the structure in Figure 8J according to some embodiments of the present disclosure is shown. Figure 8J A first die 80A having trenches 101T, conductive pads 201, and metal protrusions 203M is shown. In Figure 8K [the figure], a second die 80B having trenches 102T, conductive pads 202, and metal protrusions 205M is flip-chip bonded to the first die 80A to define a semiconductor package having a plurality of path cavities 107. In some embodiments, the electrical connections including the conductive pads 201, 202, the metal protrusions 205M, 203M, and the electroless plating portions 208 are designed to form a daisy chain arrangement, which facilitates in-situ electrical characterization (e.g., resistance measurement) during the electroless plating operation. However, in some embodiments, the electrical connections can be designed to form a suitable arrangement other than a daisy chain. The operations for forming the first die 80A can be replicated for forming the second die 80B. Subsequently, an electroless plating operation is performed by flowing an electroless plating solution into the path cavities 107. The electroless plating portions 208 can be deposited on the metal protrusions 203M, 205M and form electrical connections by bridging. In some embodiments, the electroless plating solution is selected according to the temperature constraints of a specific device. For example, when the electroless plating temperature is to be controlled at 80 degrees Celsius, an electroless plating portion 208 containing nickel (Ni) can be selected. When the electroless plating temperature is to be controlled at 50 degrees Celsius, an electroless plating portion 208 containing gold (Au) or palladium (Pd) can be selected. When the electroless plating temperature is to be controlled at 45 degrees Celsius, an electroless plating portion 208 containing copper (Cu) can be selected.

[0047] In some predetermined regions of the first substrate 101, the trenches 101T can be recessed into the substrate (e.g., the two trenches on the left side), while in other predetermined regions of the first substrate 101, the bottoms of the trenches 101T can be at the same level as the active surface of the first substrate 101 (e.g., the two trenches on the right side). Depending on the layout and depth of the active regions, some semiconductor dies in the semiconductor die can allow deeper recesses into the substrate, while some dies in the semiconductor die can only accommodate shallower recesses where the active surface of the substrate is substantially the bottom.

[0048] Figures 9A through 9Kshows a cross-sectional view of an intermediate product in various stages of manufacturing a semiconductor package according to some embodiments of the present disclosure. As Figure 9A shown, a first substrate 101 is provided. The first substrate has an active surface, and a seed layer 800, e.g., a physical vapor deposition (PVD) Ti / Cu layer, is formed over the active surface. In Figure 9B , a conductive pad 201 is formed over the active surface of the first substrate 101 through a lithography operation, e.g., a patterned photoresist 801 is formed before electrochemically depositing copper. In Figure 9C , the photoresist 801 is removed, thereby exposing the seed layer 800 that is not covered by the conductive pad 201. In Figure 9D , the exposed seed layer 800 is removed, and a dielectric layer 103I' is deposited, e.g., by silicon oxide CVD, as Figure 9E shown. The dielectric layer 103I' is deposited to cover the upper surface and side surfaces of the conductive pad 201. In Figure 9F , a pair of openings 900 are formed from the upper surface of the conductive pad 103I', thereby exposing a portion of the underlying conductive pad 201. Subsequently, a seed layer 901 or a PVD Ti / Cu layer is formed on the exposed portion of the conductive pad 201, and the surface profile of the dielectric layer 103I' is formed, as Figure 9G shown.

[0049] In Figure 9H , a pair of metal protrusions 203M' are formed over the exposed portion of the conductive pad 201 through a lithography operation, e.g., a patterned photoresist 902 is formed before electrochemically depositing copper. In Figure 9I , then the patterned photoresist 902 is removed, thereby exposing the seed layer 901. In Figure 9J , a planarization operation (e.g., a chemical mechanical polishing (CMP) operation) is performed to remove a portion of the metal protrusions 203M' that is located above the dielectric layer 103I', thereby planarizing the metal surface and the dielectric surface. In some embodiments, the planarization operation may include multiple stages using different slurries that are selective to different materials. For example, the last stage of planarization may utilize a slurry that has a higher selectivity for metal (e.g., copper) than for dielectric (e.g., silicon oxide), such that when planarization is completed, the planarized metal protrusions 203M are recessed towards the conductive pad 201, while the horizontal height of the upper surface of the dielectric layer 103I' is higher than the horizontal height of the recessed surface of the patterned metal protrusions 203M. In Figure 9K , trenches 101T are formed in the first substrate 101 and the dielectric layer 103I' through a dry etching operation. The upper surface and side surfaces of the pair of metal protrusions 203M are exposed to the trenches 101T after the dry etching operation. The metal protrusions 203M and the insulating protrusions 103I are arranged alternately.

[0050] Figure 9L shows a cross-sectional view of a semiconductor package assembled with the structure in Figure 9K . Figure 9L Shows a first die 90A having trenches 101T, conductive pads 201, and metal protrusions 203M. In Figure 9L , a second die 90B having trenches 102T, conductive pads 202, and metal protrusions 205M is flip-chip bonded to the first die 90A to define a semiconductor package having a plurality of path cavities 107. In some embodiments, the electrical connections including the conductive pads 201, 202, the metal protrusions 205M, 203M, and the electroless plating portion 208 are designed to form a daisy chain arrangement that facilitates in-situ electrical characterization (e.g., resistance measurement) during the electroless plating operation. However, in some embodiments, the electrical connections can be designed to form a suitable arrangement other than a daisy chain. The operations for forming the second die 90B can be replicated for forming the first die 90A. Subsequently, the electroless plating operation is performed by flowing an electroless plating solution into the path cavities 107. The electroless plating portion 208 can be deposited on the metal protrusions 203M, 205M and form electrical connections by bridging. In some predetermined regions of the first substrate 101, the trenches 101T can be recessed into the substrate (e.g., the two trenches on the left side), while in other predetermined regions of the first substrate 101, the bottoms of the trenches 101T can be at the same level as the active surface of the first substrate 101 (e.g., the two trenches on the right side). Depending on the layout and depth of the active regions, some of the semiconductor dies in the semiconductor die can allow deeper recesses into the substrate, while some of the dies in the semiconductor die can only accommodate shallower recesses where the active surface of the substrate is substantially the bottom.

[0051] Figures 10A through 10G shows a cross-sectional view of an intermediate product in various stages of manufacturing a semiconductor package according to some embodiments of the present disclosure. As Figure 10A shown, a first substrate 101 is provided. The first substrate has an active surface, and a seed layer 800, e.g., a physical vapor deposition (PVD) Ti / Cu layer, is formed over the active surface. In Figure 10B , a pair of metal protrusions 203M are formed over the active surface of the first substrate 101 through a lithography operation, e.g., a patterned photoresist 801 is formed before electrochemically depositing copper. In Figure 10C , the photoresist 801 is removed, thereby exposing the seed layer 800 not covered by the conductive pad 201. In Figure 10D , the exposed seed layer 800 is removed. In Figure 10EIn [description], a dielectric layer 103I' is deposited by a silicon oxide chemical vapor deposition (CVD) operation. The upper surface of the dielectric layer 103I' should cover the upper surfaces of the pair of metal protrusions 203M. In Figure 10F In [description], a planarization operation (e.g., chemical mechanical polishing (CMP)) is performed to planarize and remove a portion of the dielectric layer 103I' until the upper surfaces of the pair of metal protrusions 203M are still covered by a thin dielectric layer. In Figure 10G In [description], trenches 101T are formed in the first substrate 101 and the dielectric layer 103I' by a dry etching operation. The upper and side surfaces of the pair of metal protrusions 203M are exposed to the trenches 101T after the dry etching operation. The metal protrusions 203M and the insulating protrusions 103I are arranged alternately. Note that after the dry etching operation, the upper surface of the insulating protrusion 103I is higher than the upper surface of the metal protrusion 203M.

[0052] Figure 10H Shows a cross-sectional view of a semiconductor package assembled from the structure in Figure 10G in accordance with some embodiments of the present disclosure. Figure 10H Illustrates a first die 100A having trenches 101T and metal protrusions 203M. In Figure 10H In [description], a second die 100B having trenches 102T and metal protrusions 205M is flip-chip bonded to the first die 100A to define a semiconductor package having a path cavity 107. The operations for forming the first die 100A can be replicated for forming the second die 100B. Subsequently, an electroless plating operation is performed by flowing an electroless plating solution into the path cavity 107. The electroless plating portion 208 can be deposited on the metal protrusions 203M, 205M and form an electrical connection by bridging. In some predetermined regions of the first substrate 101, the trenches 101T can be recessed into the substrate (e.g., the two left trenches), while in other predetermined regions of the first substrate 101, the bottoms of the trenches 101T can be at the same level as the active surface of the first substrate 101 (e.g., the two right trenches). Depending on the layout and depth of the active regions, some of the semiconductor dies in the semiconductor die can allow deeper recesses into the substrate, while some of the dies in the semiconductor die can only accommodate shallower recesses where the active surface of the substrate is substantially the bottom.

[0053] As used herein and unless otherwise defined, the terms "substantially", "substantive", "about", and "approximate" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can cover instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs nearly. For example, when used in connection with a numerical value, the terms can cover a range of variation that is less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to a positional difference between two surfaces positioned along the same plane that is within a few micrometers, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of being positioned along the same plane.

[0054] As used herein, unless the context clearly indicates otherwise, the singular terms "a / an" and "the" can include plural referents. In the description of some embodiments, another component disposed "on" or "above" a component can cover both the case where the former component is directly located on the latter component (e.g., in physical contact therewith) and the case where one or more intermediate components are positioned between the former component and the latter component.

[0055] Although the present disclosure has been described and shown with reference to specific embodiments thereof, such description and illustration are not restrictive. Those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the spirit and scope of the present disclosure as defined by the claims. The drawings may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproductions and the actual devices in the present disclosure. There may be other embodiments of the present disclosure that are not specifically shown. The specification and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, substance composition, method, or process to the objectives, spirit, and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of the present disclosure. Thus, unless specifically indicated otherwise herein, the order and grouping of operations are not limiting.

Claims

1. A semiconductor package, comprising: A first substrate having a first active surface and a first trench recessed from the first active surface; A second substrate having a second trench facing the first trench; And A path cavity defined by the first trench and the second trench, Wherein the first trench includes a first metal protrusion and a first insulating protrusion, Wherein the path cavity includes a narrower width at an edge of the first substrate and a wider width at a center of the first substrate.

2. The semiconductor package according to claim 1, wherein the second trench further includes: A second metal protrusion electrically coupled to the first metal protrusion; And A second insulating protrusion connected to the first insulating protrusion.

3. The semiconductor package according to claim 2, further comprising: An electroless plating portion located between the first metal protrusion and the second metal protrusion.

4. The semiconductor package according to claim 2, further comprising: A boundary located between the first insulating protrusion and the second insulating protrusion, the horizontal height of the boundary being higher than the upper surface of the first metal protrusion.

5. The semiconductor package according to claim 1, wherein the first trench further includes a plurality of metal protrusions and a plurality of insulating protrusions, and each of the metal protrusions is staggered with respect to each of the insulating protrusions.

6. The semiconductor package according to claim 1, further comprising: A first conductive pad in the first trench, on which the first metal protrusion and the first insulating protrusion are disposed; A second metal protrusion in the second trench, the second metal protrusion being electrically coupled to the first metal protrusion; and A second conductive pad in the second trench, wherein the first conductive pad, the first metal protrusion, the second metal protrusion, and the second conductive pad form a daisy chain.

7. A semiconductor package, comprising: A first substrate having a first active surface and a first trench recessed from the first active surface; A second substrate having a second trench facing the first trench; A first fluid path defined by the first trench and the second trench; A plurality of conductive elements and a plurality of insulating portions in the first fluid path, and each of the conductive elements is staggered with respect to each of the insulating portions; and A box-to-pin connector in the first fluid path.

8. The semiconductor package according to claim 7, wherein one of the conductive elements includes a first metal protrusion extending from the first trench, a second metal protrusion extending from the second trench, and an electroless plating portion connecting the first metal protrusion and the second metal protrusion.

9. The semiconductor package according to claim 7, wherein the second trench includes two bottom horizontal heights.

10. The semiconductor package according to claim 7, further comprising: A third substrate, the third substrate having a third active surface and a third trench recessed from the third active surface, wherein the third substrate is stacked on and electrically coupled to the first substrate and the second substrate.

11. The semiconductor package according to claim 10, further comprising: A fourth substrate, the fourth substrate having a fourth trench facing the third trench; And A second fluid path defined by the third trench and the fourth trench.

12. A method for manufacturing a semiconductor package, the method comprising: Providing a first substrate and a second substrate; Forming a first metal protrusion on the first substrate; Depositing a first dielectric layer on the first substrate; Planarizing the first dielectric layer; Forming a first trench in the first substrate and exposing the first metal protrusion; And Bonding the first substrate and the second substrate by an electroless plating operation.

13. The method according to claim 12, further comprising: Forming a second metal protrusion on the second substrate; And Depositing a second dielectric layer on and covering the second metal protrusion; Forming a second trench in the second substrate and exposing the second metal protrusion; And Bonding the first substrate and the second substrate to form a path cavity defined by the first trench and the second trench.

14. The method according to claim 13, wherein bonding the first substrate and the second substrate comprises: Bringing the first dielectric layer and the second dielectric layer into contact; And Flowing an electroless plating solution into the path cavity.

15. The method according to claim 12, wherein forming the first trench in the first substrate and exposing the first metal protrusion comprises performing a dry etching operation.

16. The method according to claim 12, further comprising: Before forming the first metal protrusion, a conductive pad is formed on the first substrate.

17. The method according to claim 16, wherein forming the first metal protrusion comprises: Forming the first dielectric layer covering the conductive pad; Forming an opening in the first dielectric layer; And Filling the opening with a conductive material.

18. The method according to claim 12, wherein planarizing the first dielectric layer comprises performing a chemical mechanical polishing operation without exposing the first metal protrusion.

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