Interface system and display device comprising the same

Abstract

An interface system and a display device including the same are provided, the interface system including a receiver, a transmitter configured to transmit a signal including a common mode voltage to the receiver through a transmission line, and a plurality of bias circuits configured to adjust the common mode voltage of the signal, wherein the plurality of bias circuits are configured to receive a bias control bit to generate a biased common mode voltage.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0026717 filed on March 3, 2020, the entire contents of which are incorporated herein by reference for all purposes as if fully set forth herein. TECHNICAL FIELD

[0002] Aspects of some example embodiments of the present application relate to an interface system and a display apparatus including the same. BACKGROUND

[0003] With the development of information technology, the importance of display apparatuses providing a medium for connecting users and information has grown. In response thereto, the use of display apparatuses such as liquid crystal display apparatuses, plasma display apparatuses, organic light emitting display apparatuses, etc. has increased over time.

[0004] Generally, a display apparatus includes a plurality of pixels, a data driving integrated circuit (DDI) for driving the pixels, and a timing controller (TCON) for controlling the data driving IC.

[0005] The plurality of pixels can emit light with luminance corresponding to a supplied data signal, and the data driving IC can supply the data signal to the plurality of pixels. The timing controller can transmit the data signal, a synchronization signal, a protocol signal, etc. to the data driving IC. In this case, the timing controller and the data driving IC can communicate with each other through an interface system.

[0006] For example, a USI (Universal Serial Interface) module or a USI-T module can be used as an interface system of a display apparatus.

[0007] The interface system can include a transmitter (TX) and a receiver (RX), and the transmitter and the receiver can reliably communicate in a condition in which an input common mode voltage (VICM) and an input differential voltage (VID) correspond to each other.

[0008] In this case, an AC coupling capacitor for minimizing or reducing a direct current component of a signal can be connected to a transmission line so that the common mode voltages of the transmitter and the receiver can be matched to each other.

[0009] The above information disclosed in this Background section is only for enhancement of understanding of the background of the application, therefore, it can not necessarily constitute the prior art. SUMMARY

[0010] Aspects according to some example embodiments of the present disclosure can include an interface system in which communication performance can be improved by periodically compensating for a common mode voltage of a transmitter or a receiver, and a display device including the same.

[0011] Technical features according to embodiments of the present disclosure are not limited to the above-described technical features, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0012] According to some example embodiments, an interface system according to the present disclosure can include a receiver, a transmitter that transmits a signal including a common mode voltage to the receiver through a transmission line, and a biasing circuit for adjusting the common mode voltage of the signal, the biasing circuit can receive a bias control bit to generate a biased common mode voltage.

[0013] According to some example embodiments, the interface system can further include a balanced voltage detector for detecting a voltage of the transmission line.

[0014] According to some example embodiments, the balanced voltage detector can include a comparator that compares the voltage of the transmission line with a reference voltage input from the outside.

[0015] According to some example embodiments, the comparator can include a first comparator that compares a voltage of one of the transmission lines with a first reference voltage that is a positive voltage input from the outside, and a second comparator that compares a voltage of another of the transmission lines with a second reference voltage that is a negative voltage input from the outside.

[0016] According to some example embodiments, the first comparator and the second comparator can be amplifiers, a voltage of a first transmission line that is the one of the transmission lines can be input to a non-inverting terminal of the first comparator, the first reference voltage can be input to an inverting terminal of the first comparator, a voltage of a second transmission line that is the other of the transmission lines can be input to an inverting terminal of the second comparator, and the second reference voltage can be input to a non-inverting terminal of the second comparator.

[0017] According to some example embodiments, the interface system can further include a first switch that connects the non-inverting terminal of the first comparator and the first transmission line, and a second switch that connects the inverting terminal of the second comparator and the second transmission line.

[0018] According to some example embodiments, the first switch can be turned on in response to a balanced fault signal provided from the receiver, and the second switch can be turned on in response to a balanced check enable signal provided from the transmitter.

[0019] According to some example embodiments, the interface system can further include a bias control unit receiving a voltage output from the balanced voltage detector and a reference voltage input from the outside to control the bias circuit.

[0020] According to some example embodiments, the bias control unit can include a bias controller controlling the bias circuit to generate a bias common voltage.

[0021] According to some example embodiments, the balanced voltage detector can detect a voltage of the transmission line at each compensation period having a periodicity.

[0022] According to some example embodiments, the compensation period can include in a period in which the image data is transmitted.

[0023] According to some example embodiments, the transmission line can include a first transmission line for transmitting a signal of a first phase and a second transmission line for transmitting a signal of a second phase different from the first phase.

[0024] According to some example embodiments, the transmitter can communicate with the receiver in a differential signal method.

[0025] According to some example embodiments, the interface system can further include a combination selection circuit selectively providing a signal transmitted through the transmission line to the bias circuit or the receiver in response to a combination control signal generated from the transmitter.

[0026] According to some example embodiments, the signal input to the receiver can be increased or decreased, and then the increased or decreased signal can be decreased or increased by a predetermined voltage or more.

[0027] A display apparatus according to some example embodiments of the present invention can include a pixel unit including a pixel, a data driver providing a data signal to the pixel and including a receiver, a timing controller including a transmitter transmitting a signal including a common voltage to the receiver through a transmission line, and a balanced voltage detector for detecting a voltage of the signal including the common voltage of the transmission line, the balanced voltage detector can detect the voltage at each compensation period having a periodicity.

[0028] According to some example embodiments, the display apparatus can further include a bias circuit for adjusting the common voltage of the signal including the common voltage. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate aspects of some example embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0030] Figure 1is a block diagram showing a display device according to some example embodiments of the present application.

[0031] Figure 2 is a diagram showing an example of a configuration of one frame.

[0032] Figure 3 is a diagram showing an interface system according to some example embodiments of the present application.

[0033] Figure 4 is a diagram schematically showing a structure of a first transmission line and a second transmission line shown in Figure 3

[0034] Figure 5 is a diagram showing a change in common mode voltage according to a data signal.

[0035] Figure 6 is a diagram showing an interface system according to some example embodiments of the present application.

[0036] Figure 7 is a timing chart showing a method of driving an interface system according to some example embodiments of the present application.

[0037] Figure 8 is a timing chart showing a method of driving an interface system according to some example embodiments of the present application.

[0038] Figure 9 is a conceptual diagram of an interface system for explaining some periods of Figure 8

[0039] Figure 10 is a timing chart showing a method of driving an interface system according to some example embodiments of the present application. DETAILED DESCRIPTION

[0040] Aspects and features of some example embodiments of the present application and methods for implementing the aspects and features of some example embodiments of the present application will be more clearly understood from the following example embodiments described with reference to the accompanying drawings. However, embodiments according to the present application are not limited to the following example embodiments, but can be implemented in various different forms. The example embodiments are provided only to accomplish the disclosure of the present application and to more fully and completely inform those skilled in the art of the scope of embodiments according to the present application. Embodiments according to the present application are defined by the scope of claims and their equivalents.

[0041] ​​Although the terms first, second, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, a first component discussed below could be termed a second component without departing from the spirit and scope of the technology. Singular expressions should also include plural expressions unless the context clearly dictates otherwise.

[0042] Aspects of some example embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Like or similar components can be designated by like or similar reference numerals throughout the drawings.

[0043] Figure 1 is a block diagram illustrating a display apparatus according to some example embodiments of the present application.

[0044] Referring to Figure 1 The display apparatus 100 can include a timing controller 110, a data driver 120, an interface system ITF, a scan driver 130, and a pixel unit 140.

[0045] The timing controller 110 can control overall operations of the display apparatus 100.

[0046] The timing controller 110 can receive image data RGB1 and external control signals from the outside (e.g., from an external source). For example, the external control signals can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, a data enable signal DE, etc.

[0047] The timing controller 110 can process the image data RGB1 and the external control signals to suit operating conditions of the data driver 120, the scan driver 130, and the pixel unit 140 and generate processed image data and clock signals, etc.

[0048] The timing controller 110 can include a transmitter (TX) 200 of the interface system ITF.

[0049] The timing controller 110 can communicate with the data driver 120 through the interface system ITF. For example, the timing controller 110 can transmit the processed image data and the clock signals, etc. to the data driver 120 through the interface system ITF.

[0050] The timing controller 110 can output a scan control signal SCS to the scan driver 130. For example, the scan control signal SCS can include a scan start signal and a plurality of clock signals, etc.

[0051] According to some example embodiments, the interface system ITF can be implemented as a USI module or a USI-T module, etc.

[0052] The data driver 120 can include a receiver (RX) 300 of the interface system ITF. For example, the transmitter 200 and the receiver 300 can be connected to each other through a transmission line.

[0053] The data driver 120 can receive the processed image data and a clock signal, etc. from the timing controller 110 through the interface system ITF.

[0054] The data driver 120 can supply a data signal to the data lines D1 to Dm based on the processed image data and the clock signal, etc., where m is a natural number. For example, the data driver 120 can supply the data signal to the data lines D1 to Dm in synchronization with a scan signal corresponding to the data signal.

[0055] For example, the receiver 300 can include a clock data recovery (CDR) circuit and an equalizer, etc.

[0056] According to some example embodiments, the data driver 120 can be mounted on the display apparatus 100 in the form of a data driving IC.

[0057] The scan driver 130 can receive a scan control signal SCS.

[0058] The scan driver 130 can supply a scan signal to the scan lines S1 to Sn based on the scan control signal SCS, where n is a natural number. For example, the scan driver 130 can sequentially supply the scan signal to the scan lines S1 to Sn.

[0059] The pixel unit 140 can include a substrate and a plurality of pixels PX arranged on the substrate (e.g., in a matrix arrangement). For example, the pixel unit 140 can refer to a display area of a display panel.

[0060] The pixels PX can be connected to the corresponding data lines D1 to Dm and the scan lines S1 to Sn, and can be supplied with the data signal and the scan signal through the data lines D1 to Dm and the scan lines S1 to Sn.

[0061] The pixels PX can be arranged in regions in which the scan lines S1 to Sn and the data lines D1 to Dm cross, respectively.

[0062] The pixels PX can emit light in a gray level corresponding to the data signal.

[0063] The pixel unit 140 can further include the scan lines S1 to Sn and the data lines D1 to Dm. According to some example embodiments, the scan lines S1 to Sn can extend in a first direction (e.g., a horizontal direction), and the data lines D1 to Dm can extend in a second direction (e.g., a vertical direction) different from the first direction.

[0064] According to some example embodiments, any one of the pixels PX can be connected to at least one of the scan lines S1 to Sn and at least one of the data lines D1 to Dm.

[0065] According to some example embodiments, each of the pixels PX can include a first transistor (e.g., a switching transistor) connected to the scan lines S1 to Sn and the data lines D1 to Dm, a second transistor (e.g., a driving transistor) connected to the first transistor, and a light emitting element. Hereinafter, for convenience of description, the light emitting element is described as an organic light emitting diode. However, embodiments according to the present application are not limited thereto.

[0066] A first electrode of the first transistor can be connected to any one of the data lines D1 to Dm, a second electrode of the first transistor can be connected to the second transistor. In addition, a gate electrode of the first transistor can be connected to any one of the scan lines S1 to Sn.

[0067] A first electrode of the second transistor can be connected to the first power supply, a second electrode of the second transistor can be connected to an anode electrode of the light emitting element. In addition, a gate electrode of the second transistor can be connected to the second electrode of the first transistor.

[0068] The anode electrode of the light emitting element can be connected to the second electrode of the second transistor, and a cathode electrode of the light emitting element can be connected to the second power supply.

[0069] The light emitting element can emit light at a luminance corresponding to a driving current flowing from the first power supply to the second power supply.

[0070] The second transistor can control a driving current flowing from the first power supply to the second power supply via the light emitting element according to a data signal transmitted through the first transistor.

[0071] Embodiments according to the present application are not limited thereto, and the structure of each of the pixels PX can be variously changed according to embodiments.

[0072] According to some example embodiments, each of the pixels PX can include a red sub-pixel emitting light of a first color (e.g., red), a green sub-pixel emitting light of a second color (e.g., green), and a blue sub-pixel emitting light of a third color (e.g., blue).

[0073] Figure 2 FIG. is an example illustrating a configuration of one frame.

[0074] Referring to Figure 1 and Figure 2 , the display apparatus 100 can be driven according to consecutive frames, and each frame period can include an active data period and a vertical blanking period. The active data period and the vertical blanking period can be configured in units of horizontal line periods.

[0075] According to some example embodiments, the timing controller 110 can transmit image data embedded with a clock signal to the data driver 120.

[0076] When the frame control signal SFC is at a low level, the clock signal of the transmitter 200 and the receiver 300 can be synchronized. For example, when the frame control signal SFC is at a low level, the CDR circuit of the receiver 300 can be synchronized (i.e., phase-locked) with the clock signal of the transmitter 200 by recovering a reference clock.

[0077] When the frame control signal SFC is at a high level, each horizontal line period can be composed of a start line period SOL, a configuration period Configuration (or CONFIG), an image data period RGB Pixel Data, and a horizontal blanking period HBP.

[0078] Figure 3 is a diagram illustrating an interface system according to some example embodiments of the present application.

[0079] According to some example embodiments, the interface system ITF can be a USI-T interface module.

[0080] Referring to Figure 3 , the interface system ITF can include the transmitter 200 and the receiver 300 connected to a transmission line.

[0081] According to some example embodiments, the transmitter 200 can be included in the timing controller 110 (refer to Figure 1 ), and the receiver 300 can be included in the data driver 120 (refer to Figure 1 ).

[0082] The transmitter 200 can communicate with the receiver 300 in a differential signal method. That is, the transmission line can include a first transmission line TLP for transmitting a signal of a first phase and a second transmission line TLN for transmitting a signal of a second phase different from the first phase. The transmitter 200 can transmit a data signal through the first transmission line TLP and the second transmission line TLN.

[0083] According to some example embodiments, the first phase and the second phase can be opposite to each other.

[0084] Each of the first transmission line TLP and the second transmission line TLN can include at least one junction capacitor CC. Although four junction capacitors CC are illustrated in Figure 3 , embodiments according to the present application are not limited thereto.

[0085] The coupling capacitor CC can be connected in series to each of the first transmission line TLP and the second transmission line TLN. The coupling capacitor CC can minimize a DC component of a data signal transmitted through the first transmission line TLP and the second transmission line TLN. Accordingly, the transmitter 200 can stably communicate with the receiver 300 even when a specification of each of the transmitter 200 and the receiver 300 is different.

[0086] The transmitter 200 can transmit a reset signal BEN, a frame control signal SFC, and a lock start signal LSS to the receiver 300.

[0087] In addition, according to some example embodiments, a data signal having a worst pattern can be transmitted to the receiver 300 when the transmitter 200 is powered on. In addition, the transmitter 200 can transmit the lock start signal LSS to the receiver 300 while a data signal is being transmitted.

[0088] The worst pattern can be any one of a white pattern and a black pattern.

[0089] The receiver 300 can reset a common mode voltage of the first transmission line TLP and the second transmission line TLN according to the reset signal BEN.

[0090] In addition, the receiver 300 can transmit a lock fault signal LFS to the transmitter 200.

[0091] Figure 4 is a diagram schematically illustrating a structure of the first transmission line and the second transmission line illustrated in Figure 3 .

[0092] In this specification, a common mode voltage (VICM; input common mode voltage) and a differential voltage (VID; input differential voltage) (refer to Figure 5 ) can refer to a voltage used as a standard for determining a bit value. For example, when the common mode voltage VICM of the first transmission line TLP is 1V and the differential voltage VID of the first transmission line TLP is 0.5V, 1V can refer to a first bit value (e.g., 1) and 0.5V can refer to a second bit value (e.g., 2).

[0093] Accordingly, the common mode voltage VICM and the differential voltage VID can be important in communication between the transmitter 200 and the receiver 300. However, the common mode voltage VICM can change.

[0094] Referring to Figure 3 and Figure 4 , the first transmission line TLP and the second transmission line TLN can include a coupling capacitor CC and a receiver resistor TR connected between a transmitter node NTX and a receiver node NRX. For ease of description, in Figure 4Only one coupling capacitor CC is shown, but embodiments according to the present application are not limited thereto.

[0095] Specifically, the coupling capacitor CC can be connected between the first node N1 and the transmitter node NTX, and the receiver resistor TR can be connected between the first node N1 and the receiver node NRX. In this case, the voltage of the first node N1 can represent the common mode voltage VICM.

[0096] Accordingly, the common mode voltage VICM can be calculated according to Equation 1 below.

[0097] [Equation 1]

[0098] VICM = (VTX - VRX) * (Z2) / (Z1 + Z2)

[0099] Here, VICM denotes the common mode voltage, VTX denotes the voltage of the transmitter node NTX, VRX denotes the voltage of the receiver node NRX, Z1 denotes the impedance of the coupling capacitor CC, and Z2 denotes the impedance of the receiver resistor TR.

[0100] Accordingly, when the frequency value of the data signal increases (i.e., when the high level value and the low level value included in the data signal coincide), the common mode voltage VICM can converge to 0.

[0101] However, when the frequency value of the data signal decreases (i.e., when the high level value and the low level value included in the data signal do not coincide), the common mode voltage VICM can increase or decrease.

[0102] When the common mode voltage VICM increases or decreases, the CDR circuit of the receiver 300 can fail to synchronize (i.e., lock) with the data and clock signals of the transmitter 200. In the present specification, this phenomenon is defined as a balance failure.

[0103] Figure 5 is a graph showing a change in the common mode voltage according to a data signal.

[0104] Referring to Figure 3 and Figure 5 For example, the image data period DP can include 10 bit periods BP. For ease of description, one data signal BS corresponding to the image data period DP is shown as including 10 bits corresponding to the bit periods BP. However, embodiments according to the present application are not limited thereto.

[0105] First, the timing chart shown on the left side shows a case in which the data signal BS has a white pattern representing a white gray scale.

[0106] In this case, the data signal BS having the white pattern can include nine high-level bits and one low-level bit (e.g., a reference bit AD). Here, the reference bit AD can refer to a bit arbitrarily set regardless of the gray scale.

[0107] When the data signal BS having the white pattern is supplied, the common-mode voltage VICM of the first transmission line TLP can rise. Conversely, the common-mode voltage VICM of the second transmission line TLN can fall.

[0108] Next, the timing chart shown on the right side illustrates a case in which the data signal BS has a black pattern representing a black gray scale.

[0109] In this case, the data signal BS having the black pattern can include one high-level bit (e.g., a reference bit AD) and nine low-level bits.

[0110] When the data signal BS having the black pattern is supplied, the common-mode voltage VICM of the first transmission line TLP can fall. Conversely, the common-mode voltage VICM of the second transmission line TLN can rise.

[0111] As Figure 5 indicated in the above, when the common-mode voltage VICM rises or falls, the CDR circuit of the receiver 300 can fail to synchronize (i.e., lock) with the data and clock signals of the transmitter 200. Accordingly, a balance failure can occur.

[0112] Figure 6 is a diagram illustrating in detail an interface system according to some example embodiments of the present application.

[0113] Referring to Figure 6 , the interface system can include the transmitter 200, the receiver 300, the first transmission line TLP, the second transmission line TLN, the combination selection circuit SC, the bias control unit 400, the balance voltage detector 500, the first bias control circuit 421, and the second bias control circuit 423.

[0114] The reception circuit connected to the receiver 300 can operate in any one of a DC combination mode and an AC combination mode according to the common-mode voltage VICM of the signals transmitted through the first transmission line TLP and the second transmission line TLN.

[0115] The combination selection circuit SC can selectively provide the signals transmitted through the first transmission line TLP and the second transmission line TLN to the first bias control circuit 421 and the second bias control circuit 423 or the receiver 300 in response to the combination control signal DC / AC COB generated from the transmitter 200. For example, when the combination control signal DC / AC COB is a first level (i.e., a high level), the combination selection circuit SC can transmit the signals to the first bias control circuit 421 and the second bias control circuit 423. When the combination control signal DC / AC COB is a second level (i.e., a low level), the combination selection circuit SC can transmit the signals as a differential signal to the receiver 300.

[0116] The combination selection circuit SC can include switches SW11, SW12, SW21, and SW22. In response to the combination control signal DC / AC COB, the switches SW11, SW12, SW21, and SW22 can allow the first transmission line TLP and the second transmission line TLN to be connected to the receiver 300 through the first bias control circuit 421 and the second bias control circuit 423, respectively, or allow the first transmission line TLP and the second transmission line TLN to be directly connected to the receiver 300.

[0117] For example, when the combination control signal DC / AC COB is the first level, the switches SW12 and SW21 can be turned on, and the switches SW11 and SW22 can be turned off. Accordingly, the AC combination operation can be performed through the combination capacitor CC connected to the first bias control circuit 421 and the second bias control circuit 423. Accordingly, even if the common mode voltage of the transmitter 200 and the common mode voltage set in the receiver 300 are different from each other, the differential signal in which the common mode voltage is adjusted by the first bias control circuit 421 and the second bias control circuit 423 can be provided to the receiver 300.

[0118] For example, when the combination control signal DC / AC COB is the second level, the switches SW11 and SW22 can be turned on, and the switches SW12 and SW21 can be turned off. Accordingly, the DC combination operation in which the signals are directly transmitted to the receiver 300 as a differential signal can be performed. When the common mode voltage of the transmitter 200 and the common mode voltage set in the receiver 300 are the same, the operations of the first bias control circuit 421 and the second bias control circuit 423 can be unnecessary.

[0119] The first bias control circuit 421 can output a first bias signal in which a voltage level of a first reception signal received through the first transmission line TLP and the combination capacitor CC is increased (or decreased) by a DC bias voltage (e.g., a set or predetermined DC bias voltage) to the receiver 300. The first bias control circuit 421 can receive a common mode voltage and output a first bias common mode voltage.

[0120] The second bias control circuit 423 can output a second bias signal in which a voltage level of the second reception signal received through the second transmission line TLN and the coupling capacitor CC is increased (or decreased) by a DC bias voltage (for example, a set or predetermined DC bias voltage) to the receiver 300. The second bias control circuit 423 can receive a common mode voltage and output a second bias common mode voltage.

[0121] According to some example embodiments, the DC bias voltage set in each of the first bias control circuit 421 and the second bias control circuit 423 can be determined according to a common mode voltage set in the receiver 300. For example, when the common mode voltage set in the receiver 300 is 0.6V, the first bias control circuit 421 can increase (or decrease) the voltage level of the first reception signal by 0.6V, and the second bias control circuit 423 can increase (or decrease) the voltage level of the second reception signal by 0.6V.

[0122] According to some example embodiments, the DC bias voltage set in each of the first bias control circuit 421 and the second bias control circuit 423 can be a voltage level variable according to a control signal provided from the bias control unit 400.

[0123] The balanced voltage detector 500 can detect voltage levels of the first transmission line TLP and the second transmission line TLN. According to some example embodiments, the detection terminals of the balanced voltage detector 500 can be connected to the first transmission line TLP and the second transmission line TLN positioned adjacent to each of the input terminals of the first bias control circuit 421 and the second bias control circuit 423. However, embodiments of the present application are not limited thereto.

[0124] The balanced voltage detector 500 can include a first comparator (Comp_P) 511, a second comparator (Comp_N) 512, and switches SW31 and SW32. According to some example embodiments, the first comparator 511 and the second comparator 512 can be configured in the form of an amplifier (for example, OP-amp, operational amplifier).

[0125] According to some example embodiments, the first comparator 511 can be a positive comparator. The voltage level of the input terminal of the first bias control circuit 421 can be input to the non-inverting input terminal of the first comparator 511. The first reference voltage Ref_P provided from the outside can be input to the inverting input terminal of the first comparator 511. The first reference voltage Ref_P can be a positive voltage. A first output voltage (e.g., a set or predetermined first output voltage) DCB_P corresponding to a result value of comparing the voltage level of the input terminal of the first bias control circuit 421 and the first reference voltage Ref_P can be output through the output terminal of the first comparator 511.

[0126] According to some example embodiments, the second comparator 512 can be a negative comparator. The voltage level of the input terminal of the second bias control circuit 423 can be input to the inverting input terminal of the second comparator 512. The second reference voltage Ref_N provided from the outside can be input to the non-inverting input terminal of the second comparator 512. The second reference voltage Ref_N can be a negative voltage. A second output voltage (e.g., a set or predetermined second output voltage) DCB_N corresponding to a result value of comparing the voltage level of the input terminal of the second bias control circuit 423 and the second reference voltage Ref_N can be output through the output terminal of the second comparator 512.

[0127] The balance voltage detector 500 can include a first switch SW31 connected between the first transmission line TLP and the non-inverting input terminal of the first comparator 511, and a second switch SW32 connected between the second transmission line TLN and the inverting input terminal of the second comparator 512.

[0128] According to some example embodiments, the first switch SW31 can electrically connect or electrically disconnect the first transmission line TLP and the non-inverting input terminal of the first comparator 511 in response to the balance fault signal BFS provided from the receiver 300. For example, when the balance fault signal BFS is a first level (i.e., a high level), the first switch SW31 can be turned on to electrically connect the first transmission line TLP and the non-inverting input terminal of the first comparator 511. When the balance fault signal BFS is a second level (i.e., a low level), the first switch SW31 can be turned off to electrically disconnect the first transmission line TLP and the non-inverting input terminal of the first comparator 511.

[0129] According to some example embodiments, the second switch SW32 can electrically connect or electrically disconnect the second transmission line TLN and the inverting input terminal of the second comparator 512 in response to a balance check enable signal BCE provided from the transmitter 200. For example, when the balance check enable signal BCE is a first level (i.e., a high level), the second switch SW32 can be turned on to electrically connect the second transmission line TLN and the inverting input terminal of the second comparator 512. When the balance check enable signal BCE is a second level (i.e., a low level), the second switch SW32 can be turned off to electrically disconnect the second transmission line TLN and the inverting input terminal of the second comparator 512.

[0130] Meanwhile, in some example embodiments, the first switch SW31 and the second switch SW32 can be simultaneously turned on or turned off. In this case, the first switch SW31 and the second switch SW32 can be simultaneously turned on or turned off in response to each turn-on signal or each turn-off signal.

[0131] The bias control unit 400 can include a bias controller 410 that outputs a bias control bit BCB for controlling a DC bias voltage set in each of the first bias control circuit 421 and the second bias control circuit 423.

[0132] The bias controller 410 can receive the first output voltage DCB_P and the second output voltage DCB_N from the balance voltage detector 500 and receive the first reference voltage Ref_P and the second reference voltage Ref_N from the outside, and output the bias control bit BCB so that the first bias control circuit 421 and the second bias control circuit 423 control the DC bias voltage. The bias control bit BCB output from the bias controller 410 can be provided to the first bias control circuit 421 and the second bias control circuit 423, respectively.

[0133] The first bias control circuit 421 and the second bias control circuit 423 can control the DC bias voltage, and transmit a new common mode voltage to the receiver 300. Accordingly, a balance failure can be compensated for and minimized.

[0134] Figure 7 is a timing diagram illustrating a method of a driving interface system according to some example embodiments of the present application.

[0135] Hereinafter, a method of driving a display apparatus 100 (refer to FIG. 1) which drives a white pattern as a worst pattern will be described as an example. Figure 1 ) as an example.

[0136] Figure 7 A method of driving a driving interface system ITF when the display apparatus 100 is powered on is illustrated.

[0137] Specifically, in Figure 7In the middle, a method for measuring a balance fault time BFT of the transmitter 200 of the interface system ITF is specifically shown.

[0138] Referring to Figures 1 to 7 When the display device 100 is powered on, the driving power VDD can change from a low level to a high level.

[0139] The frame control signal SFC can have a low level when data of a training pattern is transmitted, and can have a high level in other cases.

[0140] The lock fault signal LFS can have a low level. When the display device 100 is powered on, the transmitter 200 can transmit the lock fault signal LFS to the receiver 300.

[0141] In a period in which data of a training pattern is transmitted, when locking is successful, the transmitter 200 can not transmit the lock fault signal LFS to the receiver 300.

[0142] The transmitter 200 can transmit data having a worst pattern (e.g., a white pattern or a black pattern) to the receiver 300. In Figure 7 In the middle, data White Data having a white pattern is transmitted to the receiver 300 as an example.

[0143] In this case, since a lock fault occurs, the transmitter 200 can transmit the lock fault signal LFS to the receiver 300 again.

[0144] The lock start signal LSS can have a high level. When data White Data having a white pattern is transmitted, the transmitter 200 can supply the lock start signal LSS to the receiver 300.

[0145] The receiver 300 can generate a balance fault signal BFS based on the lock start signal LSS and the lock fault signal LFS.

[0146] For example, the transmitter 200 can perform a logical AND on the lock start signal LSS and the lock fault signal LFS to generate the balance fault signal BFS. The balance fault signal BFS can be provided to the balance voltage detector 500 to turn on the first switch SW31. At the same time, the second switch SW32 can be turned on.

[0147] The balance fault time BFT can be a time from a point at which the lock start signal LSS is received to a point at which the lock fault signal LFS is received.

[0148] To identify the common mode voltage that can be problematic if a lock fault and to detect the balance fault time BFT, a first reference voltage Ref_P at a low level and a second reference voltage Ref_N at a high level can be externally provided.

[0149] Figure 8 is a timing diagram illustrating a method of driving an interface system according to some example embodiments of the present application. Figure 9 is a conceptual diagram of an interface system for explaining Figure 8 some periods. Figure 10 is a timing diagram illustrating a method of driving an interface system according to some example embodiments of the present application.

[0150] Figure 8 A method of driving an interface system ITF is illustrated when the display device 100 (refer to Figure 1 ) is generally (in real time) operated.

[0151] Referring to Figures 7 to 10 , according to some example embodiments, the transmitter 200 can transmit a balance check enable signal BCE for turning on a switch of the balance voltage detector 500 in each period CBP. A period for providing the balance check enable signal BCE using each period CBP described above is referred to as a compensation period CP.

[0152] In each compensation period CP, a voltage of a reference power source GND (for example, a ground voltage) can be supplied in an image data period RGB Pixel Data.

[0153] In the compensation period CP, the data signal BS can include a low level bit (for example, a reference bit AD) and a middle level bit.

[0154] Stopping data transmission in the compensation period CP, the balance voltage detector 500 can receive voltage levels of each input terminal of the first bias control circuit 421 and the second bias control circuit 423 and detect a common mode voltage VICM through the first comparator 511 and the second comparator 512.

[0155] According to some example embodiments, the first comparator 511 can compare the first reference voltage Ref_P with a voltage level of the first transmission line TLP at each compensation period CP. When the voltage level of the first transmission line TLP (i.e., the common mode voltage VICM) is equal to or greater than the first reference voltage Ref_P, the bias controller 410 can output a bias control bit BCB for causing the first bias control circuit 421 to decrease the common mode voltage by a DC bias voltage (e.g., a set or predetermined DC bias voltage) to the first bias control circuit 421 at each compensation period CP. The first bias control circuit 421 can output the first bias common mode voltage decreased by the DC bias voltage (e.g., the set or predetermined DC bias voltage) to the receiver 300.

[0156] According to some example embodiments, the second comparator 512 can compare the second reference voltage Ref_N with a voltage level of the second transmission line TLN at each compensation period CP. When the voltage level of the second transmission line TLN (i.e., the common mode voltage VICM) is equal to or less than the second reference voltage Ref_N, the bias controller 410 can output a bias control bit BCB for causing the second bias control circuit 423 to increase the common mode voltage by a DC bias voltage (e.g., a set or predetermined DC bias voltage) to the second bias control circuit 423 at each compensation period CP. The second bias control circuit 423 can output the second bias common mode voltage increased by the DC bias voltage (e.g., the set or predetermined DC bias voltage) to the receiver 300.

[0157] As described above, the bias control unit 400 can generate the bias control bit BCB using the first output voltage DCB_P and the second output voltage DCB_N output through the first comparator 511 and the second comparator 512 and the first reference voltage Ref_P and the second reference voltage Ref_N, and provide the bias control bit BCB to the first bias control circuit 421 and the second bias control circuit 423 to generate a new common mode voltage VICM.

[0158] As described above, when the common mode voltage of the first transmission line TLP and the second transmission line TLN is increased or decreased and then becomes higher or lower than a certain reference level, the first bias control circuit 421 and the second bias control circuit 423 can provide the first bias common mode voltage and the second bias common mode voltage, respectively, to the receiver 300. Accordingly, it is possible to compensate for and minimize the balance failure due to the increase or decrease of the common mode voltage of the first transmission line TLP and the second transmission line TLN.

[0159] The interface system according to an embodiment of the present application and a display device including the same can compensate for and minimize a balance failure due to an increase or decrease in a common mode voltage.

[0160] Effects according to embodiments are not limited by what has been described above, and include more various effects in the present specification.

[0161] As described above, example embodiments of the present application have been described with reference to the accompanying drawings. It will be appreciated by persons skilled in the art that various modifications and equivalent embodiments can be made to the embodiments according to the present application without changing the technical spirit or scope of the embodiments according to the present application. Therefore, it will be understood that the example embodiments as described above have been disclosed only for illustrative purposes and are not intended to limit the scope of the application.

Claims

1. An interface system comprising: a receiver; a transmitter configured to transmit a signal including a common mode voltage to the receiver through a transmission line; and a plurality of bias circuits configured to adjust the common mode voltage of the signal, wherein the plurality of bias circuits are configured to receive a bias control bit to generate a bias common mode voltage, and wherein the interface system further comprises a balanced voltage detector configured to detect a voltage of the transmission line at each compensation period having periodicity. 2.The interface system of claim 1, wherein the balanced voltage detector comprises a plurality of comparators configured to compare the voltage of the transmission line with a reference voltage inputted from outside.

3. The interface system of claim 2, wherein, the plurality of comparators comprises: a first comparator configured to compare a voltage of one of the transmission lines with a first reference voltage inputted from outside as a positive voltage; and a second comparator configured to compare a voltage of another of the transmission lines with a second reference voltage inputted from outside as a negative voltage, wherein the first comparator and the second comparator are amplifiers, wherein a voltage of a first transmission line as the one of the transmission lines is inputted to a non-inverting terminal of the first comparator, and the first reference voltage is inputted to an inverting terminal of the first comparator, and wherein a voltage of a second transmission line as the other of the transmission lines is inputted to an inverting terminal of the second comparator, and the second reference voltage is inputted to a non-inverting terminal of the second comparator. 4.The interface system of claim 3, further comprising: a first switch connecting the non-inverting terminal of the first comparator and the first transmission line; and a second switch connecting the inverting terminal of the second comparator and the second transmission line, wherein the first switch is configured to be turned on in response to a balanced fault signal provided from the receiver, and wherein the second switch is configured to be turned on in response to a balanced check enable signal provided from the transmitter. 5.The interface system of claim 2, further comprising: a bias control unit configured to receive a voltage outputted from the balanced voltage detector and a reference voltage inputted from outside to control the plurality of bias circuits, and wherein the bias control unit comprises a bias controller configured to control the plurality of bias circuits to generate the bias common mode voltage. 6.The interface system of claim 2, the compensation period is included in a period in which image data is transmitted. wherein the transmission line comprises a first transmission line configured to transmit a signal of a first phase, and a second transmission line configured to transmit a signal of a second phase different from the first phase.

7. The interface system of claim 1, wherein, 8.The interface system of claim 1, further comprising: a combination selection circuit configured to selectively provide a signal transmitted through the transmission line to the plurality of bias circuits or the receiver in response to a combination control signal generated from the transmitter. ​ 9. The interface system of claim 1, wherein, The signal transmitted to the receiver is increased or decreased, and then the increased or decreased signal is decreased or increased by a predetermined voltage or higher voltage.

10. A display device comprising: a pixel unit including a plurality of pixels; a data driver configured to provide a data signal to the plurality of pixels, and including a receiver; a timing controller including a transmitter configured to transmit a signal including a common mode voltage to the receiver through a transmission line; a plurality of bias circuits configured to adjust the common mode voltage of the signal, wherein the plurality of bias circuits are configured to receive a bias control bit to generate a bias common mode voltage, and a balanced voltage detector configured to detect a voltage of the signal including the common mode voltage of the transmission line, wherein the balanced voltage detector is configured to detect the voltage at each compensation period having periodicity.

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