Data driving device and data processing device operating in low power mode

Abstract

The present invention relates to a data driving device and a data processing device operating in a low power mode. The data driving device and the data processing device can reduce the amount of power consumed by standing by for data transmission or data reception in the low power mode.

Description

Technical Field

[0001] The present invention relates to a data driving device and a data processing device operating in a low power mode. Background Art

[0002] The display device may include a panel and a panel driving device for driving the panel. The panel may include a plurality of pixels, the plurality of pixels being arranged side by side with each other in vertical and horizontal directions to form a matrix, and the plurality of pixels being arranged may be positioned on the panel like a matrix.

[0003] The panel driver can drive the pixels of the panel. The panel driver can include a data driver and a data processing device. The data driver can determine a data voltage based on image data and apply the data voltage to the pixels to drive the panel. The data processing device can receive image data from a host, process the image data so that the data driver can determine the data voltage, and transmit the processed image data to the data driver. The image data is transmitted as a digital value, and the data driver can convert the image data into an analog voltage to drive each pixel.

[0004] Image data can be transmitted from a data processing device to a data driving device. Here, the data processing device can be a transmitting end, and the data driving device can be a receiving end. Here, in order to receive image data, the data driving device, as the receiving end, may always be operating to receive signals. That is, because the data driving device needs to be on standby to receive image data, the data driving device may always consume power. This may cause the receiving end to consume power. Similarly, in order to send image data, the data processing device, as the transmitting end, may always be operating to send signals. That is, because the data processing device needs to be on standby to send image data, the data processing device may always consume power. This may cause the transmitting end to consume power.

[0005] Therefore, the embodiment will provide a technology associated with an operating method for reducing the amount of power consumed by a data driving device as a receiving end and a data processing device as a transmitting end. Summary of the Invention

[0006] In this context, an aspect of an embodiment is to provide a data driving device that stands by in a low power mode for data reception and a data processing device that stands by in a low power mode for data transmission.

[0007] Another aspect of the embodiment is to provide a data driving device and a data processing device that enter a low power mode or a normal mode according to a wake-up on signal or a wake-up off signal.

[0008] According to one aspect of the present invention, a data driving device for receiving data may include: a control circuit, which is configured to operate in a low-power mode while not receiving data, enter a normal mode to receive data, and enter the low-power mode again when the reception of data is completed; a training circuit, which is configured to train a signal including a test clock in the normal mode; and a receiving circuit, which is configured to receive data when the training is completed.

[0009] In this device, the control circuit can maintain the low power mode while not receiving data, can enter the normal mode when starting to receive data, can maintain the normal mode until the reception of data is completed, and can enter the low power mode again when the reception of data is completed.

[0010] In this device, the training circuit may generate a lock-on signal indicating completion of training of the test clock or a lock-off signal indicating unlocking, and perform training again when the lock-off signal is generated.

[0011] In this device, the control circuit may enter the low power mode upon receiving a wake-up on signal while not receiving data, and may enter the normal mode from the low power mode upon receiving a wake-up off signal.

[0012] In the apparatus, the wake-up on signal and the wake-up off signal may include a plurality of logic levels different from each other and may be transmitted in a single communication line, and the data may be a clock-embedded differential signal and may be transmitted via a plurality of communication lines.

[0013] In this device, the receiving circuit may communicate in a differential manner via two communication lines in the normal mode, and may receive a logic level signal via one of the two communication lines in the low power mode.

[0014] In this device, the receiving circuit can receive the embedded clock via the two communication lines in the normal mode, the receiving circuit can include a clock recovery circuit for recovering the embedded clock, and the receiving circuit can use low power to drive the clock recovery circuit in the low power mode.

[0015] In this device, when data corresponding to one frame is received in the normal mode, the control circuit can determine that data reception is complete and can re-enter the low-power mode. According to another aspect of the present invention, a data processing device for transmitting data may include: a control circuit configured to operate in the low-power mode while not transmitting data, enter the normal mode to transmit data, and re-enter the low-power mode when data transmission is complete; a receiving circuit configured to receive a training result including a test clock signal in the normal mode; and a transmitting circuit configured to transmit data in the normal mode.

[0016] In this device, the control circuit can maintain the low power mode while not sending data, can enter the normal mode when starting to send data, can maintain the normal mode until the sending of data is completed, and can enter the low power mode again when the sending of data is completed.

[0017] In this device, the transmitting circuit may perform communication according to a differential scheme via two communication lines in the normal mode, and may transmit a logic level signal via one of the two communication lines in the low power mode.

[0018] In this device, the control circuit may enter the low power mode upon receiving a wake-up on signal while not transmitting data, and may enter the normal mode from the low power mode upon receiving a wake-up off signal.

[0019] In the apparatus, the wake-up on signal and the wake-up off signal may include a plurality of logic levels different from each other and may be transmitted via a single communication line, and the data may be a clock-embedded differential signal and may be transmitted via a plurality of communication lines.

[0020] In the device, the transmitting circuit may transmit a signal for enabling or disabling a low power mode of the data driving device.

[0021] In the apparatus, the training result may include a lock-on signal indicating completion of training of the test clock or a lock-off signal indicating unlocking, and in a case where the training result includes the lock-off signal, the receiving circuit may receive the training result again.

[0022] According to the above-described embodiments, the data driving device and the data processing device can standby in the low power mode for data transmission or data reception, and the amount of consumed power can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a diagram showing a structure of a display device according to an embodiment;

[0024] Figure 2 is a diagram showing the structure of a data driving device and a data processing device according to an embodiment;

[0025] Figure 3 is a state diagram illustrating the operation of the data driving apparatus according to the embodiment;

[0026] Figure 4 is a flowchart illustrating the operation of the data driving apparatus according to the embodiment;

[0027] Figure 5 is a state diagram illustrating the operation of a data processing apparatus according to an embodiment;

[0028] Figure 6 is a flowchart illustrating the operation of the data processing apparatus according to the embodiment; and

[0029] Figure 7 is a diagram illustrating signals transmitted or received between a data driving device and a data processing device according to an embodiment. DETAILED DESCRIPTION

[0030] Figure 1 is a diagram showing a structure of a display device according to an embodiment.

[0031] refer to Figure 1 The display device 100 may include a panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140.

[0032] In the panel 110, a plurality of data lines (DL) and a plurality of gate lines (GL) may be provided, and a plurality of pixels may be provided. A pixel may include a plurality of sub-pixels. Here, the sub-pixels may be red (R), green (G), blue (B), and white (W), etc. A single pixel may include RGB sub-pixels (SP), RGBG SP, or RGBW SP, etc. Hereinafter, for ease of description, it is shown that a single pixel includes RGB sub-pixels.

[0033] The data driving device 120 , the gate driving device 130 , and the data processing device 140 may be devices that generate signals to display an image on the panel 110 .

[0034] The gate driving device 130 can supply a gate driving signal of a turn-on voltage or a turn-off voltage to the gate line (GL). If the gate driving signal of the turn-on voltage is supplied to the sub-pixel (SP), the sub-pixel (SP) is connected to the data line (DL). If the gate driving signal of the turn-off voltage is supplied to the sub-pixel (SP), the connection between the sub-pixel (SP) and the data line (DL) is disconnected. The gate driving device 130 can be referred to as a gate driver.

[0035] The data driving device 120 may supply a data voltage (Vdata) to the sub-pixel (SP) via the data line (DL). The data voltage (Vdata) supplied via the data line (DL) may be supplied to the sub-pixel (SP) according to a gate driving signal. The data driving device 120 may be referred to as a source driver.

[0036] The data driving device 120 can generate a plurality of gamma voltages and can output a data voltage (Vdata) corresponding to the image data (RGB) among the plurality of gamma voltages. The data driving device 120 may include a digital-to-analog converter and a buffer. In response to the image data (RGB), the digital-to-analog converter may select one of the plurality of gamma voltages and may output the selected one voltage to the buffer. The buffer may amplify the selected one voltage and may provide the data voltage (Vdata) to the sub-pixel (SP) via the data line (DL). The data driving device 120 may include at least one integrated circuit, and the at least one integrated circuit may be connected to the bonding pad of the panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type according to the embodiment, may be directly provided on the panel 110, or may be integrated with the panel 110. In addition, the data driving device 120 may be implemented in a chip on film (COF) type.

[0037] The data processing device 140 can supply control signals to the gate driver 130 and the data driver 120. For example, the data processing device 140 can send a gate control signal (GCS) that enables scanning to the gate driver 130. The data processing device 140 can output image data to the data driver 120. In addition, the data processing device 140 can send a data control signal for controlling the data driver 120 to supply a data voltage (Vdata) to each sub-pixel (SP). The data processing device 140 can be referred to as a timing control circuit.

[0038] Figure 2 is a diagram showing the structure of a data driving device and a data processing device according to an embodiment.

[0039] refer to Figure 2The data driving device 120 may include a training circuit 221 , a control circuit 222 , a receiving circuit 223 and a transmitting circuit 224 .

[0040] The control circuit 222 of the data driving device 120 can operate in a low-power mode while not receiving image data. Subsequently, the control circuit 222 can enter a normal mode from the low-power mode to receive image data. When the reception of the image data is completed, the control circuit 222 can enter the low-power mode again. Upon receiving a wake-up on signal, the control circuit 222 can enter a low-power mode from an off mode. Upon receiving a wake-up off signal, the control circuit 222 can enter a normal mode from a low-power mode. Here, the off mode can be a state in which power is not supplied to the data driving device 120 and the data driving device 120 is turned off, or it can be a state in which only power is supplied to enable the minimum operation of the data driving device 120 before high-speed image data is received.

[0041] The wake-up on signal can enable the data driving device 120 in the off mode to operate in the low power mode. The wake-up off signal can enable the data driving device 120 in the low power mode to operate in the normal mode. The wake-up on signal and the wake-up off signal can be different logic level signals, for example, a high-level signal with a high voltage or a low-level signal with a low voltage. The wake-up on signal and the wake-up off signal can be transmitted via a single communication line.

[0042] Logic level signals may be transmitted or received via, for example, complementary metal oxide semiconductor (CMOS) or transistor-to-transistor logic (TTL) circuits.

[0043] During the period when a logic level signal is being transmitted or received, a clock for reading a signal may not be transmitted or received. A wake-up start signal and a wake-up stop signal for the data driver 120 may be generated by the data processing device 140 and may be transmitted to the data driver 120. The receiving circuit 223 of the data driver 120 may receive the wake-up start signal and the wake-up stop signal from the data processing device 140.

[0044] In addition, when all image data corresponding to one frame is received in the normal mode, the control circuit 222 may determine that data reception is complete. In addition, the control circuit 222 may enter the low power mode again.

[0045] As described above, the control circuit 222 can operate in low-power mode while not receiving image data, can enter normal mode when image data reception begins, and can maintain normal mode until image data reception is complete. For example, the control circuit 222 can maintain normal mode from the start of training until image data reception is complete. Alternatively, the control circuit 222 can re-enter low-power mode only after image data reception is complete.

[0046] The training circuit 221 can train a signal including a test clock in a normal mode. The data driver 120 can receive a clock-embedded image signal corresponding to image data. Before starting to receive image data, the training circuit 221 can identify whether the clock embedded for the test is normally extracted during the training process.

[0047] The training circuit 221 may generate a lock-on signal when the training circuit 221 completes the training associated with the test clock, or may generate a lock-off signal indicating unlocking. If the training circuit 221 generates the lock-off signal, the training circuit 221 may perform training again.

[0048] The receiving circuit 223 may receive the image data. Specifically, the receiving circuit 223 may receive the image data when the training associated with the test clock is completed.

[0049] The transmission circuit 224 may transmit the training result to the reception circuit 243 of the data processing device 140. The training result may include a lock-on signal indicating completion of training associated with the test clock or a lock-off signal indicating unlocking.

[0050] The data processing device 140 may include a control circuit 241 , a transmitting circuit 242 , and a receiving circuit 243 .

[0051] The control circuit 241 of the data processing device 140 may operate in the low power mode while not transmitting image data. Subsequently, the control circuit 241 may enter the normal mode to transmit image data. When the transmission of the image data is completed, the control circuit 241 may enter the low power mode again.

[0052] When the wake-up on signal is received, the control circuit 222 can enter the low-power mode from the off mode. When the wake-up off signal is received, the control circuit 222 can enter the normal mode from the low-power mode. Here, the off mode can be a state in which power is not supplied to the data processing device 140 and the data processing device 140 is off, or a state in which only power is supplied to enable the minimum operation of the data processing device 140 before high-speed image data transmission.

[0053] The wake-up on signal can enable the data processing device 140 in the shutdown mode to operate in the low-power mode. The wake-up off signal can enable the data processing device 140 in the low-power mode to operate in the normal mode. The wake-up on signal and the wake-up off signal can be signals of different logic levels, for example, a high-level signal with a high voltage or a low-level signal with a low voltage. The wake-up on signal and the wake-up off signal can be transmitted via a single communication line.

[0054] The wake-up on signal and the wake-up off signal for the data processing device 140 may be generated by the control circuit 241 or may be received from an external circuit (eg, a host).

[0055] As described above, the control circuit 241 can operate in low-power mode while not transmitting image data, can enter normal mode when image data transmission begins, and can maintain normal mode until image data transmission is completed. For example, the control circuit 222 can maintain normal mode from the start of receiving training results until image data transmission is completed. Alternatively, the control circuit 222 can re-enter low-power mode only after image data transmission is completed.

[0056] The receiving circuit 243 may receive a training result associated with a signal including a test clock from the transmitting circuit 224 of the data driving device 120 in the normal mode. The training result may include a lock-on signal indicating completion of training associated with the test clock or a lock-off signal indicating unlocking. If the training result includes the lock-off signal, the receiving circuit 223 may receive the training result again.

[0057] The transmitting circuit 242 may transmit image data in a normal mode and may transmit a wake-up on signal and a wake-up off signal for the data driving device 120 to the receiving circuit 223 of the data driving device 120 .

[0058] In addition, the transmitting circuit 242 may transmit a signal that enables or disables the low power mode of the data driving device 120. The enable signal or the disable signal may be transmitted to the data driving device 120 together with the image data including the embedded clock.

[0059] When comparing the image signal and the logic level signal, the image signal may be transmitted or received via two communication lines according to a differential scheme, and the logic level signal may be transmitted or received via one of the two communication lines.

[0060] When compared to logic level signals, image signals can be sent or received at high speeds, can have relatively low signal levels, and may require sending or receiving a clock for reading data. Conversely, logic level signals can be sent or received at low speeds, can have relatively high signal levels, and may not require sending or receiving a clock for reading data.

[0061] The clock may be transmitted by being embedded in the image signal, and the receiving circuit 243 of the data driving device 120 may include a clock recovery circuit for recovering the embedded clock. The data driving device 120 may drive the clock recovery circuit in a normal mode, and may drive the clock recovery circuit using low power (e.g., by blocking the driving power of the clock recovery circuit) in a low power mode.

[0062] In case of changing the low power mode to the normal mode, clock training needs to be performed again, and therefore, a test clock may be sent in the initial stage of the normal mode.

[0063] Figure 3 is a state diagram illustrating the operation of the data driving apparatus according to the embodiment.

[0064] refer to Figure 3 , the data driving device can operate in each of an off mode, a low power mode, and a normal mode.

[0065] If a wake-up on signal is transmitted in a single communication line in the shut-down mode, the data driving device in the shut-down mode may enter a low power mode (wake-up on).

[0066] The data driving device may always stand by in a low power mode (low power state) while not receiving image data.

[0067] If a wake-up off signal is transmitted in a single communication line in a low power mode, the data driving device in the low power mode may enter a normal mode (wake-up off).

[0068] If the data driver enters normal mode, the data driver can be trained (Training state). If the training result corresponds to Lock On, the data driver can be ready to receive image data. The image data can be a clock-embedded differential signal (RX Lock = H). The data driver can standby to receive image data (Ready state).

[0069] If unlocking is performed while the data driving device is on standby to receive image data, the data driving device may be trained again (RX Lock=L).

[0070] The data driving device may set an internal register to receive image data (CTRS detected). If the data driving device receives image data corresponding to one row (end of row), the data driving device may stand by to receive subsequent image data.

[0071] If it is determined that the data driving device has completely received the image data (end detection), the data driving device may terminate the reception of the image data (end state).

[0072] If unlocking is performed while the data driving device terminates reception of image data, the data driving device can perform training again (RX Lock=L).

[0073] If the image data is all received until the last line of one frame (end of frame), the data driving device may enter the low power mode (low power state) again.

[0074] Figure 4 is a flowchart illustrating the operation of the data driving apparatus according to the embodiment.

[0075] refer to Figure 4 , in operation S402, the data driving device may operate in a low power mode while not receiving image data.

[0076] In operation S404 , the data driving device in the low power mode may enter a normal mode to receive image data.

[0077] In operation S406 , the data driving device may perform training of a signal including a test clock in a normal mode.

[0078] When the training is completed, the data driving device may receive image data from the data processing device in operation S408 .

[0079] In operation S410, the data driving device may determine whether to unlock while receiving image data. If unlocking is performed in operation S410 (Yes), the data driving device may perform training again. If unlocking is not performed in operation S410 and the locked state continues (No), the data driving device may continue to receive image data.

[0080] In operation S412, the data driving device may determine whether the reception of the image data is complete. If the data driving device has completely received the image data in operation S412 (Yes), the data driving device may enter the low power mode again and reduce the amount of power consumed. If the reception of the image data is not complete in operation S412 (No), the data driving device may continue to receive the image data in operation S414. Figure 5 is a state diagram illustrating the operation of the data processing apparatus according to the embodiment.

[0081] refer to Figure 5 , the data processing apparatus can operate in each of a shutdown mode, a low power mode, and a normal mode.

[0082] If a wake-up on signal is transmitted in a single communication line in the shutdown mode, the data processing apparatus in the shutdown mode can enter the low power mode (wake-up on).

[0083] The data processing apparatus may always be on standby in the low power mode (low power state) while not receiving image data.

[0084] If the data processing device as the transmitting end is ready for training and the data driving device as the receiving end operates in normal mode (RX=ON / TX lock=H), the data processing device can prepare to receive training results (training status) from the data driving device.

[0085] The data processing device may receive a lock-on signal from the data driving device indicating completion of training by the data driving device. When the training is completed, the data processing device may transmit image data to the data driving device. The image data may be a clock-embedded differential signal (RX lock = H).

[0086] The data processing device may continue to send the image data (data state). When the image data is completely sent, the data processing device may terminate the sending of the image data (data completion / end configuration state).

[0087] If the transmission of the image data is terminated, or the data driving device as the receiving end is turned off, the data processing device can operate in the low power mode again (data transmission completed / RX=OFF).

[0088] Figure 6 is a flowchart illustrating the operation of the data processing apparatus according to the embodiment.

[0089] refer to Figure 6 , in operation S602, the data processing apparatus may operate in a low power mode while not transmitting image data.

[0090] In operation S604 , the data processing apparatus in the low power mode may enter a normal mode to transmit image data.

[0091] In the normal mode, in operation S606 , the data processing device may receive a training result obtained by the data driving device by training a signal including a test clock.

[0092] When the training is completed, the data processing device may transmit the image data to the data driving device in operation S608 .

[0093] In operation S610, the data processing device may determine whether to unlock while transmitting the image data. The data processing device may receive a signal associated with locking from the data driving device and may determine whether to unlock. If unlocking is performed in operation S610 (Yes), the data processing device may receive the training results again. If unlocking is not performed in operation S610 and the locked state continues (No), the data processing device may continue to transmit the image data.

[0094] In operation S612, the data processing device may determine whether the transmission of the image data is complete. If the data processing device has completely transmitted the image data in operation S612 (Yes), the data processing device may enter the low power mode again and reduce the amount of power consumed. If the transmission of the image data is not complete in operation S612 (No), the data processing device may continue to transmit the image data in operation S614.

[0095] Figure 7 is a diagram illustrating signals transmitted or received between a data driving device and a data processing device according to an embodiment.

[0096] refer to Figure 7 The first format (Format_1) is associated with image data conventionally transmitted or received between a data driving device and a data processing device, and the second format (Format_2) is associated with image data transmitted or received between a data driving device and a data processing device according to an embodiment. The data processing device may transmit a signal provided in the first format (Format_1) or the second format (Format_2) to the data driving device.

[0097] Conventionally, image data may include a clock embedded therein, as shown in the first format (Format_1). The signal from the clock region (CK) to the dummy region (DM) may be referred to as a clock embedded differential signal (CEDS) (e.g., a clock embedded signal). The clock region (CK) including the clock may be located on one side of the data region (DATA). The dummy region (DM) may be located on the other side of the clock region (CK).

[0098] According to an embodiment, an enable (EN) signal and a disable (DIS) signal may be added to the CEDS signal, as shown in the second format (Format_2). The enable signal may enable the data driving device to operate in a low power mode. Conversely, the disable signal may terminate the low power mode and may enable the data driving device to operate in an off mode or a normal mode. Although the enable signal and the disable signal may include a wake-up on signal or a wake-up off signal for the data driving device, the present invention is not limited thereto, and the signals may be independent of each other and may determine the low power mode of the data driving device.

[0099] CROSS-REFERENCE TO RELATED APPLICATIONS

[0100] This application claims priority from Korean Patent Application No. 10-2020-0027178, filed on Mar. 4, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A data driving device for receiving data, the data driving device comprising: a control circuit configured to operate in a low power mode while reception of data is not being performed, enter a normal mode to receive data, and enter the low power mode again if reception of data is completed; a training circuit configured to train a signal including a test clock in the normal mode; as well as a receiving circuit configured to receive data if the training is completed, Wherein, the data driving device: In the normal mode, control is performed based on data as clock-embedded differential signals via a plurality of communication lines, and In the low power mode, control is performed based on logic levels via a single communication line, and The data as the clock embedded differential signal further includes an enable EN signal for controlling the low power mode and a disable DIS signal for controlling the normal mode.

2. The data driving device according to claim 1, wherein: The control circuit maintains the low power mode while not receiving data, enters the normal mode when starting to receive data, maintains the normal mode until data reception is completed, and enters the low power mode again when data reception is completed.

3. The data driving device according to claim 1, wherein: The training circuit generates a lock-on signal indicating completion of training of the test clock or a lock-off signal indicating unlocking, and performs training again when the lock-off signal is generated.

4. The data driving device according to claim 1, wherein: The control circuit enters the low power mode upon receiving a wake-up on signal while not receiving data, and enters the normal mode from the low power mode upon receiving a wake-up off signal.

5. The data driving device according to claim 1, wherein: The receiving circuit communicates in a differential manner via two communication lines in the normal mode, and receives a logic level signal via one of the two communication lines in the low power mode. The data driving device according to claim 5 , wherein: The receiving circuit receives an embedded clock via the two communication lines in the normal mode, includes a clock recovery circuit for recovering the embedded clock, and drives the clock recovery circuit using low power in the low power mode.

7. The data driving device according to claim 1, wherein: When data corresponding to one frame is received in the normal mode, the control circuit determines that data reception is completed and enters the low power mode again.

8. A data processing device for sending data, the data processing device comprising: a control circuit configured to operate in a low power mode while transmission of data is not in progress, enter a normal mode to transmit data, and re-enter the low power mode upon completion of transmission of data; a receiving circuit configured to receive a training result including a signal of a test clock in the normal mode; as well as a transmitting circuit configured to transmit data in the normal mode, Wherein, the data processing device: In the normal mode, control is performed based on data as clock-embedded differential signals via a plurality of communication lines, and In the low power mode, control is performed based on logic levels via a single communication line, and The data as the clock embedded differential signal further includes an enable EN signal for controlling the low power mode and a disable DIS signal for controlling the normal mode.

9. The data processing apparatus according to claim 8, wherein: The control circuit maintains the low power mode while not transmitting data, enters the normal mode when starting data transmission, maintains the normal mode until data transmission is completed, and enters the low power mode again when data transmission is completed.

10. The data processing apparatus according to claim 8, wherein: The transmitting circuit communicates in a differential manner via two communication lines in the normal mode, and transmits a logic level signal via one of the two communication lines in the low power mode.

11. The data processing apparatus according to claim 8, wherein: The control circuit enters the low power mode upon receiving a wake-up on signal while not transmitting data, and enters the normal mode from the low power mode upon receiving a wake-up off signal.

12. The data processing apparatus according to claim 8, wherein: The training result includes a lock-on signal indicating completion of training of the test clock or a lock-off signal indicating unlocking, and Wherein, in a case where the training result includes the lock-off signal, the receiving circuit receives the training result again.

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