Processing input / output store instructions

Abstract

A data processing system (210) and method for processing input / output store instructions (30) include a system nest (18) communicatively coupled to at least one input / output bus (22) via an input / output bus controller (20). The data processing system (210) further includes at least a data processing unit (216), which includes a kernel (12), system firmware (10), and an asynchronous kernel-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load data from at least one external device (214) communicatively coupled to the input / output bus (22) and / or store data to the at least one external device. The data processing unit (216) is configured to complete the input / output store instruction (30) before the execution of the input / output store instruction (30) in the system nest (18) is completed.

Description

Technical Field

[0001] This invention relates generally to data processing systems, and more specifically to methods for processing input / output stored instructions for external devices, as well as computer program products and data processing systems. Background Technology

[0002] A computing environment may include one or more types of input / output devices, including different types of adapters. One type of adapter is a Peripheral Component Interconnect (PCI) or Fast Peripheral Component Interconnect (PCIe) adapter. This adapter includes one or more address spaces for transferring data between the adapter and the system attached to the adapter.

[0003] In some systems, a portion of the address space of the central processing unit (CPU) coupled to the adapter is mapped into the adapter's address space, allowing CPU instructions that access memory to directly manipulate data in the adapter's address space.

[0004] Communication with an adapter (such as a PCI or PCIe adapter) can be facilitated by control commands specifically designed to send and receive data to and from the adapter and to facilitate communication.

[0005] In the prior art, storage instructions for storing data in an adapter include, for example, obtaining machine instructions for execution, which are defined according to a computer architecture for computer execution. These machine instructions include, for example, an opcode field identifying the store-to-adapter instruction. A first field identifies a first location including the data to be stored in the adapter. A second field identifies a second location and includes a function handle identifying the adapter, the name of the address space within the adapter where the data will be stored, and an offset within that address space. The machine instructions are executed, including using the function handle to obtain a function table entry associated with the adapter. At least one of the information in the function table entry and the offset is used to obtain the adapter's data address. Data is stored from the first location in a specific location within the address space identified by the name of the address space, which is identified by the adapter's data address.

[0006] A common feature of large multiprocessor systems is the ability to quiesce all processors within a target region. The purpose of quiescing is to temporarily halt or alter the state of a processor or group of processors to perform, for example, system updates or backups. In some instances, quiescing interrupts apply only to a subset of system resources. In such cases, the system can be partitioned into different regions. For a quiescing operation applicable to one region (the target region), processors outside the target region are allowed to continue running, although new transitions may be blocked. Typically, at least one system controller or other mechanism broadcasts quiescing to all physical processors in the system, collects quiescing status information, and either instructs the requesting processor when all processors have been started, or ignores (filters out) the quiescing request.

[0007] A silence controller can be communicatively coupled to a processor in a multiprocessor system and a silence state machine configured to receive silence requests. The computer system is configured to perform a method comprising: receiving a silence request from a requesting processor, which is one of a plurality of processors in the multiprocessor system, at the silence controller; and determining, based on the state of the silence state machine, that the silence request is not accepted. The method further comprises, based on the unaccepted request, generating a rejection message configured to indicate that the silence request has been rejected; retaining the rejection message until a silence command is broadcast to the multiprocessor system, the silence command being based on a different silence request; and, based on the silence controller detecting the broadcast of the silence command, sending a rejection message to the requesting processor. Summary of the Invention

[0008] A data processing system for processing input / output store instructions is proposed, comprising a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system further includes at least a data processing unit comprising a kernel, system firmware, and an asynchronous kernel-nested interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load data from and / or store data to at least one external device communicatively coupled to the input / output bus.

[0009] The data processing system is configured to execute: (i) an operating system running on the data processing system issues an input / output store instruction that specifies at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data; (ii) a data processing unit is configured to identify the input / output function by the address specified in the input / output store instruction; (iii) a data processing unit is configured to verify whether access to the input / output function is permitted in the address space and at the client instance level, the client running on the data processing system; (iv) a data processing unit is configured to complete the input / output store instruction before the execution of the input / output store instruction in the system nesting is completed; and (v) the system firmware is configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output store instruction.

[0010] Advantageously, the cycle count per instruction can be improved by replacing synchronous PCI instructions with reliable asynchronous instruction sending mechanisms. PCI memory instructions can be executed asynchronously through the asynchronous execution and asynchronous state handling of PCIe memory effects. Asynchronous reliable execution is based on reliable forwarding mechanisms in the microarchitecture.

[0011] A data processing system according to a first embodiment of the present invention includes instructions loaded from at least one external device of the data processing system and stored in at least one external device of the data processing system via an input / output bus. Asynchronous instructions are completed before the data is stored in the external device, while synchronous instructions are completed after the data is stored in the external device. Within the embodiments described herein, PCI will be interchangeably used with any other input / output technology, and therefore the embodiments of the invention are not limited to PCI.

[0012] Embodiments of the present invention describe the execution of input / output stored instructions in a strictly ordered manner observable from the architectural boundaries, while the actual execution within the hardware of the data processing unit (CPU) may be unordered.

[0013] According to embodiments of the present invention, PCI storage instructions can be executed asynchronously through asynchronous execution and asynchronous state processing of PCIe storage effects. Asynchronous reliable execution is based on the reliable forwarding mechanism in the microarchitecture of the data processing system of the present invention.

[0014] Existing PCI storage and block instructions are typically synchronous until the PCI storage data has been transferred to the PCIe interface and completed and returned to the processing unit.

[0015] The PCI standard only requires asynchronous transmission commands for PCI information, which is typically achieved by aggregating asynchronously transmitted data through a storage queue in the processor.

[0016] Advantageously, according to embodiments of the invention, improvements in the number of cycles per instruction can be achieved by replacing synchronous PCI instructions with reliable asynchronous transmission processing of input / output storage instructions.

[0017] As a replacement or supplement to the data to be transmitted, the storage instructions according to embodiments of the present invention may also specify a pointer to the main memory, which should be used to retrieve data from it rather than directly containing the data.

[0018] The client instance level can also mean that a single client or host can run on the data processing system.

[0019] The address of the offset of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually translated into physical addresses by the memory management unit (MMU), and then the physical address can be used to identify which function and offset are being referred to.

[0020] In this article, the physical address refers to "the lowest address in the address translation hierarchy that can be accessed from within the client / operating system".

[0021] According to an advantageous embodiment of the data processing system of the present invention, the aggregation buffer can be communicatively coupled to an asynchronous kernel-nested interface via an asynchronous bus. Thus, the aggregation buffer can continuously process data sent directly by the asynchronous kernel-nested interface until all data to be transmitted to external devices has been stored in the aggregation buffer.

[0022] According to an advantageous embodiment of the data processing system of the present invention, if the length of the source data exceeds 8 bytes, the data can be transmitted to the aggregation buffer in multiple data packets via an asynchronous transmission mechanism with early completion messages, using input / output storage instructions; otherwise, the data can be transmitted in a single data packet. This asynchronous transmission mechanism is advantageous because the transmitting device is free for reuse in earlier states.

[0023] According to an advantageous embodiment of the data processing system of the present invention, the system firmware may include asynchronous input / output driver code for processing input / output storage instructions. Thus, an asynchronous transfer mechanism can be used to transfer data from the data processing unit to an external device.

[0024] According to an advantageous embodiment of the data processing system of the present invention, the kernel may include asynchronous setup code for processing memory requests for state information of asynchronous input / output driver code. This asynchronous setup code may further facilitate asynchronous transfer mechanisms via aggregate buffers to system nesting and input / output bus controllers.

[0025] According to an advantageous embodiment of the data processing system of the present invention, the asynchronous kernel-nested interface may include an asynchronous kernel-nested interface forwarding component for forwarding locally completed data. This component may be implemented in the hardware of the asynchronous kernel-nested interface. Therefore, advantageous asynchronous transmission modes for sending data in packets to an aggregation buffer can be supported.

[0026] According to an advantageous embodiment of the data processing system of the present invention, the aggregation buffer may include early completion logic for transmitting an idle-for-reuse message after a request has been sent. This enables processing to continue earlier, via the aggregation buffer, to the system nesting and input / output bus controllers.

[0027] According to an advantageous embodiment of the data processing system of the present invention, the aggregation buffer can be communicatively coupled to an asynchronous kernel-nested interface via an asynchronous bus. In this way, an asynchronous transfer mechanism for transferring data from the asynchronous kernel-nested interface can be advantageously supported.

[0028] According to an advantageous embodiment, the data processing system of the present invention may further include an input / output status buffer that collects returned statuses from system nesting and / or from input / output bus controllers, particularly from completion messages from system nesting. This input / output status buffer collects returned statuses and acts as an asynchronous system message buffer supporting asynchronous transmission processes.

[0029] According to an advantageous embodiment of the data processing system of the present invention, the asynchronous kernel-nested interface may include an input / output state buffer. Advantageously, the input / output state buffer is directly integrated into the asynchronous kernel-nested interface for fast response.

[0030] According to an advantageous embodiment of the data processing system of the present invention, the system message may include one of the following: a hierarchical physical target address; an identifier for an SMT (Simultaneous Multithreading) thread or aggregation buffer; a data length; an input / output bus address; or a sequence number of a recovery algorithm. This ensures the advantageous transmission of relevant information through the data processing system.

[0031] Furthermore, a method is proposed for processing input / output memory instructions for at least one external device of a data processing system, the data processing system including a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system also includes at least one data processing unit comprising a kernel, system firmware, and an asynchronous kernel-nested interface. The data processing unit is communicatively coupled to the system nest via an aggregate buffer. The external device is communicatively coupled to the input / output bus.

[0032] The method includes: (i) an operating system running on a data processing system issuing an input / output store instruction that specifies at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data; (ii) a data processing unit being configured to identify the input / output function by the address specified in the input / output store instruction; (iii) a data processing unit being configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, the client running on the data processing system; (iv) a data processing unit being configured to complete the input / output store instruction before the execution of the input / output store instruction in the system nesting is completed; and (v) system firmware being configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output store instruction.

[0033] Advantageously, the cycle count per instruction can be improved by replacing synchronous PCI instructions with reliable asynchronous instruction sending mechanisms. PCI memory instructions can be executed asynchronously through the asynchronous execution and asynchronous state handling of PCIe memory effects. Asynchronous reliable execution is based on reliable forwarding mechanisms in the microarchitecture.

[0034] A method according to another embodiment of the invention includes loading and storing instructions from at least one external device of the data processing system to at least one external device of the data processing system via an input / output bus. Asynchronous instructions are completed before the data is stored on the external device, while synchronous instructions are completed after the data is stored on the external device. Within the embodiments described herein, PCI will be interchangeably used with any other input / output technology, and therefore the embodiments of the invention are not limited to PCI.

[0035] Embodiments of the method of the present invention describe the execution of input / output stored instructions in a strictly ordered manner observable from the architectural boundaries, while the actual execution within the hardware of the data processing unit (CPU) may be unordered.

[0036] According to embodiments of the method of the present invention, PCI storage instructions can be executed asynchronously through asynchronous execution of PCIe storage effects and asynchronous state processing. Asynchronous reliable execution is based on the reliable forwarding mechanism in the microarchitecture of the data processing system of the present invention.

[0037] Existing PCI storage and block instructions are typically synchronous until the PCI storage data has been transferred to the PCIe interface and completed and returned to the processing unit.

[0038] The PCI standard only requires asynchronous sending commands for PCI information, which is typically achieved by aggregating asynchronously sent data through a storage queue in the processor.

[0039] Advantageously, according to embodiments of the method of the invention, improvements in the cycle time for each instruction can be achieved by replacing synchronous PCI instructions with reliable asynchronous transmission processing of input / output storage instructions.

[0040] As a replacement or supplement to the data to be transmitted, the storage instruction according to an embodiment of the present invention may also specify a pointer to the main memory, which should be used to retrieve data from it rather than directly containing the data.

[0041] The client instance level can also mean that a single client or host can run on the data processing system.

[0042] The address of the offset of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually translated into physical addresses by the memory management unit (MMU), and then the physical address can be used to identify which function and offset are being referred to.

[0043] In this article, the physical address refers to "the lowest address in the address translation hierarchy that can be accessed from within the client / operating system".

[0044] According to an advantageous embodiment, the method may further include: (i) the operating system issuing an input / output storage instruction; (ii) depending on the length of the data: if the length of the data exceeds 8 bytes, the system firmware software repeatedly issues system messages to send data packets to the aggregation buffer until all data in the storage block has been forwarded to the aggregation buffer, the system firmware software waiting until the system message has sent the data; otherwise, the system firmware issues a system message to send the data to the aggregation buffer; further independent of the length of the data, (iii) the system firmware issues a system message to the aggregation buffer to asynchronously forward the data as a single nested message to the input / output bus controller, while waiting for the aggregation buffer to send a completion message; (iv) the aggregation buffer will send the nested message... Information is injected into the system nest, where the aggregation buffer is idle for immediate reuse after the send operation, thereby signaling back to the system firmware; then the aggregation buffer sends an idle-for-reuse message; (v) the system nest forwards the message to the target location; (vi) the input / output bus controller receives the message and forwards the data in the data frame to the input / output bus; (vii) the input / output bus controller sends a completion message to the system nest; (viii) the system nest forwards the completion message to the initiating aggregation buffer; (ix) the aggregation buffer forwards the completion message to the asynchronous kernel-nested interface; (x) the asynchronous kernel-nested interface signals the completion of the operation to the system firmware; and (xi) the system firmware asynchronously signals the defect to the operating system.

[0045] Only step (ii) is related to the length of the data, and it is different for data lengths exceeding 8 bytes compared to data lengths not exceeding 8 bytes.

[0046] According to an embodiment of the method of the present invention, data is transmitted to an aggregation buffer in the form of slices until all data of the storage block is forwarded to the aggregation buffer, wherein the system firmware waits until the data has been sent by the asynchronous kernel-nested interface.

[0047] Therefore, if the data is less than 8 bytes, the process of filling the aggregate buffer with data packets in fragments can be skipped, and the data transfer to the external device can be completed in a single step.

[0048] According to an advantageous embodiment of the method of the invention, if the length of the source data exceeds 8 bytes, the data can be transmitted to the aggregation buffer in multiple data packets via an asynchronous transmission mechanism with early completion messages, using input / output storage instructions. This asynchronous transmission mechanism is advantageous because the transmitting device is free for reuse in earlier states.

[0049] According to an advantageous embodiment of the method of the present invention, the system firmware can use asynchronous input / output driver code to process input / output storage instructions. Thus, data can be transferred from the data processing unit to external devices using an asynchronous transfer mechanism.

[0050] According to an advantageous embodiment of the method of the present invention, the kernel can use asynchronous setup code to handle memory requests for state information of asynchronous input / output driver code. This asynchronous setup code can further facilitate asynchronous transfer mechanisms to system nesting and input / output bus controllers via aggregate buffers.

[0051] According to an advantageous embodiment of the method of the present invention, the asynchronous kernel-nested interface can use the asynchronous kernel-nested interface forwarding component to forward locally completed data. Therefore, advantageous asynchronous transmission modes for sending data in packets to the aggregation buffer can be supported.

[0052] According to an advantageous embodiment of the method of the present invention, the aggregation buffer can use early completion logic to deliver an idle-for-reuse message after a send request. This enables processing of data transfer to the system nesting and I / O bus controllers via the aggregation buffer to continue earlier.

[0053] According to an advantageous embodiment of the method of the invention, input / output status buffers can collect return status from system nesting and / or from input / output bus controllers, particularly completion messages from system nesting. These input / output status buffers can collect return status, thereby acting as asynchronous system message buffers supporting asynchronous transmission processes.

[0054] According to an advantageous embodiment of the method of the present invention, the system message may include one of the following: a hierarchical physical target address; an identifier for the SMT thread or aggregate buffer; the length of the data; an input / output bus address; or a sequence number of the recovery algorithm. This ensures the advantageous transmission of relevant information through the data processing system.

[0055] Furthermore, an advantageous computer program product is proposed for processing input / output storage instructions to at least one external device of a data processing system comprising a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system also includes at least one data processing unit comprising a kernel, system firmware, and an asynchronous kernel-nested interface. The data processing unit is communicatively coupled to the system nest via an aggregate buffer. The external device is communicatively coupled to the input / output bus.

[0056] The computer program product includes a computer-readable storage medium having program instructions embodied therein, which are executable by the computer system to cause the computer system to perform a method comprising: (i) an operating system running on the data processing system issuing the input / output storage instruction, specifying at least an input / output function having an offset of an address, data to be transferred and / or a pointer to the data to be transferred, and a length of the data; (ii) the data processing unit being configured to identify the input / output function by means of the address specified in the input / output storage instruction; (iii) the data processing unit being configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, the client running on the data processing system; (iv) the data processing unit being configured to complete the input / output storage instruction before the system has completed the execution of the nested input / output storage instruction; and (v) the system firmware being configured to notify the operating system by interrupting and sending data of the failed asynchronous execution if an error is detected by the data processing unit during the asynchronous execution of the input / output storage instruction.

[0057] Furthermore, a data processing system for executing data processing procedures is proposed, the data processing system including computer-readable program instructions for executing the above methods. Attached Figure Description

[0058] The invention, as well as the above and other objects and advantages, can be best understood from the following detailed description of the embodiments, but the invention is not limited to these embodiments.

[0059] Figure 1A block diagram of a data processing system for processing input / output storage instructions for an external device, according to an embodiment of the present invention, is shown.

[0060] Figure 2 A message sequence diagram illustrating a method for processing input / output storage instructions for an external device according to an embodiment of the present invention is shown.

[0061] Figure 3 A flowchart illustrating an embodiment of the present invention for processing input / output storage instructions for an external device is shown.

[0062] Figure 4 An exemplary embodiment of a data processing system for performing the method according to the invention is shown. Detailed Implementation

[0063] In the accompanying drawings, the same elements are denoted by the same reference numerals. The drawings are merely schematic and are not intended to describe specific parameters of the invention. Furthermore, the drawings are intended to illustrate only typical embodiments of the invention and should not be considered as limiting the scope of the invention.

[0064] The illustrative embodiments described herein provide a data processing system and method for disposing of input / output storage instructions. The data processing system includes a system nest communicatively coupled to at least one input / output bus via an input / output bus controller. The data processing system further includes at least one data processing unit, which includes a kernel, system firmware, and an asynchronous kernel-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load data from and / or store data to external devices communicatively coupled to the input / output bus.

[0065] An illustrative embodiment may be used in a method comprising: (i) an operating system running on a data processing system specifying at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data; (ii) a data processing unit configured to identify the input / output function by means of an address specified in an input / output store instruction; (iii) a data processing unit configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, the client running on the data processing system; (iv) a data processing unit configured to complete the input / output store instruction before execution of said input / output store instruction is completed within said system nesting; and (v) system firmware configured to notify the operating system by interrupting and sending data of failed asynchronous execution if an error is detected by the data processing unit during asynchronous execution of the input / output store instruction.

[0066] Alternatively or additionally, for the data to be transmitted, the storage instruction according to an embodiment of the present invention may also specify a pointer that should be used to retrieve the data from the main memory, rather than directly containing the data.

[0067] The client instance level can also mean that a single client or host can run on the data processing system.

[0068] The address of the offset of the input / output function itself can be a virtual, physical, or logical address. Virtual and logical addresses are usually translated into physical addresses by the memory management unit (MMU), and then the physical address can be used to identify which function and offset are being referred to.

[0069] In the context of this specification, a physical address refers to "the lowest address in the address translation hierarchy accessible from within the client / operating system".

[0070] Figure 1 A block diagram of a data processing system 210 for processing input / output stored instructions 30 to at least one external device 214 according to an embodiment of the present invention is shown. The data processing system 210 includes a system nest 18 communicatively coupled to an input / output bus 22 via an input / output bus controller 20, and a data processing unit 216 including a kernel 12, system firmware 10, and an asynchronous kernel-nested interface 14.

[0071] Data processing unit 216 is communicatively coupled to system nest 18 via aggregation buffer 16. System nest 18 is configured to asynchronously load data from and / or store data to external device 214, which is communicatively coupled to input / output bus 22, via buffer input / output bus controller interface 28, which is part of system nest 18, and input / output bus controller 28.

[0072] Aggregate buffer 16 is communicatively coupled to asynchronous kernel-nested interface 14. System firmware 10 includes asynchronous input / output driver code 32 for processing input / output store instructions 30. Kernel 12 includes asynchronous setup code 34 for handling memory requests for status information of asynchronous input / output driver code 32. Asynchronous kernel-nested interface 14 includes asynchronous kernel-nested interface forwarding component 36 for forwarding locally completed data. Aggregate buffer 16 includes early completion logic 26 for transmitting free for reuse messages after a request is sent. Aggregate buffer 16 is coupled to asynchronous kernel-nested interface 14 via asynchronous bus 38. Input / output status buffer 24 is included, which collects return status from system nest 18 and / or from input / output bus controller 20, particularly completion messages from system nest 18. Input / output status buffer 24 is directly integrated into asynchronous kernel-nested interface 14.

[0073] According to an embodiment of the method of the present invention, an operating system running on a data processing system 210 issues an input / output store instruction 30, which specifies at least an input / output function having an offset address, data to be transferred, and / or a pointer to the data to be transferred, and the length of said data. A data processing unit 216 is thus configured to identify the input / output function by the address specified in the input / output store instruction 30. The data processing unit 216 is configured to verify whether access to the input / output function is permitted at the address space and at the client instance level, on which the client runs on the data processing system 210. The data processing unit 216 is configured to complete the input / output store instruction 30 before the completion of its execution within system nesting 18. The system firmware 10 is configured to notify the operating system by interrupting and sending data indicating failed asynchronous execution if an error is detected by the data processing unit 216 during the asynchronous execution of the input / output store instruction 30.

[0074] The input / output storage instruction 30 is located in the data processing system 210 on the side of the user interface 40, which separates the system hardware / firmware 50 from the user side 40 at the architectural boundary.

[0075] Therefore, if the length of the source data exceeds 8 bytes, the data can be transmitted to the aggregation buffer 16 in multiple data packets by the input / output storage instruction 30 through an asynchronous transmission mechanism with an early completion message; otherwise, the data can be transmitted in a single data packet.

[0076] The system messages of an embodiment of the data processing system according to the present invention include one of the following: a hierarchical physical target address; an identifier for an SMT thread or aggregate buffer; the length of the data; an input / output bus address; or the serial number of the recovery algorithm.

[0077] Figure 2 A message sequence diagram illustrating a method for processing input / output storage instructions 30 for an external device 214 according to an embodiment of the present invention is shown.

[0078] like Figure 2 As shown, the method begins with the operating system issuing an input / output store instruction 30. Then, as shown in steps S100 and S104, if the data length exceeds 8 bytes, the system firmware 10 repeatedly issues a system message to send the data packet to the aggregation buffer 16 until all data in the store block has been forwarded to the aggregation buffer 16. Meanwhile, the system firmware 10 waits until the data has been sent via a system message. In steps S102 and S106, a local completion message is sent back to the system firmware 10.

[0079] Then in step S108, the system firmware 10 sends a system message to the aggregation buffer 16 to asynchronously forward data to the input / output bus controller 20 in the form of a single nested message, while waiting for the aggregation buffer 16 to send a completion message.

[0080] Next, in step S110, the aggregation buffer 16 injects the nested message into the system nest 18, wherein the aggregation buffer 16 immediately becomes idle for reuse after the sending operation and sends a signal back to the system firmware 10. Then, the aggregation buffer 16 sends an idle for reuse message.

[0081] In step S112, system nest 18 forwards the message to the target location. Then, in step S114, input / output bus controller 20 receives the message and forwards the data in the data frame to the input / output bus. Then, in step S116, input / output bus controller 20 sends a completion message to system nest 18.

[0082] Next, in step S118, system nesting 18 forwards the completion message to the originating aggregation buffer 16. Then, in step S120, aggregation buffer 16 forwards the completion message to asynchronous kernel-nested interface 14. Finally, in step S122, asynchronous kernel-nested interface 14 sends a signal to system firmware 10 notifying that the operation is complete.

[0083] In the event of an error during data transmission, system firmware 10 asynchronously sends a signal to the operating system notifying it of the defect.

[0084] If the data to be transmitted is less than 8 bytes, skip the repeated padding of the aggregation buffer 16.

[0085] Figure 3 A flowchart illustrating the processing of input / output storage instructions 30 for an external device 214 according to an embodiment of the present invention is shown.

[0086] In step S200, the system firmware of the data processing unit starts. In step S202, the system firmware receives the input / output store block instruction.

[0087] Then, in step S204, it is checked whether more than 8 bytes need to be transferred. If so, in step S206, the kernel-nested interface fills the aggregation buffer with a message of up to 16 bytes. The system firmware waits in step S208 until a local completion message is sent in step S210, returning to step S204. If less than 8 bytes remain in the check in step S204, the process continues in step S212, where the kernel-nested interface sends an asynchronous input / output message, and then waits for the buffer response in step S216 in step S214. Then, in step S218, a completion memory block instruction is executed, and then the process ends in step S220 with the end of the system firmware.

[0088] In step S228, the asynchronous kernel-nested interface logic starts the outbound processing loop. Subsequently, in step S222, a completion message for the aggregation buffer is received, and in step S224, the data message is forwarded to the aggregation buffer. Then, in step S226, the completion message is sent back to the system firmware. In step S230, an asynchronous input / output send message is received, and then the input / output send message is forwarded to the aggregation buffer.

[0089] In step S238, the aggregation buffer logic begins the outbound processing loop, followed by receiving data in step S234 and aggregating the data in the aggregation buffer in steps S22 and S236. In step S240, the aggregation buffer also receives input / output send messages, and then forwards the data in the aggregation buffer with input / output send messages in step S242. Next, in step S244, a response message from the aggregation buffer is sent to the system firmware via the kernel-nested interface.

[0090] Now refer to Figure 4The diagram illustrates an example of a data processing system 210. Data processing system 210 is merely one example of a suitable data processing system and is not intended to impose any limitation on the scope of use or functionality of the embodiments of the invention described herein. In any case, data processing system 210 can be implemented and / or perform any of the functions described above.

[0091] Data processing system 210 includes computer system / server 212, which can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with computer system / server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the aforementioned systems or devices, etc.

[0092] Computer system / server 212 can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer system / server 212 can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules may reside on both local and remote computer system storage media, including memory storage devices.

[0093] like Figure 4 As shown, the computer system / server 212 in the data processing system 210 is illustrated in the form of a general-purpose computing device. The components of the computer system / server 212 may include, but are not limited to, one or more processors or processing units 216, system memory 228, and a bus 218 that couples the various system components, including the system memory 228, to the processor 216.

[0094] Bus 218 represents one or more of several types of bus architectures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of the various bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA (EISA) buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.

[0095] Computer system / server 212 typically includes various computer system readable media. Such media can be any available media that can be accessed by computer system / server 212, and includes volatile and non-volatile media, removable and non-removable media.

[0096] System memory 228 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 230 and / or cache memory 232. Computer system / server 212 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 234 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown, commonly referred to as "hard disk drives"). Although not shown, disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disc drives for reading and writing to removable non-volatile optical discs such as CD-ROMs, DVD-ROMs, or other optical media may be provided. In such instances, each may be connected to bus 218 via one or more data media interfaces. As will be further described and illustrated below, memory 228 may include at least one program product having a set (e.g., at least one) of program modules configured to perform embodiments of the invention.

[0097] A program / utility 240 having a set (at least one) of program modules 242, along with an operating system, one or more applications, other program modules, and program data, may be stored in memory 228 in an exemplary, rather than limiting, manner. Each of the operating system, one or more applications, other program modules, and program data, or a combination thereof, may comprise an embodiment of a networked environment. Program modules 242 typically perform the functions and / or methods of embodiments of the invention described herein.

[0098] Computer system / server 212 can also communicate with: one or more external devices 214 such as a keyboard, pointing device, or display 224; one or more devices that enable a user to interact with computer system / server 212; and / or any device that enables computer system / server 212 to communicate with one or more other computing devices (e.g., network interface card, modem, etc.). Such communication can be performed via input / output (I / O) interface 222. Furthermore, computer system / server 212 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via network adapter 220. As shown, network adapter 220 communicates with other components of computer system / server 212 via bus 218. It should be understood that, although not shown, other hardware and / or software components can be used in conjunction with computer system / server 212. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems.

[0099] The present invention can be a system, method, and / or computer program product. The computer program product may comprise a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0100] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves with instructions recorded thereon), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0101] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0102] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet provided by an Internet service provider). In some embodiments, electronic circuitry (including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs)) may execute the computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of the invention.

[0103] This document describes aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0104] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that, upon execution by the processor of the computer or other programmable data processing apparatus, the instructions create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that instructs a computer, programmable data processing apparatus, and / or other means to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0105] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other apparatus to cause a series of operational steps to be performed on the computer, other programmable apparatus or other apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other apparatus, perform the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or performs a combination of dedicated hardware and computer instructions.

[0107] Various embodiments of the invention have been described for illustrative purposes, but the above description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to the technology on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0108] Figure Labels

[0109] 10 System FW

[0110] 12 kernels

[0111] 14 Asynchronous Kernel - Nested IF

[0112] 16 Aggregation Buffer

[0113] 18 System Nesting

[0114] 20 I / O bus controller

[0115] 22 I / O bus

[0116] 24 I / O status buffer

[0117] 26. Early Completion Logic

[0118] 28 Buffer - I / O Bus Controller IF

[0119] 30 I / O storage instructions

[0120] 32 Asynchronous I / O Driver Code

[0121] 34 I / O setup codes

[0122] 36 Asynchronous forwarding

[0123] 38 Asynchronous Bus

[0124] 40 User IF 42 44 46 48

[0129] 50 System HW / FW

[0130] 210 Data Processing System

[0131] 212 Computer Systems / Servers

[0132] 214 External Devices

[0133] 216 CPU / Data Processing Unit

[0134] 218 Input / Output Bus

[0135] 220 Network Adapter

[0136] 222 Input / Output Interface

[0137] 224 monitor

[0138] 228 memory

[0139] 230 RAM

[0140] 232 Cache Memory

[0141] 234 Storage System

[0142] 240 Programs / Utilities

[0143] 242 Program Module

Claims

1. A data processing system (210) for processing an input / output store instruction (30), comprising: a system nest (18) communicatively coupled to at least one input / output bus (22) by an input / output bus controller (20), further comprising at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14), wherein the data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16), and wherein (i) an operating system running on the data processing system (210) issues the input / output store instruction (30) specifying at least an input / output function with an offset by an address, data to be transferred and / or a pointer to data to be transferred and a length of the data; (ii) the data processing unit (216) is configured to identify the input / output function by the address specified in the input / output store instruction (30); (iii) the data processing unit (216) is configured to verify whether access to the input / output function is allowed on an address space and on a guest instance level, the guest running on the data processing system (210); (iv) the data processing unit (216) is configured to complete the input / output store instruction (30) before execution of the input / output store instruction (30) in the system nest (18) is completed, the system nest (18) is configured to load data and / or store data to at least one external device (214) communicatively coupled to the input / output bus (22) asynchronously, the external device (214) being located outside the system nest (18), the aggregation buffer (16) and the data processing unit (216); (v) the system firmware (10) is configured to issue a system message to send a data packet to the aggregation buffer (16) until all data has been forwarded to the aggregation buffer (16); (vi) the system firmware (10) is configured to issue a system message to the aggregation buffer (16) to forward data in the form of a single nest message to the input / output bus controller (20) asynchronously, while waiting for the aggregation buffer (16) to send a completion message in the meantime; (vii) the data processing unit (216) is configured to receive a free-for-reuse message from the aggregation buffer (16); (viii) the system nest (18) is configured to forward the free-for-reuse message to a target location; (ix) the input / output bus controller (20) is configured to receive the free-for-reuse message and forward data in the form of data frames to an input / output bus, the input / output bus controller (20) is configured to send a completion message to the system nest (18); (x) the system nest (18) is configured to forward the completion message to the aggregation buffer (16); (xi) the aggregation buffer (16) is configured to forward the completion message to the asynchronous core-nest interface (14); (xii) the asynchronous core-nest interface (14) is configured to send an operation completion signal to the system firmware (10); (xiii) the system firmware (10) is configured to asynchronously inform the operating system by interrupting, sending failed asynchronously executed data, if an error is detected by the data processing unit (216) during the asynchronous execution of the input / output store instruction (30), including data transfer.

2. The data processing system of claim 1, the aggregation buffer (16) is communicatively coupled to the asynchronous core-nest interface (14).

3. The data processing system of claim 1 or 2, wherein, If the length of the source data exceeds 8 bytes, the data can be transferred by the input / output store instruction (30) in multiple data packets to the aggregation buffer (16) by an asynchronous transfer mechanism with early completion messages, otherwise the data is transferred in one data packet.

4. The data processing system of claim 1 or 2, the system firmware (10) comprises an asynchronous input / output driver code (32) for processing the input / output store instruction (30).

5. The data processing system of claim 4, the core (12) comprises an asynchronous setup code (34) for handling memory requirements for status information of the asynchronous input / output driver code (32).

6. The data processing system of claim 1 or 2, the asynchronous core-nest interface (14) comprises an asynchronous core-nest interface forwarding component (36) for forwarding locally completed data.

7. The data processing system of claim 1 or 2, the aggregation buffer (16) comprises an early completion logic (26) for communicating an idle-for-reuse message after sending a request.

8. The data processing system of claim 1 or 2, the aggregation buffer (16) is communicatively coupled to the asynchronous core-nest interface (14) via an asynchronous bus (38).

9. The data processing system of claim 1 or 2, further comprising an input / output status buffer (24) that collects returned status from the system nest (18) and / or from the input / output bus controller (20).

10. The data processing system of claim 9, the asynchronous core-nest interface contains the input / output status buffer (24).

11. The data processing system of claim 1 or 2, the system message comprises one of the following: - a hierarchical physical target address, - a SMT thread or aggregation buffer identifier is provided, - a length of data, - an input / output bus address, - a sequence number of a recovery algorithm.

12. A method for processing an input / output store instruction (30) directed to at least one external device (214) of a data processing system (210), the data processing system (210) comprising: a system nest (18) communicatively coupled to at least one input / output bus (22) by an input / output bus controller (20), and further comprising at least a data processing unit (216), the data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14), wherein the data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16), wherein the external device (214) is communicatively coupled to the input / output bus (22), the method comprising: (i) an operating system running on the data processing system (210) issuing the input / output store instruction (30) specifying at least an input / output function with an offset by an address, data to be transferred and / or a pointer to data to be transferred and a length of the data; (ii) the data processing unit (216) identifying the input / output function by the address specified in the input / output store instruction (30); (iii) the data processing unit (216) verifying whether access to the input / output function is allowed on an address space and on a guest instance level, the guest running on the data processing system (210); (iv) the data processing unit (216) completing the input / output store instruction (30) before execution of the input / output store instruction (30) in the system nest (18) is completed, the system nest (18) asynchronously loading data from and / or storing data to at least one external device (214) communicatively coupled to the input / output bus (22), the external device (214) being located outside the system nest (18), the aggregation buffer (16) and the data processing unit (216); (v) the system firmware (10) issuing a system message to send data packets to the aggregation buffer (16) until all data has been forwarded to the aggregation buffer (16); (vi) the system firmware (10) issuing a system message to the aggregation buffer (16) to forward data in a single nest message asynchronously to the input / output bus controller (20) while waiting for the aggregation buffer (16) to send a completion message; (vii) the data processing unit (216) receiving an idle for reuse message from the aggregation buffer (16); (viii) the system nest (18) forwarding the idle for reuse message to a target location; (ix) the input / output bus controller (20) receives the free-for-reuse message and forwards data in the form of data frames to the input / output bus, the input / output bus controller (20) being configured to send a completion message to the system nest (18); (x) the system nest (18) forwards the completion message to the aggregation buffer (16); (xi) the aggregation buffer (16) forwards the completion message to the asynchronous core-nest interface (14); (xii) the asynchronous core-nest interface (14) sends an operation completion signal to the system firmware (10); (xiii) if an error is detected by the data processing unit (216) during the asynchronous execution of the input / output store instruction (30), including during data transfer, the system firmware (10) asynchronously notifies the operating system by interrupting, sending failed data of the asynchronously executed operation.

13. The method according to claim 12, further comprising: (i) the operating system issuing the input / output store instruction (30); (ii) depending on the length of data: if the length of data exceeds 8 bytes, the system firmware (10) repeatedly issues a system message to send a data packet to the aggregation buffer (16) until all data of the store block has been forwarded to the aggregation buffer (16), while the system firmware (10) waits until data has been sent by the system message; otherwise the system firmware (10) issues the system message to send the data to the aggregation buffer (16); (iii) the aggregation buffer (16) injects the nest message into the system nest (18), wherein the aggregation buffer (16) is just freed for reuse after the sending operation, signaling back to the system firmware (10); the aggregation buffer (16) then sends a free-for-reuse message; (iv) in case of an error, the system firmware (10) signals the defect to the operating system.

14. The method according to claim 12 or 13, further, if the length of data exceeds 8 bytes, the data is transferred by the input / output store instruction (30) in multiple data packets to the aggregation buffer (16) by an asynchronous transfer mechanism with an early completion message.

15. The method according to claim 12 or 13, further, the system firmware (10) uses an asynchronous input / output driver code (32) for processing the input / output store instruction (30).

16. The method according to claim 15, further, the core (12) uses an asynchronous setup code (34) for processing memory requirements for status information of the asynchronous input / output driver code (32).

17. The method according to claim 12 or 13, further, the asynchronous core-nest interface (14) uses an asynchronous core-nest interface forwarding component (36) for forwarding locally completed data.

18. The method according to claim 12 or 13, further, the aggregation buffer (16) using early completion logic (26) for transmitting an idle for reuse message after a send request.

19. The method according to claim 12 or 13, further, an input / output status buffer (24) collecting returned status from the system nest (18) and / or from the input / output bus controller (20).

20. The method of claim 12 or 13, wherein, The system message comprises one of: - a hierarchical physical target address, - a provided SMT thread or aggregation buffer identifier, - a length of data, - an input / output bus address, - a sequence number of a recovery algorithm.

21. A computer program product for processing input / output store instructions (30) for at least one external device (214) of a data processing system (210), the data processing system (210) comprising: a system nest (18) communicatively coupled to at least one input / output bus (22) by an input / output bus controller (20), and, further, comprising at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14), wherein the data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16), wherein the external device (214) is communicatively coupled to the input / output bus (22), the computer program product comprising program instructions executable by the computer system (212) to cause the computer system (212) to perform a method as claimed in any one of claims 12-20.

22. A data processing system (210) for executing a data processing program (240), the data processing system comprising computer readable program instructions for performing a method according to any one of claims 12 to 20.

22. A data processing system (210) for executing a data processing program (240), the data processing system comprising computer readable program instructions for performing a method according to any one of claims 12 to 20.

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