Method and apparatus for decoding received uplink transmissions

Abstract

Embodiments of the present disclosure relate to methods and apparatus for decoding received uplink transmissions using log-likelihood ratio optimization. In one embodiment, a method includes: performing soft demapping on resource elements based on soft demapping parameters as part of a process for generating log-likelihood ratio (LLR) values; decoding the LLRs to generate decoded data; and identifying a target performance value. The method also includes determining a performance metric from the decoded data; and executing a machine learning algorithm that dynamically adjusts the soft demapping parameters to move the performance metric toward the target performance value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 975,080, filed on February 11, 2020, entitled “LOG-LIKELIHOOD RATIO (LLR) OPTIMIZATION FOR 5G BY MACHINE LEARNING,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of the present invention relate to the operation of telecommunications networks. More particularly, the exemplary embodiments of the present invention relate to receiving and processing data streams using wireless telecommunications networks. Background Art

[0004] With the rapidly growing trend of mobile and remote data access through high-speed communication networks (such as Long Term Evolution (LTE), fourth generation (4G), and fifth generation (5G) cellular services), accurately delivering and decrypting data streams has become increasingly challenging and difficult. High-speed communication networks capable of delivering information include, but are not limited to, wireless networks, cellular networks, wireless personal area networks ("WPANs"), wireless local area networks ("WLANs"), wireless metropolitan area networks ("MANs"), and the like. While a WPAN may be Bluetooth or ZigBee, a WLAN may be a Wi-Fi network compliant with the IEEE 802.11 WLAN standard.

[0005] In 5G systems, reference signals, data, and uplink control information (UCI) may be included in uplink transmissions from user terminals. Reference signals (RS) are used to estimate channel conditions or for other purposes. However, reference signals are mixed with data so that when data and / or UCI information is processed, the reference signals must be considered. For example, when processing resource elements (REs) received in uplink transmissions, special processing may be required to skip resource elements containing reference signals. Even if the reference signal is set to zero or empty, the resource elements of the reference signal still need to be considered when processing the received data. It is also desirable to provide efficient descrambling, combining, and decoding functions to process the received uplink transmissions.

[0006] Therefore, it would be desirable to have a system that supports efficient processing of data and UCI information received in uplink transmissions. Summary of the Invention

[0007] In various exemplary embodiments, a method and apparatus for a decoding system is provided that supports fast and efficient processing of received 4G and / or 5G uplink transmissions. In various exemplary embodiments, a decoder is provided that uses log-likelihood ratio (LLR) optimization to decode received uplink transmissions.

[0008] In one embodiment, a resource element identifier indexes the uplink control information (UCI) of the received uplink symbols and classifies them into one of three categories. For example, UCI information includes hybrid automatic repeat request ("HARQ") acknowledgement ("ACK"), first channel state information ("CSI1"), and second channel state information (CSI2). For example, category 0 is data or CSI2 information, category 1 is ACK information, and category 2 is CSI1 information. In one embodiment, the classification information is forwarded to a combiner / extractor, which receives the descrambled resource elements. The classification information is used to identify and combine uplink control information from the descrambled resource elements for each symbol. For example, resource elements containing ACK are combined, resource elements containing CSI1 are combined, and resource elements containing CSI2 are combined. The combining is performed on a selected number of received symbols.

[0009] In one embodiment, a decoder system is provided that includes an LLR preprocessor that divides an LLR stream into separate data and CSI2 LLR streams. A separate decoder decodes the streams to generate decoded information. Thus, in various exemplary embodiments, received uplink control information is descrambled, combined, and decoded to obtain UCI information, providing efficient processing and enhanced system performance.

[0010] In one embodiment, a method is provided that includes: soft-demapping resource elements based on soft demapping parameters as part of a process of generating log-likelihood ratio (LLR) values; decoding the LLRs to generate decoded data; and identifying a target performance value. The method also includes determining a performance metric from the decoded data and executing a machine learning algorithm that dynamically adjusts the soft demapping parameters to move the performance metric toward the target performance value.

[0011] In one embodiment, an apparatus is provided, comprising: a soft demapper configured to soft-demapped resource elements based on soft demapping parameters as part of a process of generating log-likelihood ratio (LLR) values; a decoder configured to decode data from the LLRs. The apparatus also includes machine learning circuitry configured to: identify a target performance value; determine a performance metric from the decoded data; and execute a machine learning algorithm that dynamically adjusts the soft demapping parameters to move the performance metric toward the target performance value.

[0012] In one embodiment, an apparatus is provided that includes: means for soft-demapping resource elements based on soft-demapping parameters as part of a process of generating log-likelihood ratio (LLR) values; means for decoding the LLRs to generate decoded data; means for identifying a target performance value; means for determining a performance metric from the decoded data; and means for executing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to move the performance metric toward the target performance value.

[0013] Other features and benefits of exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims set forth below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The exemplary aspects of the present invention will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present invention. However, the present invention should not be limited to specific embodiments but is only for description and understanding.

[0015] Figure 1 A block diagram of a communications network is shown in which resource elements received in uplink transmissions from user terminals are descrambled and combined by an exemplary embodiment of a descrambling and combining system.

[0016] Figure 2 An exemplary detailed embodiment of a descrambling and combining system is shown.

[0017] Figure 3 Shown is a diagram Figure 2 A block diagram of a detailed exemplary embodiment of the RE identifier block is shown in FIG.

[0018] Figure 4A Shown is a diagram Figure 2 A block diagram of a detailed exemplary embodiment of a descrambler is shown in FIG.

[0019] Figure 4B The diagram shows the Figure 4A Block diagram of the operations performed by the descrambler shown in .

[0020] Figure 5AShown is a diagram Figure 2 A block diagram of an exemplary embodiment of a combiner / extractor is shown in FIG.

[0021] Figure 5B The diagram shows the Figure 5A A block diagram of the operations performed by the combiner / extractor shown in .

[0022] Figure 6 An exemplary method for performing resource element classification according to an exemplary embodiment of a resource element identification system is shown.

[0023] Figure 7 An exemplary method for performing descrambling according to an exemplary embodiment of a descrambling and combining system is shown.

[0024] Figure 8 An exemplary method for performing combining according to an exemplary embodiment of a descrambling and combining system is shown.

[0025] Figures 9A to 9B An exemplary method for performing combining according to an exemplary embodiment of a descrambling and combining system is shown.

[0026] Figure 10A An exemplary block diagram of a decoder system is shown.

[0027] Figure 10B The diagram shows the input Figure 10A An exemplary detailed diagram of an embodiment of an LLR stream of a decoder system is shown in FIG.

[0028] Figure 11 An exemplary method for performing decoding according to an exemplary embodiment of a decoder system is shown.

[0029] Figure 12 Show Figure 2 An exemplary embodiment of a portion of a descrambling and combining system is shown in FIG.

[0030] Figure 13 Show Figure 12 An exemplary detailed embodiment of a machine learning circuit is shown in .

[0031] Figure 14 Show Figure 13 An exemplary embodiment of a parameter table is shown in .

[0032] Figure 15 An exemplary embodiment of a soft demapper circuit for use in embodiments of the present invention is shown.

[0033] FIG16 shows an exemplary detailed diagram illustrating the operation of the system.

[0034] Figure 17An exemplary method for executing a machine learning algorithm to optimize performance according to an exemplary embodiment of a decoder system is shown.

[0035] Figure 18 An exemplary method for executing a machine learning algorithm according to an exemplary embodiment of a machine learning circuit is shown.

[0036] Figure 19 A block diagram illustrating a processing system having an exemplary embodiment of a decoder system including machine learning circuitry is shown. DETAILED DESCRIPTION

[0037] Aspects of the present invention are described below in the context of methods and apparatus for processing uplink information received in a wireless transmission.

[0038] The purpose of the following detailed description is to provide an understanding of one or more embodiments of the present invention. Those skilled in the art will appreciate that the following detailed description is merely illustrative and is not intended to be limiting. Other embodiments will readily suggest themselves to those skilled in the art having benefit of this disclosure and / or this description.

[0039] For the sake of clarity, not all conventional features of the implementation described herein are shown and described. Of course, it should be understood that in the development of any such actual implementation, many implementation-specific decisions may be made in order to achieve the developer's specific goals (such as, complying with application and business-related constraints), and these specific goals will vary from one implementation to another and from one developer to another. In addition, it should be understood that such development work may be complex and time-consuming, but for those of ordinary skill in the art who benefit from embodiments of the present disclosure, this will still be a routine matter of engineering.

[0040] The various embodiments of the present invention shown in the accompanying drawings may not be drawn to scale. Rather, the dimensions of various features may be enlarged or reduced for clarity. In addition, some figures may be simplified for clarity. Therefore, the accompanying drawings may not depict all components of a given device (e.g., apparatus) or method. Throughout the accompanying drawings and the following detailed description, the same reference numerals will be used to refer to the same or similar parts.

[0041] The term "system" or "device" is used generally herein to describe any number of components, elements, subsystems, devices, packet switching elements, packet switches, access switches, routers, networks, modems, base stations, eNBs (eNodeBs), computers, and / or communication devices or mechanisms, or combinations of components thereof. The term "computer" includes a processor, memory, and bus capable of executing instructions, where a computer refers to one or a cluster of the following: a computer, a personal computer, a workstation, a mainframe, or a combination of computers.

[0042] An IP communication network, IP network, or communication network refers to any type of network having an access network capable of transmitting data in the form of packets or cells (e.g., ATM (Asynchronous Transfer Mode) type) over a transmission medium (e.g., TCP / IP or UDP / IP type). An ATM cell is the result of breaking down (or segmenting) the data packets, the IP type, and the packets (here, IP packets) comprising an IP header (a header specific to the transport medium (e.g., UDP or TCP)) and payload data. An IP network may also include a satellite network, a DVB-RCS (Digital Video Broadcasting - Return Channel System) network providing Internet access via satellite, or an SDMB (Digital Multimedia Broadcasting - Satellite) network, a terrestrial network, a cable (xDSL) network, or a mobile or cellular network (GPRS / EDGE or UMTS (suitable for MBMS (Multimedia Broadcast / Multicast Service) type), or an evolution of UMTS known as LTE (Long Term Evolution), or DVB-H (Digital Video Broadcasting - Handheld), or a hybrid (satellite and terrestrial) network.

[0043] Figure 1 A block diagram of a communication network 100 is shown in which resource elements received in an uplink transmission from a user terminal are decoded by an exemplary embodiment of a decoder system 156. The network 100 includes a packet data network gateway ("P-GW") 120, two serving gateways ("S-GW") 121-122, two base stations (or cell sites) 102-104, a server 124, and the Internet 150. The P-GW 120 includes various components 140, such as a charging module 142, a subscription module 144, and / or a tracking module 146, to facilitate routing activities between a source and a destination. It should be noted that if one or more blocks (or devices) are added to or removed from the network 100, the basic concepts of the exemplary embodiments will not change.

[0044] The network 100 can operate as a fourth generation ("4G"), long term evolution (LTE), fifth generation (5G), new radio (NR), or a combination of 4G and 5G cellular network configurations. In one aspect, a mobility management entity (MME) 126 is coupled to the base stations (or cell sites) and the S-GW, which can facilitate data transfer between 4G LTE and 5G. The MME 126 performs various control / management functions, network security, and resource allocation.

[0045] In one example, an S-GW 121 or 122 coupled to a P-GW 120, an MME 126, and a base station 102 or 104 can route data packets from a base station 102 or eNodeB to the P-GW 120 and / or the MME 126. The function of the S-GW 121 or 122 is to perform an anchor function for mobility between 3G and 4G equipment. The S-GW 122 can also perform various network management functions, such as terminating paths, paging idle UEs, storing data, routing information, generating replicas, etc.

[0046] The P-GW 120, coupled to the S-GWs 121 to 122 and the Internet 150, can provide network communications between user terminals ("UEs") and IP-based networks, such as the Internet 150. The P-GW 120 is used for connectivity, packet filtering, inspection, data usage, billing, or PCRF (Policy and Charging Rules Function) enforcement, etc. The P-GW 120 also provides an anchor function for mobility between 4G and 5G packet core networks.

[0047] Base station 102 or 104 (also known as a cell site, Node B, or eNodeB) includes one or more radio towers 110 or 112. Radio tower 110 or 112 is also coupled to various UEs such as cellular phone 106, handheld device 108, tablet computer, and / or other UEs via wireless communications or channels 137 to 139. 107. Devices 106 to 108 may be portable or mobile devices, such as Etc. Base station 102 facilitates network communications between mobile devices such as UEs 106-107 and S-GW 121 via radio tower 110. It should be noted that a base station or cell site may include additional radio towers and other terrestrial switching circuitry.

[0048] To improve efficiency and / or speed up processing of uplink control information received in uplink transmissions from user terminals, a decoder system 156 is provided to decode data and UCI information received in the uplink transmissions. A more detailed description of the decoder system 156 is provided below.

[0049] Figure 2An exemplary detailed embodiment of an REI system 152 is shown. Figure 2 A user terminal ("UE") 224 is shown having an antenna 222 that allows for wireless communication with the base station 112 via wireless transmission 226. The UE 224 transmits uplink communications 230 that are received by a base station front end (FE) 228. In one embodiment, the base station includes a gain normalizer 202, an inverse transform block (IDFT) 204, configuration parameters 222, a processing type detector 208, an RS remover 210, a layer demapper 212, a despreader 214, and an REI system 152. In one embodiment, the REI system 152 includes an RE identifier 232, a soft demapper 216, an SINR calculator 234, and a descrambling and combining system (DCS) 154. In one embodiment, the DCS 154 includes a descrambler 218 and a combiner / extractor 220. In one embodiment, the combined data and UCI information output from the DCS 154 is input to a decoder system 156, which outputs decoded information. In one embodiment, a machine learning circuit (MLC) 250 is provided that receives the decoded data / UCI 252 and generates performance metrics that are used by a machine learning algorithm to determine updated soft demapper parameters 256 for performing soft demapping to achieve a selected system performance.

[0050] In one embodiment, the receiver of the uplink transmission processes one symbol at a time, which can be from multiple layers for NR, and processes a slot or an entire subframe of layers for LTE, which covers a 1ms transmission time interval (TTI), a 7-OFDM symbol (OS) short (s)TTI, and a 2 / 3-OS sTTI. The modulation order can be obtained as follows.

[0051] 1. For NR, (π / 2)BPSK

[0052] 2. For LTE sub-PRB, QPSK, 16QAM, 64QAM and 256QAM, (π / 2)BPSK

[0053] Furthermore, the demapping rules apply to the constellations as defined in the LTE (4G) and / or NR (5G) standards.

[0054] Configuration Parameters (Block 222)

[0055] In one embodiment, the configuration parameters 222 include multiple fields, including Figure 22. The configuration parameters 222 may be used by the various blocks shown in FIG. For example, some of the configuration parameters 222 control the operation of the gain normalizer 202, the IDFT 204, the REI system 152, and the decoder system 156. In one embodiment, the configuration parameters 222 may indicate that the gain normalizer 202 and the IDFT 204 are to be bypassed. In one embodiment, the configuration parameters 222 are used by the soft demapper 216 to determine when to soft-demap the received resource elements and when to apply special processing. The configuration parameters 222 are also used to control the operation of the descrambler 218, the combiner / extractor 220, and / or the SINR calculator 234.

[0056] Gain Normalizer (Block 202)

[0057] In one embodiment, gain normalizer 202 performs a gain normalization function on the received uplink transmission. For example, gain normalizer 202 is applicable to LTE and NR DFT-s-OFDM scenarios. On a per-subcarrier, per-data symbol basis, the input samples are normalized as follows, where a normalized gain value is calculated per symbol as follows:

[0058] Gainnorm_out[Ds][sc]=(Gainnorm_in[Ds][sc]) / (Norm_Gain[Ds])

[0059] IDFT (block 204)

[0060] IDFT 204 operates to provide an inverse transform to generate a time domain signal. In one embodiment, IDFT 204 is enabled only for LTE and NRDFT-s-OFDM and LTE sub-PRBs. In one embodiment, the input and output are assumed to be 16-bit I and Q values, respectively. The DFT and IDFT operations are defined as follows.

[0061]

[0062] and

[0063]

[0064] Where W N =e -2πj / N .

[0065] Process Type Detector (Block 208)

[0066] In an exemplary embodiment, the process type detector 214 detects the type of process to be performed by the system. For example, this information can be detected from the configuration parameters 222. In one embodiment, the process type detector 208 operates to detect one of two process types that cover the operation of the system as follows.

[0067] 1. Type 1 - 5G NR DFT-s-OFDM

[0068] 2. Type 1 - 5G NR CP-OFDM

[0069] 3. Type 2 - 5G NR PUCCH format 4

[0070] RS Remover (Block 210)

[0071] In one embodiment, the RS remover 210 operates during type 1 processing to remove RS resource elements from the received data stream to produce a data stream that is input to the layer demapper. For example, the RE positions of the RS symbols are identified, and the data is rewritten into one or more buffers to remove the RS symbols to produce an output containing only data / UCI. In one embodiment, type 1 processing includes RS / DTX removal, layer demapping with an interleaving structure, soft demapping, and descrambling. One benefit of removing RS REs before layering is that it enables a single shot descrambling process without any interference in a continuous pattern, without the need for additional buffering.

[0072] Layer Demapper (Block 212)

[0073] In one embodiment, data and signal-to-interference-and-noise ratio (SINR) values ​​from multiple layers of a subcarrier are transferred to a layer demapping circuit (not shown) via a multi-threaded read DMA operation. In this case, each thread points to a different memory location for a symbol. The layer demapper 212 generates demapped data and multiple pSINR reports for each layer. In one embodiment, for NR, DMRS / PTRS / DTX REs are removed from the information stream before soft demapping for both I / Q and SINR samples.

[0074] Despreader (Block 214)

[0075] In one embodiment, despreader 214 provides despreading type 2 processing only for PUCCH format 4. Despreading involves combining repeated symbols along the frequency axis by multiplying them with the conjugate of the appropriate spreading sequence. The spreading sequence index and the spreading type used to correctly combine the information are given by configuration parameter 222. This process is always performed on a total of 12 REs. Depending on the spreading type, the number of REs that will be pushed to the subsequent frame after despreading will be reduced by half or 1 / 4. The combined results will be averaged and stored as 16 bits before soft demapping.

[0076] REI System (Box 152)

[0077] In one embodiment, the REI system 152 includes an RE identifier 232, a soft demapper 216, a descrambler 218, a combiner / extractor 220, and an SINR calculator 234. During operation, the REI system 152 classifies resource elements and passes these classified REs to the soft demapper 216 and one or more other blocks of the REI system 152. In one embodiment, the soft demapper 216 uses the classified REs to determine when to apply special treatment to the soft demapping process.

[0078] In another embodiment, described in greater detail below, the RE identifier 232 receives requests for hypothetical index values ​​for resource elements containing data / CSI2 information. The RE identifier 232 processes these requests to determine whether the RE contains data or a CSI2 value, and determines whether the RE contains a CSI2 value by providing a hypothetical index value associated with the CSI2 value.

[0079] Resource Element Identifier (Block 232)

[0080] In one embodiment, the RE identifier 232 operates to process the received information stream of resource elements to identify, index, and classify each element. The index and classification of each element (e.g., RE information 236) is passed to the soft demapper 216 and other blocks of the REI system 152. A more detailed description of the operation of the RE identifier 232 is provided below.

[0081] Figure 3 Shown is a diagram Figure 2 A block diagram of a detailed exemplary embodiment of the RE identifier 232 is shown in FIG. Figure 3 As illustrated in , the RE identifier 232 includes an RE input interface 302 , a parameter receiver 304 , a classifier 306 , and an RE output interface 308 .

[0082] During operation, uplink transmissions are received and processed by the above blocks to produce information streams, such as information stream 312. For example, the received uplink transmissions are processed by at least one of the following: the processing type detector 208, the layer demapper 212, or the debracket 214. As a result, the information stream 312 does not contain any reference signals (RSs), but does contain data or data multiplexed with UCI information, and the stream is input to the RE identifier 232.

[0083] In one embodiment, the information stream 312 includes information or data bits and UCI bits. In one example, UCI bits such as ACK bits, CSI1 bits, and / or data / CSI2 bits are interspersed throughout the information stream 312. For example, as shown, the UCI bits are intermixed with the data bits.

[0084] In one embodiment, during 5G operation, RE identifier 232 correctly identifies the RE index of the UCI bit for use in Figure 2 The soft demapper special processing, descrambler coding modifications, and UCI combining / extraction are shown in . The RE index of the UCI bit is also used to generate the SINR report value for ACK and CSI1, as well as for NR CP-OFDM operation.

[0085] In one embodiment, the RE identification process processes two REs per cycle, as indicated at 314. For example, the resource elements of the received stream 312 are received by the RE input interface 302, which provides the received information to the classifier 306. The parameter receiver 304 receives parameters 310 from the configuration parameter block 222. The classifier 306 uses these parameters to classify the received resource elements, and after classifying the received REs, the classifier 306 stores the classified REs in an array, such as array 316, which shows the index, RE value, and category. In one embodiment, the identification of RE1 can be obtained based on multiple hypotheses for RE0. Similarly, the identification of RE2 can be obtained based on multiple hypotheses for RE0 and RE1. The RE output interface 308 outputs the classified REs to the soft demapper 216, the descrambler 218, the UCI combiner 220, and the SINR calculator 234. In one aspect, the components of the soft demapper 216, the descrambler 218, the UCI combiner 220, and the SINR calculator 234 are interconnected to communicate certain information between the components.

[0086] In an exemplary embodiment, RE identifier 232 receives a request 318 for a hypothesis index value for an RE that contains data / CSI2 information. This request is received from combiner / extractor 220. In response to request 318, RE identifier 232 determines whether the RE contains data or CSI2 information. If the RE contains CSI2 information, a hypothesis index value associated with the CSI2 value is determined. In one embodiment, there are up to 11 (0-10) hypotheses associated with the CSI2 information. RE identifier 232 then outputs the determined hypothesis index value 320 to combiner / extractor for further processing.

[0087] Reference again Figure 2 In various embodiments, the soft demapper 216 provides special handling of REs based on certain UCI categories. The descrambler 218 can provide scrambling code modification based on certain UCI categories. The UCI combiner / extractor 220 can combine DATA, ACK, CSI1, and / or CSI2 information. The SINR calculator 234 can calculate data / CSI2 SINR and other SINRs associated with REs, such as ACK SINR and CSI SINR.

[0088] Soft Demapper

[0089] The soft demapping principle is based on computing the log-likelihood ratio (LLR) of a bit, which quantifies the level of certainty about whether the bit is a logic 0 or a logic 1. The soft demapper 216 processes on a symbol-by-symbol basis and within a symbol on a RE-by-RE basis.

[0090] The soft demapping principle is based on calculating the log-likelihood ratio (LLR) of a bit, which quantifies the level of certainty about whether the bit is a logic 0 or a logic 1. Under the assumption of Gaussian noise, the LLR for the i-th bit is given by:

[0091]

[0092] where c j and c k is the constellation point, for c j and c k , where the i-th bit takes the values ​​0 and 1, respectively. Note that for the grayscale mapping modulation scheme given in [R1], x can take values ​​to refer to a single dimension, I or Q. The computational complexity increases linearly with the modulation order. To reduce the computational complexity, the maximum logarithmic MAP approximation has been adopted. Note that this approximation is not necessary for QPSK, as the LLR for QPSK has only one term in both the numerator and denominator.

[0093]

[0094] This approximation is sufficiently accurate (especially in the high SNR region) and can greatly simplify the LLR calculation, thus avoiding complex exponential and logarithmic operations. Given that I and Q are the real and imaginary parts of the input samples, the soft LLRs are defined as follows for (π / 2) BPSK, QPSK, 16QAM, 64QAM, and 256QAM, respectively.

[0095] In one embodiment, the soft demapper 216 includes a first minimum functional component ("MFC"), a second MFC, a special processing component ("STC"), a subtractor, and / or an LLR generator. The function of the soft demapper 216 is to demap or ascertain soft bit information associated with a received symbol or bit stream. For example, the soft demapper 216 employs a soft demapping principle based on calculating a log-likelihood ratio (LLR) of a bit, which quantifies the level of certainty as to whether the bit is a logic 0 or a logic 1. To reduce noise and interference, the soft demapper 216 can also discard one or more unused constellation points from the constellation diagram that are related to the frequency of the bit stream.

[0096] In one aspect, the STC is configured to force an infinity value as an input to the first MFC when the bit stream is identified and requires special processing. For example, predefined control signals with a specific set of coding categories (such as ACK with a set of predefined coding categories) require special processing. In one aspect, one of the special processing is to force an infinity value as an input to the MFC. For example, when the bit stream is identified as ACK or CSI1 with a predefined coding category, the STC forces an infinity value as an input to the first MFC and the second MFC. In one instance, the STC is configured to determine whether special processing (or special processing function) is required based on the received bit stream or symbol. In one aspect, 1-bit and 2-bit control signals with the predefined coding categories listed in Table 1 require special processing. It should be noted that Table 1 is exemplary and other configurations are possible.

[0097] Table 1

[0098]

[0099]

[0100] SINR calculator (block 234)

[0101] The SINR calculator 234 calculates the SINR for each UCI type based on the category received from the REI block 232 .

[0102] Descrambler (Block 218)

[0103] Descrambler 218 is configured to generate the descrambling sequence of bit or bit stream. For example, after generating sequence according to input value, descrambler determines whether the descrambling sequence modification is needed for certain categories of control information to be descrambled. For example, descrambler 218 receives classified RE information 236 from RE identifier 232, and uses this information to determine when descrambling sequence modification is required. In one embodiment, descrambler also provides storage of intermediate linear feedback shift register (LFSR) state to facilitate continuous descrambling sequence generation over multiple symbols. The descrambled resource element 244 of symbol is passed to combiner / extractor 220 together with corresponding descrambling sequence 246. A more detailed description of descrambler 218 is provided below.

[0104] Combiner / Extractor (Block 220)

[0105] The combiner / extractor 220 provides combining and extraction functionality to combine the descrambled soft bits from the descrambler 218 and extract uplink control information. In one embodiment, the combiner / extractor 220 modifies its operation based on the category received from the REI block 232. A more detailed description of the combiner / extractor 220 is provided below.

[0106] Decoder System (Block 156)

[0107] The decoder system 156 decodes the raw LLRs received from the combiner / extractor 220, as well as the combined data / UCI information 254. In one embodiment, the decoder system 156 partitions the combined data and CSI2 information into separate LLR streams based on the configuration parameters 222. The decoder system 156 then decodes each stream separately to generate decoded data and CSI2 (UCI) information 252. A more detailed description of the decoder system 156 is provided below.

[0108] Machine Learning Circuit (MLC) (Block 250)

[0109] In one embodiment, a machine learning circuit 250 is provided that receives decoded data / UCI information 252 and determines a performance metric. Based on the determined performance metric, the MLC 250 executes a machine learning algorithm to generate updated soft demapper parameters 256, which are input to the configuration parameters 222. In one embodiment, the parameters 256 are input to the soft demapper 216 and used to determine soft-demapped REs 242, which are processed into raw LLRs and combined data / UCI information 254, which are decoded by the decoder system 156. In one embodiment, the MLC 250 adjusts the soft demapper parameters 256 until the desired performance metric is achieved. A more detailed description of the MLC 250 is provided below.

[0110] Figure 4A Shown is a diagram Figure 2 , a block diagram of a detailed exemplary embodiment of the descrambler 218 is shown in . In one embodiment, the descrambler 218 includes a descrambler processor 402, an internal memory 404, linear feedback shift registers LFSR0 and LFSR1, and an output interface 406. The descrambler processor 402 also includes a sequence modifier 412 that operates to modify the descrambling sequence for certain categories of ACK and CSI1 information.

[0111] Figure 4B The diagram shows the Figure 4A 4. A block diagram of the operations performed by the descrambler 218 is shown in FIG. During operation, the descrambler processor 402 receives the soft-demapped REs 242 from the soft demapper 216. The descrambler processor 402 also receives selected configuration parameters 222, RE information 236, and initialization values ​​416. In one embodiment, the initialization values ​​416 are provided by a central processor or other receiver entity and are stored as INIT0 408 and INIT1 410. The descrambler processor 402 initializes LFSR0 and LFSR1 using the initialization values ​​INIT0 408 and INIT1 410, respectively. The outputs of the shift registers LFSR0 and LFSR1 are used to determine the descrambled bits used to descramble the received REs 242. For example, the outputs of the shift registers LFSR0 and LFSR1 are mathematically combined by the descrambler processor 402 to determine the descrambled bits to be used to descramble the received REs 242.

[0112] When the resource elements of the first symbol are received, the descrambler processor 402 descrambles the received REs 242 using the descrambling bits determined from the output of the shift register. For example, when the resource elements of symbol S0 are received, the descrambler processor 402 descrambles the received resource elements using the generated descrambling bits. As each RE is descrambled (as indicated by path 418), the descrambled REs are stored in the internal memory 404. After descrambling all REs of the symbol, the descrambler processor 402 stores the state of the shift registers LFSR0 / 1 in the external memory 414. For example, at the end of symbol S0, the state 422 of LFSR0 / 1 is stored in the external memory 414. It should also be noted that the sequence modifier 412 can be used to modify the descrambling sequence for certain categories of ACK and CSI1 information.

[0113] Before the REs of the next symbol (e.g., S1) are descrambled, the LSFR state 422 is restored from the external memory 414 and provided to the descrambler processor 402 as an initial value 416. Thus, the restored state allows the operation of the shift registers to continue from where they left off after completing the descrambling of the previous symbol (e.g., S0). After descrambling symbol S1, the descrambler processor 402 stores the state of the shift registers (indicated at 424) into the external memory 414. Before commencing descrambling of symbol S3, the state 424 is restored to the LFSR registers of the descrambler processor 402 as described above. This process of storing and restoring the shift register states continues until all REs for all symbols have been descrambled. It should be noted that the REs include data or UCI information. For example, symbol S0 includes Figure 4B After the REs are descrambled, they are output as descrambled REs 244 by the descrambler output interface 406 to the combiner / extractor 220. In one embodiment, the descrambling sequence 246 used to descramble the REs is also provided to the combiner / extractor 220.

[0114] Figure 5A Shown is a diagram Figure 2, which is a block diagram of a detailed exemplary embodiment of the combiner / extractor 220 shown in FIG. In one embodiment, the combiner / extractor 220 includes a combiner / extractor processor 502 and an internal memory 504. The processor 502 includes a hypothesis processor 516. During operation, the processor 502 receives RE information 236 and descrambled REs 244 from the descrambler 218. The processor 502 also receives a descrambling sequence 246, which is used to descramble the descrambled REs 244. The processor 502 uses the RE information 236 to determine which REs represent UCI values. For example, the RE information 236 includes indexed and sorted RE information so that the processor 502 can use the information to determine when selected UCI REs are received.

[0115] At the beginning of a symbol, the processor 502 initializes the ACK 508, CSI1 510, and 11 (0-10) hypothetical CSI2 512 values ​​in the memory 504. When REs containing ACK and CSI1 information are received, the processor 502 combines this information with the current values ​​in the memory 504. For example, the processor 502 uses the REI information 236 to determine when ACK information bits are received and combines these bits with the currently stored ACK bits 508. This process continues for the ACK 508 and CSI1 510.

[0116] When CSI2 information is received, 512, a hypothesis processor 516 operates to determine one of the hypotheses 512 in which to accumulate the CSI2 information. A more detailed description of the operation of the hypothesis processor 516 is provided below.

[0117] After all REs for a symbol have been received, the combined values ​​are written out to external memory 514. Before the start of the next symbol, the values ​​in external memory 514 are returned to processor 502 and restored to internal storage 504. Combining of the UCI values ​​for the next symbol is then performed.

[0118] After the UCI information in each symbol is combined, the result is stored in the external memory 514. This process continues until the UCI information from the selected number of symbols has been combined. After the combining process is complete, the processor 502 outputs the combined result 506 to the decoder.

[0119] Figure 5B The diagram shows the Figure 5A, which is a block diagram of the operations performed by the combiner / extractor 220 shown in FIG. In one embodiment, assume that the processor 516 receives the descrambled RE stream 244 and the descrambling sequence 246, which is used to descramble the REs of the descrambled stream. The processor 516 drops or erases the ACK information (indicated at 518) from the descrambled stream 416 to generate a stream that includes only CSI1 and data / CSI2 information. Next, the processor 516 drops the CSI1 information (indicated at 520) from the stream to generate a stream that includes only data / CSI2 information. The processor 516 then performs function 522 to identify the hypothesis associated with the data / CSI2 stream. For example, the processor 516 sends a request 318 to the RE identifier 232 to identify the hypothesis index value associated with the data / CSI2 information. The RE identifier 232 returns identification information indicating whether the data / CSI2 information includes data or CSI2 information. If the information includes data, data 524 is output for further processing. If the information contains CSI2, a hypothesis index is received that indicates the hypothesis associated with the CSI2 information. The CSI2 information and its hypothesis 526 are then further processed.

[0120] Hypothesis processor 516 receives CSI2 / hypothesis (Hyp) 526 and performs further processing. If the hypothesis is in the range of (2-10), as indicated at 530, the CSI2 information is passed for accumulation in memory 504. If the hypothesis is in the range of (0-1), the CSI2 value is input to rescrambling function 532, which rescrambles the CSI2 information using the received descrambling sequence 246 to recover the CSI2 information 536 before descrambling. The descrambling sequence 246 is modified by modifier function 534 to generate a modified descrambling sequence 540. The modified descrambling sequence 540 is used by descrambling function 542 to descramble the rescrambled CSI2 information 536 to generate modified descrambled CSI2 information 544. The modified CSI2 information is passed for accumulation in memory 504.

[0121] Soft output for UCI combination

[0122] In an exemplary embodiment, the output for UCI soft combining may be summarized as follows.

[0123] 1-bit UCI case

[0124] A. 1 soft-combined UCI output with a bit width of 16 bits

[0125] B. One soft-combined 'x' marked bit output, which has a bit width of 16 bits, is used for ACK and is only used for 16QAM, 64QAM and 256QAM.

[0126]

[0127] For the 2-bit UCI case

[0128] A. 3 soft-combined UCI outputs for 2-bit UCI case, which has a bit width of 16 bits

[0129] B. 1 soft-combined 'x' marked bit output, which has a bit width of 16 bits, is used for ACK and is only used for 16QAM, 64QAM and 256QAM

[0130]

[0131] For RM coding (3≤O UCI ≤11)

[0132] A. A set of 32 soft-combined UCI outputs, which have a bit width of 16 bits, are used as input to the RM decoder.

[0133] struct UCI_REPORT_RM{

[0134] int16_t uci_soft_combined

[32] ;

[0135] }

[0136] CSI2 situation

[0137] In an exemplary embodiment, there will be a total of up to 11 soft-combined results, each corresponding to a hypothesis. The soft-combining methodology for each hypothesis is fixed and is given in Table 2 below.

[0138] Table 2 CSI2 soft combination for each hypothesis

[0139]

[0140] Note that, prior to the soft combining operation, depending on the modulation type and scrambling sequence, LLR modification may be required for both Assumption 0 and Assumption 1 due to the presence of the 'x' and 'y' bits. This is illustrated in Table 3 below.

[0141]

[0142]

[0143] * indicates x / y bit modification

[0144] Table 3: Examples of CSI2 combinations for multiple assumptions

[0145] Figure 6 An exemplary method 600 for performing resource element classification according to an exemplary embodiment of the REI system is shown. For example, the method 600 is suitable for use with Figure 2 1 and 2 for use with the REI system 152 shown in FIG.

[0146] At block 602, an uplink transmission is received in a 5G communication network. For example, the uplink transmission is received in a 5G communication network. Figure 2 Received at the front end 228 shown in .

[0147] At block 604, gain normalization is performed. For example, gain normalization is performed by Figure 2 The gain normalizer 202 shown in FIG.

[0148] At block 606, an inverse Fourier transform is performed to obtain a time domain signal. For example, this process is performed by Figure 2 The IDFT block 204 shown in FIG.

[0149] At block 608, a determination is made as to the type of processing to be performed. For example, a description of two types of processing is provided above. If the first type of processing is to be performed, the method proceeds to block 610. If the second type of processing is to be performed, the method proceeds to block 624. For example, the operation is performed by Figure 2 The processing type detector 208 shown in FIG.

[0150] At block 624, when the processing type is type 2, despreading is performed on the received resource elements. For example, this operation is performed by Figure 2 The method then proceeds to block 614.

[0151] When the processing type is type 1, the following operations are performed.

[0152] At block 610, reference signals are removed from the received resource elements. For example, resource elements containing RS / DTX are removed. This operation is performed by Figure 2 The RS remover 210 shown in FIG.

[0153] At block 612, layer demapping is performed. For example, resource elements without RS / DTX are layer demapped. This operation is performed by the layer demapper 212.

[0154] At block 614, RE identification and classification is performed. Figure 3As illustrated in , RE identifier 232 receives a stream of REs, classifies the REs, and then outputs an array 316 in which the REs are indexed and include classification values.

[0155] At block 616, soft demapping is performed. For example, the soft demapper 216 soft-demaps the REs with special processing provided based on the classification of the received REs. The soft demapper 216 produces a soft-demapped output that is input to the descrambler 218.

[0156] At block 618, descrambling is performed. For example, the descrambler 218 receives the soft-demapped bits from the soft demapper 216 and generates descrambled bits. In one embodiment, a modified descrambler code is used based on the classification of REs. In one embodiment, the descrambler 218 operates to preserve the LFSR state between symbols so that continuous descrambling code generation can be provided from symbol to symbol.

[0157] At block 620, combining and extracting the UCI information is performed. For example, the combiner / extractor 220 receives the descrambled bits, combines the bits, and extracts the UCI information. For example, the combiner / extractor 220 utilizes the RE classification information to identify the UCI resource elements and combines these elements into the memory 504. The combined UCI value is output at the end of the symbol, and the memory is reinitialized for UCI combining for the next symbol.

[0158] At block 622, SINR calculations are performed to calculate Data / CSI2, ACK, and CSI1 SINR values.

[0159] Thus, according to an exemplary embodiment, method 600 operates to provide resource element identification and classification.It should be noted that the operations of method 600 may be modified, added, deleted, rearranged, or otherwise altered within the scope of the embodiments.

[0160] Figure 7 An exemplary method 700 for performing descrambling according to an exemplary embodiment of a descrambling and combining system is shown. For example, the method 700 is suitable for use with Figure 2 For use with the DCS 154 shown in FIG.

[0161] At block 702, configuration parameters and initialization values ​​are received by the descrambler 218. For example, the configuration parameters 222 are received by the descrambler processor 402. Additionally, the initialization value 416 is received by the descrambler processor 402. In one embodiment, the initialization value 416 is received at the receiver from a central processing entity. In another embodiment, the initialization value 416 is LFSR state information received from the external memory 414.

[0162] At block 704, one or more linear feedback shift registers are initialized. For example, processor 402 initializes registers LFSR0 and LFSR1 using initialization values ​​INIT0 408 and INIT1 410, respectively.

[0163] At block 706, resource elements of a symbol are received. Figure 4B As shown in , processor 402 receives resource elements of symbol S0.

[0164] At block 708, a descrambling code is generated. For example, the processor 402 generates a descrambling code based on the outputs of the shift registers LFSR0 and LFSR1.

[0165] At block 710 , the RE information is accessed by the processor to determine information about the current resource element. For example, the processor 402 accesses information about the current resource element based on the RE information 236 and the parameters 222 .

[0166] At block 712, a determination is made as to whether a scrambling code modification should be performed. For example, processor 402 determines whether a descrambling code modification is required to descramble the current resource element based on RE information 236 and parameter 222. If a scrambling code modification is required, the method proceeds to block 714. If no modification is required, the method proceeds to block 716.

[0167] At block 714, the scrambling codes are modified as needed by the processor 402. For example, the sequence modifier 412 modifies certain types of scrambling codes for ACK and CSI1 information.

[0168] At block 716, the RE is descrambled using the scrambling code. For example, the processor 402 descrambles the RE using the current scrambling code.

[0169] At block 718, a determination is made as to whether there are more REs to be descrambled in the current symbol. For example, processor 402 makes this determination from configuration parameters 222 and / or RE information 236. If there are no more REs to be descrambled, the method proceeds to block 720. If there are more REs to be descrambled in the current symbol, the method proceeds to block 706.

[0170] At block 720, a determination is made as to whether there are more symbols to be descrambled. For example, processor 402 makes this determination based on configuration parameters 222 and / or RE information 236. If there are no more symbols to be descrambled, the method ends. If there are more symbols to be descrambled, the method proceeds to block 722.

[0171] At block 722, the LFSR states are stored. For example, processor 422 pushes the current states of registers LFSR0 and LFSR1 to external memory 414 (eg, as shown by 422).

[0172] At block 724, the LFSR state is restored before the next symbol is descrambled. For example, the stored LFSR state from memory 414 is provided to processor 402 as a new set of initialization values ​​416, which are used to restore the states of registers LFSR0 and LFSR1. Thus, the LFSR generates a descrambling sequence based on the restored state. The method then proceeds to block 706, where descrambling continues until the desired number of symbols have been descrambled.

[0173] Thus, method 700 operates in accordance with an exemplary embodiment of a descrambling and combining system to provide descrambling.It should be noted that the operations of method 700 may be modified, added, deleted, rearranged, or otherwise changed within the scope of the embodiments.

[0174] Figure 8 An exemplary method 800 is shown for performing combining according to an exemplary embodiment of a descrambling and combining system. For example, the method 800 is suitable for use with Figure 2 For use with the DCS 154 shown in FIG.

[0175] At block 802, initialization of ACK, CSI1, and CSI2 values ​​in memory is performed. For example, in one embodiment, processor 502 initializes the values ​​of ACK 508, CSI1 510, and CSI2 512 in memory 504.

[0176] At block 804, descrambled REs for a symbol are received. For example, processor 502 receives descrambled REs 244.

[0177] At block 806 , RE classification information is received. For example, the processor 502 receives the RE information 236 .

[0178] At block 808, a determination is made as to whether the current RE contains an ACK value. The processor 502 makes this determination from the RE information 236. If the current RE contains an ACK value, the method proceeds to block 810. If the current RE does not contain an ACK value, the method proceeds to block 812.

[0179] At block 810 , the ACK value contained in the current RE is combined with the ACK value in the memory. For example, the processor 502 combines the current RE value with the stored ACK value 508 and restores the combined value back to the memory 504 .

[0180] At block 812, a determination is made as to whether the current RE contains a CSI1 value. The processor 502 makes this determination from the RE information 236. If the current RE contains a CSI1 value, the method proceeds to block 814. If the current RE does not contain a CSI1 value, the method proceeds to block 816.

[0181] At block 814 , the CSI1 value contained in the current RE is combined with the CSI1 value in the memory. For example, the processor 502 combines the current RE value with the stored CSI1 value 510 and restores the combined value back to the memory 504 .

[0182] At block 816, a determination is made as to whether the current RE contains a CSI2 value. The processor 502 makes this determination from the RE information 236. If the current RE contains a CSI2 value, the method proceeds to block 818. If the current RE does not contain a CSI2 value, the method proceeds to block 820.

[0183] At block 818, the CSI2 value contained in the current RE is combined with the CSI2 value in the memory. For example, the processor 502 combines the current RE value with one of the stored hypothetical CSI2 values ​​512 and restores the combined value back to the memory 504. Figures 9A to 9B Provides a detailed description of the combination of CSI2 values.

[0184] At block 820, a determination is made as to whether there are more REs to be combined in the current symbol. Processor 502 makes this determination from RE information 236. If there are more REs to be combined, the method proceeds to block 804. If there are no more REs to be combined, the method proceeds to block 822.

[0185] At block 822 , the accumulated UCI values ​​are pushed to the external memory. For example, the accumulated UCI values ​​are pushed to the external memory 514 .

[0186] At block 824, a determination is made as to whether there are more symbols to be combined. In one embodiment, processor 502 makes this determination based on REI information 236. If there are no more symbols to be combined, the method ends. If there are more symbols to be combined, the method proceeds to block 826.

[0187] At block 826, the UCI value stored in the external memory is retrieved and input to the processor 502 as a new initialization value. For example, the accumulated UCI value stored in the external memory 514 is retrieved by the processor 502. The method then proceeds to block 802, where the UCI value retrieved from the external memory is used to initialize the UCI values ​​508, 510, and 512 in the internal memory 504.

[0188] Thus, method 800 operates in accordance with an exemplary embodiment of a descrambling and combining system to provide combining.It should be noted that the operations of method 800 may be modified, added, deleted, rearranged, or otherwise altered within the scope of the embodiments.

[0189] Figures 9A to 9B An exemplary method 900 is shown for performing combining according to an exemplary embodiment of a descrambling and combining system. For example, the method 900 is suitable for use with Figure 2 For use with the DCS154 shown in .

[0190] Now refer to Figure 9A At block 902, initialization is performed for the ACK, CSI1, and 11 hypothetical CSI2 values ​​stored in the memory. For example, in one embodiment, the processor 502 initializes the ACK 508, CSI1 510, and 11 hypothetical CSI2 values ​​512 in the memory 504. In one embodiment, the values ​​used to initialize the memory 504 are received from the external memory 514 (indicated by D).

[0191] At block 904, descrambled REs for a symbol are received. For example, processor 502 receives descrambled REs 244.

[0192] At block 906 , a descrambled sequence is received. For example, the processor 502 receives the descrambled sequence 246 .

[0193] At block 908 , RE classification information is received. For example, the processor 502 receives the RE information 236 .

[0194] At block 910, a determination is made as to whether the RE is an ACK value. If the received RE is an ACK value, the method proceeds to block 912. If the received RE is not an ACK value, the method proceeds to block 914.

[0195] At block 912, ACK processing is performed as described elsewhere in this document. The method then proceeds to block 938 (indicated by B).

[0196] At block 914 , a determination is made as to whether the received RE is a CSI1 value. If the received RE is a CSI1 value, the method proceeds to block 916 . If the received RE is not a CSI1 value, the method proceeds to block 918 .

[0197] At block 916, CSI1 processing is performed as described elsewhere in this document. The method then proceeds to block 938 (indicated by B).

[0198] At block 918, the RE includes data / CSI2, and thus a request for a hypothesis value for the RE is generated. For example, the processor 516 outputs the request 318 to the RE identifier 232 to obtain a hypothesis index valued for the data / CSI2 information. In one embodiment, the response 320 generated by the RE identifier 232 indicates that the data / CSI2 information is data. In one embodiment, the response 320 generated by the RE identifier 232 indicates that the data / CSI2 information is CSI2 information associated with the selected hypothesis value (e.g., x).

[0199] At block 920 , a determination is made as to whether the data / CSI2 information is data. If the response from the RE identifier 232 indicates that the data / CSI2 information is data, the method proceeds to block 922 . If not, the method proceeds to block 924 .

[0200] At block 922, the data is processed as described elsewhere in this document.The method then proceeds to block 938 (indicated by B).

[0201] At block 924, a determination is made as to whether the hypothesis index associated with the CSI2 information is in the range of (2-10). If the hypothesis index is in the range of (2-10), the method proceeds to block 926. If not, the method proceeds to block 928 (indicated by A).

[0202] At block 926, as described elsewhere in this document, based on the hypothetical value, the CSI2 information is accumulated with the appropriate CSI2 information in memory 504. The method then proceeds to block 936 (indicated by B).

[0203] Now refer to Figure 9B , at block 928 , the current CSI2 information is identified as being associated with hypothesis 0 or 1.

[0204] At block 930 , the CSI2 REs are re-scrambled using the received descrambling sequence. For example, the processor 516 re-scrambles the received scrambled CSI2 REs 528 using the received descrambling sequence 246 to generate re-scrambled CSI2 REs 536 .

[0205] At block 932 , the descrambling sequence 246 is modified to generate a modified descrambling sequence. The processor 516 executes a modification function 534 to modify the received descrambling sequence 246 to generate a modified descrambling sequence 540 .

[0206] At block 934 , the re-scrambled REs are descrambled using the modified descrambling sequence to generate modified descrambled REs. For example, the processor 516 executes the descrambling function 542 to descramble the re-scrambled CSI2 REs 536 to generate modified descrambled CSI2 REs 544 .

[0207] At block 936 , the modified descrambled CSI2 REs 544 are accumulated with the appropriate hypothesis values ​​in memory 504 .

[0208] At block 938, a determination is made as to whether there are more REs to be combined in the current symbol. Processor 502 makes this determination based on RE information 236. If there are more REs to be combined, the method proceeds to block 904 (indicated by C). If there are no more REs to be combined, the method proceeds to block 940.

[0209] At block 940 , the accumulated UCI values ​​in the memory 504 are stored in the external memory 514 .

[0210] At block 942, a determination is made as to whether there are more symbols with UCI information to be combined. If there are more symbols with UCI information to be combined (e.g., in a slot or subframe), the method proceeds to block 902 (indicated by D). In this path, information stored in external memory 514 is used to initialize the values ​​stored in memory 504 before combining information from additional symbols. If there are no more symbols to be combined, the method ends.

[0211] Thus, method 900 operates in accordance with an exemplary embodiment of a descrambling and combining system to provide combining.It should be noted that the operations of method 900 may be modified, added, deleted, rearranged, or otherwise altered within the scope of the embodiments.

[0212] Figure 10AAn exemplary block diagram of the decoder system 156 is shown. In one embodiment, the decoder system 156 includes LLR preprocessors 1002A-1002B, a data decoder 1004, and a CSI2 decoder 1006. A memory 1008 is also shown in FIG10. In one embodiment, the memory 1008 receives the combined data and UCI information 506 from the combiner / extractor processor 502 shown in FIG5. For example, the memory 1008 receives the combined hypothesized CSI2 values ​​1010 and outputs these values ​​to the decoder system 156 in an LLR stream 1012.

[0213] In 5G or NR, data and UCI LLRs are multiplexed in both time and frequency. UCI includes CSI1 / CSI2 and ACK fields. In one embodiment, the CSI1 and ACK LLRs can be separated and / or removed from the LLR stream. However, the CSI2 LLRs cannot be separated before generating the composite output LLR stream 1012 that is provided as input to the decoder system 156. To extract the required LLRs from this composite stream, LLR preprocessors 1002A and 1002B perform this operation. For example, in one embodiment, preprocessor 1002A extracts the data LLRs from stream 1012 and discards the remaining LLRs to form the data LLR stream. In another embodiment, preprocessor 1002B extracts the CSI2 LLRs and discards the remaining LLRs to form the CSI2 LLR stream.

[0214] In one embodiment, data decoder 1004 decodes the data LLR stream to generate decoded data. CSI2 decoder 1006 decodes the CSI2 LLR stream to generate decoded CSI2 information. In another embodiment, Reed-Muller (RM), 1-bit, or 2-bit encoded CSI2 LLRs (indicated at 1016) are provided directly to CSI2 decoder 1006.

[0215] Figure 10B An exemplary detailed diagram illustrating an embodiment of an LLR stream 1012 according to one embodiment of the present invention is shown, which is input to the decoder system 156. The LLR stream 1012 includes LLRs for CSI2, LLRs for data, and padding LLRs. Figure 10B They are identified by their corresponding shading. In one embodiment, LLR pre-processors 1002A-1002B perform an algorithm to remove padding LLRs to generate a second stream 1014, which contains LLRs for data and LLRs for CSI2. For example, after the padding LLRs are discarded by pre-processors 1002A-1002B, the remaining LLR stream follows the pattern shown in stream 1014.

[0216] In one embodiment, in each half-slot, there can be up to three bursts of CSI2 LLRs and up to two bursts of data LLRs, alternating with each other. Each burst of data LLRs corresponds to a group of data LLRs in a DMRS symbol. With frequency hopping, there can be up to two DMRS symbols in each half-slot, and therefore two bursts of data LLRs are possible. Each burst of CSI2 LLRs corresponds to a continuous group of CSI2 LLRs that are not interrupted by data LLRs.

[0217] The burst sizes of the CSI2 LLRs are denoted by px_a0, px_a1, and px_a2. And the burst sizes of the data LLRs are denoted by px_b0 and p1_b1, respectively. Following these CSI2 and data bursts, there can be periodic, alternating CSI2 and data LLRs that repeat "a_k" times. Each cycle begins with a CSI2 LLR of length "px_a_r," followed by data LLRs of length "px_a_d-px_a_r." Following this periodic pattern, the remaining data LLRs will be data LLRs until the end of 'num_rd_dma_word_px'. Overall, these bursts repeat twice. For example, for part 0, px becomes p0, and for part 1, px becomes p1.

[0218] Configuration

[0219] In one embodiment, the following configuration parameters 222 shown in Table 4 below are used by the LLR pre-processors 1002A-1002B to separate data and CSI2 LLR operations. These parameters will appear in the polar decoder (PDEC) block and the AB_CFG portion of the LDPC decoder (LDEC) in the configuration parameters 222. All of these parameters do not necessarily appear in the same 64-bit word or in consecutive words.

[0220] Table 4: Configuration parameters

[0221]

[0222]

[0223] LLR Preprocessor Operations

[0224] In an exemplary embodiment, the following pseudo-code describes the operation of the LLR pre-processors 1002A-1002B of the decoding system to separate the data and CSI2 LLRs to the appropriate decoder. For example, the following pseudo-code utilizes the configuration parameters shown in Table 4 to remove the padded (e.g., "tagged") LLRs and separate the data and CSI2 LLRs from the input stream to generate data and CSI2 streams, which are passed to the appropriate decoder.

[0225]

[0226]

[0227] Step 0:

[0228] Discard all marked LLRs.

[0229] Step 1: Part 0 Getting Started

[0230]

[0231] Step 2:

[0232]

[0233] Step 3:

[0234] Repeat steps 1 and 2 one or more times, where csi2_count = 'preproc_p0_csi2_len1' and data count = 'preproc_p0_data_len1'

[0235] Step 4:

[0236]

[0237]

[0238] Step 5:

[0239]

[0240] Step 6:

[0241]

[0242] Step 7:

[0243] Repeat steps 5 and 6 'preproc_p0_num_repeat' times

[0244] Step 8: End of Part 0

[0245]

[0246] Step 9: Part 1 Getting Started

[0247] Repeat steps 1 to 7 by replacing all instances of 'p0' with 'p1'

[0248] Step 10: End of Part 1

[0249]

[0250] Figure 11 An exemplary method 1100 for performing decoding according to an exemplary embodiment of a decoder system is shown. For example, the method 1100 is suitable for use with Figure 2 1 and 2 for use with the decoder system 156 shown in FIG.

[0251] At block 1102, a stream of data, CSI2, and padding LLRs is received. For example, in one embodiment, stream 1012 is received by decoder 156 from memory 1008. In one embodiment, both LLR pre-processors 1002A-1002B receive the stream.

[0252] At block 1104, configuration parameters are received. In one embodiment, configuration parameters 222 are received by pre-processors 1002A-1002B.

[0253] At block 1106, the filler LLRs are removed from the stream. For example, the pre-processors 1002A-1002B remove the filler ("tagged") LLRs from the streams they have received.

[0254] At block 1108, the data and CSI2 LLR are separated. For example, the pre-processors 1102A-1102B separate the data and CSI2 LLR based on the received configuration parameters. For example, each of the LLR pre-processors 1102A-1102B performs the above-described algorithm to separate the data or CSI2 LLR from the received streams.

[0255] At block 1110, the data LLRs are decoded. For example, the data decoder 1004 receives the data LLRs and decodes them.

[0256] At block 1112, the CSI2 LLR is decoded. For example, the CSI2 decoder 1006 receives the CSI2 LLR and decodes it.

[0257] Thus, the method 1100 operates in accordance with an exemplary embodiment to provide decoding.It should be noted that the operations of the method 1100 may be modified, added, deleted, rearranged, or otherwise altered within the scope of the embodiments.

[0258] LLR Optimization Using Machine Learning

[0259] The quality and range of LLRs generated by an LLR generator in a 5G system are critical to achieving the best possible physical layer performance. In various embodiments, machine learning circuitry operates to provide parameters to the soft demapping process of the LLR generator to achieve a selected performance target. In an iterative process, the machine learning algorithm adjusts the soft demapping parameters based on measured performance metrics to move system performance toward the selected target performance until the target performance is achieved. The machine learning circuitry includes a parameter table that stores the generated soft demapping parameters after each iteration. The table also provides storage for the soft demapping parameters generated for each of a plurality of decoders operating with a plurality of modulation and coding schemes.

[0260] Figure 12 Shown Figure 2 An exemplary embodiment of a portion of a descrambling and combining system is shown in FIG. Figure 12 , the REI system 152 generates raw LLRs 254 and includes a soft demapper 216. The REI system 152 receives input from the layer demapper 212 or the despreader 214 and generates raw LLRs and combined data / UCI information 254. The REI system 152 receives configuration parameters 222, which are used to control the operation of various functional blocks of the REI system 152, including the soft demapper 216.

[0261] In one embodiment, the configuration parameters 222 include soft demapping parameters 256, which are passed to the soft demapper 216 and used to control the soft demapping process. A more detailed description of the soft demapping parameters 256 is provided below.

[0262] In a 5G system, the LLRs generated by the LLR generator are fed into one or more decoders. For example, in one embodiment, the decoder 156 includes a turbo decoder (TDEC) block, an LDPC decoder (LDEC) block, and an X decoder (XDEC) block. Any decoder block can be used to generate the decoded data / UCI output 252. For various reasons, the internal fixed point implementations of all these decoders may be different. To ensure the best possible performance from each of these decoders, the configuration parameters 222 of the LLR generator are carefully selected.

[0263] In one embodiment, the machine learning circuit 250 receives the decoded data / UCI output 252 and determines a performance metric indicative of system performance. In one embodiment, the MLC 250 executes a machine learning algorithm to generate updated soft demapping parameters 256, which are used to adjust the operation of the soft demapper 216 to move the measured performance toward a desired target performance. In one embodiment, the MLC 250 executes the machine learning algorithm based on a reinforcement learning process to generate the updated parameters 256 to achieve the desired target performance.

[0264] Figure 13 Shown Figure 12 13. The machine learning circuit 250 includes a processor 1302, a memory 1304, and a performance metric circuit 1306, all coupled to communicate via a bus 1312. The memory 1304 includes performance target(s) 1308 and a parameter table 1310.

[0265] Machine Learning Approach

[0266] Traditionally, machine learning approaches are divided into broad categories based on the nature of the "signal" or "feedback" available to the learning system. In an exemplary embodiment, the machine learning algorithm 1314 performs reinforcement learning to interact with a dynamic environment in which it must perform a certain goal (such as adjusting soft demapper parameters to meet a performance goal). As the algorithm navigates the performance space, it is provided with feedback (e.g., a performance metric) that the algorithm uses to adjust the soft demapper parameters 256 to move the performance metric toward the performance goal 1308.

[0267] Various types of models have been used and studied to implement machine learning systems. In one embodiment, machine learning algorithm 1314 is implemented by an artificial neural network, which interconnects groups of nodes, similar to the vast network of neurons in the brain. For example, processor 1302 executes algorithm 1314, which implements the neural network to perform the operations described herein.

[0268] During operation, performance measurement circuitry 1306 receives decoded data / UCI 252 and determines one or more performance metrics. For example, a performance metric may include a block error rate (BLER) or any other suitable performance metric. For example, the performance metric may be the minimum SINR required to achieve a certain BLER, which may be user-defined, such as a BLER of 10%. Processor 1302 executes a machine learning algorithm 1314, which adjusts parameters in parameter table 1310 such that subsequent performance metrics move toward performance target 1308 until the performance target is achieved. Thus, machine learning algorithm 1314 dynamically adjusts parameters for soft demapper 216 to adjust system performance toward performance target 1308 without manual intervention. In one embodiment, the target performance is a specific performance level or represents a range of performance.

[0269] Figure 14 Shown Figure 13 14. An exemplary embodiment of a parameter table 1310 is shown in FIG. In one embodiment, parameter table 1310 includes columns for decoder types 1402. Each decoder type 1402 includes parameters for multiple modulation and coding scheme (MCS) values ​​1404. The parameters include a modulation (MOD) scale value 1406, a first right shift (RSFT1) value 1408, a second right shift (RSFT2) value 1410, an LLR offset value 1412, and an LLR bit width value 1414. Based on decoder type 1402 and MCS value 1404, machine learning algorithm 1314 adjusts soft demapper parameters 256 to move a performance metric toward target performance 1308. For example, the performance metric may be the minimum SINR required to achieve a certain BLER, which may be user-defined, such as a BLER of 10%. In one embodiment, the parameters of parameter table 1310 may be initialized with any desired initial values.

[0270] Figure 15 An exemplary embodiment of a soft demapper circuit 1500 for use in embodiments of the present invention is shown. For example, the soft demapper circuit 1500 is suitable for use as at least a portion of the soft demapper 216. In one embodiment, the soft demapper circuit 1500 includes minimization (MIN) detectors 1502 and 1504, rounding circuits 1506 and 1508, an LLR offset circuit 1510, and a saturation (SAT) circuit 1512. The circuit 1500 also includes multipliers 1514, 1516, and 1518, an adder 1520, and a subtractor 1522.

[0271] During operation, the received I / Q bits are input to multiplier 1514. Multiplier 1514 also receives a selected constant (e.g., 1, 3, 5, 7, 9, 13, and 15), and the result of the multiplication is a 20-bit value that is input to adder 1520. Adder 1520 also receives a constant (MX_CONSTY), which is an unsigned 18-bit value. Adder 1520 outputs the sum of its inputs as a 21-bit value, which is input to both minimization circuits 1502 and 1504. Each minimization circuit outputs the minimum input of its inputs. Minimization control circuit 1524 outputs a control value to each minimization circuit 1502 and 1504. The control value controls which value is output from each minimization circuit. For example, the minimum value is selected for a specific modulation format. The output of the minimization circuit is input to a subtractor 1522 which subtracts the values ​​and generates a 22-bit output which is input to a multiplier 1516. In one embodiment, equation (Equation 1) is implemented.

[0272] The second multiplier 1518 receives the 24-bit unsigned SINR signal and the 16-bit unsigned modulation metric value. The product of these signals is input to the rounding circuit 1508, which shifts and rounds its input value based on the first shift value (RSFT1). For example, the following operations are performed to generate the RS1 value.

[0273] [Input + (2^(RSFT1-1))] >> 2^RSFT1 = 40-bit RS1 value; or

[0274] [Input + (2^(RSFT1-1))] / 2^RSFT1 = 40-bit RS1 value

[0275] The RS1 value is input to a multiplier 1516, which multiplies its inputs to generate a 62-bit value that is input to a second rounding circuit 1506. The rounding circuit 1506 shifts and rounds the input value based on a second shift value (RSFT2). For example, the following operations are performed to generate the RS2 value.

[0276] [Input + (2^(RSFT2-1))] / 2^RSFT2 = 40-bit RS2 value

[0277] The LLR offset circuit 1510 receives the RS2 value and the LLR offset value and performs an offset operation. The LLR offset value is an unsigned (k-1) bit value. The output of the offset circuit 1510 is input to the saturation circuit 1512. The saturation circuit 1512 receives the LLR_bit_width value and scales its input to prevent saturation to determine the soft-demapped REs 242. The soft-demapped REs 242 are processed into the original LLRs and the combined data / UCI information 254, which are decoded by the decoder system 156.

[0278] Optimization of LLR_bit_width

[0279] Depending on the internal implementation details of the decoder, the decoder may perform differently with different LLR bit widths. In a first operation, an optimal bit width is determined at which the selected decoder achieves its hard decoding performance. In one embodiment, the following operations are performed by processor 1302 to determine the optimal LLR bit width to use during the decoding process.

[0280] 1. Maximize all multipliers and minimize all dividers, forcing the LLRs to go into saturation. For example, processor 1302 outputs parameters to force LLR 242 into saturation.

[0281] 2. Adjust the LLR_bit_width value 1414 for optimal performance for a particular decoder / MCS. For example, the processor 1302 adjusts the LLR_bit_width parameter to achieve optimal LLR performance. The LLR_bit_width value is then stored in the parameter table 1310.

[0282] Parameter optimization based on machine learning

[0283] After the LLR_bit_width parameter is determined, the machine learning algorithm 1314 operates to adjust the remaining soft demapping parameters to achieve the target performance. In one embodiment, the following operations are performed by the machine learning circuit 250 to adjust the soft demapping parameters.

[0284] 1. The performance metric is determined by the performance metric circuit 1306.

[0285] 2. Target performance 1308 is obtained from memory 1304.

[0286] 3. The machine learning algorithm 1314 uses the current performance metric and the target performance to adjust the MOD_SCALE 1406, RSF1 1408, RSFT2 1410, and LLR_OFFSET 1412 parameters for a specific decoder / MCS to move the performance metric toward the target performance. It should be noted that as a result of the above operations, each decoder will have its own unique set of configuration parameters to achieve the associated target performance. For example, the LLR bit width parameter 1414 is determined for a specific decoder / MCS. Other parameters are set to initial conditions. The machine learning algorithm 1314 uses the current performance metric and the target performance to adjust the MOD_SCALE 1406, RSF1 1408, RSFT2 1410, and LLR_OFFSET 1412 parameters for a specific decoder / MCS to move the performance metric toward the target performance in an iterative process until the target performance is achieved. After each iteration, the updated parameters are stored in the parameter table 1310.

[0287] FIG16 shows exemplary diagrams illustrating the operation of a system for adjusting LLR generation based on the received SINR for a differential modulation scheme. Plot 1602 shows a plot of the mean of the absolute values ​​of the LLR values ​​(e.g., mean(abs(LLR))) versus the signal-to-interference-and-noise ratio (SINR). Plot 1604 shows a plot of the variance of the absolute values ​​of the LLR values ​​(e.g., var(abs(LLR))) versus the SINR. For example, these plots depict the range of LLRs generated by the LLR generator for a fixed configuration at different SINR values. In one embodiment, the LLR_bit_width parameter controls the upper and lower saturation limits of the LLRs, while the shift values ​​RSFT1 and RSFT2 shift the curve along the SINR axis to determine where saturation occurs. For each decoder type, these curves are carefully shaped for optimal performance. With different internal implementations, each decoder fed by the LLR generator requires a different set of soft demapping configuration parameters. With minimal or no external intervention, these optimal configuration parameters for each decoder are generated by the machine learning algorithm 1314. The machine learning algorithm 1314 receives feedback from the decoder in the form of performance metrics in order to drive the optimization process to achieve the target performance.

[0288] Figure 17 An exemplary method 1700 is shown for utilizing machine learning to optimize performance according to an exemplary embodiment of a decoder system. For example, the method 1700 is suitable for use with Figure 12 The descrambling shown in is used together with part of a combined system.

[0289] At block 1702, a stream of data, CSI2, and padding LLRs is received.

[0290] At block 1704, soft demapping is performed using the soft demapping parameters as part of LLR processing to generate raw LLRs.

[0291] At block 1706, the original LLRs are decoded by the selected decoder.

[0292] At block 1708 , a performance metric and a target performance are determined. For example, the performance metric is determined by the performance metric circuitry 1306 and the target performance 1308 is stored in the memory 1304 .

[0293] At block 1710 , a determination is made as to whether the performance metric meets the target performance. If the performance metric meets the performance target, the method ends. If the performance metric does not meet the performance target, the method proceeds to block 1712 .

[0294] At block 1712, a machine learning algorithm is executed to adjust the soft demapping parameters to move the performance metric toward the performance target. For example, the machine learning algorithm 1314 is executed.

[0295] At block 1714, the parameter table is updated with the updated soft demapping parameters. For example, the parameter table 1310 is updated with the newly determined soft demapper parameters. The method then proceeds to block 1702 to receive and process more received streams.

[0296] Thus, method 1700 operates in accordance with an exemplary embodiment of a decoder system to utilize machine learning to optimize performance. It should be noted that the operations of method 1700 may be modified, added, deleted, combined, rearranged, or otherwise altered within the scope of the embodiments.

[0297] Figure 18 An exemplary method 1800 for executing a machine learning algorithm according to an exemplary embodiment of a machine learning circuit is shown. For example, the method 1800 is suitable for Figure 17 In one embodiment, the method 1800 is performed by Figure 13 The machine learning circuit 250 shown in FIG. 1 performs

[0298] At block 1802, a determination is made as to whether this is the first pass through the machine learning process for the selected decoder and MCS. If this is the first pass, the method proceeds to block 1804. If this is not the first pass, the method proceeds to block 1808.

[0299] At block 1804, parameter values ​​are adjusted to achieve LLR saturation for the selected decoder / MCS. For example, parameters are set such that all multipliers in the demapping circuit 1500 are maximized and all dividers are minimized to force the LLRs into saturation for the selected decoder / MCS.

[0300] At block 1806, based on the LLR saturation level, an LLR_bit_width value is determined for the selected decoder / MCS. The bit width value is selected to avoid saturation.

[0301] At block 1808, the target performance for the selected decoder / MCS is obtained from the memory 1304. For example, the target performance 1308 is obtained from the memory 1304.

[0302] At block 1808, a performance metric for the selected decoder / MCS is obtained. For example, the performance metric circuit 1306 determines the performance metric for the selected decoder / MCS by analyzing the decoded data 252. In one embodiment, the performance metric is a BLER value.

[0303] At block 1812, a machine learning algorithm is executed to adjust the soft demapping parameters to move the performance metric toward the target performance. In one embodiment, the MLC 250 executes the machine learning algorithm 1314 based on a reinforcement learning process to generate updated parameters 256 to achieve the desired target performance. The determined soft demapper parameters are passed to block 1714 where they are stored in the parameter table 1310.

[0304] Thus, method 1800 operates in accordance with an exemplary embodiment of a decoder system to execute a machine learning algorithm to optimize performance. It should be noted that the operations of method 1800 may be modified, added, deleted, combined, rearranged, or otherwise altered within the scope of the embodiments.

[0305] Figure 19 A block diagram is shown illustrating a processing system 1900 having an exemplary embodiment of a decoder system 1930 including machine learning circuitry that adjusts soft demapping parameters to achieve performance targets for a selected decoder. For example, in one embodiment, the decoder system 1930 includes Figure 2 The machine learning circuit 250 is shown in FIG. It will be apparent to one of ordinary skill in the art that other alternative computer system architectures may also be employed.

[0306] System 1900 includes a processing unit 1901, an interface bus 1912, and an input / output ("IO") unit 1920. Processing unit 1901 includes processor 1902, main memory 1904, system bus 1911, static memory device 1906, bus control unit 1909, mass storage memory 1908, and decoder system 1930. Bus 1911 is used to transfer information between various components and processor 1902 for data processing. Processor 1902 can be a variety of general-purpose processors, embedded processors, or microprocessors, such as Embedded processors, Core TM 2 Duo, Core TM 2 Quad, Pentium TM microprocessor, series processors, Embedded processor or Power PC TM microprocessor.

[0307] The main memory 1904 can store frequently used data and instructions, and the main memory 1904 can include multiple levels of cache memory. The main memory 1904 can be RAM (random access memory), MRAM (magnetic RAM), or flash memory. The static memory 1906 can be ROM (read-only memory) that is coupled to the bus 1911 and is used to store static information and / or instructions. The bus control unit 1909 is coupled to the buses 1911 to 1912 and controls which component (such as the main memory 1904 or the processor 1902) can use the bus. The mass storage memory 1908 can be a magnetic disk, a solid-state drive ("SSD"), an optical disk, a hard drive, a floppy disk, a CD-ROM, and / or flash memory for storing large amounts of data.

[0308] In one example, I / O unit 1920 includes a display 1921, a keyboard 1922, a cursor control device 1923, and a communication device 1929. Display device 1921 can be a liquid crystal device, a flat panel display, a cathode ray tube ("CRT"), a touch screen display, or other suitable display device. Display 1921 projects or displays a graphic image or window. Keyboard 1922 can be a conventional alphanumeric input device for communicating information between computer system 1900 and a computer operator. Another type of user input device is cursor control device 1923, such as a mouse, touch mouse, trackball, or other type of cursor, for communicating information between system 1900 and a user.

[0309] Communication device 1929 is coupled to bus 1912 for accessing information from a remote computer or server via a wide area network. Communication device 1929 may include a modem, a router, or a network interface device, or other similar device that facilitates communication between computer 1900 and a network. In one aspect, communication device 1929 is configured to perform wireless functions. Alternatively, decoder system 1930 and communication device 1929 perform resource element classification, descrambling and combining, decoding, and machine learning optimization functions according to embodiments of the present invention.

[0310] In one aspect, decoder system 1930 is coupled to bus 1911 and is configured to perform decoding and machine learning and optimization functions on received uplink communications as described above to improve overall receiver performance. In one embodiment, decoder system 1930 includes hardware, firmware, or a combination of hardware and firmware.

[0311] In one embodiment, an apparatus is provided that includes means for soft-demapping resource elements based on soft-demapping parameters as part of a process of generating log-likelihood ratio (LLR) values, which, in one embodiment, includes a demapper 216. The apparatus also includes means for decoding the LLRs to generate decoded data, which, in one embodiment, includes a decoder system 156. The apparatus also includes means for identifying a target performance value, means for determining a performance metric from the decoded data, and means for executing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to move the performance metric toward the target performance value, which, in one embodiment, includes a machine learning circuit 250.

[0312] While particular embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that, based on the teachings herein, changes and modifications may be made without departing from the exemplary embodiments of the present invention and its broader aspects. It is therefore intended that the appended claims encompass within their scope all such changes and modifications as come within the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. A method for communication, comprising: performing soft demapping on resource elements based on the soft demapping parameters as part of a process for generating log-likelihood ratio (LLR) values; decoding the LLRs to generate decoded data; Identify target performance values; determining a performance metric from the decoded data; as well as executing a machine learning algorithm that dynamically adjusts the soft demapping parameters to move the performance metric toward the target performance value, The soft demapping parameters include: a modulation scale MOD_SCALE value, a first shift RSFT1 value, a second shift RSFT2 value, and an LLR offset value.

2. The method of claim 1 , wherein the resource elements are derived from symbols received in a New Radio (NR) uplink transmission.

3. The method according to claim 1, further comprising: The decoded data is output. The method of claim 1 , wherein the soft demapping parameters further comprise an LLR bit width value.

5. The method of claim 4, wherein executing the operation of the machine learning algorithm comprises: The soft demapping parameters are adjusted to determine the LLR saturation level.

6. The method according to claim 5, wherein the operation of adjusting comprises: The LLR saturation level is used to determine a selected LLR bit width value.

7. The method of claim 6, wherein executing the operations of the machine learning algorithm comprises: Based on the selected LLR bit width value, the machine learning algorithm is executed to update the soft demapping parameters.

8. The method of claim 7, wherein executing the operations of the machine learning algorithm comprises: The machine learning algorithm is executed in an iterative process to update the soft demapping parameters until the performance metric meets the target performance.

9. A device for communication, comprising: a soft demapper configured to soft demap resource elements based on soft demapping parameters as part of a process for generating log-likelihood ratio (LLR) values; a decoder configured to decode data from the LLRs; as well as The machine learning circuit is configured to: Identify target performance values; determining a performance metric from the decoded data; as well as executing a machine learning algorithm that dynamically adjusts the soft demapping parameters to move the performance metric toward the target performance value, The soft demapping parameters include: a modulation scale MOD_SCALE value, a first shift RSFT1 value, a second shift RSFT2 value, and an LLR offset value.

10. The apparatus of claim 9, wherein the resource elements are derived from symbols received in a New Radio (NR) uplink transmission.

11. The apparatus of claim 9, wherein the decoder outputs the decoded data, and the decoded data is input to the machine learning circuit.

12. The apparatus of claim 9, wherein the soft demapping parameters further comprise an LLR bit width value.

13. The apparatus of claim 12, wherein the machine learning circuit adjusts the soft demapping parameters to determine an LLR saturation level.

14. The apparatus of claim 13, wherein the machine learning circuitry uses the LLR saturation level to determine the selected LLR bit width value.

15. The apparatus of claim 14, wherein the machine learning circuitry performs the machine learning algorithm based on the selected LLR bit width value to update the soft demapping parameters.

16. The apparatus of claim 15, wherein the machine learning algorithm performs an iterative process to update the soft demapping parameters until the performance metric meets the target performance.

17. An apparatus for communication, comprising: means for soft-demapping resource elements based on soft-demapping parameters as part of a process for generating log-likelihood ratio (LLR) values; means for decoding the LLRs to generate decoded data; Components used to identify target performance values; means for determining a performance metric from said decoded data; as well as means for executing a machine learning algorithm that dynamically adjusts the soft demapping parameters to move the performance metric toward the target performance value, The soft demapping parameters include: a modulation scale MOD_SCALE value, a first shift RSFT1 value, a second shift RSFT2 value, and an LLR offset value.

18. The apparatus of claim 17, wherein the soft demapping parameters further comprise an LLR bit width value.

19. The apparatus of claim 18, wherein the means for executing the machine learning algorithm updates the soft demapping parameters based on the selected LLR bit width value.

20. The apparatus of claim 19, wherein the means for executing the machine learning algorithm performs an iterative process to update the soft demapping parameters until the performance metric meets the target performance.

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