Display device

Abstract

A display device includes a display panel, a drive circuit that supplies a drive signal to the display panel and includes at least one drive transistor, and a clock signal wiring for supplying a clock signal to the drive circuit. The drive circuit includes an active pattern, a gate pattern that overlaps the active pattern in a plan view, a source pattern whose main surface plane is arranged in a layer different from a layer in which the active pattern is arranged, the source pattern being electrically connected to the active pattern, a shield pattern that is arranged between the gate pattern and the clock signal wiring and to which a constant voltage is applied, and the clock signal wiring that overlaps the gate pattern in the plan view and is arranged on the source pattern.

Description

Technical Field

[0001] The embodiments pertain to a display device. More specifically, the embodiments pertain to a display device including a shielding pattern. Background Technology

[0002] To date, traditional cathode ray tubes (CRTs) have been widely used in display devices that offer numerous advantages in terms of performance and price. However, display devices with advantages such as miniaturization or portability that overcomes the drawbacks of CRTs, as well as those with advantages such as small size, reduced weight, and low power consumption, have attracted attention. Examples include plasma displays, liquid crystal displays (LCDs), and organic light-emitting diode (OLEDs).

[0003] Attempts have been made to reduce the bezel area of ​​display devices. For example, bezel-less display devices and display devices with notches have been developed. Wiring within the bezel area can be reconfigured to reduce the bezel size. Summary of the Invention

[0004] An embodiment provides a display device including a shielding pattern.

[0005] According to an example embodiment, a display device includes: a display panel; a driving circuit that provides a driving signal to the display panel and includes at least one driving transistor; and a clock signal wiring that provides a clock signal to the driving circuit. The driving circuit includes an active pattern, a gate pattern, a source pattern, and a shielding pattern. The gate pattern overlaps with the active pattern in a planar view. The main surface plane of the source pattern is disposed in a layer different from the layer in which the active pattern is disposed. The source pattern is electrically connected to the active pattern. The shielding pattern is disposed between the gate pattern and the clock signal wiring and is subjected to a constant voltage. The clock signal wiring overlaps with the gate pattern in a planar view and is disposed on the source pattern.

[0006] In an embodiment, the shielding pattern may be arranged below the main surface plane of the source pattern.

[0007] In an embodiment, the shielding pattern in the plan view can completely overlap with the entire area where the gate pattern overlaps with the clock signal wiring.

[0008] In an embodiment, the display device may further include: a connection wiring arranged in the same layer as the clock signal wiring, and the connection wiring transmitting a constant voltage to the shielding pattern.

[0009] In an embodiment, the display device may further include: a connection wiring arranged between a shielding pattern and a clock signal wiring, the connection wiring transmitting a constant voltage to the shielding pattern.

[0010] In an embodiment, the connection wiring may not overlap with each of the clock signal wiring and gate patterns in the plan view.

[0011] In an embodiment, the gate pattern may include a first sub-gate pattern and a second sub-gate pattern.

[0012] In an embodiment, the first sub-gate pattern and the second sub-gate pattern can be arranged below the main surface plane of the source pattern.

[0013] In an embodiment, the first sub-gate pattern and the second sub-gate pattern may overlap with the shielding pattern in a plan view.

[0014] In an embodiment, only one of the first sub-gate pattern and the second sub-gate pattern may overlap with the shielding pattern in a planar view.

[0015] In an embodiment, the first sub-gate pattern and the second sub-gate pattern can be arranged in the same layer.

[0016] In an embodiment, the driving circuit may further include a drain pattern disposed between the first sub-gate pattern and the second sub-gate pattern and electrically connected to the active pattern.

[0017] In an embodiment, only one of the first sub-gate pattern and the second sub-gate pattern may overlap with the shielding pattern in a planar view.

[0018] In an embodiment, the shielding pattern may include a first sub-shielding pattern and a second sub-shielding pattern.

[0019] In an embodiment, the first sub-gate pattern and the second sub-gate pattern may overlap with the first sub-shielding pattern and the second sub-shielding pattern respectively in a plan view.

[0020] In one embodiment, the shielding pattern may be arranged on the source pattern.

[0021] In this embodiment, the driving circuit may include a p-type transistor.

[0022] In this embodiment, the driving circuit may include an n-type transistor.

[0023] In one embodiment, the driving circuit may include a dual-gate transistor.

[0024] The display device according to an embodiment may include: a display panel, a driving circuit that provides driving signals to the display panel and includes at least one driving transistor, and clock signal wiring for providing clock signals to the driving circuit. The driving circuit includes an active pattern, a gate pattern overlapping the active pattern, a source pattern disposed in a different layer from the active pattern and electrically connected to the active pattern, and a shielding pattern disposed between the gate pattern and the clock signal wiring to which a constant voltage is applied. The clock signal wiring overlaps with the gate pattern and is disposed on the source pattern. Therefore, the bezel area of ​​the display device can be reduced. Furthermore, coupling phenomena that may occur between the gate pattern and the clock signal wiring can be effectively prevented.

[0025] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0026] Various aspects of embodiments of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram illustrating an embodiment of the structure of a scan driver.

[0029] Figure 3 This is a schematic diagram illustrating an embodiment of the scan drive circuit built into the scan shift register.

[0030] Figure 4 This is a schematic diagram of an embodiment of the structure of the transmitter driver.

[0031] Figure 5 This is a schematic diagram illustrating an embodiment of the transmit drive circuit built into the transmit shift register.

[0032] Figure 6 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0033] Figure 7 This is a plan view illustrating an embodiment of the driving transistor.

[0034] Figure 8 It is along Figure 7 The cross-sectional view taken from line II-II'.

[0035] Figure 9 This is a plan view illustrating another embodiment of the driving transistor.

[0036] Figure 10 It is along Figure 9 The cross-sectional view taken from line III-III'.

[0037] Figure 11 This is a plan view illustrating yet another embodiment of the driving transistor.

[0038] Figure 12 It is along Figure 11 The cross-sectional view taken from line IV-IV'.

[0039] Figure 13 This is a plan view of yet another embodiment of the dual-gate transistor driving circuit.

[0040] Figure 14 It is along Figure 13 A cross-sectional view taken from line V-V'.

[0041] Figure 15 This is a plan view of another embodiment of the dual-gate transistor driving circuit.

[0042] Figure 16 It is along Figure 15 The cross-sectional view taken from line VI-VI'.

[0043] Figure 17 This is a plan view of yet another embodiment of the dual-gate transistor driving circuit.

[0044] Figure 18 It is along Figure 17 The cross-sectional view taken from line VII-VII'.

[0045] Figure 19 This is a plan view of yet another embodiment of the dual-gate transistor driving circuit.

[0046] Figure 20 It is along Figure 19 The cross-sectional view taken from line VIII-VIII'.

[0047] Figure 21 This is a plan view illustrating another embodiment of the driving transistor.

[0048] Figure 22 It is along Figure 21 The cross-sectional view taken from line IX-IX'. Detailed Implementation

[0049] In the following description, a display device according to an embodiment of the present invention will be described with reference to the accompanying drawings, in which embodiments are illustrated. The same or similar reference numerals may be used for the same or similar elements in the drawings.

[0050] This invention can have various modifications and can be embodied in different forms, and embodiments will be described in detail with reference to the accompanying drawings. However, this invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, it should include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0051] In the accompanying drawings, the dimensions of the structures have been exaggerated for clarity. It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of the invention, a first element may be referred to as a second element. Similarly, a second element may be referred to as a first element. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of this document, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms containing “at least one” unless the context clearly indicates otherwise. In the specification and claims, for the purposes of their meaning and interpretation, the term “and / or” is intended to include any combination of the terms “and” and “or.” For example, “A and / or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in combined or separate meanings and may be understood to be equivalent to “and / or.”

[0053] For the purposes of its meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”. When following a list of elements, the term “at least one of…” modifies the entire list of elements without modifying any individual elements in the list.

[0054] It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the said feature, number, step, operation, element, component or combination thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof.

[0055] It will also be understood that when a layer, film, region, plate, etc., is referred to as being "on" or "above" another component, it can be "directly" "on" that other component or an intermediate layer may also be present. It will also be understood that when a layer, film, region, plate, etc., is referred to as being "below" or "under" another component, it can be "directly" "below" that other component or an intermediate layer may also be present. When an element is referred to as being arranged "on" another element, it can be arranged below that other element.

[0056] For ease of description, the spatial relative terms “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or component and another, as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device illustrated in the drawings is flipped, the device located “below” or “under” another device may be placed “above” the other device. Therefore, the illustrative term “below” may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, the spatial relative terms may be interpreted differently depending on the orientation.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0058] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present invention. Figure 2 This is a schematic diagram of an embodiment of the structure of the scan driver. Figure 2 It is a floor plan. Figure 3 This is a schematic diagram illustrating an embodiment of the scan drive circuit built into the scan shift register. Figure 4 This is a schematic diagram of an embodiment of the structure of the transmitter driver. Figure 4 It is a floor plan. Figure 5 This is a schematic diagram illustrating an embodiment of the transmit drive circuitry built into the transmit shift register, and Figure 6 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0059] refer to Figures 1 to 6The display device 1000 may include a display panel 120 comprising a plurality of pixels 400 and a driving circuit 130 for driving the display panel 120. The driving circuit 130 may include a data driver 100 that provides a data signal 110 to the plurality of pixels 400, a scan driver 200 that provides a scan signal 210 to the plurality of pixels 400, and a transmission driver 300 that provides a transmission signal 310 to the plurality of pixels 400.

[0060] Display panel 120 may include a plurality of pixels 400 connected to a plurality of data lines and a plurality of scan lines. Pixels 400 may be arranged in a matrix over the entire area of ​​display panel 120. However, this is exemplary, and the arrangement of pixels 400 according to the invention is not limited thereto. Each pixel 400 may include at least two transistors, at least one capacitor, and an organic light-emitting diode 580. Display panel 120 may be an organic light-emitting display panel. Pixels 400 may be hybrid oxide polycrystalline (HOP) pixels suitable for low-frequency driving to reduce power consumption. HOP pixels may include at least one low-temperature polycrystalline silicon (LTPS) PMOS transistor and at least one oxide NMOS transistor. However, this is exemplary, and the invention is not limited thereto.

[0061] exist Figure 1 The illustration shows the scan driver 200 and the transmit driver 300 located on opposite sides of the display panel 120, but this is exemplary and the invention is not limited thereto. In another embodiment, for example, the positions of the scan driver 200 and the transmit driver 300 can be changed. Alternatively, both the scan driver 200 and the transmit driver 300 can be positioned on the same side of the display panel 120.

[0062] like Figure 2 As illustrated, the scan driver 200 may include a plurality of scan shift registers 220 and a plurality of clock signal traces CLK connected to the plurality of scan shift registers 220. In an embodiment, the plurality of clock signal traces CLK may be arranged to overlap with the scan shift registers 220 in a plan view. When the plurality of clock signal traces CLK are arranged to overlap with the plurality of scan shift registers 220 in a plan view, the bezel area of ​​the display device 1000 can be reduced.

[0063] The scan shift register 220 may include a scan drive circuit 10. In an embodiment, the scan drive circuit 10 may include first scan drive transistors T1 to eighth scan drive transistors T8, a first capacitor C1, and a second capacitor C2. Coupling may occur in some scan drive transistors T2, T4, T6, and T7 that are not directly supplied with multiple clock signals CLK1 and CLK2 as gate turn-on signals and are not directly supplied with constant voltages (i.e., the first constant voltage VGH and the second constant voltage VGL) as gate turn-on signals. When coupling occurs, a fault may occur in the scan output. As a result, the performance of the display device 1000 may deteriorate. Figure 3 In the scan drive circuit 10, clock signal CLK1 is applied as a gate turn-on signal to the third scan drive transistor T3, clock signal CLK2 is applied as a gate turn-on signal to the first scan drive transistor T1 and the fifth scan drive transistor T5, and the second constant voltage VGL can be applied as a gate turn-on signal to the eighth scan drive transistor T8. The output signal Scan is synchronized with the output signal OUT of the nth scan shift register 220. <n>Correspondingly, here, n is a natural number. The output signal OUT... <n-1>To OUT<n+2> These correspond to the output signals of the (n-1)th scan shift register 220 to the (n+2)th scan shift register 220, respectively.

[0064] Figure 3 The scan drive circuit 10 is illustrated as including a p-type transistor, but the invention is not limited thereto. In another embodiment, the scan drive circuit 10 may include an n-type transistor.

[0065] like Figure 4 As illustrated, the transmit driver 300 may include a plurality of transmit shift registers 320 and a plurality of clock signal traces CLK connected to the plurality of transmit shift registers 320. In an embodiment, the plurality of clock signal traces CLK may be arranged in a plan view to overlap with the plurality of transmit shift registers 320. When the plurality of clock signal traces CLK are arranged in a plan view to overlap with the plurality of transmit shift registers 320, the bezel area of ​​the display device 1000 can be reduced.

[0066] The emitter shift register 320 may include emitter drive circuitry 20. In an embodiment, emitter drive circuitry 20 may include ninth emitter drive transistors T9 to twentieth emitter drive transistors T20 and third to fifth capacitors C3, C4, C5. Coupling may occur in some emitter drive transistors T9, T10, T13, T14, T17, T18, and T20 that are not directly subjected to multiple clock signals CLK1 and CLK3 as gate turn-on signals and are not directly subjected to constant voltages (i.e., the first constant voltage VGH and the second constant voltage VGL) as gate turn-on signals. Figure 5 In the emitter drive circuit 20, clock signal CLK1 can be applied as a gate turn-on signal to the fifteenth emitter drive transistor T15 and the nineteenth emitter drive transistor T19, clock signal CLK3 can be applied as a gate turn-on signal to the sixteenth emitter drive transistor T16, and the second constant voltage VGL can be applied as a gate turn-on signal to the eleventh emitter drive transistor T11 and the twelfth emitter drive transistor T12. Furthermore, the output signal EM is synchronized with the output signal OUT1 of the nth emitter shift register 320. <n>Correspondingly, the output signal OUT1 <n-1>To OUT1<n+2> These correspond to the output signals of the (n-1)th transmit shift register 320 to the (n+2)th transmit shift register 320, respectively.

[0067] Figure 5 The emitter drive circuit 20 is illustrated as including a p-type transistor, but the invention is not limited thereto. In another embodiment, the emitter drive circuit 20 may include an n-type transistor.

[0068] like Figure 6 As illustrated, the display panel 120 may include a substrate 510, a buffer layer 515, a gate insulating layer 520, a display panel transistor 598, a first interlayer insulating layer 530, a second interlayer insulating layer 535, a capacitor electrode 536, a first through-hole insulating layer 540, a connection electrode 556, a second through-hole insulating layer 550, a pixel defining layer 560, and an organic light-emitting diode 580. The display panel transistor 598 may include an active pattern 591, a source pattern 594, a drain pattern 595, and a gate pattern 596. The organic light-emitting diode 580 may include a lower electrode 555, an intermediate layer 565, and an upper electrode 570.

[0069] The substrate 510 may include, or be formed of, various materials such as quartz, synthetic quartz, calcium fluoride, fluorine-doped quartz, soda-lime glass, alkali-free glass, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, etc.

[0070] A buffer layer 515 may be disposed on the substrate 510. The buffer layer 515 can prevent metal atoms or impurities from diffusing from the substrate 510 to the pixel 400. The buffer layer 515 can achieve a substantially uniform active pattern 591 by controlling the heat transfer rate during the crystallization process used to form the active pattern 591. In addition, when the top surface of the substrate 510 is non-uniform, the buffer layer 515 can be used to improve the flatness of the top surface of the substrate 510. Two or more buffer layers 515 may be provided on the substrate 510 depending on the type of substrate 510. Alternatively, the buffer layer 515 may not be disposed on the substrate 510. That is, the buffer layer 515 may be omitted. In embodiments, the buffer layer 515 may comprise organic or inorganic materials. For example, the buffer layer 515 may have a single-layer or multi-layer structure comprising an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, or formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0071] The active pattern 591 can be disposed on the buffer layer 515. The active pattern 591 may include metal-oxide-semiconductor, inorganic semiconductor, or organic semiconductor, etc. The active pattern 591 may include a channel region, a source region, and a drain region.

[0072] A gate insulating layer 520 may be disposed on a buffer layer 515. The gate insulating layer 520 may cover the active pattern 591 on the buffer layer 515 and have a flat top surface without forming steps around the active pattern 591. Optionally, the gate insulating layer 520 may be disposed on the buffer layer 515 to have substantially the same thickness along the contour of the active pattern 591. The gate insulating layer 520 may include silicon compounds, metal oxides, etc. For example, the gate insulating layer 520 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc. In embodiments, the gate insulating layer 520 may have a multilayer structure comprising multiple insulating layers. The insulating layers may be of different materials and different thicknesses. These may be used individually or in combination with each other.

[0073] Gate pattern 596 can be disposed on gate insulating layer 520. Gate pattern 596 can be disposed on a portion of active pattern 591 located below gate insulating layer 520. Gate pattern 596 can include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, gate pattern 596 can be formed from one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can be formed as a single layer or multiple layers.

[0074] A first interlayer insulating layer 530 may be disposed on the gate insulating layer 520. The first interlayer insulating layer 530 may cover the gate pattern 596 on the gate insulating layer 520 and may have a flat top surface without forming steps around the gate insulating layer 520. Optionally, the first interlayer insulating layer 530 may be disposed on the gate insulating layer 520 to have substantially the same thickness along the contour of the gate pattern 596. The first interlayer insulating layer 530 may include silicon compounds, metal oxides, etc. For example, the first interlayer insulating layer 530 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc. In embodiments, the first interlayer insulating layer 530 may have a multilayer structure comprising multiple insulating layers. The insulating layers may be of different materials and different thicknesses. These may be used individually or in combination with each other.

[0075] The capacitor electrode 536 can be disposed on the first interlayer insulating layer 530. The capacitor electrode 536 can be disposed on a portion of the first interlayer insulating layer 530 below the gate pattern 596 thereunder. The capacitor electrode 536 can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the capacitor electrode 536 can include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), or be formed therefrom, and can be formed as a single layer or multiple layers.

[0076] The second interlayer insulating layer 535 may cover the capacitor electrode 536 on the first interlayer insulating layer 530 and may have a flat top surface without forming steps around the capacitor electrode 536. Optionally, the second interlayer insulating layer 535 may be disposed on the first interlayer insulating layer 530 to have substantially the same thickness along the contour of the capacitor electrode 536. The second interlayer insulating layer 535 may include silicon compounds, metal oxides, etc. For example, the second interlayer insulating layer 535 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc. In embodiments, the second interlayer insulating layer 535 may have a multilayer structure comprising multiple insulating layers. The insulating layers may be of different materials and different thicknesses. These may be used individually or in combination with each other.

[0077] Source pattern 594 and drain pattern 595 can be disposed on the second interlayer insulating layer 535. Source pattern 594 can be connected to the source region of active pattern 591 through contact holes passing through the first interlayer insulating layer 530, the second interlayer insulating layer 535, and the gate insulating layer 520. In an embodiment, source pattern 594 and the source region of active pattern 591 can constitute a source electrode. Drain pattern 595 can be connected to the drain region of active pattern 591 through contact holes passing through the first interlayer insulating layer 530, the second interlayer insulating layer 535, and the gate insulating layer 520. In an embodiment, drain pattern 595 and the drain region of active pattern 591 can constitute a drain electrode. Source pattern 594 and drain pattern 595 can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the source pattern 594 and the drain pattern 595 may include or be formed of one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or multiple layers.

[0078] A first via insulating layer 540 may be disposed on a second interlayer insulating layer 535 and may cover the source pattern 594 and the drain pattern 595. The first via insulating layer 540 may be disposed with a relatively thick thickness to sufficiently cover the source pattern 594 and the drain pattern 595, and in this case, the first via insulating layer 540 may have a substantially flat top surface. To achieve this flat top surface of the first via insulating layer 540, a planarization process may be added to the first via insulating layer 540. Optionally, the first via insulating layer 540 may cover the source pattern 594 and the drain pattern 595 and may be disposed with a uniform thickness along the contours of the source pattern 594 and the drain pattern 595. The first via insulating layer 540 may be made of organic or inorganic materials. In embodiments, the first via insulating layer 540 may be formed of organic materials such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0079] The connection electrode 556 can be disposed on the first via insulating layer 540. The connection electrode 556 can be connected to the source pattern 594 or the drain pattern 595 through a contact hole passing through the first via insulating layer 540. The connection electrode 556 can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the connection electrode 556 can be formed of one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can be formed as a single layer or multiple layers.

[0080] A second via insulating layer 550 can be disposed on the first via insulating layer 540 and can cover the connection electrode 556. The second via insulating layer 550 can be disposed with a relatively thick thickness to sufficiently cover the connection electrode 556, and in this case, the second via insulating layer 550 can have a substantially flat top surface. To achieve this flat top surface of the second via insulating layer 550, a planarization process can be added to the second via insulating layer 550. Optionally, the second via insulating layer 550 can cover the connection electrode 556 and can be disposed with a uniform thickness along the contour of the connection electrode 556. The second via insulating layer 550 can be made of organic or inorganic materials. In embodiments, the second via insulating layer 550 can comprise a material substantially the same as or similar to the first via insulating layer 540.

[0081] The lower electrode 555 can be disposed on the second through-hole insulating layer 550. The lower electrode 555 may include a transparent electrode, a reflective electrode, or a transflective electrode. The lower electrode 555 can be connected to the connecting electrode 556 through a contact hole passing through the second through-hole insulating layer 550. In an embodiment, the lower electrode 555 may be one of a positive electrode and a negative electrode.

[0082] A pixel defining layer 560 exposing a portion of the upper surface of the lower electrode 555 may be disposed on the second via insulating layer 550. The pixel defining layer 560 may include an organic material.

[0083] Intermediate layer 565 can be disposed on the lower electrode 555, a portion of its upper surface of which is exposed by pixel-defining layer 560. Intermediate layer 565 can have a structure in which hole injection layer, hole transport layer, light emission layer, electron transport layer, electron injection layer, etc., are stacked in single or complex structures.

[0084] The upper electrode 570 may be disposed on the intermediate layer 565. The upper electrode 570 may include a semi-transparent electrode or a reflective electrode. In one embodiment, the upper electrode 570 may be one of a cathode and a anode.

[0085] Figure 7 This is a plan view illustrating an embodiment of the driving transistor, and Figure 8 It is along Figure 7 The cross-sectional view taken from line II-II'.

[0086] refer to Figure 7 and Figure 8 , Figure 7 The transistors can be arranged in Figure 1 The transistors in the scan driver 200 or the emitter driver 300. Figure 7 The transistor can be with Figure 3 The scanning drive circuit 10 and Figure 5 This corresponds to the transistors in the emitter drive circuit 20 that are not directly supplied with a clock signal as a turn-on signal and are not directly supplied with a constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) as a turn-on signal. In the embodiment, Figure 7 The transistor can be with Figure 3 The second scan drive transistor T2, the fourth scan drive transistor T4, the sixth scan drive transistor T6, and the seventh scan drive transistor T7 correspond to one of them. In the embodiment, Figure 7 The transistor can be with Figure 5 This corresponds to one of the ninth emitter driver transistor T9, the tenth emitter driver transistor T10, the thirteenth emitter driver transistor T13, the fourteenth emitter driver transistor T14, the seventeenth emitter driver transistor T17, the eighteenth emitter driver transistor T18, and the twentieth emitter driver transistor T20. This is for Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 and Figure 21 The transistors can be the same.

[0087] The driving circuit 130 may include a substrate 510, a buffer layer 515, a gate insulating layer 520, a driving transistor 528a, a first interlayer insulating layer 530, a second interlayer insulating layer 535, a first via insulating layer 540, a second via insulating layer 550, a shielding pattern 527, and a clock signal wiring 545. The driving transistor 528a may include an active pattern 521, a source pattern 524, a drain pattern 525, and a gate pattern 526. In an embodiment, the source regions of the source pattern 524 and the active pattern 521 may constitute source electrodes, and the drain patterns 525 and the drain regions of the active pattern 521 may constitute drain electrodes.

[0088] The second interlayer insulation layer 535 may cover the shielding pattern 527 disposed on the first interlayer insulation layer 530 and may have a flat top surface without forming steps around it. Alternatively, the second interlayer insulation layer 535 may be disposed on the first interlayer insulation layer 530 to have substantially the same thickness along the contour of the shielding pattern 527.

[0089] Clock signal wiring 545 can be arranged on the first via insulating layer 540. Clock signals can be supplied through clock signal wiring 545. Figure 2 The scan shift register 220 and Figure 4 The transmit shift register 320. In an embodiment, clock signal wiring 545 can be connected to... Figure 6 The connection electrodes 556 are arranged in the same layer. The clock signal wiring 545 can be made by... Figure 6 The connecting electrodes 556 are formed simultaneously from the same material. In an embodiment, clock signal wiring 545 can be arranged on source pattern 524 and drain pattern 525. Clock signal wiring 545 can be arranged in a plan view to overlap with gate pattern 526. Since clock signal wiring 545 and gate pattern 526 are arranged to overlap each other in a plan view, parasitic capacitance may occur between clock signal wiring 545 and gate pattern 526. Coupling may occur between clock signal wiring 545 and gate pattern 526 due to parasitic capacitance. When coupling occurs, it may cause malfunctions in scan driver 200 and transmit driver 300. Coupling may cause malfunctions in scan signal and transmit signal. Due to the occurrence of malfunctions, short circuits may occur, which may increase power consumption. According to the invention, shielding pattern 527 can be arranged to prevent such coupling.

[0090] The shielding pattern 527 can be arranged on the first interlayer insulating layer 530. In an embodiment, the shielding pattern 527 can be... Figure 6 The capacitor electrodes 536 are arranged in the same layer. The shielding pattern 527 can be made of... Figure 6 The capacitor electrodes 536 are formed simultaneously from the same material.

[0091] A shielding pattern 527 can be arranged between the source pattern 524 and the drain pattern 525 so as not to overlap with either the source pattern 524 or the drain pattern 525 in a plan view. The shielding pattern 527 can be arranged between the gate pattern 526 and the clock signal wiring 545. The shielding pattern 527 can be arranged in a plan view to overlap with both the gate pattern 526 and the clock signal wiring 545. A constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) can be applied to the shielding pattern 527. Because the constant voltage has a constant polarity and magnitude, the shielding pattern 527 with the applied constant voltage can shield both the gate pattern 526 and the clock signal wiring 545 by being positioned between them. Since the shielding pattern 527 shields both the gate pattern 526 and the clock signal wiring 545, coupling that may occur between them can be effectively prevented.

[0092] The second via insulating layer 550 can be disposed on the clock signal wiring 545. The second via insulating layer 550 may comprise or be made of organic or inorganic materials. In an embodiment, the first via insulating layer 540 may be formed of an organic material such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0093] Figure 9 This is a plan view illustrating another embodiment of the driving transistor, and Figure 10 It is along Figure 9 The cross-sectional view taken from line III-III'.

[0094] refer to Figure 9 and Figure 10 The driving circuit 130 may include a substrate 510, a buffer layer 515, a gate insulating layer 520, an active pattern 521 and a gate pattern 526 for a driving transistor, a first interlayer insulating layer 530, a second interlayer insulating layer 535, a first via insulating layer 540, a second via insulating layer 550, a shielding pattern 527, a clock signal wiring 545, and a connection wiring 546. The active pattern 521 can electrically contact the source pattern 524 and the drain pattern 525 when turned on.

[0095] In an embodiment, the connection wiring 546 may be arranged in the same layer as the clock signal wiring 545. The connection wiring 546 may be arranged spaced apart from the clock signal wiring 545. The connection wiring 546 may be connected to the shielding pattern 527 through contact holes passing through the first via insulating layer 540 and the second interlayer insulating layer 535. A constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) may be applied to the connection wiring 546. The constant voltage applied to the connection wiring 546 may be transmitted to the shielding pattern 527 through the contact holes. The shielding pattern 527 can effectively prevent coupling between the clock signal wiring 545 and the gate pattern 526 by using a constant voltage. The connection wiring 546 may be arranged in the same layer as the clock signal wiring 545. The connection wiring 546 may be formed simultaneously from the same material as the clock signal wiring 545. In an embodiment, the connection wiring 546 and the clock signal wiring 545 may be arranged on the source pattern 524.

[0096] Figure 11 This is a plan view illustrating yet another embodiment of the driving transistor, and Figure 12 It is along Figure 11 The cross-sectional view taken from line IV-IV'.

[0097] refer to Figure 11 and Figure 12 The driving circuit 130 may include a substrate 510, a buffer layer 515, a gate insulating layer 520, an active pattern 521 and a gate pattern 526 for a driving transistor, a first interlayer insulating layer 530, a second interlayer insulating layer 535, a first via insulating layer 540, a second via insulating layer 550, a shielding pattern 527, a clock signal wiring 545, and a connection wiring 547. The active pattern 521 can electrically contact the source pattern 524 and the drain pattern 525 when turned on.

[0098] In the plan view, gate pattern 526 may partially overlap with active pattern 521 and may be arranged on gate insulating layer 520. Shielding pattern 527 may partially overlap with gate pattern 526 in the plan view and may be arranged on first interlayer insulating layer 530. Shielding pattern 527 may be arranged between clock signal wiring 545 and gate pattern 526 to prevent coupling between clock signal wiring 545 and gate pattern 526. Clock signal wiring 545 may be arranged in the plan view to overlap with shielding pattern 527 within the overlapping area of ​​gate pattern 526 and shielding pattern 527.

[0099] Connection wiring 547 can be disposed on the second interlayer insulation layer 535. Connection wiring 547 can be connected to shielding pattern 527 through contact holes passing through the second interlayer insulation layer 535. A constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) can be applied to connection wiring 547. The constant voltage applied to connection wiring 547 can be transmitted to shielding pattern 527 through contact holes. Shielding pattern 527 can effectively prevent coupling between clock signal wiring 545 and gate pattern 526 by using a constant voltage.

[0100] In one embodiment, the connection wiring 547 may be disposed on the same layer as the source pattern 524 and the drain pattern 525. The connection wiring 547 may comprise or be formed of the same material as the source pattern 524 and the drain pattern 525. In another embodiment, clock signal wiring 545 may be disposed on the source pattern 524, the drain pattern 525, and the connection wiring 547.

[0101] Figure 13 This is a plan view of yet another embodiment of the dual-gate transistor driving circuit, and Figure 14 It is along Figure 13 A cross-sectional view taken from line V-V'.

[0102] refer to Figure 13 and Figure 14 The driving circuit 130 may include a substrate 510, a buffer layer 515, a gate insulating layer 520, a driving transistor 528b, a first interlayer insulating layer 530, a second interlayer insulating layer 535, a first via insulating layer 540, a second via insulating layer 550, a shielding pattern 527, and a clock signal wiring 545. The driving transistor 528b may include an active pattern 521, a source pattern 524, a drain pattern 525, and a gate pattern 526.

[0103] Gate pattern 526 can be disposed on gate insulating layer 520. Gate pattern 526 can be a dual gate including first sub-gate pattern 526a and second sub-gate pattern 526b. First sub-gate pattern 526a and second sub-gate pattern 526b can be disposed between source pattern 524 and drain pattern 525 in a plan view. In an embodiment, shielding pattern 527 can shield both first sub-gate pattern 526a and second sub-gate pattern 526b to prevent coupling. Further, shielding pattern 527 can be disposed below the main surface plane of source pattern 524 and drain pattern 525 (which is disposed on second interlayer insulating layer 535). Clock signal wiring 545 can be disposed on source pattern 524 and drain pattern 525.

[0104] The shielding pattern 527 can be arranged in a plan view to overlap with the first sub-gate pattern 526a and the second sub-gate pattern 526b. The shielding pattern 527 can prevent coupling between the first sub-gate pattern 526a and the second sub-gate pattern 526b and the clock signal wiring 545.

[0105] Figure 15 This is a plan view of another embodiment of the dual-gate transistor driving circuit, and Figure 16 It is along Figure 15 The cross-sectional view taken from line VI-VI'.

[0106] like Figure 15 and Figure 16 As illustrated, the shielding pattern 527 can overlap with one of the first sub-gate pattern 526a and the second sub-gate pattern 526b in a plan view.

[0107] Figure 17 This is a plan view of yet another embodiment of the dual-gate transistor driving circuit, and Figure 18 It is along Figure 17 The cross-sectional view taken from line VII-VII'.

[0108] refer to Figure 17 and Figure 18 The driving circuit 130 may include a substrate 510, a buffer layer 515, a gate insulating layer 520, a driving transistor 528c, a first interlayer insulating layer 530, a second interlayer insulating layer 535, a first via insulating layer 540, a second via insulating layer 550, a shielding pattern 527, and a clock signal wiring 545. The driving transistor 528c may include an active pattern 521, a source pattern 524, a drain pattern 525, and a gate pattern 526. The source pattern 524 may include a first sub-source pattern 524a and a second sub-source pattern 524b.

[0109] The gate pattern 526 can be disposed on the gate insulating layer 520. The gate pattern 526 can be a dual gate including a first sub-gate pattern 526a and a second sub-gate pattern 526b. The first sub-gate pattern 526a and the second sub-gate pattern 526b can be disposed between the first sub-source pattern 524a and the second sub-source pattern 524b.

[0110] A shielding pattern 527 may be disposed on the first interlayer insulating layer 530. The shielding pattern 527 may include a first sub-shielding pattern 527a and a second sub-shielding pattern 527b. The shielding pattern 527 may be arranged to overlap with the gate pattern 526 in a plan view. In an embodiment, the first sub-shielding pattern 527a may be arranged to overlap with the first sub-gate pattern 526a in a plan view, and the second sub-shielding pattern 527b may be arranged to overlap with the second sub-gate pattern 526b in a plan view. This effectively prevents coupling between the clock signal wiring 545 and each of the first sub-gate pattern 526a and the second sub-gate pattern 526b.

[0111] The first sub-source pattern 524a, the second sub-source pattern 524b, and the drain pattern 525 can be arranged on the second interlayer insulating layer 535. The first sub-source pattern 524a and the second sub-source pattern 524b can be connected to the first source region and the second source region of the active pattern 521 through contact holes passing through the gate insulating layer 520, the first interlayer insulating layer 530, and the second interlayer insulating layer 535. The drain pattern 525 can be connected to the drain region of the active pattern 521 through contact holes passing through the gate insulating layer 520, the first interlayer insulating layer 530, and the second interlayer insulating layer 535. In an embodiment, clock signal wiring 545 can be arranged on the first sub-source pattern 524a, the second sub-source pattern 524b, and the drain pattern 525.

[0112] Figure 19 This is a plan view of yet another embodiment of the dual-gate transistor driving circuit, and Figure 20 It is along Figure 19 The cross-sectional view taken from line VIII-VIII'.

[0113] like Figure 19 and Figure 20 As illustrated, the shielding pattern 527 can overlap with one of the first sub-gate pattern 526a and the second sub-gate pattern 526b in a plan view.

[0114] Figure 21 This is a plan view illustrating another embodiment of the driving transistor, and Figure 22 It is along Figure 21 The cross-sectional view taken from line IX-IX'.

[0115] refer to Figure 21 and Figure 22 The driving circuit 130 may include a substrate 510, a buffer layer 515, a gate insulating layer 520, a driving transistor 528a, a first interlayer insulating layer 530, a second interlayer insulating layer 535, a first via insulating layer 540, a second via insulating layer 550, a clock signal wiring 548, and a shielding pattern 549. The driving transistor 528a may include an active pattern 521, a source pattern 524, a drain pattern 525, and a gate pattern 526.

[0116] A shielding pattern 549 may be disposed on the first via insulating layer 540. In a plan view, the shielding pattern 549 may be arranged to overlap with the gate pattern 526. In a plan view, the shielding pattern 549 may not overlap with the source pattern 524 and the drain pattern 525. A constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) may be applied to the shielding pattern 549. When a constant voltage is applied to the shielding pattern 549, the shielding pattern 549 may shield the gate pattern 526. In an embodiment, the shielding pattern 549 may be disposed with... Figure 10 The connection wiring 546 is arranged in the same layer. That is, the shielding pattern 549 can be arranged on the source pattern 524 and the drain pattern 525.

[0117] Clock signal wiring 548 can be arranged on the second via insulating layer 550. Clock signal wiring 548 can be arranged on shielding pattern 549. Clock signals can flow through clock signal wiring 548. Since shielding pattern 549 is arranged to overlap with gate pattern 526 in the plan view, coupling between gate pattern 526 and clock signal wiring 548 can be effectively prevented. Shielding pattern 549 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These can be used individually or in combination with each other.

[0118] The inventive concept can be applied to display devices and electronic devices including such display devices. For example, the inventive concept can be applied to smartphones, cellular phones, video phones, smart tablets, smartwatches, tablet PCs, car navigation systems, televisions, computer monitors, portable computers, head-mounted displays, MP3 players, etc.

[0119] The foregoing is illustrative of the embodiments and should not be construed as limiting the embodiments. Although embodiments have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. It is therefore to be understood that the foregoing is illustrative of the embodiments and should not be construed as limiting oneself to the disclosed exemplary embodiments, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. < / n> < / n>

Claims

1. A display device, comprising: Display panel; A driving circuit that provides driving signals to the display panel and includes at least one driving transistor; as well as Clock signal wiring, which provides the clock signal to the drive circuit. The driving circuit includes an active pattern, a gate pattern, a source pattern, and a shielding pattern. The gate pattern overlaps with the active pattern in a planar view. The main surface plane of the source pattern is arranged in a different layer than the layer in which the active pattern is arranged. The source pattern is electrically connected to the active pattern. The shielding pattern is arranged between the gate pattern and the clock signal wiring and is subjected to a constant voltage. The clock signal wiring overlaps with the gate pattern in the plan view and is arranged on the source pattern.

2. The display device according to claim 1, wherein, The shielding pattern is arranged below the main surface plane of the source pattern.

3. The display device according to claim 1, wherein, The shielding pattern overlaps in the plan view and the entire area where the gate pattern overlaps with the clock signal wiring.

4. The display device according to claim 1, further comprising: The connecting wiring is arranged in the same layer as the clock signal wiring, and the connecting wiring transmits the constant voltage to the shielding pattern.

5. The display device according to claim 1, further comprising: A connecting wire is arranged between the shielding pattern and the clock signal wiring, and the connecting wire transmits the constant voltage to the shielding pattern.

6. The display device according to claim 5, wherein, The connection wiring does not overlap with each of the clock signal wiring and the gate pattern in the plan view.

7. The display device according to claim 1, wherein, The grid pattern includes a first sub-grid pattern and a second sub-grid pattern.

8. The display device according to claim 7, wherein, The first sub-gate pattern and the second sub-gate pattern are arranged below the main surface plane of the source pattern.

9. The display device according to claim 8, wherein, The first sub-grid pattern and the second sub-grid pattern overlap with the shielding pattern in the plan view.

10. The display device according to claim 8, wherein, Only one of the first sub-grid pattern and the second sub-grid pattern overlaps with the shielding pattern in the plan view.

11. The display device according to claim 7, wherein, The first sub-gate pattern and the second sub-gate pattern are arranged in the same layer.

12. The display device according to claim 11, wherein, The driving circuit further includes a drain pattern disposed between the first sub-gate pattern and the second sub-gate pattern and electrically connected to the active pattern.

13. The display device according to claim 12, wherein, Only one of the first sub-grid pattern and the second sub-grid pattern overlaps with the shielding pattern in the plan view.

14. The display device according to claim 12, wherein, The shielding pattern includes a first sub-shielding pattern and a second sub-shielding pattern.

15. The display device according to claim 14, wherein, The first sub-gate pattern and the second sub-gate pattern overlap with the first sub-shielding pattern and the second sub-shielding pattern, respectively, in the plan view.

16. The display device according to claim 1, wherein, The shielding pattern is arranged on the source pattern.

17. The display device according to claim 1, wherein, The driving circuit includes a p-type transistor.

18. The display device according to claim 1, wherein, The driving circuit includes an n-type transistor.

19. The display device according to claim 1, wherein, The driving circuit includes a dual-gate transistor.

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