Display device

Abstract

A display device includes: a plurality of first pixels, the plurality of first pixels being connected to a first scan line and a first data line; a plurality of second pixels, the plurality of second pixels being connected to a second scan line and the first data line; a plurality of third pixels, the plurality of third pixels being connected to the second data line and the first scan line or the second scan line; and a scan driver, the scan driver including a plurality of stages for supplying scan signals to one of the first scan line and the second scan line.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device. Background Art

[0002] With the development of the information society, display devices for displaying images have been used in various fields. For example, such display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigators, and smart TVs. The display device can be a flat panel display device, such as a liquid crystal display device, a field emission display device, or a light-emitting display device. Since the light-emitting display device among the flat panel display devices includes a light-emitting element in which each pixel in the display panel emits light by itself, the light-emitting display device can display images without using a backlight unit for providing light to the display panel.

[0003] A display device generally includes: a display panel including data lines, scan lines, and pixels connected to the data lines and the scan lines; a data driver for supplying data signals to the data lines; and a scan driver including a shift register for supplying scan signals to the scan lines. Summary of the Invention

[0004] In a display device, pixels emitting light of different colors may be connected to the same data line. In such a display device, a lighting voltage may be applied to each of the pixels connected to the same data line to perform a lighting check on the pixels. As the resolution of the display device increases, the charging rate of the data line may decrease.

[0005] An embodiment of the present invention will provide a display device in which a lighting voltage can be applied to each of a plurality of pixels connected to one data line and emitting light of different colors from each other, and a reduction in the charging rate of the data line can be prevented to effectively check the lighting of each of the pixels.

[0006] According to an embodiment of the present disclosure, a display device includes: a plurality of first pixels, the plurality of first pixels being connected to a first data line and a plurality of first scan lines; a plurality of second pixels, the plurality of second pixels being connected to a first data line and a plurality of second scan lines; a plurality of third pixels, the plurality of third pixels being connected to a second data line and a first scan line or a second scan line; and a scan driver, the scan driver including a plurality of stages for supplying a scan signal to one of the first scan line and the second scan line.

[0007] In an embodiment, the plurality of stages may include: a plurality of first stages, which sequentially supply a scan signal to each of a plurality of first scan lines based on a first start signal; and a plurality of second stages, which sequentially supply a scan signal to each of a plurality of second scan lines based on a second start signal.

[0008] In an embodiment, the first stage may include: a first-first stage, the first-first stage outputting a first-first scanning signal based on the first start signal; and a second-first stage, the second-first stage outputting a second-first scanning signal based on the first-first scanning signal.

[0009] In an embodiment, the second stage may include: a first-second stage, the first-second stage outputting a first-second scanning signal based on the second start signal; and a second-second stage, the second-second stage outputting a second-second scanning signal based on the first-second scanning signal.

[0010] In an embodiment, the display device may further include a first test transistor that supplies a first lighting voltage to the first data line based on a test gate signal; and a second test transistor that supplies a second lighting voltage to the second data line based on the test gate signal.

[0011] In an embodiment, when the first light-up voltage has a first voltage level that turns on the first pixel or the second pixel, the second light-up voltage may have a second voltage level that turns off the first pixel or the second pixel.

[0012] In an embodiment, the plurality of stages may include: a plurality of first stages, which sequentially supply a scan signal to each of a plurality of first scan lines when a start signal is supplied during a first period; and a plurality of second stages, which sequentially supply a scan signal to each of a plurality of second scan lines when a start signal is supplied during a second period different from the first period.

[0013] In an embodiment, the first stage may include: a first-first stage, which outputs a first-first scanning signal when a start signal is supplied during a first period; and a second-first stage, which outputs a second-first scanning signal based on the first-first scanning signal.

[0014] In an embodiment, the second stage may include: a first-second stage, which outputs a first-second scanning signal when a start signal is supplied during a second period; and a second-second stage, which outputs a second-second scanning signal based on the first-second scanning signal.

[0015] In an embodiment, the first pixel may be connected to the second scan line and the third data line, the second pixel may be connected to the first scan line and the third data line, and the third pixel may be connected to the fourth data line and the first scan line or the second scan line.

[0016] In an embodiment, the display device may further include: a first test transistor that supplies the first lighting voltage to the first data line based on the first test gate signal; and a second test transistor that supplies the first lighting voltage to the third data line based on the second test gate signal.

[0017] In an embodiment, the display device may further include: a third test transistor that supplies a third lighting voltage to the third data line based on the first test gate signal; and a fourth test transistor that supplies the third lighting voltage to the first data line based on the second test gate signal.

[0018] In an embodiment, when the first light-up voltage has a first voltage level that turns on the first pixel or the second pixel, the third light-up voltage may have a second voltage level that turns off the first pixel or the second pixel.

[0019] In an embodiment, when the third light-up voltage has a first voltage level that turns on the first pixel or the second pixel, the first light-up voltage may have a second voltage level that turns off the first pixel or the second pixel.

[0020] In an embodiment, the display device may further include: a fifth test transistor that supplies the second lighting voltage to the second data line based on the third test gate signal, and a sixth test transistor that supplies the second lighting voltage to the fourth data line based on the third test gate signal.

[0021] In an embodiment, multiple first pixels may be connected to the second scan line and the third data line, multiple second pixels may be connected to the first scan line and the third data line, and multiple third pixels may be connected to the fourth data line and the first scan line or the second scan line.

[0022] In an embodiment, the display device may further include: a first test transistor that supplies the first lighting voltage to the first data line based on the first test gate signal; and a second test transistor that supplies the first lighting voltage to the third data line based on the second test gate signal.

[0023] In an embodiment, the display device may further include: a third test transistor that supplies a third lighting voltage to the third data line based on the first test gate signal; and a fourth test transistor that supplies the third lighting voltage to the first data line based on the second test gate signal.

[0024] In an embodiment, when the first light-up voltage has a first voltage level that turns on the first pixel or the second pixel, the third light-up voltage may have a second voltage level that turns off the first pixel or the second pixel.

[0025] In an embodiment, the display device may further include: a fifth test transistor that supplies the second lighting voltage to the second data line based on the third test gate signal, and a sixth test transistor that supplies the second lighting voltage to the fourth data line based on the third test gate signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present invention will become more apparent by describing in detail embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 is a perspective view of a display device according to an embodiment;

[0028] Figure 2 is a plan view of a display device according to an embodiment;

[0029] Figure 3 is a block diagram of a display device according to an embodiment;

[0030] Figure 4 is a circuit diagram illustrating a pixel of a display device according to an embodiment;

[0031] Figure 5 is a block diagram illustrating a scan driver of a display device according to an embodiment;

[0032] Figure 6 is a waveform diagram illustrating input / output signals of a scan driver in a display device according to an embodiment;

[0033] Figure 7 The diagram shows Figure 5 Waveform diagrams of input / output signals of odd-numbered stages in a display device;

[0034] Figure 8 is a diagram illustrating a process of supplying a lighting voltage in a display device according to an embodiment;

[0035] Figure 9 is a waveform diagram illustrating a lighting voltage and a test gate signal in a display device according to an embodiment;

[0036] Figure 10 The diagram shows Figure 9 A diagram showing a result of a lighting inspection of a first pixel in a display device;

[0037] Figure 11is a waveform diagram illustrating a lighting voltage and a test gate signal in a display device according to an alternative embodiment;

[0038] Figure 12 The diagram shows Figure 11 A diagram showing a result of a lighting inspection of a second pixel in a display device;

[0039] Figure 13 The diagram shows Figure 5 Waveform diagram of input / output signals of even-numbered stages in a display device;

[0040] Figure 14 The diagram shows Figure 13 A diagram showing a result of a lighting inspection of a second pixel in a display device;

[0041] Figure 15 The diagram shows Figure 13 A diagram showing a result of a lighting inspection of a first pixel in a display device;

[0042] Figure 16 is a block diagram illustrating a scan driver of a display device according to an alternative embodiment;

[0043] Figure 17 The diagram shows Figure 16 Waveform diagrams of input / output signals of odd-numbered stages in a display device;

[0044] Figure 18 The diagram shows Figure 16 Waveform diagram of input / output signals of even-numbered stages in a display device;

[0045] Figure 19 is a plan view of a display device according to an alternative embodiment;

[0046] Figure 20 is a diagram illustrating a process of supplying a lighting voltage in a display device according to an alternative embodiment;

[0047] Figure 21 is a waveform diagram illustrating a lighting voltage and a test gate signal in a display device according to an embodiment; and

[0048] Figure 22 is a waveform diagram illustrating a light-up voltage and a test gate signal in a display device according to an alternative embodiment. DETAILED DESCRIPTION

[0049] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. As those skilled in the art will recognize, the described embodiments can be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0050] Parts irrelevant to the description will be omitted to clearly describe the present disclosure, and the same reference numerals denote the same elements throughout the specification.

[0051] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise indicated, the presence or absence of cross hatching or shading cannot convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the illustrated elements and / or any other feature, attribute, characteristic, etc. of the elements. Further, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, a particular process can be performed in an order different from the order described. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the order described.

[0052] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on, connected to or coupled to another element or layer, or there can be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this reason, the term "connected" can refer to physical, electrical and / or fluid connections with or without intermediate elements. Further, the X-axis, Y-axis and Z-axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis and a z-axis) and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] Although the terms "first," "second," etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0054] Spatially relative terms, such as, for example, "below," "beneath," "lower," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes and thereby to describe the relationship of one element to another element(s) as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture other than the orientation depicted in the accompanying drawings. For example, if the device in the drawings were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0055] As used herein, the term "comprising" and "including" are intended to include plural forms unless otherwise clearly indicated by context. In addition, when the term "comprising" and its variations and / or "including" and its variations are used in this specification, the existence of the features, integers, steps, operations, elements, parts and / or its combination stated is specified, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or its combination is not excluded. It should also be noted that, as used herein, the term "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and therefore, are utilized to explain the measured values, calculated values ​​and / or the inherent deviation in the provided values ​​that those of ordinary skill in the art will recognize.

[0056] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations, which are schematic illustrations of idealized embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations, for example due to manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the regions, but should include deviations in shape, for example due to manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not necessarily intended to be limiting.

[0057] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings with functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections, etc.), and electronic (or optical) circuits can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. When blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and a processor performing other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the present invention. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0059] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 is a perspective view of a display device according to an embodiment, Figure 2 is a plan view of a display device according to an embodiment, and Figure 3 is a block diagram of a display device according to an embodiment.

[0061] In this specification, "upper," "above," "top," "upper side," or "upper surface" refers to the upward direction relative to the display device 10, that is, the Z-axis direction, and "lower side," "lower side," "bottom," "bottom side," or "lower surface" refers to the downward direction relative to the display device 10, that is, the direction opposite to the Z-axis direction. Furthermore, "left," "right," "upper," and "lower" refer to directions when the display device 10 is viewed from a plane. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Z-axis direction, and "lower" refers to the direction opposite to the Z-axis direction.

[0062] Reference Figures 1 to 3 , embodiments of the display device 10 as a device for displaying moving images or still images may be devices including a display screen such as a television, a laptop or notebook computer, a display, a billboard, the Internet of Things (“IOT”), and portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (“PC”), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (“PMP”), a navigator, and an ultra mobile PC (“UMPC”).

[0063] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro light-emitting display device using a micro light-emitting diode. Hereinafter, for ease of description, an embodiment in which the display device 10 is an organic light-emitting display device will be described, but the present invention is not limited thereto.

[0064] An embodiment of the display device 10 may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0065] The display panel 100 may have a rectangular planar shape having a short side along a first direction (X-axis direction) and a long side along a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The corner where the short side in the first direction (X-axis direction) meets the long side in the second direction (Y-axis direction) may have a right angle shape or a circular shape with a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangular shape and may be modified variously into another polygonal shape, a circular shape, or an elliptical shape. The display panel 100 may be flat, but the shape of the display panel 100 is not limited thereto. The display panel 100 may include a curved portion at the left and right ends of the display panel 100 and having a constant curvature or a variable curvature. The display panel 100 may be flexibly formed to be warped, bent, folded, or curled.

[0066] The display panel 100 may include a display area DA in which pixels SP are arranged to display an image, and a non-display area NDA that is a peripheral area of ​​the display area DA. The display area DA may include pixels SP, scan lines SL connected to the pixels SP, emission control lines EL, data lines DL, and voltage supply lines VL. The scan lines SL and the emission control lines EL may be arranged in parallel in a first direction. The data lines DL and the voltage supply lines VL may be arranged in parallel in a second direction that intersects the first direction.

[0067] Each of the pixels SP may be connected to a corresponding scan line SL, a corresponding data line DL, a corresponding emission control line EL, and a corresponding voltage supply line VL. Figure 2 In the embodiment in which each pixel SP is connected to two scan lines SL, one data line DL, one emission control line EL, and one voltage supply line VL, the present invention is not limited thereto. In an alternative embodiment, for example, each pixel SP may be connected to three scan lines SL.

[0068] The pixel SP may include first to third pixels RP, BP, and GP. The first pixel RP may be connected to the first data line DL1 and the first scan line SL1. The second pixel BP may be connected to the first data line DL1 and the second scan line SL2. The first pixel RP and the second pixel BP may be connected to the same data line DL, and may be connected to scan lines SL different from each other. The first pixel RP may be arranged in odd rows to be connected to the scan lines SL1, SL3, ..., SL(n-1) (n is a multiple of 2) of the odd rows, and the second pixel BP may be arranged in even rows to be connected to the scan lines SL2, SL4, ..., SLn in the even rows. The first pixel RP and the second pixel BP are not limited to Figure 2 , and may be alternately arranged along the same data line DL. In one embodiment, for example, the scan driver 400 may perform a lighting check of the first pixel RP by supplying a scan signal to some of the plurality of scan lines SL. In an alternative embodiment, for example, the scan driver 400 may perform a lighting check of the second pixel BP by supplying a scan signal to other scan lines of the plurality of scan lines SL.

[0069] The third pixel GP may be connected between a corresponding scan line among the plurality of scan lines SL and the second data line DL2. The third pixel GP may be arranged along the same data line DL. In one embodiment, for example, the first pixel RP and the second pixel BP may be connected to odd-numbered data lines DL1, DL3, ..., DL(m-1) (m is a multiple of 2), and the third pixel GP may be connected to even-numbered data lines DL2, DL4, ..., DLm.

[0070] Each pixel SP may include a driving transistor, a switching transistor, a light-emitting element, and a capacitor. When a scan signal is applied from a scan line SL, the switching transistor may be turned on, and thus, the data voltage of the data line DL may be applied to the gate electrode of the driving transistor. The driving transistor may supply a driving current to the light-emitting element based on the data voltage applied to the gate electrode, and the light-emitting element may emit light having a predetermined brightness corresponding to the intensity of the driving current. In one embodiment, for example, the driving transistor and the switching transistor may be thin film transistors. The light-emitting element may be an organic light-emitting diode including a first electrode, an organic light-emitting layer, and a second electrode. The capacitor may maintain a constant data voltage applied to the gate electrode of the driving transistor.

[0071] The non-display area NDA may be defined as an area from the display area DA to an edge of the display panel 100. The non-display area NDA may further include a scan driver 400 for applying a scan signal to the scan line SL, a fan-out line between the data line DL and the display driver 200, a pad DP connected to the display driver 200 to supply a data voltage, a test pad TP for supplying a light-up voltage, and a test gate pad TGP for supplying a test gate signal.

[0072] In one embodiment, for example, the display driver 200 may be disposed on one side of the display panel 100, and the pads DP, the test pads TP, and the test gate pads TGP may be disposed at an edge portion of the display panel 100. The pads DP, the test pads TP, and the test gate pads TGP may be disposed closer to the edge of the display panel 100 than the display driver 200.

[0073] The test pads TP may include first to third test pads TP1, TP2, and TP3. The first to third test pads TP1, TP2, and TP3 may receive first to third lighting voltages, respectively. Each of the first to third lighting voltages may be a grayscale voltage for turning on the pixel SP or a black voltage for turning off the pixel SP. Each of the first to third lighting voltages may be a DC voltage, but is not limited thereto. In one embodiment, for example, the first to third test pads TP1, TP2, and TP3 may be connected to a lighting device or a power supply device and may receive the first to third lighting voltages.

[0074] The non-display area NDA may further include test transistors connected between the test pad TP and the display driver 200. The test transistors may include first to fourth test transistors TT1 to TT4. The first test transistor TT1 may be connected between the first test pad TP1 and the first data line DL1, and the second test transistor TT2 may be connected between the second test pad TP2 and the second data line DL2. The third test transistor TT3 may be connected between the third test pad TP3 and the third data line DL3, and the fourth test transistor TT4 may be connected between the second test pad TP2 and the fourth data line DL4. Each of the first to fourth test transistors TT1 to TT4 may be connected between a corresponding test pad among the test pads TP and a corresponding data line DL among the plurality of data lines DL, thereby selectively supplying the first to third lighting voltages to the plurality of data lines. In one embodiment, for example, each of the first to fourth test transistors TT1 to TT4 may receive the same test gate signal to be turned on or off simultaneously.

[0075] The test gate pad TGP may receive a test gate signal and may be connected to a gate electrode of each of the first to fourth test transistors TT1 to TT4. In one embodiment, for example, the test gate pad TGP may be connected to a lighting device and may receive a test gate signal from the lighting device to turn on the first to fourth test transistors TT1 to TT4.

[0076] The scan driver 400 may be connected to the display driver 200 through a plurality of scan control lines SCL. The scan driver 400 may receive a scan control signal SCS and an emission control signal ECS from the display driver 200 through the plurality of scan control lines SCL.

[0077] In an embodiment, Figure 3 As shown in , the scan driver 400 may include a scan driving circuit 410 and an emission control driving circuit 420 .

[0078] The scan driving circuit 410 may generate a scan signal based on the scan control signal SCS and may sequentially output the scan signal to the scan lines SL. The emission control driving circuit 420 may generate an emission signal corresponding to the emission control signal ECS from the display driver 200 and may sequentially output the emission signal to the emission control lines EL.

[0079] The scan driver 400 may include a plurality of thin film transistors. The scan driver 400 may be formed in the same layer as the thin film transistors of the pixels SP. Figure 2As shown in FIG, the scan driver 400 is formed in the non-display area NDA located on one side (e.g., the left side) of the display area DA, but the present invention is not limited thereto. In an alternative embodiment, for example, the scan driver 400 may be formed in the non-display area NDA located on two opposite sides (e.g., the left and right sides) of the display area DA.

[0080] In an embodiment, Figure 3 As shown in , the display driver 200 may include a timing controller 210 , a data driver 220 , and a power supply unit 230 .

[0081] The timing controller 210 may receive digital video data DATA and a timing signal from the circuit board 300. Based on the timing signal, the timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220, a scan control signal SCS for controlling the operation timing of the scan driving circuit 410, and an emission control signal ECS for controlling the operation timing of the emission control driving circuit 420. The timing controller 210 may supply the digital video data DATA and the data control signal DCS to the data driver 220. The timing controller 210 may supply the scan control signal SCS to the scan driving circuit 410 via a plurality of scan control lines SCL, and may supply the emission control signal ECS to the emission control driving circuit 420.

[0082] The data driver 220 may convert the digital video data DATA into analog data voltages and supply the analog data voltages to the data lines DL through the fan-out lines. The scan signals of the scan driver 400 may select pixels SP to which data voltages are supplied, and the data driver 220 may supply the data voltages to the selected pixels SP.

[0083] The power supply unit 230 may generate a first driving voltage and supply the first driving voltage to the voltage supply line VL. The power supply unit 230 may generate a second driving voltage and supply the second driving voltage to the cathode electrode of the light-emitting element of each pixel SP. Here, the first driving voltage may be a high potential voltage for driving the light-emitting element, and the second driving voltage may be a low potential voltage for driving the light-emitting element. That is, the first driving voltage may have a higher potential than the second driving voltage.

[0084] In an embodiment, the display driver 200 is formed as an integrated circuit ("IC") and can be attached to the display panel 100 by a chip-on-glass ("COG") method, a chip-on-plastic ("COP") method, or an ultrasonic bonding method. However, the present invention is not limited thereto. In an alternative embodiment, for example, the display driver 200 can be attached to the circuit board 300.

[0085] The circuit board 300 may be attached to the pad DP using an anisotropic conductive film. Thus, the leads of the circuit board 300 may be electrically connected to the pad DP. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0086] Figure 4 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0087] Reference Figures 2 to 4 In an embodiment, the pixels SP may be arranged along a plurality of rows and a plurality of columns on the display panel 100. In one embodiment, for example, the pixels SP may be arranged in the k-th row and the j-th column of the display area DA. In this case, the pixels SP may be connected to the (k-1)-th (herein, k is a natural number of 2 or greater) scan line SL(k-1), the k-th scan line SLk, the k-th emission control line ELk, and the j-th (herein, j is a natural number) data line DLj. In such an embodiment, the pixels SP may be connected to a voltage supply line VL that supplies a first driving voltage VDD, an initialization voltage line that supplies an initialization voltage VINT, and a voltage supply line that supplies a second driving voltage VSS.

[0088] The pixel SP may include a driving transistor DT, a light emitting element E, a switching element, and a first capacitor C1. In one embodiment, for example, the switching element may include first to sixth switching transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0089] The driving transistor DT controls a source-drain current (Isd) (hereinafter referred to as "driving current") based on a data voltage applied to a gate electrode. When the source-gate voltage (Vsg) of the driving transistor DT exceeds a threshold voltage (Vth), the driving current (Isd) may flow through the channel of the driving transistor DT. In one embodiment, for example, the driving current (Isd) is proportional to the square of the difference between the gate-source voltage (Vsg) and the threshold voltage (Vth) of the driving transistor DT, as shown in Equation 1 below.

[0090] [Equation 1]

[0091] Isd=k′X(Vsg-Vth) 2

[0092] In Equation 1, k′ represents a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vsg represents a source-gate voltage of the driving transistor DT, and Vth represents a threshold voltage of the driving transistor DT.

[0093] The light emitting element E may receive a driving current (Isd) to emit light. The emission amount or brightness of the light emitting element E may be proportional to the intensity of the driving current (Isd).

[0094] The light-emitting element E may be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. Alternatively, the light-emitting element E may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. Alternatively, the light-emitting element E may be a quantum dot light-emitting element comprising a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first electrode and the second electrode. Alternatively, the light-emitting element E may be a micro light-emitting diode. In one embodiment, for example, the first electrode of the light-emitting element E may be an anode electrode, and the second electrode of the light-emitting element E may be a cathode electrode, but the present invention is not limited thereto.

[0095] The first electrode or anode electrode of the light emitting element E can be connected to the second electrode or drain electrode of the fourth switching transistor ST4 and the second electrode or drain electrode of the sixth switching transistor ST6. The second electrode or cathode electrode of the light emitting element E can be connected to a voltage supply line supplying the second driving voltage VSS.

[0096] The first switching transistor ST1 can selectively supply an initialization voltage VINT to the gate electrode of the driving transistor DT. In one embodiment, for example, the first switching transistor ST1 can be a dual transistor including a first-first switching transistor ST1-1 and a second-first switching transistor ST1-2. The first-first switching transistor ST1-1 and the second-first switching transistor ST1-2 can be turned on in response to a scan signal of the (k-1)th scan line SL(k-1) to supply the initialization voltage VINT to the gate electrode of the driving transistor DT. The gate electrode of the driving transistor DT can receive the initialization voltage VINT to be discharged. The gate electrode of the first-first switching transistor ST1-1 can be connected to the (k-1)th scan line SL(k-1), the first electrode of the first-first switching transistor ST1-1 can be connected to the initialization voltage line that supplies the initialization voltage VINT, and the second electrode of the first-first switching transistor ST1-1 can be connected to the first electrode of the second-first switching transistor ST1-2. The gate electrode of the second-first switching transistor ST1-2 may be connected to the (k-1)th scan line SL(k-1), the first electrode of the second-first switching transistor ST1-2 may be connected to the second electrode of the first-first switching transistor ST1-1, and the second electrode of the second-first switching transistor ST1-2 may be connected to the gate electrode of the driving transistor DT. In one embodiment, for example, the first electrode of the first switching transistor ST1 may be a source electrode, and the second electrode of the first switching transistor ST1 may be a drain electrode.

[0097] The second switching transistor ST2 can selectively supply a data voltage to the first electrode of the driving transistor DT. The second switching transistor ST2 can be turned on in response to a scan signal of the k-th scan line SLk to supply the data voltage to the first electrode of the driving transistor DT. The gate electrode of the second switching transistor ST2 can be connected to the k-th scan line SLk, the first electrode of the second switching transistor ST2 can be connected to the j-th data line DLj, and the second electrode of the second switching transistor ST2 can be connected to the first electrode of the driving transistor DT. In one embodiment, for example, the first electrode of the second switching transistor ST2 can be a source electrode, and the second electrode of the second switching transistor ST2 can be a drain electrode.

[0098] The third switching transistor ST3 can selectively connect the second electrode and gate electrode of the driving transistor DT. In one embodiment, for example, the third switching transistor ST3 can be a dual transistor including a first-third switching transistor ST3-1 and a second-third switching transistor ST3-2. The first-third switching transistor ST3-1 and the second-third switching transistor ST3-2 can be turned on in response to a scan signal of the k-th scan line SLk to connect the second electrode and gate electrode of the driving transistor DT. That is, when the first-third switching transistor ST3-1 and the second-third switching transistor ST3-2 are turned on, the second electrode and gate electrode of the driving transistor DT are connected, and thus, the driving transistor DT can be driven as a diode. The gate electrode of the first-third switching transistor ST3-1 can be connected to the k-th scan line SLk, the first electrode of the first-third switching transistor ST3-1 can be connected to the second electrode of the driving transistor DT, and the second electrode of the first-third switching transistor ST3-1 can be connected to the first electrode of the second-third switching transistor ST3-2. The gate electrodes of the second-third switching transistors ST3-2 may be connected to the k-th scan line SLk, the first electrodes of the second-third switching transistors ST3-2 may be connected to the second electrodes of the first-third switching transistors ST3-1, and the second electrodes of the second-third switching transistors ST3-2 may be connected to the gate electrode of the driving transistor DT. In one embodiment, for example, the first electrode of the third switching transistor ST3 may be a source electrode, and the second electrode of the third switching transistor ST3 may be a drain electrode.

[0099] The fourth switching transistor ST4 can selectively supply an initialization voltage VINT to the first electrode of the light-emitting element E. The fourth switching transistor ST4 can be turned on in response to a scan signal of the k-th scan line SLk to supply the initialization voltage VINT to the first electrode of the light-emitting element E. The first electrode of the light-emitting element E can receive the initialization voltage VINT and be discharged. A gate electrode of the fourth switching transistor ST4 can be connected to the k-th scan line SLk, a first electrode of the fourth switching transistor ST4 can be connected to an initialization voltage line that supplies the initialization voltage VINT, and a second electrode of the fourth switching transistor ST4 can be connected to the first electrode of the light-emitting element E. In one embodiment, for example, the first electrode of the fourth switching transistor ST4 can be a source electrode, and the second electrode of the fourth switching transistor ST4 can be a drain electrode.

[0100] The fifth switching transistor ST5 can selectively supply the first driving voltage VDD to the first electrode of the driving transistor DT. The fifth switching transistor ST5 can be turned on in response to the emission signal of the kth emission control line ELk to supply the first driving voltage VDD to the first electrode of the driving transistor DT. The gate electrode of the fifth switching transistor ST5 can be connected to the kth emission control line ELk, the first electrode of the fifth switching transistor ST5 can be connected to the voltage supply line VL that supplies the first driving voltage VDD, and the second electrode of the fifth switching transistor ST5 can be connected to the first electrode of the driving transistor DT. In one embodiment, for example, the first electrode of the fifth switching transistor ST5 can be a source electrode, and the second electrode of the fifth switching transistor ST5 can be a drain electrode.

[0101] The sixth switching transistor ST6 can selectively connect the second electrode of the driving transistor DT and the first electrode of the light-emitting element E. The sixth switching transistor ST6 can be turned on in response to the emission signal of the kth emission control line ELk to connect the second electrode of the driving transistor DT and the first electrode of the light-emitting element E. The gate electrode of the sixth switching transistor ST6 can be connected to the kth emission control line ELk, the first electrode of the sixth switching transistor ST6 can be connected to the second electrode of the driving transistor DT, and the second electrode of the sixth switching transistor ST6 can be connected to the first electrode of the light-emitting element E. In one embodiment, for example, the first electrode of the sixth switching transistor ST6 can be a source electrode, and the second electrode of the sixth switching transistor ST6 can be a drain electrode. When both the fifth switching transistor ST5 and the sixth switching transistor ST6 are turned on, a driving current (Isd) can be supplied to the light-emitting element E.

[0102] The first capacitor C1 may be connected between the gate electrode of the driving transistor DT and the voltage supply line VL. One electrode of the first capacitor C1 may be connected to the voltage supply line VL, and the other electrode of the first capacitor C1 may be connected to the gate electrode of the driving transistor DT, thereby maintaining a potential difference between the voltage supply line VL and the gate electrode of the driving transistor DT.

[0103] In one embodiment, for example, the semiconductor layer of each of the first to sixth switching transistors ST1, ST2, ST3, ST4, ST5, ST6 and the driving transistor DT may be formed by a low-temperature polysilicon ("LTPS") process using polysilicon, but the present invention is not limited thereto.

[0104] Figure 5 is a block diagram illustrating a scan driver of a display device according to an embodiment.

[0105] Reference Figure 5, an embodiment of the scan driving circuit 410 may include a first scan driving circuit 411 and a second scan driving circuit 412. The first scan driving circuit 411 may be arranged on one side of the display panel 100 and may include a plurality of stages STG1 to STGn. The second scan driving circuit 412 may be arranged on the other side of the display panel 100 and may include a plurality of stages STG1 to STGn. The first scan driving circuit 411 and the second scan driving circuit 412 may be arranged opposite to each other. In one embodiment, for example, the first scan driving circuit 411 and the second scan driving circuit 412 may be respectively arranged on opposite sides of the display panel 100 to output the same scan signal, but the present invention is not limited thereto. Hereinafter, for the sake of convenience of description, the plurality of stages STG1 to STGn of the first scan driving circuit 411 will be mainly described, and any repeated detailed description of the plurality of stages STG1 to STGn of the second scan driving circuit 412 will be omitted.

[0106] Each of the plurality of stages STG1 to STGn may include first and second clock terminals CT1 and CT2 , a start terminal ST, and an output terminal OUT.

[0107] The first stage STG1 can be connected to the first clock line CL1 through the first clock terminal CT1, can be connected to the third clock line CL3 through the second clock terminal CT2, and can be connected to the first start signal line STL1 through the start terminal ST. The first clock terminal CT1 of the first stage STG1 can receive the first clock signal from the first clock line CL1, the second clock terminal CT2 of the first stage STG1 can receive the third clock signal from the third clock line CL3, and the start terminal ST of the first stage STG1 can receive the first start signal from the first start signal line STL1. The output terminal OUT of the first stage STG1 can be connected to the first scan line SL1 and the start terminal ST of the third stage STG3.

[0108] The second stage STG2 can be connected to the second clock line CL2 through the first clock terminal CT1, can be connected to the fourth clock line CL4 through the second clock terminal CT2, and can be connected to the second start signal line STL2 through the start terminal ST. The first clock terminal CT1 of the second stage STG2 can receive the second clock signal from the second clock line CL2, the second clock terminal CT2 of the second stage STG2 can receive the fourth clock signal from the fourth clock line CL4, and the start terminal ST of the second stage STG2 can receive the second start signal from the second start signal line STL2. The output terminal OUT of the second stage STG2 can be connected to the second scan line SL2 and the start terminal ST of the fourth stage STG4.

[0109] The third stage STG3 can be connected to the third clock line CL3 through the first clock terminal CT1, can be connected to the first clock line CL1 through the second clock terminal CT2, and can be connected to the output terminal OUT of the first stage STG1 through the start terminal ST. The first clock terminal CT1 of the third stage STG3 can receive the third clock signal from the third clock line CL3, the second clock terminal CT2 of the third stage STG3 can receive the first clock signal from the first clock line CL1, and the start terminal ST of the third stage STG3 can receive the output signal of the first stage STG1. The output terminal OUT of the third stage STG3 can be connected to the third scan line SL3 and the start terminal ST of the fifth stage STG5.

[0110] The fourth stage STG4 can be connected to the fourth clock line CL4 through the first clock terminal CT1, can be connected to the second clock line CL2 through the second clock terminal CT2, and can be connected to the output terminal OUT of the second stage STG2 through the start terminal ST. The first clock terminal CT1 of the fourth stage STG4 can receive the fourth clock signal from the fourth clock line CL4, the second clock terminal CT2 of the fourth stage STG4 can receive the second clock signal from the second clock line CL2, and the start terminal ST of the fourth stage STG4 can receive the output signal of the second stage STG2. The output terminal OUT of the fourth stage STG4 can be connected to the fourth scan line SL4 and the start terminal ST of the sixth stage STG6.

[0111] In such an embodiment, Figure 5 As shown in , the starting terminal ST of the (2p-1)th level STG(2p-1) (hereinafter, p is a natural number of n / 2 or less) can be connected to the output terminal OUT of the (2p-3)th level STG(2p-3), and the starting terminal ST of the 2pth level STG(2p) can be connected to the output terminal OUT of the (2p-2)th level STG(2p-2). Therefore, the (2p-1)th level STG(2p-1) can receive the scan signal of the (2p-3)th level STG(2p-3), and the 2pth level STG(2p) can receive the scan signal of the (2p-2)th level STG(2p-2). Here, the (2p-1)th level STG(2p-1) can be an odd-numbered level that supplies the scan signal to the pixels SP arranged in the odd rows, and the 2pth level STG(2p) can be an even-numbered level that supplies the scan signal to the pixels SP arranged in the even rows.

[0112] The (2p-1)th stage STG (2p-1) can receive the scan signal of the (2p-3)th stage STG (2p-3), and can alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels arranged in the odd rows. The 2pth stage STG (2p) can receive the scan signal of the (2p-2)th stage STG (2p-2), and can alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels arranged in the even rows.

[0113] When the scan driver 400 receives the first start signal from the first start signal line STL1 and does not receive the second start signal from the second start signal line STL2, the (2p-1)th stage STG(2p-1) may supply the scan signal to the scan lines SL1, SL3, ..., SLn-1 in the odd rows, and the 2pth stage STG(2p) may not supply the scan signal to the scan lines SL2, SL4, ..., SLn in the even rows. In one embodiment, for example, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd rows, and the second pixel BP is connected to the scan line in the even rows, the scan driver 400 may perform a lighting check on the first pixel RP of the first pixel RP and the second pixel BP based on the first start signal. In such an embodiment, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd rows, and the second pixel BP is connected to the scan line in the even rows, the scan driver 400 may perform a lighting check on the second pixel BP of the first pixel RP and the second pixel BP based on the second start signal. Therefore, in the embodiment of the display device 10, the lighting check can be selectively performed on pixels in odd-numbered rows or even-numbered rows among the pixels SP arranged in multiple rows, thereby fully ensuring the charging time of the corresponding data lines. In the embodiment of the display device 10, when the lighting check is performed on multiple pixels SP with high resolution, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting check can be improved.

[0114] Figure 6 is a waveform diagram illustrating input / output signals of a scan driver in a display device according to an embodiment. Figure 6 The input / output signals of the scan driver 400 are signals provided in the display mode of the display device 10 , and are different from signals provided in the lighting check mode of the display device 10 .

[0115] Reference Figure 6, the first start signal STS1 may be applied to the start terminal ST of the first stage STG1, and the second start signal STS2 may be applied to the start terminal ST of the second stage STG2. In one embodiment, for example, the first start signal STS1 may be applied to the start terminal ST of the first stage STG1. Figure 6 The first start signal STS2 may have a gate low voltage during a first period t1 of one frame (one frame in the example), and the second start signal STS2 may have a gate low voltage during a second period t2 of one frame.

[0116] The first clock signal CLK1 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the (2p-1)th stage STG(2p-1) (hereinafter, p is a natural number of n / 2 or less), and the second clock signal CLK2 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the 2pth stage STG(2p). During the (4q-3)th period (hereinafter, q is a natural number of n / 4 or less) starting from the first period t1 of one frame, the first clock signal CLK1 may have a gate low voltage, and during the (4q-2)th period starting from the second period t2 of one frame, the second clock signal CLK2 may have a gate low voltage.

[0117] The third clock signal CLK3 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the (2p-1)th stage STG(2p-1), and the fourth clock signal CLK4 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the 2pth stage STG(2p). During the (4q-1)th period starting from the third period t3 of one frame, the third clock signal CLK3 may have a gate low voltage, and during the 4qth period starting from the fourth period t4 of one frame, the fourth clock signal CLK4 may have a gate low voltage.

[0118] The plurality of stages STG1 to STGn may output a plurality of scan signals SC1 to SCn, the phases of which are sequentially delayed based on the first and second start signals STS1, STS2, and the first to fourth clock signals CLK1 to CLK4. The plurality of stages STG1 to STGn may supply the scan signals SC1 to SCn to the plurality of pixels SP through the plurality of scan lines SL1 to SLn, and the plurality of pixels SP may emit light having a predetermined brightness based on the scan signals SC1 to SCn and the data voltage.

[0119] Figure 7 The diagram shows Figure 5 Here, the odd-numbered stage may be the (2p-1)th stage STG(2p-1) that supplies the scan signal to the scan line SL in the odd-numbered row among the plurality of stages STG1 to STGn.

[0120] Reference Figure 7 , a first start signal STS1 may be applied to a start terminal ST of the first stage STG1, and the first start signal STS1 may have a gate low voltage during a first period t1 of one frame. The first stage STG1 may output a first scan signal SC1 based on the first start signal STS1 and the first and third clock signals CLK1 and CLK3. The first scan signal SC1 may be applied to the first scan line SL1 and the start terminal ST of the third stage STG3.

[0121] The third stage STG3 may output a third scan signal SC3 based on the first scan signal SC1 of the first stage STG1 and the first and third clock signals CLK1 and CLK3 . The third scan signal SC3 may be applied to the third scan line SL3 and the start terminal ST of the fifth stage STG5 .

[0122] In an embodiment, as described above, the (2p-1)th level STG(2p-1) can receive the scan signal of the (2p-3)th level STG(2p-3), and can alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels SP arranged in the odd rows.

[0123] The second start signal STS2 may be applied to the start terminal ST of the second stage STG2. When a light check is performed on the pixels SP arranged in the odd rows, the second start signal STS2 may maintain a gate high voltage during one frame. The second stage STG2 may not output the second scan signal SC2, and the 2p stage STG (2p) may not output a scan signal. Therefore, the pixels SP arranged in the even rows may maintain an extinguished state.

[0124] In one embodiment, for example, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to a scan line in an odd row, and the second pixel BP is connected to a scan line in an even row, the scan driver 400 can perform a lighting check on the first pixel RP among the first pixel RP and the second pixel BP based on the first start signal STS1. Therefore, in the embodiment of the display device 10, the lighting check can be selectively performed on pixels in odd rows among the pixels SP arranged in multiple rows, thereby fully ensuring the charging time of the corresponding data lines. In the embodiment of the display device 10, when the lighting check is performed on multiple pixels SP with high resolution, color mixing between the first pixel RP and the second pixel BP can be prevented, and the reliability of the lighting check can be improved.

[0125] Figure 8is a diagram illustrating a process of supplying a lighting voltage in a display device according to an embodiment.

[0126] Reference Figure 8 , the test pad TP may include first to third test pads TP1, TP2, and TP3. The first to third test pads TP1, TP2, and TP3 may receive first to third lighting voltages DC1, DC2, and DC3, respectively. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a grayscale voltage for turning on the pixel SP or a black voltage for turning off the pixel SP. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a direct current ("DC") voltage, but is not limited thereto. In one embodiment, for example, the first to third test pads TP1, TP2, and TP3 may be connected to a lighting device or a power supply device, and may receive the first to third lighting voltages DC1, DC2, and DC3.

[0127] The test transistors may include first to fourth test transistors TT1 to TT4. The first test transistor TT1 may be connected between the first test pad TP1 and the jth data line DLj, and the second test transistor TT2 may be connected between the second test pad TP2 and the (j+1)th data line DLj+1. The third test transistor TT3 may be connected between the third test pad TP3 and the (j+2)th data line DLj+2, and the fourth test transistor TT4 may be connected between the second test pad TP2 and the (j+3)th data line DLj+3. Each of the first to fourth test transistors TT1 to TT4 is connected between a corresponding test pad TP among the test pads TP and a corresponding data line DL among the plurality of data lines DL, thereby selectively supplying the first to third lighting voltages DC1, DC2, and DC3 to the plurality of data lines DL. In one embodiment, for example, the first to fourth test transistors TT1 to TT4 may receive the same test gate signal TG and, therefore, may be turned on or off at the same time.

[0128] The test gate pad TGP may receive a test gate signal TG and may be connected to a gate electrode of each of the first to fourth test transistors TT1 to TT4. In one embodiment, for example, the test gate pad TGP may be connected to a lighting device and may receive a test gate signal TG from the lighting device to turn on the first to fourth test transistors TT1 to TT4.

[0129] Figure 9 is a waveform diagram showing a lighting voltage and a test gate signal in a display device according to an embodiment, and Figure 10 The diagram shows Figure 9FIG. 1 is a diagram showing a result of a lighting inspection of a first pixel in a display device.

[0130] Reference Figure 9 and Figure 10 In an embodiment of the display device 10, a lighting inspection may be performed on some pixels among the plurality of pixels SP. In an embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

[0131] The first light-up voltage DC1 may maintain the gray voltage GV of the pixel SP during one frame or during the first to eighth periods t1 to t8. The second and third light-up voltages DC2 and DC3 may maintain the black voltage BV of the pixel SP during one frame or during the first to eighth periods t1 to t8. When the pixel SP receives the gray voltage GV from the data line DL, the pixel SP may be turned on, and when the pixel SP receives the black voltage BV from the data line DL, the pixel SP may be turned off.

[0132] The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t8. Therefore, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

[0133] Reference Figures 7 to 10, when a lighting check is performed on the first pixel RP and the second pixel BP connected to the first data line DL1 or the j-th data line DLj, the first start signal STS1 may have the gate low voltage VGL during the first period t1 of one frame, and the second start signal STS2 may maintain the gate high voltage VGH during one frame. The (2p-1)th stage STG(2p-1) may supply scan signals SC1, SC3, SC5, ... to the scan lines SL1, SL3, SL5, ... in odd rows, and the 2pth stage STG(2p) may not output a scan signal. The first lighting voltage DC1 may maintain the gray voltage GV during one frame, and the second and third lighting voltages DC2 and DC3 may maintain the black voltage BV during one frame. Therefore, among the first pixels RP and second pixels BP connected to the first data line DL1 or the j-th data line DLj, the first pixels RP connected to the scan lines SL1, SL3, SL5, ... in odd-numbered rows can be turned on, and the second pixels BP connected to the scan lines SL2, SL4, SL6, ... in even-numbered rows can be turned off. In one embodiment, for example, in the display device 10, after turning on the first pixel RP connected to the first data line DL1 and the first scan line SL1, the first pixel RP connected to the third scan line SL3 is turned on without turning on the second pixel BP connected to the second scan line SL2, thereby fully ensuring the charging time of the first data line DL1. In such an embodiment of the display device 10, color mixing between the first pixels RP and the second pixels BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0134] Figure 11 is a waveform diagram showing a lighting voltage and a test gate signal in a display device according to an alternative embodiment, and Figure 12 The diagram shows Figure 11 FIG. 1 is a diagram showing a result of a lighting inspection of a second pixel in a display device.

[0135] Reference Figure 11 and Figure 12 In an embodiment of the display device 10, a lighting inspection may be performed on some pixels among the plurality of pixels SP. In an embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

[0136] The first light-up voltage DC1 and the second light-up voltage DC2 may maintain the black voltage BV of the pixel SP during one frame or during the first period t1 to the eighth period t8. The third light-up voltage DC3 may maintain the gray voltage GV of the pixel SP during one frame or during the first period t1 to the eighth period t8. When the pixel SP receives the gray voltage GV from the data line DL, the pixel SP may be turned on, and when the pixel SP receives the black voltage BV from the data line DL, the pixel SP may be turned off.

[0137] The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t8. Therefore, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

[0138] Reference Figure 7 、 Figure 8 、 Figure 11 and Figure 12 , when a lighting check is performed on the first pixel RP and the second pixel BP of the second pixel BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the first start signal STS1 may have the gate low voltage VGL during the first period t1 of one frame, and the second start signal STS2 may maintain the gate high voltage VGH during one frame. The (2p-1)th stage STG(2p-1) may supply scan signals SC1, SC3, SC5, ... to the scan lines SL1, SL3, SL5, ... in odd rows, and the 2pth stage STG(2p) may not output a scan signal. The first light-up voltage DC1 and the second light-up voltage DC2 may maintain the black voltage BV during one frame, and the third light-up voltage DC3 may maintain the gray voltage GV during one frame. Therefore, among the first pixels RP and second pixels BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the second pixels BP connected to the scan lines SL1, SL3, SL5, ... in the odd rows can be turned on, and the first pixels RP connected to the scan lines SL2, SL4, SL6, ... in the even rows can be turned off. In one embodiment, for example, in the display device 10, after turning on the second pixel BP connected to the third data line DL3 and the first scan line SL1, the charging time of the third data line DL3 can be fully guaranteed by turning on the second pixel BP connected to the third scan line SL3 without turning on the first pixel RP connected to the second scan line SL2. In the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0139] Figure 13 The diagram shows Figure 5Here, the even-numbered stage may be the 2p-th stage STG(2p) among the plurality of stages STG1 to STGn that supplies the scan signal to the scan line SL in the even-numbered row.

[0140] Reference Figure 13 , the second start signal STS2 may be applied to the start terminal ST of the second stage STG2, and the second start signal STS2 may have a gate low voltage during the second period t2 of one frame. The second stage STG2 may output a second scan signal SC2 based on the second start signal STS2 and the second and fourth clock signals CLK2 and CLK4. The second scan signal SC2 may be applied to the second scan line SL2 and the start terminal ST of the fourth stage STG4.

[0141] The fourth stage STG4 may output a fourth scan signal SC4 based on the second scan signal SC2 of the second stage STG2 and the second and fourth clock signals CLK2 and CLK4. The fourth scan signal SC4 may be applied to the fourth scan line SL4 and the start terminal ST of the sixth stage STG6.

[0142] In such an embodiment, as described above, the 2p-th level STG (2p) can receive the scan signal of the (2p-2)-th level STG (2p-2), and can alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels arranged in the even rows.

[0143] The first start signal STS1 may be applied to the start terminal ST of the first stage STG1. When a lighting check is performed on the pixels SP arranged in the even rows, the first start signal STS1 may maintain a gate high voltage during one frame. The first stage STG1 may not output the first scan signal SC1, and the (2p-1)th stage STG(2p-1) may not output a scan signal. Therefore, the pixels SP arranged in the odd rows may maintain an extinguished state.

[0144] In one embodiment, for example, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd row, and the second pixel BP is connected to the scan line in the even row, the scan driver 400 can perform a lighting check on the second pixel BP of the first pixel RP and the second pixel BP based on the second start signal. As described above, in the embodiment of the display device 10, the lighting check can be selectively performed on the pixels in the even row among the pixels SP arranged in the plurality of rows, thereby fully ensuring the charging time of the corresponding data line. In the embodiment of the display device 10, when the lighting check is performed on the plurality of pixels SP with high resolution, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting check can be improved.

[0145] Figure 14 The diagram shows Figure 13 FIG. 1 is a diagram showing a result of a lighting inspection of a second pixel in a display device.

[0146] Reference Figure 14 as well as Figure 8 、 Figure 9 and Figure 13 In an embodiment of the display device 10, a lighting inspection may be performed on some pixels among the plurality of pixels SP. In an embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

[0147] The first light-up voltage DC1 may maintain the gray voltage GV of the pixel SP during one frame or during the first to eighth periods t1 to t8. The second and third light-up voltages DC2 and DC3 may maintain the black voltage BV of the pixel SP during one frame or during the first to eighth periods t1 to t8. When the pixel SP receives the gray voltage GV from the data line DL, the pixel SP may be turned on, and when the pixel SP receives the black voltage BV from the data line DL, the pixel SP may be turned off.

[0148] The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t8. Therefore, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

[0149] When a lighting check is performed on the second pixel BP among the first pixel RP and the second pixel BP connected to the first data line DL1 or the j-th data line DLj, the second start signal STS2 may have a gate low voltage VGL during the second period t2 of one frame, and the first start signal STS1 may maintain a gate high voltage VGH during one frame. The 2p-th stage STG (2p) may supply scan signals SC2, SC4, SC6, ... to the scan lines SL2, SL4, SL6, ... in the even-numbered rows, and the (2p-1)-th stage STG (2p-1) may not output a scan signal. The first lighting voltage DC1 may maintain a gray voltage GV during one frame, and the second and third lighting voltages DC2 and DC3 may maintain a black voltage BV during one frame. Therefore, among the first pixels RP and second pixels BP connected to the first data line DL1 or the j-th data line DLj, the second pixels BP connected to the scan lines SL2, SL4, SL6, ... in even-numbered rows can be turned on, and the first pixels RP connected to the scan lines SL1, SL3, SL5, ... in odd-numbered rows can be turned off. In one embodiment, for example, in the display device 10, after turning on the second pixels BP connected to the first data line DL1 and the second scan line SL2, the charging time of the first data line DL1 can be fully guaranteed by turning on the second pixels BP connected to the fourth scan line SL4 without turning on the first pixels RP connected to the third scan line SL3. In such an embodiment of the display device 10, color mixing between the first pixels RP and the second pixels BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0150] Figure 15 The diagram shows Figure 13 FIG. 1 is a diagram showing a result of a lighting inspection of a first pixel in a display device.

[0151] Reference Figure 15 as well as Figure 8 、 Figure 11 and Figure 13 In an embodiment of the display device 10, a lighting inspection may be performed on some pixels among the plurality of pixels SP. In an embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

[0152] The first light-up voltage DC1 and the second light-up voltage DC2 may maintain the black voltage BV of the pixel SP during one frame or during the first period t1 to the eighth period t8. The third light-up voltage DC3 may maintain the gray voltage GV of the pixel SP during one frame or during the first period t1 to the eighth period t8. When the pixel SP receives the gray voltage GV from the data line DL, the pixel SP may be turned on, and when the pixel SP receives the black voltage BV from the data line DL, the pixel SP may be turned off.

[0153] The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t8. Therefore, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

[0154] When a lighting check is performed on the first pixel RP and the second pixel BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the second start signal STS2 may have a gate low voltage VGL during the second period t2 of one frame, and the first start signal STS1 may maintain a gate high voltage VGH during one frame. The 2p stage STG (2p) may supply scan signals SC2, SC4, SC6, ... to the scan lines SL2, SL4, SL6, ... in the even-numbered rows, and the (2p-1)th stage STG (2p-1) may not output a scan signal. The first light-up voltage DC1 and the second light-up voltage DC2 may maintain a black voltage BV during one frame, and the third light-up voltage DC3 may maintain a grayscale voltage GV during one frame. Therefore, among the first pixels RP and second pixels BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the first pixels RP connected to the scan lines SL2, SL4, SL6, ... in the even rows can be turned on, and the second pixels BP connected to the scan lines SL1, SL3, SL5, ... in the odd rows can be turned off. In one embodiment, for example, in the display device 10, after turning on the first pixel RP connected to the third data line DL3 and the second scan line SL2, the charging time of the third data line DL3 can be fully guaranteed by turning on the first pixel RP connected to the fourth scan line SL4 without turning on the second pixel BP connected to the third scan line SL3. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0155] Figure 16 is a block diagram illustrating a scan driver of a display device according to an alternative embodiment.

[0156] In addition to the start signal line STL, Figure 16The scan driver of the display device and Figure 5 Therefore, the following description will be omitted or simplified. Figure 5 Any repeated description of the same or similar elements is detailed.

[0157] Reference Figure 16 , an embodiment of the scan driving circuit 410 may include a first scan driving circuit 411 and a second scan driving circuit 412. The first scan driving circuit 411 may be arranged on one side of the display panel 100 and may include a plurality of stages STG1 to STGn. The second scan driving circuit 412 may be arranged on the other side of the display panel 100 and may include a plurality of stages STG1 to STGn. In one embodiment, for example, the first scan driving circuit 411 and the second scan driving circuit 412 may be respectively arranged on opposite sides of the display panel 100 to output the same scan signal, but the present invention is not limited thereto.

[0158] Each of the plurality of stages STG1 to STGn may include first and second clock terminals CT1 and CT2 , a start terminal ST, and an output terminal OUT.

[0159] The first stage STG1 can be connected to the first clock line CL1 through the first clock terminal CT1, can be connected to the third clock line CL3 through the second clock terminal CT2, and can be connected to the start signal line STL through the start terminal ST. The first clock terminal CT1 of the first stage STG1 can receive a first clock signal from the first clock line CL1, the second clock terminal CT2 of the first stage STG1 can receive a third clock signal from the third clock line CL3, and the start terminal ST of the first stage STG1 can receive a start signal from the start signal line STL. The output terminal OUT of the first stage STG1 can be connected to the first scan line SL1 and the start terminal ST of the third stage STG3.

[0160] The second stage STG2 can be connected to the second clock line CL2 through the first clock terminal CT1, can be connected to the fourth clock line CL4 through the second clock terminal CT2, and can be connected to the start signal line STL through the start terminal ST. The first clock terminal CT1 of the second stage STG2 can receive the second clock signal from the second clock line CL2, the second clock terminal CT2 of the second stage STG2 can receive the fourth clock signal from the fourth clock line CL4, and the start terminal ST of the second stage STG2 can receive the start signal from the start signal line STL. The output terminal OUT of the second stage STG2 can be connected to the second scan line SL2 and the start terminal ST of the fourth stage STG4.

[0161] The starting terminal ST of the (2p-1)th level STG(2p-1) can be connected to the output terminal OUT of the (2p-3)th level STG(2p-3), and the starting terminal ST of the 2pth level STG(2p) can be connected to the output terminal OUT of the (2p-2)th level STG(2p-2). Therefore, the (2p-1)th level STG(2p-1) can receive the scan signal of the (2p-3)th level STG(2p-3), and the 2pth level STG(2p) can receive the scan signal of the (2p-2)th level STG(2p-2). Here, the (2p-1)th level STG(2p-1) can be an odd-numbered level that supplies the scan signal to the pixels SP arranged in the odd-numbered rows, and the 2pth level STG(2p) can be an even-numbered level that supplies the scan signal to the pixels SP arranged in the even-numbered rows.

[0162] The (2p-1)th stage STG (2p-1) can receive the scan signal of the (2p-3)th stage STG (2p-3), and can alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels arranged in the odd rows. The 2pth stage STG (2p) can receive the scan signal of the (2p-2)th stage STG (2p-2), and can alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels arranged in the even rows.

[0163] When the scan driver 400 receives a start signal having a gate low voltage during a first period t1 and a gate high voltage during a second period t2 from the start signal line STL, the (2p-1)th level STG(2p-1) may supply the scan signal to the scan lines SL1, SL3, ..., SLn-1 in the odd rows, and the 2pth level STG(2p) may not supply the scan signal to the scan lines SL2, SL4, ..., SLn in the even rows.

[0164] In one embodiment, for example, when a first pixel RP and a second pixel BP are connected to the same data line DL, the first pixel RP is connected to a scan line in an odd row, and the second pixel BP is connected to a scan line in an even row, the scan driver 400 may perform a lighting check on the first pixel RP of the second pixel RP based on a start signal having a gate-low voltage only during a first period t1. In such an embodiment, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to a scan line in an odd row, and the second pixel BP is connected to a scan line in an even row, the scan driver 400 may perform a lighting check on the second pixel BP of the first pixel RP and the second pixel BP based on a start signal having a gate-low voltage only during a second period t2. Therefore, since the display device 10 includes a plurality of stages STG1 to STGn connected to a single start signal line STL to control the timing at which the start signal has a gate-low voltage, the lighting check can be selectively performed on pixels in odd or even rows among the pixels SP arranged in a plurality of rows, thereby fully ensuring the charging time of the corresponding data lines. In such an embodiment of the display device 10 , color mixing between the first pixel RP and the second pixel BP may be prevented, and reliability of lighting inspection may be improved.

[0165] Figure 17 The diagram shows Figure 16 Waveform diagram of the input / output signals of the odd-numbered stages in the display device.

[0166] In addition to the start signal STS, Figure 17 The odd-numbered input / output signals are Figure 7 The input / output signals of the odd-numbered stages are substantially the same. Therefore, the descriptions of the above references will be omitted or simplified in the following text. Figure 7 Any repeated description of the same or similar elements is detailed.

[0167] Reference Figure 17 , the start signal STS may be applied to the start terminal ST of the first stage STG1 and the start terminal ST of the second stage STG2. When a lighting check is performed on the pixels SP arranged in odd rows, the start signal STS may have a gate low voltage during a first period t1 of one frame, and may have a gate high voltage during a second period t2 of one frame. The first stage STG1 may output a first scan signal SC1 based on the start signal STS having a gate low voltage during the first period t1 and the first and third clock signals CLK1 and CLK3. The first scan signal SC1 may be applied to the first scan line SL1 and the start terminal ST of the third stage STG3.

[0168] The second stage STG2 may receive the start signal having the gate high voltage during the second period t2 and may not output the second scan signal SC2 . Therefore, the pixels SP disposed in the even-numbered rows may maintain a turned-off state.

[0169] The third stage STG3 may output a third scan signal SC3 based on the first scan signal SC1 of the first stage STG1 and the first and third clock signals CLK1 and CLK3 . The third scan signal SC3 may be applied to the third scan line SL3 and the start terminal ST of the fifth stage STG5 .

[0170] In such an embodiment, as described above, the (2p-1)th level STG(2p-1) can receive the scan signal of the (2p-3)th level STG(2p-3), and can alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels arranged in odd rows.

[0171] In one embodiment, for example, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to a scan line in an odd row, and the second pixel BP is connected to a scan line in an even row, the scan driver 400 can perform a lighting check on the first pixel RP of the second pixel BP based on the start signal STS having a gate low voltage during the first period t1. As described above, in an embodiment of the display device 10, the lighting check can be selectively performed on pixels in odd rows among the pixels SP arranged in a plurality of rows, thereby fully ensuring the charging time of the corresponding data lines. In such an embodiment of the display device 10, when the lighting check is performed on a plurality of pixels SP having a high resolution, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting check can be improved.

[0172] Figure 18 The diagram shows Figure 16 Waveform diagram of input / output signals of even-numbered stages in a display device.

[0173] In addition to the start signal STS, Figure 18 The input / output signals of the even-numbered levels are Figure 13 The input / output signals of the even-numbered stages are substantially the same. Therefore, the descriptions of the above references will be omitted or simplified below. Figure 13 Any repeated description of the same or similar elements is detailed.

[0174] Reference Figure 18, the start signal STS may be applied to the start terminal ST of the first stage STG1 and the start terminal ST of the second stage STG2. When a lighting check is performed on the pixels SP arranged in the even-numbered rows, the start signal STS may have a gate high voltage during a first period t1 of one frame, and may have a gate low voltage during a second period t2 of one frame. The second stage STG2 may output a second scan signal SC2 based on the start signal STS having a gate low voltage during the second period t2 and the second and fourth clock signals CLK2 and CLK4. The second scan signal SC2 may be applied to the second scan line SL2 and the start terminal ST of the fourth stage STG4.

[0175] The first stage STG1 may receive a start signal having a gate high voltage during the first period t1 and may not output the first scan signal SC1. Therefore, the pixels SP disposed in odd-numbered rows may maintain a turned-off state.

[0176] The fourth stage STG4 may output a fourth scan signal SC4 based on the second scan signal SC2 of the second stage STG2 and the second and fourth clock signals CLK2 and CLK4. The fourth scan signal SC4 may be applied to the fourth scan line SL4 and the start terminal ST of the sixth stage STG6.

[0177] As described above, the 2p-th level STG (2p) can receive the scan signal of the (2p-2)-th level STG (2p-2), and can alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels arranged in the even rows.

[0178] In one embodiment, for example, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to a scan line in an odd row, and the second pixel BP is connected to a scan line in an even row, the scan driver 400 can perform a lighting check on the second pixel BP of the first pixel RP and the second pixel BP based on the start signal STS having a gate low voltage during the second period t2. As described above, in an embodiment of the display device 10, the lighting check can be selectively performed on pixels in even rows among the pixels SP arranged in a plurality of rows, thereby fully ensuring the charging time of the corresponding data lines. In such an embodiment of the display device 10, when the lighting check is performed on a plurality of pixels SP having a high resolution, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting check can be improved.

[0179] Figure 19 is a plan view of a display device according to an alternative embodiment, and Figure 20is a diagram illustrating a process of supplying a lighting voltage in a display device according to an alternative embodiment.

[0180] In addition to the test transistor and test gate pad, Figure 19 and Figure 20 Display device and Figure 2 and Figure 8 Therefore, the following description will be omitted or simplified. Figure 2 and Figure 8 Any repeated description of the same or similar elements is detailed.

[0181] Reference Figure 19 and Figure 20 In an embodiment of the display device, the test pad TP may include first to third test pads TP1, TP2, and TP3. The first to third test pads TP1, TP2, and TP3 may receive first to third lighting voltages DC1, DC2, and DC3, respectively. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a grayscale voltage for turning on the pixel SP or a black voltage for turning off the pixel SP. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a DC voltage, but is not limited thereto. In one embodiment, for example, the first to third test pads TP1, TP2, and TP3 may be connected to a lighting device or a power supply device, and may receive the first to third lighting voltages DC1, DC2, and DC3.

[0182] The test transistors may include first to sixth test transistors TT1 to TT6. A gate electrode of the first test transistor TT1 may be connected to a first test gate pad TGP1. The first test transistor TT1 may be connected between the first test pad TP1 and the j-th data line DLj. The first test transistor TT1 may selectively supply a first lighting voltage DC1 to the j-th data line DLj based on a first test gate signal TG1 received from the first test gate pad TGP1.

[0183] A gate electrode of the second test transistor TT2 may be connected to a second test gate pad TGP2. The second test transistor TT2 may be connected between the first test pad TP1 and the (j+2)th data line DLj+2. The second test transistor TT2 may selectively supply a first light-up voltage DC1 to the (j+2)th data line DLj+2 based on a second test gate signal TG2 received from the second test gate pad TGP2.

[0184] A gate electrode of the third test transistor TT3 may be connected to the first test gate pad TGP1. The third test transistor TT3 may be connected between the third test pad TP3 and the (j+2)th data line DLj+2. The third test transistor TT3 may selectively supply a third light-up voltage DC3 to the (j+2)th data line DLj+2 based on a first test gate signal TG1 received from the first test gate pad TGP1.

[0185] A gate electrode of the fourth test transistor TT4 may be connected to the second test gate pad TGP2. The fourth test transistor TT4 may be connected between the third test pad TP3 and the j-th data line DLj. The fourth test transistor TT4 may selectively supply a third light-up voltage DC3 to the j-th data line DLj based on a second test gate signal TG2 received from the second test gate pad TGP2.

[0186] A gate electrode of each of the fifth test transistor TT5 and the sixth test transistor TT6 may be connected to the third test gate pad TGP3. The fifth test transistor TT5 may be connected between the second test pad TP2 and the (j+1)th data line DLj+1, and the sixth test transistor TT6 may be connected between the second test pad TP2 and the (j+3)th data line DLj+3. The fifth test transistor TT5 may selectively supply a second lighting voltage DC2 to the (j+1)th data line DLj+1 based on a third test gate signal TG3 received from the third test gate pad TGP3. The sixth test transistor TT6 may selectively supply a second lighting voltage DC2 to the (j+3)th data line DLj+3 based on a third test gate signal TG3 received from the third test gate pad TGP3.

[0187] Each of the first to sixth test transistors TT1 to TT6 may be connected between a corresponding one of the test pads TP and a corresponding one of the plurality of data lines DL, thereby selectively supplying first to third lighting voltages DC1, DC2, and DC3 to the plurality of data lines DL.

[0188] The first to third test gate pads TGP1, TGP2, and TGP3 may receive first to third test gate signals TG1, TG2, and TG3, respectively. Each of the first to third test gate pads TGP1, TGP2, and TGP3 may be connected to a gate electrode of at least one transistor selected from the first to sixth test transistors TT1 to TT6. In one embodiment, for example, the test gate pad TGP may be connected to a lighting device and may receive a test gate signal from the lighting device that turns on the first to sixth test transistors TT1 to TT6.

[0189] Figure 21 is a waveform diagram illustrating a light-up voltage and a test gate signal in a display device according to an embodiment.

[0190] Reference Figure 21 In an embodiment of the display device 10, a lighting inspection may be performed on some pixels among the plurality of pixels SP. In an embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the first to third test gate signals TG1, TG2, and TG3 may be supplied through the first to third test gate pads TGP1, TGP2, and TGP3.

[0191] The first light-up voltage DC1 may maintain the gray voltage GV of the turned-on pixel SP during one frame or during the first period t1 to the eighth period t8. The second light-up voltage DC2 and the third light-up voltage DC3 may maintain the black voltage BV of the turned-off pixel SP during one frame or during the first period t1 to the eighth period t8. When the pixels SP receive the gray voltage GV from the data line DL, the pixels SP may be turned on, and when the pixels SP receive the black voltage BV from the data line DL, the pixels SP may be turned off.

[0192] The first test gate signal TG1 may maintain the gate low voltage VGL during the first period t1, the third period t3, the fifth period t5, and the seventh period t7, and may maintain the gate high voltage VGH during the second period t2, the fourth period t4, the sixth period t6, and the eighth period t8. The second test gate signal TG2 may maintain the gate high voltage VGH during the first period t1, the third period t3, the fifth period t5, and the seventh period t7, and may maintain the gate low voltage VGL during the second period t2, the fourth period t4, the sixth period t6, and the eighth period t8.

[0193] Reference Figure 10 、 Figure 17 、 Figure 20 and Figure 21, when a lighting check is performed on the first pixel RP and the second pixel BP connected to the first data line DL1 or the j-th data line DLj, the start signal STS may have a gate low voltage VGL during a first period t1 of a frame, and may have a gate high voltage VGH during a second period t2 of the frame. The (2p-1)th stage STG(2p-1) may supply scan signals SC1, SC3, SC5, ... to the scan lines SL1, SL3, SL5, ... in odd rows, and the 2pth stage STG(2p) may not output a scan signal. The first lighting voltage DC1 may maintain the grayscale voltage GV during a frame, and the second lighting voltage DC2 and the third lighting voltage DC3 may maintain the black voltage BV during a frame. Therefore, among the first pixels RP and the second pixels BP connected to the first data line DL1 or the j-th data line DLj, the first pixels RP connected to the scan lines SL1, SL3, SL5, ... in odd rows may be turned on, and the second pixels BP connected to the scan lines SL2, SL4, SL6, ... in even rows may be turned off. In one embodiment, for example, in the display device 10, after turning on the first pixel RP connected to the first data line DL1 and the first scan line SL1, the first pixel RP connected to the third scan line SL3 is turned on without turning on the second pixel BP connected to the second scan line SL2. This ensures sufficient charging time for the first data line DL1. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0194] In an alternative embodiment, the display device 10 includes Figure 7 The first start signal STS1 is configured instead of Figure 17 In the case of the configuration of the start signal STS, you can get Figure 10 The lighting inspection results.

[0195] Reference Figure 14 、 Figure 18 、 Figure 20 and Figure 21When a lighting check is performed on the second pixel BP among the first pixel RP and the second pixel BP connected to the first data line DL1 or the j-th data line DLj, the start signal STS may have a gate high voltage VGH during a first period t1 of a frame and may have a gate low voltage VGL during a second period t2 of the frame. The 2p-th stage STG (2p) may supply scan signals SC2, SC4, SC6, ... to the scan lines SL2, SL4, SL6, ... in even-numbered rows, and the (2p-1)-th stage STG (2p-1) may not output a scan signal. The first lighting voltage DC1 may maintain the grayscale voltage GV during a frame, and the second lighting voltage DC2 and the third lighting voltage DC3 may maintain the black voltage BV during a frame. Therefore, among the first pixels RP and the second pixels BP connected to the first data line DL1 or the j-th data line DLj, the second pixels BP connected to the scan lines SL2, SL4, SL6, ... in even-numbered rows may be turned on, and the first pixels RP connected to the scan lines SL1, SL3, SL5, ... in odd-numbered rows may be turned off. In one embodiment, for example, in the display device 10, after turning on the second pixel BP connected to the first data line DL1 and the second scan line SL2, the second pixel BP connected to the fourth scan line SL4 is turned on without turning on the first pixel RP connected to the third scan line SL3. This ensures sufficient charging time for the first data line DL1. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0196] In an alternative embodiment, the display device 10 includes Figure 13 The second start signal STS2 is configured instead of Figure 18 In the case of the configuration of the start signal STS, you can get Figure 14 The lighting inspection results.

[0197] Figure 22 is a waveform diagram illustrating a light-up voltage and a test gate signal in a display device according to an alternative embodiment.

[0198] Reference Figure 22 In an embodiment of the display device 10, a lighting inspection may be performed on some pixels among the plurality of pixels SP. In the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the first to third test gate signals TG1, TG2, and TG3 may be supplied through the first to third test gate pads TGP1, TGP2, and TGP3.

[0199] The first lighting voltage DC1 and the second lighting voltage DC2 can maintain the black voltage BV of the pixel SP during one frame or during the first period t1 to the eighth period t8. The third lighting voltage DC3 can maintain the gray voltage GV of the pixel SP during one frame or during the first period t1 to the eighth period t8. When the pixel SP receives the gray voltage GV from the data line DL, the pixel SP can be turned on, and when the pixel SP receives the black voltage BV from the data line DL, the pixel SP can be turned off.

[0200] The first test gate signal TG1 may maintain the gate low voltage VGL during the first period t1, the third period t3, the fifth period t5, and the seventh period t7, and may maintain the gate high voltage VGH during the second period t2, the fourth period t4, the sixth period t6, and the eighth period t8. The second test gate signal TG2 may maintain the gate high voltage VGH during the first period t1, the third period t3, the fifth period t5, and the seventh period t7, and may maintain the gate low voltage VGL during the second period t2, the fourth period t4, the sixth period t6, and the eighth period t8.

[0201] Reference Figure 12 、 Figure 17 、 Figure 20 and Figure 21, when a lighting check is performed on the first pixel RP and the second pixel BP of the second pixel BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the start signal STS may have the gate low voltage VGL during the first period t1 of one frame, and may have the gate high voltage VGH during the second period t2 of one frame. The (2p-1)th stage STG(2p-1) may supply scan signals SC1, SC3, SC5, ... to the scan lines SL1, SL3, SL5, ... in odd rows, and the 2pth stage STG(2p) may not output a scan signal. The first light-up voltage DC1 and the second light-up voltage DC2 may maintain the black voltage BV during one frame, and the third light-up voltage DC3 may maintain the gray voltage GV during one frame. Therefore, among the first pixels RP and second pixels BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the second pixels BP connected to the scan lines SL1, SL3, SL5, ... in the odd rows can be turned on, and the first pixels RP connected to the scan lines SL2, SL4, SL6, ... in the even rows can be turned off. In one embodiment, for example, in the display device 10, after turning on the second pixels BP connected to the third data line DL3 and the first scan line SL1, the charging time of the third data line DL3 can be fully guaranteed by turning on the second pixels BP connected to the third scan line SL3 without turning on the first pixels RP connected to the second scan line SL2. In such an embodiment of the display device 10, color mixing between the first pixels RP and the second pixels BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0202] In an alternative embodiment, the display device 10 includes Figure 7 The first start signal STS1 is configured instead of Figure 17 In the case of the configuration of the start signal STS, you can get Figure 10 The lighting inspection results.

[0203] Reference Figure 15 、 Figure 18 、 Figure 20 and Figure 21, when a lighting check is performed on the first pixel RP and the second pixel BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the start signal STS may have a gate high voltage VGH during a first period t1 of one frame, and may have a gate low voltage VGL during a second period t2 of one frame. The 2p stage STG (2p) may supply scan signals SC2, SC4, SC6, ... to the scan lines SL2, SL4, SL6, ... in the even-numbered rows, and the (2p-1)th stage STG (2p-1) may not output a scan signal. The first lighting voltage DC1 and the second lighting voltage DC2 may maintain the black voltage BV during one frame, and the third lighting voltage DC3 may maintain the gray voltage GV during one frame. Therefore, among the first pixels RP and second pixels BP connected to the third data line DL3 or the (j+2)th data line DLj+2, the first pixels RP connected to the scan lines SL2, SL4, SL6, ... in the even rows can be turned on, and the second pixels BP connected to the scan lines SL1, SL3, SL5, ... in the odd rows can be turned off. In one embodiment, for example, in the display device 10, after turning on the first pixel RP connected to the third data line DL3 and the second scan line SL2, the charging time of the third data line DL3 can be fully guaranteed by turning on the first pixel RP connected to the fourth scan line SL4 without turning on the second pixel BP connected to the third scan line SL3. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

[0204] In an alternative embodiment, the display device 10 includes Figure 13 The second start signal STS2 is configured instead of Figure 18 In the case of the configuration of the start signal STS, you can get Figure 14 The lighting inspection results.

[0205] According to an embodiment of a display device, as described herein, the display device may include a first pixel and a second pixel connected to the same data line to emit light of different colors, and a scan driver that supplies a scan signal to one of the first pixel and the second pixel. When a lighting voltage is supplied to the data line, the display device can supply the lighting voltage to one of the first pixel and the second pixel while fully ensuring the charging time of the data line. Therefore, the display device can effectively prevent color mixing between the first pixel and the second pixel and improve the reliability of lighting inspection of the first pixel and the second pixel.

[0206] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0207] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, comprising: a plurality of first pixels connected to a first data line and a plurality of first scan lines; a plurality of second pixels connected to the first data line and a plurality of second scan lines; a plurality of third pixels connected to the second data line and the first scan line or the second scan line; a scan driver including a plurality of stages for supplying a plurality of scan signals to one of the first scan line and the second scan line; a first test transistor connected between a first test pad and the first data line; a second test transistor connected between a second test pad and the second data line; a third test transistor connected between a third test pad and a third data line; as well as a fourth test transistor connected between the second test pad and a fourth data line, In which, when the grayscale voltage is supplied to the first test pad as the first lighting voltage, the black voltage is supplied to the second test pad as the second lighting voltage, the black voltage is supplied to the third test pad as the third lighting voltage, and the multiple scan signals are output to the first scan line and not output to the second scan line, the multiple first pixels are turned on and the multiple second pixels and the multiple third pixels are turned off.

2. The display device according to claim 1, wherein The multiple stages include: a plurality of first stages that sequentially supply the scan signal to each of the plurality of first scan lines based on a first start signal; and A plurality of second stages sequentially supply the scan signal to each of the plurality of second scan lines based on a second start signal.

3. The display device according to claim 2, wherein: The first level includes: a first-first stage that outputs a first-first scanning signal based on the first start signal; and The second-first stage outputs a second-first scanning signal based on the first-first scanning signal.

4. The display device according to claim 2, wherein The second level includes: a first-second stage, the first-second stage outputting first-second scanning signals based on the second start signal; and A second-second stage outputs a second-second scanning signal based on the first-second scanning signal.

5. The display device according to claim 2, wherein The first test transistor supplies the first lighting voltage received from the first test pad to the first data line based on a test gate signal, and The second test transistor supplies the second light-up voltage received from the second test pad to the second data line based on the test gate signal.

6. The display device according to claim 5, in, When the first light-up voltage has a first voltage level that turns on the first pixel or the second pixel, the second light-up voltage has a second voltage level that turns off the first pixel or the second pixel.

7. The display device according to claim 1, wherein The multiple stages include: a plurality of first stages that sequentially supply the scan signal to each of the plurality of first scan lines when a start signal is supplied during a first period; and A plurality of second stages sequentially supply the scan signal to each of the plurality of second scan lines when the start signal is supplied during a second period different from the first period.

8. The display device according to claim 7, wherein: The first level includes: a first-first stage that outputs a first-first scanning signal when the start signal is supplied during the first period; and The second-first stage outputs a second-first scanning signal based on the first-first scanning signal.

9. The display device according to claim 7, wherein: The second level includes: a first-second stage that outputs first-second scanning signals when the start signal is supplied during the second period; and A second-second stage outputs a second-second scanning signal based on the first-second scanning signal.

10. A display device comprising: a plurality of first pixels connected to the first data line and the plurality of first scan lines, and connected to the third data line and the plurality of second scan lines; a plurality of second pixels connected to the first data line and the plurality of second scan lines, and connected to the third data line and the plurality of first scan lines; a plurality of third pixels connected to one of the second data line and the fourth data line and one of the first scan line and the second scan line; a scan driver including a plurality of stages for supplying a plurality of scan signals to one of the first scan line and the second scan line; a first test transistor that supplies a first lighting voltage to the first data line based on a first test gate signal; a second test transistor that supplies the first light-up voltage to the third data line based on a second test gate signal; as well as a third test transistor that supplies a third light-up voltage to the third data line based on the first test gate signal.

11. The display device according to claim 10, further comprising: a fourth test transistor that supplies the third lighting voltage to the first data line based on the second test gate signal.

12. The display device according to claim 11, in, When the first light-up voltage has a first voltage level that turns on the first pixel or the second pixel, the third light-up voltage has a second voltage level that turns off the first pixel or the second pixel.

13. The display device according to claim 11, in, When the third light-up voltage has a first voltage level that turns on the first pixel or the second pixel, the first light-up voltage has a second voltage level that turns off the first pixel or the second pixel.

14. The display device according to claim 11, further comprising: a fifth test transistor configured to supply a second lighting voltage to the second data line based on a third test gate signal; and a sixth test transistor that supplies the second light-up voltage to the fourth data line based on the third test gate signal.

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