Semiconductor device

Abstract

The present application provides a semiconductor device capable of increasing channel width density per unit area and reducing on-resistance. The semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer (3) of a second conductivity type, a first semiconductor region (7) of the first conductivity type, a second semiconductor region (8) of the second conductivity type, a gate insulating film, a gate electrode (10), an interlayer insulating film, a first electrode, a second electrode, and a trench. The first semiconductor region (7) and the second semiconductor region (8) are periodically arranged in a first direction (y direction) in which the trench extends in a stripe shape in a mutually separated manner.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Silicon carbide (SiC) is anticipated as a next-generation semiconductor material to replace silicon (Si). Semiconductor devices using silicon carbide (hereinafter referred to as silicon carbide semiconductor devices) offer various advantages over existing semiconductor devices using silicon, including reducing the resistance of the device in the on-state to a fraction of a percent and enabling operation at much higher temperatures (above 200°C). This is due to the inherent advantages of silicon carbide, which has a band gap approximately three times larger than that of silicon, and an insulation breakdown electric field strength nearly an order of magnitude greater than that of silicon.

[0003] As silicon carbide semiconductor devices, the commercially available products to date include Schottky Barrier Diode (SBD), planar gate structure and / or trench gate structure vertical MOSFET (MetalOxide Semiconductor Field Effect Transistor).

[0004] A trench gate structure is a MOS gate structure in which a MOS gate is buried in a trench formed on the front side of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewalls of the trench in a direction perpendicular to the front side of the semiconductor substrate. Therefore, compared to a planar gate structure where a channel is formed along the front side of the semiconductor substrate, it is cost-effective because it can increase the unit cell (component unit) density per unit area and the current density per unit area. A planar gate structure is a MOS gate structure in which a MOS gate is disposed in a plate-like form on the front side of the semiconductor substrate.

[0005] The structure of existing silicon carbide semiconductor devices will be described using trench MOSFETs as an example (see, for example, Patent Documents 1 and 2 below). Figure 17 This is a cross-sectional view showing the structure of an existing silicon carbide semiconductor device. For example... Figure 17 As shown, the trench MOSFET150 in n + An n-type silicon carbide epitaxial layer 102 is deposited on the front side of the n-type silicon carbide substrate 101. The n-type silicon carbide epitaxial layer 102 is relative to the n... + An n-type high-concentration region 106 is provided on the surface side opposite to the n-type silicon carbide substrate 101. Furthermore, in the n-type high-concentration region 106 relative to the n-type substrate... + The surface layer on the opposite side of the silicon carbide substrate 101 is selectively provided with a first p+ Type base region 104. In the n-type high concentration region 106, a second p-type base is selectively provided in such a way that it covers the entire bottom surface of the trench 118. + Base region 105.

[0006] In addition, the trench MOSFET 150 also has a p-type silicon carbide epitaxial layer 103 and an n-type silicon carbide epitaxial layer 103. + Type source polar region 107, p ++ The structure includes a contact area 108, a gate insulating film 109, a gate electrode 110, an interlayer insulating film 111, a source electrode 113, a back electrode 114, a trench 118, a source electrode pad (not shown), and a drain electrode pad (not shown). The source electrode 113 is located on the n-type contact area. + Type source polar region 107, p ++ The contact area 108 is provided with a source electrode pad, and the source electrode 113 is provided with a source electrode pad.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2018-019045

[0010] Patent Document 2: Japanese Patent Application Publication No. 2018-019046 Summary of the Invention

[0011] Technical issues

[0012] Figure 18 This represents the structure of existing silicon carbide semiconductor devices. Figure 17 The A-A' plan view. (See diagram below.) Figure 18 As shown, the grooves 118 are arranged in a striped pattern, and n stripes are arranged sequentially between the grooves 118 in a striped pattern. + Type source polar region 107, p ++ Type contact area 108, n + Type source polar region 107.

[0013] p ++ The p-type contact region 108 is necessary to maintain the p-type silicon carbide epitaxial layer 103 at the same potential as the source electrode 113. In existing silicon carbide semiconductor devices, this is achieved by sandwiching a striped n-type contact region. + p between type source pole region 107 ++ The p-type contact region 108 is used to keep the p-type silicon carbide epitaxial layer 103 and the source electrode 113 at the same potential.

[0014] However, n is set between the trenches 118 + Type source polar region 107, p ++ Type contact area 108, n+ In the structure of the source pole region 107, there are limits to narrowing the cell spacing and to increasing the channel width density.

[0015] In order to eliminate the problems caused by the prior art, the present invention aims to provide a semiconductor device that can increase the channel width density per unit area and reduce the on-resistance.

[0016] Technical solution

[0017] To solve the aforementioned problems and achieve the objectives of the present invention, the semiconductor device of the present invention has the following features. A first semiconductor layer of a first conductivity type is disposed on the front side of a semiconductor substrate of a first conductivity type, the impurity concentration of the first semiconductor layer of the first conductivity type being lower than the impurity concentration of the semiconductor substrate. A second semiconductor layer of a second conductivity type is selectively disposed on the surface of the first semiconductor layer opposite to the semiconductor substrate side. A first semiconductor region of a first conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the semiconductor substrate side. A second semiconductor region of a second conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the semiconductor substrate side. A striped trench is disposed penetrating the second semiconductor layer and reaching the first semiconductor layer. A gate electrode is disposed inside the trench, separated by a gate insulating film. A first electrode is disposed on the surface of the second semiconductor layer, the first semiconductor region, and the second semiconductor region. A second electrode is disposed on the back side of the semiconductor substrate. The first semiconductor region and the second semiconductor region are periodically arranged in a mutually separated manner in a first direction extending in a striped pattern from the trench.

[0018] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, the width direction of the trench perpendicular to the first direction on the front surface is set as the second direction. If, in the semiconductor device, the length of the first direction of the first semiconductor region is set as Wn, the length of the first direction of the second semiconductor region is set as Wpc, the length of the first direction between the first semiconductor region and the second semiconductor region is set as Wp, the length of the second direction of the gate electrode is set as Lg, the length of the second direction of the first semiconductor region is set as Ln, and in a semiconductor device in which the first semiconductor region and the second semiconductor region are arranged in a stripe pattern parallel to the trench, the length of the second direction of the gate electrode is set as Lg', the length of the second direction of the first semiconductor region is set as Ln', and the length of the second direction of the second semiconductor region is set as Lp', then Wn≥(2Wp+Wpc)×(Lg+Ln) / (Lg'+2Ln'+Lp'-Lg-Ln) holds true.

[0019] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, it further includes a diode unit region, wherein the diode unit region is provided only on the surface layer of the second semiconductor layer that is opposite to the semiconductor substrate side.

[0020] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, a third semiconductor region of a second conductivity type is provided that contacts the bottom of the trench, the third semiconductor region is provided in the region of the diode unit region that is opposite to the second semiconductor region in the depth direction, and the third semiconductor region is provided in the unit regions other than the diode unit region in the regions other than the region that is opposite to the first semiconductor region in the depth direction.

[0021] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, if the length of the second direction of the second semiconductor region in the diode unit region is set as Lp, then Wn≥(2Wp+Wpc)×{n(Lg+Ln)+Lg+Lp} / {n(Lg'+2Ln'+Lp')-n(Lg+Ln)-Lg-Lp} holds.

[0022] Furthermore, the semiconductor device of the present invention is characterized in that, in the above-described invention, a plurality of trenches are provided, and the second semiconductor region is disposed between the trenches and may or may not be in contact with one of the trenches.

[0023] According to the invention described above, n + Type source region (first semiconductor region of first conductivity type) and p++ Type-contact regions (second semiconductor regions of the second conductivity type) are provided between the trenches in such a way that they contact the trenches in the x-direction and are periodically arranged to be separated from each other in the y-direction. This enables n... + Type source pole region and p ++ The width of the contact area is narrowed. Therefore, the cell spacing can be narrowed, and the channel width density per unit area can be increased, thereby reducing the on-resistance.

[0024] Additionally, in n + Type source pole region and p ++ Spacing is provided between the contact areas to expose the p-type silicon carbide epitaxial layer. This prevents n-type contact areas from being exposed. + Type source pole region and p ++ The contact areas overlap. Therefore, it can prevent n-type contact areas from overlapping. + Type source pole region and p ++ The overlapping of the contact areas can cause defects and improve gate reliability.

[0025] Technical effect

[0026] The semiconductor device according to the present invention has the effect of increasing the channel width density per unit area and reducing the on-resistance. Attached Figure Description

[0027] Figure 1 This is a plan view showing the structure of the silicon carbide semiconductor device according to Embodiment 1.

[0028] Figure 2 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 A-A' cross-sectional view.

[0029] Figure 3 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 The B-B' cross-sectional view.

[0030] Figure 4 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 The C-C' cross-sectional view.

[0031] Figure 5 This is a plan view showing other structures of the silicon carbide semiconductor device according to Embodiment 1.

[0032] Figure 6 This is a graph showing the channel width density of the silicon carbide semiconductor device in Embodiment 1.

[0033] Figure 7 This is one of the cross-sectional views showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0034] Figure 8 This is a cross-sectional view (part two) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0035] Figure 9 This is a cross-sectional view (part 3) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0036] Figure 10 This is a cross-sectional view (fourth in a series) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0037] Figure 11 This is a cross-sectional view (part 5) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0038] Figure 12 This is a cross-sectional view (part six) showing the state during the manufacturing process of the silicon carbide semiconductor device of Embodiment 1.

[0039] Figure 13 This is a plan view showing the structure of the silicon carbide semiconductor device according to Embodiment 2.

[0040] Figure 14 This represents the structure of the silicon carbide semiconductor device in Embodiment 2. Figure 12 A-A' cross-sectional view.

[0041] Figure 15 This represents the structure of the silicon carbide semiconductor device in Embodiment 2. Figure 12 The B-B' cross-sectional view.

[0042] Figure 16 This is a graph showing the channel width density of the silicon carbide semiconductor device in Embodiment 2.

[0043] Figure 17 It is a cross-sectional view showing the structure of an existing silicon carbide semiconductor device.

[0044] Figure 18 This represents the structure of existing silicon carbide semiconductor devices. Figure 17 Plan view A-A'.

[0045] Symbol Explanation

[0046] 1. 101: n + Silicon carbide substrate

[0047] 2. 102: n-type silicon carbide epitaxial layer

[0048] 2a: First n-type silicon carbide epitaxial layer

[0049] 2b: Second n-type silicon carbide epitaxial layer

[0050] 3. 103: p-type silicon carbide epitaxial layer

[0051] 4, 104: First p + Base region

[0052] 5, 105: Second p + Base region

[0053] 6, 106: High concentration area of ​​n-type

[0054] 6a: Lower n-type high-concentration region

[0055] 6b: Upper n-type high-concentration region

[0056] 7, 107: n + Type source polar region

[0057] 8, 108: p ++ Type contact area

[0058] 9, 109: Gate insulating film

[0059] 10, 110: Gate electrode

[0060] 11, 111: Interlayer insulating film

[0061] 13, 113: Source electrode

[0062] 14, 114: Back electrode

[0063] 18, 118: Trench

[0064] 20: Diode unit area

[0065] 21: MOS cell region

[0066] 50, 51, 150: Trench MOSFETs Detailed Implementation

[0067] Hereinafter, preferred embodiments of the silicon carbide semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers and regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols marked with n or p respectively indicate that the impurity concentration is higher and lower than the impurity concentration in layers or regions not marked with + and - respectively. The same markings for n or p containing + and - indicate similar concentrations, and the concentrations are not limited to being equal. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used for the same structures, and repeated descriptions are omitted. Additionally, in this specification, in the notation of the Miller index, "-" indicates the horizontal line following the index, and a negative index is indicated by marking "-" before the index.

[0068] (Implementation Method 1)

[0069] The semiconductor device of Embodiment 1 is constructed using a semiconductor with a bandgap wider than that of silicon (Si) (denoted as a wide bandgap semiconductor). Taking, for example, silicon carbide (SiC) as the wide bandgap semiconductor, the structure of the semiconductor device of Embodiment 1 will be described. Figure 1 This is a plan view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 2 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 A-A' cross-sectional view. Figure 3 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 The B-B' cross-sectional view. Figure 4 This represents the structure of the silicon carbide semiconductor device in Embodiment 1. Figure 1 The C-C' cross-sectional view.

[0070] like Figures 2-4 As shown, the trench MOSFET 50 has a MOS gate with a trench gate structure on the front side of the semiconductor substrate (the side of the p-type silicon carbide epitaxial layer 3 described later). The silicon carbide semiconductor substrate is an n-type silicon carbide semiconductor substrate. + An n-type silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) 2 and a p-type silicon carbide epitaxial layer (second semiconductor layer of the second conductivity type) 3 are sequentially epitaxially grown on an n-type silicon carbide substrate (semiconductor substrate of the first conductivity type) 1. Alternatively, a high-concentration n-type region 6 can be epitaxially grown on the n-type silicon carbide epitaxial layer 2.

[0071] The gate of a trench gate MOS structure consists of p-type silicon carbide epitaxial layers 3 and n. + Type source region (first semiconductor region of the first conductivity type) 7, p ++ It consists of a contact area (second semiconductor region of the second conductivity type) 8, a trench 18, a gate insulating film 9, and a gate electrode 10.

[0072] Specifically, trench 18 extends from the front side of the semiconductor substrate through the p-type silicon carbide epitaxial layer 3 along the depth direction z to reach the n-type high-concentration region 6 (in the absence of the n-type high-concentration region 6, it is the n-type silicon carbide epitaxial layer 2, hereinafter referred to as (2)). The depth direction z is from the front side of the semiconductor substrate toward the back side. Trench 18 is configured in a stripe shape.

[0073] A gate insulating film 9 is disposed along the inner wall of the trench 18, and a gate electrode 10 is disposed on the gate insulating film 9 in a manner embedded into the trench 18. A unit cell of the main semiconductor element is formed by the gate electrode 10 within a trench 18 and the adjacent mesa region (the region between adjacent trenches 18) separated by the gate electrode 10. Figure 2 and Figure 3 Although only one trench MOS structure is shown in the figure, a large number of trench MOS gate (insulated gate composed of metal-oxide-semiconductor) structures can be further arranged side by side.

[0074] An n-type region (hereinafter referred to as the n-type high-concentration region) 6 may be formed on the surface layer of the n-type silicon carbide epitaxial layer 2 on the source side (the source electrode 13 side described later) in such a way as to contact the p-type silicon carbide epitaxial layer 3. The n-type high-concentration region 6 is a so-called current spreading layer (CSL) that reduces the diffusion resistance of charge carriers. This n-type high-concentration region 6 is uniformly formed, for example, in a direction parallel to the front side of the substrate (the front side of the semiconductor substrate), in a way that covers the inner wall of the trench 18.

[0075] The n-type high-concentration region 6 extends from the interface with the p-type silicon carbide epitaxial layer 3 to a depth deeper than the bottom surface of the trench 18, closer to the drain side (the back electrode 14 side described later). A first p-type high-concentration region 6 can be selectively provided within the n-type high-concentration region 6. + Type base region 4, second p + Type base region 5. First p + The base region 4 is located between adjacent trenches 18 (platform area) and is connected to the second p. + The base region 5 is configured to contact the trench 18, and it is in contact with the p-type silicon carbide epitaxial layer 3. The second p-type... + The base region 5 covers at least the bottom surface of the trench 18 and the bottom corner of the bottom surface. The bottom corner of the trench 18 is the boundary between the bottom surface of the trench 18 and the sidewall.

[0076] First p + Type base region 4, second p +The pn junction between the base region 5 and the n-type silicon carbide epitaxial layer 2 is formed at a depth deeper than the bottom surface of the trench 18, closer to the drain side. Alternatively, the n-type high-concentration region 6 can be omitted, and the first pn junction can be... + Type base region 4, second p + The base region 5 is disposed inside the n-type silicon carbide epitaxial layer 2. For the first p + Type base region 4, second p + Regarding the depth position of the drain-side end of the base region 5, the first p + Type base region 4, second p + The pn junction between the base region 5 and the n-type silicon carbide epitaxial layer 2 is located deeper than the bottom surface of the trench 18, closer to the drain side, and can be modified according to various design conditions. Through the first p... + Type base region 4, second p + The base region 5 can prevent a high electric field from being applied to the gate insulating film 9 on the part along the bottom surface of the trench 18.

[0077] n-type silicon carbide epitaxial layer 3 is selectively provided inside the p-type silicon carbide epitaxial layer 3. + Type source pole region 7. With n + The source and pole regions are separated by 7 intervals, and p is selectively provided. ++ Type 8 contact area. + The source region 7 is in contact with the gate insulating film 9 of the sidewall of the trench 18 and is opposite to the gate electrode 10 through the gate insulating film 9 of the sidewall of the trench 18.

[0078] An interlayer insulating film 11 is disposed on the entire front side of the semiconductor substrate in such a way that it covers the gate electrode 10. A contact hole is formed in the interlayer insulating film 11, extending through the interlayer insulating film 11 in the depth direction z to reach the front side of the substrate.

[0079] The source electrode (first electrode) 13 is located within the contact hole and is connected to the semiconductor substrate (n). + The source electrode 7) is an ohmic contact and is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 13. ++ In the case of contact region 8, source electrode 13 and p ++ The contact area 8 is used for ohmic contact.

[0080] On the back side of the semiconductor substrate, a back electrode (second electrode) 14, which serves as the drain electrode, is provided. A drain electrode pad (not shown) is provided on the back electrode 14.

[0081] Here, in implementation method 1, as Figure 1 As shown, the groove 18 extends in a stripe pattern along the y-direction (first direction) and in the n-direction... +Multiple n are arranged on the front side of the silicon carbide substrate 1 in the x direction (second direction) perpendicular to the y direction. + Type source polar regions 7 and p ++ The contact area 8 is disposed between the grooves 18 in a manner that contacts the grooves 18 along the x-direction, and is periodically arranged in a manner that separates them from each other along the y-direction.

[0082] By configuring n in this way + Type source polar regions 7 and p ++ Type contact area 8, thereby enabling n + Type source polar regions 7 and p ++ The width of the contact area 8 is narrowed, which also allows for a narrower cell spacing (the distance between trenches 18). Therefore, the silicon carbide semiconductor device of Embodiment 1 can increase the channel width density per unit area and reduce the on-resistance.

[0083] Additionally, in n + Type source pole region 7 and p ++ A gap is provided between the contact areas 8, exposing a p-type silicon carbide epitaxial layer 3 in the gap. Since the y-direction is n... + The offset angle of the silicon carbide substrate 1 makes it easy for the position of the ion implantation mask to shift. If the position of the ion implantation mask shifts, n + Type source pole region 7 and p ++ If the contact areas overlap, point defects will occur, reducing gate reliability.

[0084] In implementation method 1, by n + Type source pole region 7 and p ++ Spacing is provided between the contact areas 8, so that even if n is formed + Type source pole region 7 or p ++ The position of the ion implantation mask in contact region 8 was shifted, which also prevents n + Type source pole region 7 and p ++ The contact area overlaps in type 8. Therefore, it can prevent the contact area from being affected by n. + Type source pole region 7 and p ++ The overlapping of the 8-type contact area can generate point defects, which can improve gate reliability.

[0085] Additionally, n + Type source pole region 7 and p ++ The positions of the ion implantation masks for each of the contact regions 8 may be offset by approximately 0.2 μm. Furthermore, due to ion diffusion during implantation, n + Type source polar regions 7 and p ++ The area of ​​contact region 8 may extend by approximately 0.3 μm. Therefore, n + Type source pole region 7 and p ++The spacing between the contact areas 8 is preferably (0.3+0.2)×2=1.0μm or more.

[0086] In addition, such as Figure 2 and Figure 4 As shown, n is provided between the depth direction z and the groove 18. + The region opposite the source region 7 is configured with a p-type silicon carbide epitaxial layer 3 and an n-type high-concentration region 6 (2). For example... Figure 3 and Figure 4 As shown, p is provided between the depth direction z and the groove 18. ++ The regions of the contact area 8 are respectively disposed in contact with each other, and the regions are respectively disposed with p-type silicon carbide epitaxial layer 3 and first p-type contact area 8. + Type base region 4 and second p + Type base region 5. For example... Figure 4 As shown, no p is set between the depth direction z and the trench 18. ++ Type contact area 8 and n + The regions of the source region 7 are respectively disposed in contact with each other, and the regions are respectively disposed with p-type silicon carbide epitaxial layer 3 and first p-type source region 7. + Type base region 4 and second p + Type base region 5.

[0087] Figure 5 This is a plan view showing other structures of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 In the structure shown, p ++ The contact area 8 contacts the groove 18 on both sides. However, as... Figure 5 As shown, p ++ The contact area 8 may contact the groove 18 on only one side, or it may not contact the groove 18 on either side.

[0088] The conditions for increasing the channel width density of the silicon carbide semiconductor device used in Embodiment 1 will be described in detail below. First, the channel width density Dch' of a conventional silicon carbide semiconductor device is determined. The width of the gate electrode 110 in the conventional silicon carbide semiconductor device is set as Lg' (μm), n + The length of the source pole region 107 in the x-direction is set as Ln' (μm), p ++ The length of the contact area 108 in the x direction is set as Lp' (μm) (refer to...) Figure 18 For example, their respective values ​​are Lg' = 0.7 μm, Ln' = 0.85 μm, and Lp' = 1 μm.

[0089] Here, if the element spacing Py' in the y direction is set to a fixed value, such as 1 μm, then the element spacing Px' (μm) in the x direction, the element spacing Py' (μm) in the y direction, the channel width Wch' (μm) in the y direction, and the channel width density Dch' (μm / μm) are... 2 As described below.

[0090] Px'=Lg'+2Ln'+Lp'

[0091] Py'=1

[0092] Wch'=2Py'

[0093] Dch'=Wch' / (Px'×Py')=2 / (Lg'+2Ln'+Lp')

[0094] In Embodiment 1, the width of the gate electrode 10 is also set to Lg, and n + The length of the source pole region 7 in the x-direction is set as Ln. In embodiment 1, n is also... + The length of the source pole region 7 in the y direction is set as Wn, p ++ The length of the contact area 8 in the y direction is set as Wpc, n + Type source pole region 7 and p ++ The length of the y-direction of the interval between the type contact areas 8 is set as Wp (refer to...). Figure 1 ).

[0095] In this case, the element spacing Px (μm) in the x-direction, the element spacing Py (μm) in the y-direction, the channel width Wch (μm) in the y-direction, and the channel width density Dch (μm / μm) are... 2 As described below.

[0096] Px=Lg+Ln

[0097] Py = 2Wp + Wpc + Wn

[0098] Wch = 2Wn (because the channel is formed at n) + (Both sides of the source pole region 7)

[0099] Dch=Wch / (Px×Py)=2Wn / {(Lg+Ln)×(2Wp+Wpc+Wn)}

[0100] Therefore, the condition for increasing the channel width density in the silicon carbide semiconductor device of Embodiment 1 is Dch≥Dch'. Thus, since Wn≥(2Wp+Wpc)×Px / (Px'-Px)=(2Wp+Wpc)×(Lg+Ln) / (Lg'+2Ln'+Lp'-Lg-Ln) holds, it is possible to increase the channel width density in the silicon carbide semiconductor device of Embodiment 1 compared to conventional silicon carbide semiconductor devices.

[0101] Figure 6 This is a graph showing the channel width density of the silicon carbide semiconductor device in Embodiment 1. Figure 6 In the diagram, the horizontal axis represents Wn(n) + The x-axis represents the length of the source pole region 7, in μm. The y-axis represents the channel width density Dch, in μm / μm. 2 In existing silicon carbide semiconductor devices, this represents the channel width density at Lg' = 0.7 μm, Ln' = 0.85 μm, and Lp' = 1 μm.

[0102] The silicon carbide semiconductor device of Embodiment 1 represents the cases where Lg = 0.7 μm, Ln = 1.1 μm, Wp = 1 μm, and Wpc = 1 μm in Embodiment 1 and the cases where Lg = 0.7 μm, Ln = 0.85 μm, Wp = 1 μm, and Wpc = 1 μm in Embodiment 2.

[0103] Depend on Figure 6 It can be seen that in Example 1, when Wn≥3.375μm, the channel width density Dch becomes higher than that of existing silicon carbide semiconductor devices. In Example 2, when Wn≥2.514μm, the channel width density Dch becomes higher than that of existing silicon carbide semiconductor devices.

[0104] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1)

[0105] Next, the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1 will be described. Figures 7-12 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0106] First, prepare n-type silicon carbide. + Type 1 silicon carbide substrate. Furthermore, in this n... + On the first main surface of the silicon carbide substrate 1, an n-type impurity, such as nitrogen atoms (N), is doped, while a first n-type silicon carbide epitaxial layer 2a is epitaxially grown to a thickness of, for example, about 30 μm. The state up to this point is shown in... Figure 7 .

[0107] Next, an ion implantation mask with predetermined openings is formed on the surface of the first n-type silicon carbide epitaxial layer 2a using, for example, an oxide film, via photolithography. Furthermore, p-type impurities such as aluminum are implanted into the openings of the oxide film to form a first p-type epitaxial layer with a depth of approximately 0.5 μm. + Type base region 4.

[0108] Additionally, with the first p adjacent to it + The base regions 4 are formed with a distance of approximately 1.5 μm between them. The first p... + The impurity concentration in base region 4 is set to, for example, 5 × 10⁻⁶. 18 / cm 3 about.

[0109] Next, a portion of the ion implantation mask can be removed, and n-type impurities such as nitrogen can be implanted into the opening to form a lower n-type high-concentration region 6a with a depth of approximately 0.5 μm, for example, on a portion of the surface region of the first n-type silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type high-concentration region 6a is set to, for example, 1 × 10⁻⁶. 17 / cm 3 Left and right. The current state is shown as follows: Figure 8 .

[0110] Next, a second n-type silicon carbide epitaxial layer 2b, doped with n-type impurities such as nitrogen, is formed on the surface of the first n-type silicon carbide epitaxial layer 2a with a thickness of approximately 0.5 μm. The impurity concentration of the second n-type silicon carbide epitaxial layer 2b is set to reach 3 × 10⁻⁶. 15 / cm 3 Left and right. Then, the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b together become n-type silicon carbide epitaxial layer 2.

[0111] Next, along the depth direction z of the second n-type silicon carbide epitaxial layer 2b, and without setting n... + On the surface of the region opposite to the first p-type source region 7, an ion implantation mask with predetermined openings is formed by photolithography using, for example, an oxide film. Furthermore, p-type impurities such as aluminum are implanted into the openings of the oxide film to interact with the first p-type source region 7. + The second p-type base region 4 is formed by overlapping to a depth of approximately 0.5 μm. + Type base region 5 (not shown). The second p + The impurity concentration in base region 5 is set to, for example, 5 × 10⁻⁶. 18 / cm 3 about.

[0112] Next, a portion of the ion implantation mask can be removed, and n-type impurities such as nitrogen can be implanted into the opening to form an upper n-type high-concentration region 6b with a depth of approximately 0.5 μm, for example, on a portion of the surface region of the second n-type silicon carbide epitaxial layer 2b. The impurity concentration of the upper n-type high-concentration region 6b is set to, for example, 1 × 10⁻⁶. 17 / cm 3 Left and right. The upper n-type high-concentration region 6b and the lower n-type high-concentration region 6a are formed in contact with each other at least partially, thus forming the n-type high-concentration region 6. However, there are cases where the n-type high-concentration region 6 is formed on the entire surface of the substrate and cases where it is not formed on the entire surface of the substrate. The state up to this point is shown in... Figure 9 .

[0113] Next, a p-type silicon carbide epitaxial layer 3 with a thickness of approximately 1.1 μm is formed on the surface of the n-type silicon carbide epitaxial layer 2 by epitaxial growth. The impurity concentration of the p-type silicon carbide epitaxial layer 3 is set to 4 × 10⁻⁶. 17 / cm 3 Left and right. After forming a p-type silicon carbide epitaxial layer 3 by epitaxial growth, p-type impurity ions such as aluminum can be further implanted into the channel region of the p-type silicon carbide epitaxial layer 3.

[0114] Next, an ion implantation mask with predetermined openings is formed on the surface of the p-type silicon carbide epitaxial layer 3 using, for example, an oxide film, by photolithography. Nitrogen (N), phosphorus (P), and other n-type impurities are ion implanted into these openings, forming an n-type impurity on a portion of the surface of the p-type silicon carbide epitaxial layer 3. + Type source pole region 7. Next, remove the part used to form n + An ion implantation mask for the p-type source region 7 is formed using the same method, and an ion implantation mask with a predetermined opening is formed. P-type impurities such as phosphorus are ion implanted onto a portion of the surface of the p-type silicon carbide epitaxial layer 3 to form a p-type silicon carbide epitaxial layer. ++ Type contact area 8 (not shown). ++ The impurity concentration of the n-type contact region 8 is set to be higher than that of the p-type silicon carbide epitaxial layer 3. + Type source polar regions 7 and p ++ Type 8 contact area is formed as Figure 1 The shape of the plan view. The state up to this point is shown in... Figure 10 . Figure 10 express Figure 1 The A-A' section.

[0115] Next, heat treatment (annealing) was carried out in an inert gas environment at approximately 1700℃ to implement the first p + Type base region 4, second p + Type base region 5, n + Type source polar regions 7 and p++ Activation treatment of contact region 8. It should be noted that, as described above, each ion implantation region can be activated by a single heat treatment, or it can be activated by heat treatment each time ion implantation is performed.

[0116] Next, a trench formation mask with predetermined openings is formed on the surface of the p-type silicon carbide epitaxial layer 3 using, for example, an oxide film, by photolithography. Then, a trench 18 is formed through the p-type silicon carbide epitaxial layer 3, reaching the n-type high-concentration region 6(2), by dry etching. The bottom of the trench 18 can also reach the first p-type epitaxial layer formed in the n-type high-concentration region 6(2). + Base region 4. Next, remove the mask used for trench formation. The state up to this point is shown in... Figure 11 .

[0117] Next, along n + A gate insulating film 9 is formed on the surface of the source region 7 and on the bottom and sidewalls of the trench 18. This gate insulating film 9 can be formed by thermal oxidation at a temperature of approximately 1000°C in an oxygen environment. Alternatively, the gate insulating film 9 can also be formed by deposition using a chemical reaction such as high-temperature oxidation (HTO).

[0118] Next, a polysilicon film doped with, for example, phosphorus atoms is formed on the gate insulating film 9. This polysilicon film can be formed by filling the trench 18. The polysilicon film is patterned by photolithography, and the gate electrode 10 is formed by leaving the polysilicon film inside the trench 18.

[0119] Next, an interlayer insulating film 11 is formed by depositing, for example, phosphor glass with a thickness of about 1 μm, covering the gate insulating film 9 and the gate electrode 10. The interlayer insulating film 11 and the gate insulating film 9 are then patterned by photolithography to form an interlayer insulating film 11. + Type source polar regions 7 and p ++ The contact holes in contact area 8 are exposed. Subsequently, heat treatment (reflow) is performed to planarize the interlayer insulating film 11. The state up to this point is shown in... Figure 12 Furthermore, after forming contact holes in the interlayer insulating film 11, a barrier metal composed of titanium (Ti), titanium nitride (TiN), or a stack of titanium and titanium nitride can be formed. In this case, n is also provided on the barrier metal. + Type source polar regions 7 and p ++ Type 8 contact area exposed contact hole.

[0120] Next, a conductive film, which serves as the source electrode 13, is formed within the contact holes and on the interlayer insulating film 11. The conductive film is, for example, a nickel (Ni) film. Additionally, in n +A nickel (Ni) film is also formed on the second main surface of the silicon carbide substrate 1. Subsequently, a heat treatment is performed at a temperature of, for example, around 970°C, to silicide the nickel film inside the contact holes, thus forming the source electrode 13. Simultaneously, the nickel film formed on the second main surface becomes compatible with the Ni film. + A back electrode 14 of an ohmic junction is formed on a silicon carbide substrate 1. Thereafter, unreacted nickel film is selectively removed, leaving only the source electrode 13, for example, in a contact hole.

[0121] Next, source electrode pads (not shown) are formed by embedding contact holes. A portion of the metal layer deposited to form the source electrode pads can be used as the gate pads. In n + On the back side of the silicon carbide substrate 1, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the contact portion of the back electrode 14 using sputtering deposition or the like. This metal film can also be formed by stacking multiple Ni and Ti films. Subsequently, annealing, such as rapid thermal annealing (RTA), is performed to silicide the metal film and form an ohmic contact. Then, a thick film, such as a stacked film consisting of a Ti film, a Ni film, and a gold (Au) film, is formed by electron beam deposition or the like, and the back electrode 14 is formed.

[0122] In the epitaxial growth and ion implantation described above, n-type impurities (n-type dopants) can be used, for example, nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb), which are n-type for silicon carbide. P-type impurities (p-type dopants) can be used, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl), which are p-type for silicon carbide. Thus, the process is completed. Figures 1-4 The trench MOSFET50 shown.

[0123] As explained above, according to the silicon carbide semiconductor device of Embodiment 1, n + Type source pole region and p ++ The contact areas are arranged between the grooves such that they contact the grooves in the x-direction and are periodically arranged to be separated from each other in the y-direction. This allows n... + Type source pole region and p ++ The width of the contact area is narrowed. Therefore, the cell spacing can be narrowed, and the channel width density per unit area can be increased, thereby reducing the on-resistance.

[0124] Additionally, in n + Type source pole region and p ++ Spacing is provided between the contact areas to expose the p-type silicon carbide epitaxial layer. This prevents n-type contact areas from being exposed. + Type source pole region and p++ The contact areas overlap. Therefore, it can prevent n-type contact areas from overlapping. + Type source pole region and p ++ The overlapping of the contact areas can generate point defects and improve gate reliability.

[0125] (Implementation Method 2)

[0126] Figure 13 This is a plan view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 14 This represents the structure of the silicon carbide semiconductor device in Embodiment 2. Figure 12 A-A' cross-sectional view. Figure 15 This represents the structure of the silicon carbide semiconductor device in Embodiment 2. Figure 12 The B-B' cross-sectional view.

[0127] The difference between the silicon carbide semiconductor device 51 of Embodiment 2 and the silicon carbide semiconductor device 50 of Embodiment 1 is that the latter includes a p-shaped structure disposed in the entire region enclosed by the trench 18. ++ The diode unit region 20 is a type contact area 8. By providing the diode unit region 20, it is not necessary to connect an external diode when using the silicon carbide semiconductor device 51 in an inverter or the like.

[0128] like Figure 14 and Figure 15 As shown, in the diode cell region 20, a p is provided between the depth direction z and the trench 18. ++ The regions opposite each other in the contact region 8 are provided with p-type silicon carbide epitaxial layers 3 and the first p-type silicon carbide epitaxial layer 3 in contact with each other. + Type base region 4 and second p + Type base region (third semiconductor region of the second conductivity type) 5.

[0129] Between the diode cell regions 20, there are provided areas with n in the trenches. + Type source pole region and p ++ The MOS stripes in the contact area are configured with one or more MOS cell regions 21. Figure 13 This illustrates an example where three MOS stripes are arranged in MOS cell region 21. In MOS cell region 21, similar to embodiment 1, n + Type source polar regions 7 and p ++ The contact area 8 is arranged between the grooves 18 in such a way that it contacts the grooves 18 in the x direction, and is periodically arranged in such a way that it is separated from each other in the y direction.

[0130] like Figure 14 As shown, n is provided between the depth direction z and the trench 18 in the MOS cell region 21. +In the region opposite the source region 7, similar to Embodiment 1, a p-type silicon carbide epitaxial layer 3 and an n-type high-concentration region 6 (2) are disposed. Although not shown, a p-type silicon carbide epitaxial layer 3 is disposed between the trench 18 in the MOS cell region 21 and the depth direction z. ++ In the regions opposite to the contact region 8, p-type silicon carbide epitaxial layers 3 and the first p-type contact region are disposed in contact with each other. + Type base region 4 and second p + Type base region 5. That is, it has the same structure as diode cell region 20. Although not shown, no p is provided between the depth direction z and the trench 18 in MOS cell region 21. ++ Type contact area 8 and n + In the regions opposite to the source region 7, p-type silicon carbide epitaxial layers 3 and the first p-type source region 7 are disposed in contact with each other. + Type base region 4 and second p + Type base region 5. That is, it has the same structure as diode unit region 20.

[0131] Additionally, in the first p in diode cell region 20 + n of type base region 4 + The surface area ratio of the silicon carbide substrate 1 side to the first p in the MOS cell region 21 is... + n of type base region 4 + The surface of the silicon carbide substrate 1 is shallow, that is, in the first p-type diode cell region 20. + n of type base region 4 + The surface of the silicon carbide substrate 1 can be located on the source electrode 13 side. In this case, when avalanche breakdown occurs during operation in the diode cell region 20, the continuous p-type region facilitates current flow and reduces the potential difference.

[0132] In Implementation 2, p is similar to that in Implementation 1. ++ The contact area 8 may contact the groove 18 on only one side, or it may not contact the groove 18 on either side.

[0133] The conditions for increasing the channel width density of the silicon carbide semiconductor device used in Embodiment 2 will be described in detail below. The number of MOS cell regions 21 arranged between diode cell regions 20 is set to n, and p... ++ The length of the contact area 8 in the x direction is set as Lp.

[0134] In this case, the element spacing Px (μm) in the x-direction, the element spacing Py (μm) in the y-direction, the channel width Wch (μm) in the y-direction, and the channel width density Dch (μm / μm) are... 2 As described below.

[0135] Px=n×(Lg+Ln)+Lg+Lp

[0136] Py = 2Wp + Wpc + Wn

[0137] Wch=2nWn

[0138] Dch=Wch / (Px×Py)=2nWn / [{n(Lg+Ln)+Lg+Lp}×(2Wp+Wpc+Wn)]

[0139] Therefore, the condition for increasing the channel width density in the silicon carbide semiconductor device of Embodiment 2 is Dch≥Dch'. Thus, since Wn≥(2Wp+Wpc)×Px / (nPx'-Px)=(2Wp+Wpc)×{n(Lg+Ln)+Lg+Lp} / {n(Lg'+2Ln'+Lp')-n(Lg+Ln)-Lg-Lp} holds, it is possible to increase the channel width density in the silicon carbide semiconductor device of Embodiment 2 compared to conventional silicon carbide semiconductor devices.

[0140] Figure 16 This is a graph showing the channel width density of the silicon carbide semiconductor device in Embodiment 2. Figure 16 In the diagram, the horizontal axis represents Wn(n) + The x-axis represents the length of the source pole region 7, in μm. The y-axis represents the channel width density Dch, in μm / μm. 2 In existing silicon carbide semiconductor devices, this represents the channel width density at Lg' = 0.7 μm, Ln' = 0.85 μm, and Lp' = 1 μm.

[0141] The silicon carbide semiconductor device of Embodiment 2 represents the cases where Lg = 0.7 μm, Ln = 1.1 μm, Wp = 1 μm, and Wpc = 1 μm in Embodiment 1, and the cases where Lg = 0.7 μm, Ln = 0.85 μm, Wp = 1 μm, and Wpc = 1 μm in Embodiment 2. In Embodiments 1 and 2, n (containing in the MOS cell region 21, having n in the trench) represents the area between the trenches. + Type source polar regions 7 and p ++ (The number of MOS stripes in contact region 8) is 1 to 4.

[0142] Depend on Figure 16It can be seen that in Example 1, when n ≥ 2, the channel width density Dch is higher than that of existing silicon carbide semiconductor devices. Specifically, it is known that when n = 2, the channel width density Dch becomes higher than that of existing silicon carbide semiconductor devices when Wn ≥ 11.572 μm; when n = 3, the channel width density Dch becomes higher when Wn ≥ 7.2 μm; and when n = 4, the channel width density Dch becomes higher than that of existing silicon carbide semiconductor devices when Wn ≥ 5.87 μm. Furthermore, it can be seen that in Example 2, when n ≥ 1, the channel width density Dch is higher than that of existing silicon carbide semiconductor devices. Specifically, it is known that when n = 1, the channel width density Dch becomes higher than that of existing silicon carbide semiconductor devices when Wn ≥ 31 μm; when n = 2, the channel width density Dch becomes higher when Wn ≥ 6.489 μm; when n = 3, the channel width density Dch becomes higher when Wn ≥ 4.65 μm; and when n = 4, the channel width density Dch becomes higher than that of existing silicon carbide semiconductor devices when Wn ≥ 3.975 μm.

[0143] The silicon carbide semiconductor device of Embodiment 2 can be manufactured in the same way as that of Embodiment 1, therefore the description of the manufacturing method is omitted.

[0144] As explained above, the silicon carbide semiconductor device according to Embodiment 2 has the same effect as Embodiment 1 even when a diode unit region is provided. Furthermore, by providing the diode unit region, it is not necessary to connect an external diode when using the silicon carbide semiconductor device in an inverter or similar device.

[0145] As described above, the present invention can be modified in various ways without departing from its spirit. In the various embodiments described above, for example, the size of each part and / or the impurity concentration can be set in various ways according to the required specifications. In addition, although the first conductivity type is set to n-type and the second conductivity type is set to p-type in each embodiment, the present invention is equally valid even if the first conductivity type is set to p-type and the second conductivity type is set to n-type.

[0146] Industrial applicability

[0147] As described above, the silicon carbide semiconductor device of the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machinery, ignition systems for automobiles, etc.

Claims

1. A semiconductor device, characterized in that, have: First conductivity type semiconductor substrate; A first semiconductor layer of a first conductivity type is disposed on the front side of the semiconductor substrate, and the impurity concentration is lower than that of the semiconductor substrate. A second semiconductor layer of a second conductivity type is selectively disposed on the surface of the first semiconductor layer that is opposite to the semiconductor substrate side; A first semiconductor region of a first conductivity type is selectively disposed on the surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate side; A second semiconductor region of a second conductivity type is selectively disposed on a surface layer of the second semiconductor layer that is opposite to the semiconductor substrate side; Striped trenches that penetrate the second semiconductor layer and reach the first semiconductor layer; A gate electrode is disposed inside the trench, separated by a gate insulating film; A first electrode is disposed on the surface of the second semiconductor layer, the first semiconductor region, and the second semiconductor region; as well as The second electrode is disposed on the back side of the semiconductor substrate. The first semiconductor region and the second semiconductor region are periodically arranged in a mutually separated manner in a first direction in which the trench extends in a stripe pattern. The width direction of the groove, which is perpendicular to the first direction within the front surface, is taken as the second direction. If the length of the first direction of the first semiconductor region is set to Wn, the length of the first direction of the second semiconductor region is set to Wpc, the length of the first direction between the first semiconductor region and the second semiconductor region is set to Wp, the length of the second direction of the gate electrode is set to Lg, the length of the second direction of the first semiconductor region is set to Ln, and the channel width density is set to Dch, Furthermore, when the first semiconductor region and the second semiconductor region are arranged in a stripe pattern parallel to the trench, the length of the gate electrode in the second direction is set to Lg'=0.7μm, the length of the first semiconductor region in the second direction is set to Ln'=0.85μm, the length of the second semiconductor region in the second direction is set to Lp'=1μm, and the channel width density is set to Dch'. Then Dch'=2 / (Lg'+2Ln'+Lp')=2 / 3.4, Dch≥Dch', and Dch=2Wn / {(Lg+Ln)×(2Wp+Wpc+Wn)} hold true.

2. The semiconductor device according to claim 1, characterized in that, Wn≥(2Wp+Wpc)×(Lg+Ln) / (Lg'+2Ln'+Lp'-Lg-Ln) holds true.

3. The semiconductor device according to claim 1 or 2, characterized in that, It also includes: a diode unit region, wherein only the second semiconductor region is provided on the surface layer of the second semiconductor layer that is opposite to the semiconductor substrate side.

4. The semiconductor device according to claim 3, characterized in that, It has a third semiconductor region of a second conductivity type that contacts the bottom of the trench. The diode unit region has the third semiconductor region disposed in a region opposite the second semiconductor region along the depth direction. The third semiconductor region is provided in the cell region other than the diode cell region, except for the region that is opposite to the first semiconductor region along the depth direction.

5. The semiconductor device according to claim 3 or 4, characterized in that, If the length of the second direction of the second semiconductor region in the diode unit region is set to Lp, and the number of unit regions other than the diode unit region arranged between the diode unit regions is set to n, Then Wn≥(2Wp+Wpc)×{n(Lg+Ln)+Lg+Lp} / {n(Lg'+2Ln'+Lp')-n(Lg+Ln)-Lg-Lp} holds true.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The trenches are provided in a plurality of manner, and the second semiconductor region is disposed between the trenches and may or may not be in contact with one of the trenches.

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