Memory device, integrated circuit device and forming method

Abstract

A memory device includes at least one bit line, at least one word line, and at least one memory cell including a capacitor and a transistor. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The insulating material is configured to break down at a predetermined breakdown voltage or a higher breakdown voltage applied between the first end and the second end. Embodiments of the present invention also disclose an integrated circuit device and a method for forming a memory device.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory devices, integrated circuit devices, and methods of forming the same. Background Art

[0002] Integrated circuit (IC) device comprises a plurality of semiconductor devices represented by IC layout diagram. IC layout diagram is hierarchical and comprises modules that perform higher level functions according to semiconductor device design specifications. Modules are usually constructed by a combination of cells, each cell representing one or more semiconductor structures configured to perform a specific function. Cells (sometimes also referred to as standard cells) with pre-designed layout diagrams are stored in standard cell libraries (hereinafter referred to as "libraries" or "cell libraries" for simplicity) and can be accessed, generated, optimized and verified by various tools (such as electronic design automation (EDA) tools). Examples of semiconductor devices and cells include memory devices and memory cells, respectively. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a memory device is provided, comprising: at least one bit line; at least one word line; and at least one memory cell, comprising a capacitor and a transistor, the transistor having: a gate terminal coupled to the word line; a first terminal, and a second terminal, the capacitor having: a first end coupled to the first terminal of the transistor, a second end coupled to the bit line; and an insulating material located between the first end and the second end and configured to break down at a predetermined breakdown voltage or a higher breakdown voltage applied between the first end and the second end.

[0004] According to another aspect of an embodiment of the present invention, an integrated circuit (IC) device is provided, comprising: a substrate having a plurality of transistors thereon; a metal layer located above the substrate, the metal layer comprising at least one bit line; and a plurality of capacitors located between the metal layer and the substrate in a thickness direction of the substrate, wherein each of the plurality of capacitors is coupled between at least one bit line and a first source / drain region of a corresponding transistor of the plurality of transistors; and each of the plurality of capacitors comprises an insulating material, the insulating material being configured to break down at a predetermined breakdown voltage or a higher breakdown voltage applied across the insulating material.

[0005] According to another aspect of an embodiment of the present invention, a method for forming a memory device is provided, comprising: forming a plurality of transistors above a substrate, wherein the plurality of transistors are arranged in an array, the array comprising rows and columns transverse to the rows; forming a plurality of word lines above the plurality of transistors, wherein a gate of the transistor in each of the columns is electrically coupled to at least one corresponding word line in the plurality of word lines; forming a plurality of metal-insulator-metal (MIM) capacitors above the plurality of transistors, wherein the plurality of capacitors are arranged in the same array as the plurality of transistors; each of the plurality of capacitors overlaps with a corresponding transistor in the plurality of transistors in a thickness direction of the substrate; each of the plurality of capacitors comprises a first end and a second end, the second end being electrically coupled to a source / drain region of the corresponding transistor; and forming a plurality of bit lines above the plurality of capacitors, wherein the first end of the capacitor in each of the rows is electrically coupled to a corresponding bit line in the plurality of bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the sizes of various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic block diagram of a memory device according to some embodiments.

[0008] FIG. 2A to FIG. 2C is a schematic circuit diagram of a memory cell in various operations according to some embodiments.

[0009] Figure 3 is a schematic circuit diagram of a memory device according to some embodiments.

[0010] 4A to 4D is a schematic diagram at various layers in an IC layout diagram of a memory device according to some embodiments.

[0011] Figure 5A is a schematic diagram of an IC layout diagram of a memory device according to some embodiments.

[0012] Figure 5B is a schematic diagram of an IC layout diagram of a memory device according to some embodiments, including a circuit diagram.

[0013] FIG. 6A to FIG. 6C are schematic cross-sectional views of various IC devices according to some embodiments.

[0014] 7A to 7D are schematic cross-sectional views of an IC device being fabricated at various stages of the fabrication process according to some embodiments.

[0015] Figure 8 is a flow chart of a method according to some embodiments.

[0016] Fig. 9 is a flow chart of a method according to some embodiments.

[0017] Fig.10 is a flow chart of a method according to some embodiments.

[0018] Fig.11 is a block diagram of an EDA system according to some embodiments.

[0019] Fig.12 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of elements, materials, values, steps, operations, materials, arrangements, etc. are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. Other elements, values, operations, materials, arrangements, etc. can be envisioned. For example, in the following description, forming a first component above or on a second component can include an embodiment in which the first component is in direct contact with the second component, and can also include an embodiment in which an additional component is formed between the first component and the second component so that the first component is not in direct contact with the second component. In addition, the present invention can repeat reference numbers and / or characters in multiple instances. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] In some embodiments, the memory cell has a one-transistor-one-capacitor (1T1C) configuration having a capacitor and a transistor coupled in series between a bit line and ground. The gate terminal of the transistor is coupled to a word line. The capacitor is a metal-to-metal (or insulator-to-metal) (MIM) capacitor above the transistor. The insulating material of the capacitor is configured to break down at a predetermined breakdown voltage or a higher breakdown voltage applied across the insulating material. When the insulating material has not yet broken down, the memory cell stores a first data, such as a logic "1". When the insulating material breaks down, the memory cell stores a second data, such as a logic "0". Compared to other methods such as gate oxide antifuses and metal fuses, the memory cell in at least one embodiment provides one or more improvements, including but not limited to a smaller chip area, a lower programming voltage, a lower interference voltage, etc.

[0023] Figure 1 1 is a schematic block diagram of a memory device 100 according to some embodiments. The memory device is an IC device. In at least one embodiment, the memory device is a single IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuits other than the memory device for other functions.

[0024] The memory device 100 includes at least one memory cell MC and a controller (also referred to as a "control circuit") 102, which is coupled to control the operation of the memory cell MC. Figure 1In an example configuration, the memory device 100 includes a plurality of memory cells MC arranged in a plurality of columns and rows in a memory array 104. The memory device 100 also includes: a plurality of word lines WL_0 to WL_m extending along the rows, a plurality of source lines SL_0 to SL_m extending along the rows, and a plurality of bit lines (also referred to as "data lines") BL_0 to BL_k extending along the columns of the memory cells MC. Each memory cell MC is coupled to the controller 102 through at least one of the word lines, at least one of the source lines, and at least one of the bit lines. Examples of word lines include, but are not limited to, a read word line for transmitting an address of a memory cell MC to be read therefrom, a write word line for transmitting an address of a memory cell MC to be written thereto, and the like. In at least one embodiment, a group of word lines is configured to be used as both a read word line and a write word line. Examples of bit lines include a read bit line for transmitting data read from a memory cell MC represented by a corresponding word line, a write bit line for transmitting data to be written to a memory cell MC represented by a corresponding word line, and the like. In at least one embodiment, a set of bit lines is configured to function as both read bit lines and write bit lines. In one or more embodiments, each memory cell MC is coupled to a pair of bit lines referred to as a bit line and a bit line bar. Word lines are generally referred to herein as WL, source lines are generally referred to herein as SL, and bit lines are generally referred to herein as BL. Various numbers of word lines and / or bit lines and / or source lines in the memory device 100 are within the scope of various embodiments. In at least one embodiment, the source lines SL are arranged in columns rather than in rows, as in Figure 1 In at least one embodiment, the source line SL is omitted.

[0025] exist Figure 1 In an example configuration, the controller 102 includes a word line driver 112, a source line driver 114, a bit line driver 116, and a sense amplifier (SA) 118, which are configured to perform at least one of a read operation or a write operation. In at least one embodiment, the controller 102 also includes: one or more clock generators for providing clock signals to various elements of the memory device 100; one or more input / output (I / O) circuits for exchanging data with external devices; and / or one or more controllers for controlling various operations in the memory device 100. In at least one embodiment, the source line driver 114 is omitted.

[0026] The word line driver 112 is coupled to the memory array 104 via the word line WL. The word line driver 112 is configured to decode the row address of the memory cell MC selected for access in the read operation or the write operation. The word line driver 112 is configured to provide a voltage to the selected word line WL corresponding to the decoded row address, and to provide a different voltage to other unselected word lines WL. The source line driver 114 is coupled to the memory array 104 via the source line SL. The source line driver 114 is configured to provide a voltage to the selected source line SL corresponding to the selected memory cell MC, and to provide a different voltage to other unselected source lines SL. The bit line driver 116 (also referred to as a "write driver") is coupled to the memory array 104 via the bit line BL. The bit line driver 116 is configured to decode the column address of the memory cell MC selected for access in the read operation or the write operation. The bit line driver 116 is configured to provide a voltage to the selected bit line BL corresponding to the decoded column address, and to provide a voltage to other unselected bit lines BL. In a write operation, the bit line driver 116 is configured to provide a write voltage (also referred to as a "programming voltage") to the selected bit line BL. In a read operation, the bit line driver 116 is configured to provide a read voltage to the selected bit line BL. SA 118 is coupled to the memory array 104 via the bit line BL. In a read operation, SA 118 is configured to sense data read from the accessed memory cell MC and retrieved through the corresponding bit line BL. The described memory device configurations are examples, and other memory device configurations are within the scope of various embodiments. In at least one embodiment, the memory device 100 is a one-time programmable (OTP) non-volatile memory, and the memory cell MC is an OTP memory cell. Other types of memory are within the scope of various embodiments. Exemplary storage types of the memory device 100 include, but are not limited to, electric fuses (eFuse), antifuses, magnetoresistive random access memories (MRAM), and the like.

[0027] FIG. 2A to FIG. 2C is a schematic circuit diagram of a memory cell 200 in various operations according to some embodiments. In at least one embodiment, the memory cell 200 corresponds to at least one of the memory cells MC in the memory device 100.

[0028] exist Figure 2A , the memory cell 200 includes a capacitor C and a transistor T. The transistor T has a gate terminal 222 coupled to a word line WL, a first terminal 224, and a second terminal 226. The capacitor C has a first end 234 coupled to the first terminal 224 of the transistor T, a second end 236 coupled to the bit line BL, and an insulating material ( Figure 2A(not shown). The insulating material is configured to break down at a predetermined breakdown voltage or higher applied between the first end 234 and the second end 236 .

[0029] exist Figure 2A In an example configuration of , the second terminal 226 is coupled to the source line SL. In other words, the capacitor C and the transistor T are coupled in series between the bit line BL and the source line SL. In at least one embodiment, the word line WL corresponds to at least one of the word lines WL in the memory device 100, the source line SL corresponds to at least one of the source lines SL in the memory device 100, and the bit line BL corresponds to at least one of the bit lines BL in the memory device 100. In at least one embodiment, the source line SL is omitted, and the second terminal 226 is coupled to a node having a predetermined voltage. Examples of the predetermined voltage include, but are not limited to, a ground voltage VSS, a positive power supply voltage VDD, and the like.

[0030] Examples of transistor T include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductors (CMOS) transistors, P-channel metal oxide semiconductors (PMOS), N-channel metal oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with source / drain bumps, nanosheet FETs, nanowire FETs, etc. The first terminal 224 is the source / drain of transistor T, and the second terminal 226 is the other source / drain of transistor T. Figure 2A In the example configuration depicted, transistor T is an NMOS transistor, first terminal 224 is the drain of transistor T, and second terminal 226 is the source of transistor T. Other configurations including PMOS transistors instead of NMOS transistors are within the scope of various embodiments.

[0031] Examples of capacitor C include, but are not limited to, MIM capacitors. Other capacitor configurations, such as MOS capacitors, are within the scope of various embodiments. The MIM capacitor includes a lower electrode corresponding to one of the first end 234 or the second end 236, an upper electrode corresponding to the other of the first end 234 or the second end 236, and an insulating material sandwiched between the lower electrode and the upper electrode. Examples of insulating materials include, but are not limited to, silicon dioxide, ZrO, TiO2, HfO x, high-k dielectrics, etc. Examples of high-k dielectrics include, but are not limited to, zirconium dioxide, hafnium dioxide, zirconium silicate, hafnium silicate, etc. In at least one embodiment, the insulating material of capacitor C is the same or similar to the gate dielectric included in a transistor such as transistor T. In at least one embodiment, transistor T is formed in a semiconductor substrate. Front-end-of-line (FEOL) processing is first performed, and then capacitor C is formed as a MIM capacitor in a back-end-of-line (BEOL) processing above transistor T. About FIG. 6A to FIG. 6B and 7A to 7D Memory cells according to some embodiments are described.

[0032] In some embodiments, the operation of the memory unit 200 is controlled by a controller, such as the controller 102 of the memory device 100 .

[0033] For example, when the memory cell 200 is selected in a programming operation (also referred to as a "write operation"), the controller 102 is configured to apply a turn-on voltage to the gate terminal 222 of the transistor T via the word line WL to turn on the transistor T. The controller 102 is further configured to apply a programming voltage to the second end 236 of the capacitor C via the bit line BL, and to apply a ground voltage VSS to the source line SL. In at least one embodiment, the source line SL is always grounded. When the transistor T is turned on by the turn-on voltage and the first end 234 of the capacitor C is electrically coupled to the ground voltage VSS on the source line SL, the programming voltage applied from the bit line BL to the second end 236 causes a predetermined breakdown voltage or a higher breakdown voltage to be applied between the first end 234 and the second end 236 of the capacitor C. As a result, at the applied breakdown voltage or a higher breakdown voltage, a short circuit occurs in the insulating material of the capacitor C. In other words, the insulating material is broken down and becomes a resistive structure, for example, as described with respect to Figure 2B The broken-down insulating material corresponds to first data or a first logic value stored in the memory cell 200. In at least one embodiment, the first data corresponding to the broken-down insulating material is a logic "0".

[0034] When the memory cell 200 is not selected in the programming operation, the controller 102 is configured not to apply at least one of the turn-on voltage, the programming voltage, or the ground voltage VSS to the corresponding gate terminal 222, the bit line BL, or the source line SL. As a result, the insulating material of the capacitor C is not broken down, and the capacitor C maintains, for example, about Figure 2C The insulating material that has not been broken down corresponds to the second data or the second logic value stored in the memory cell 200. In at least one embodiment, the second reference corresponding to the insulating material that has not been broken down is a logic "1".

[0035] When the memory cell 200 is selected in a read operation, the controller 102 is configured to apply a turn-on voltage to the gate terminal 222 of the transistor T via the word line WL to turn on the transistor T. The controller 102 is further configured to apply a read voltage to the second end 236 of the capacitor C via the bit line BL, and to apply a ground voltage VSS to the source line SL. In at least one embodiment, the source line SL is always grounded. When the transistor T is turned on by the turn-on voltage and the first end 234 of the capacitor C is electrically coupled to the ground voltage VSS on the source line SL, the controller 102 is configured to sense the current flowing in the memory cell 200, for example, by using the SA 118, to detect the data stored in the memory cell 200.

[0036] exist Figure 2B In the embodiment, when the memory cell 200 has been pre-programmed to store logic "0", the insulating material of the capacitor C has been broken down and turned into a resistive structure 238, and the read voltage applied to the bit line BL causes the current Iread to flow through the resistive structure 238 and the turned-on transistor T to the ground voltage VSS at the source line SL. The SA 118 is configured to sense the current Iread. The controller 102 is configured to detect that the memory cell 200 stores logic "0" based on the sensed current Iread.

[0037] exist Figure 2C In the example, when the memory cell 200 has not been preprogrammed, the memory cell 200 stores logic "1", the insulating material of the capacitor C has not yet been broken down, and the capacitor C maintains a capacitive structure. The read voltage applied to the bit line BL is lower than the breakdown voltage, and no current or a current close to zero Iread flows through the capacitor C and the turned-on transistor T to the ground at the source line SL. The SA 118 is configured to sense the absence of a current or a current close to zero Iread flowing through the memory cell 200. Therefore, the controller 102 is configured to detect that the memory cell 200 stores logic "1".

[0038] In at least one embodiment, the turn-on voltage in the programming operation is the same as the turn-on voltage in the read operation. Other configurations that apply different turn-on voltages in different operations are within the scope of various embodiments. The read voltage is lower than the programming voltage. In at least one embodiment, the programming voltage is about 1.2V or less, the breakdown voltage is about 1.2V, and the read voltage is about 0.75V. Other voltage schemes are within the scope of various embodiments.

[0039] In some embodiments, a memory cell having the described 1T1C configuration enables one or more advantages to be achieved compared to other approaches, including but not limited to smaller chip area (i.e., the area occupied by the memory cells on the wafer), lower programming voltage, lower interference voltage, improved reliability, enhanced data security, etc.

[0040] For example, a memory cell according to other methods using a gate oxide antifuse occupies about 0.066 μm 2 The chip area is about 0.038 μm, and has a program voltage of about 3.5 V, a program disturb voltage of about 2.0 V, and a read disturb voltage of about 1.3 V. In contrast, an exemplary memory cell having a 1T1C configuration according to some embodiments occupies about 0.038 μm 2 The present invention relates to a memory cell that is memory-compatible with a gate oxide anti-fuse and has a smaller chip area, a lower programming voltage of about 1.2V, and a lower disturb voltage. The higher programming voltage of the memory cell using the gate oxide anti-fuse causes reliability issues. The lower memory cell programming voltage according to some embodiments results in lower memory cell stress, thereby improving reliability. The memory cell according to some embodiments is further suitable for advanced process nodes. In contrast, the memory cell using the gate oxide anti-fuse may encounter scalability and / or manufacturability issues at advanced process nodes.

[0041] For another example, a memory cell according to other methods using metal fuses occupies about 1.663 μm 2 chip area, and has a programming voltage of about 1.8 V. In contrast, example memory cell embodiments according to some examples having a 1T1C configuration occupy about 0.038 μm 2 The present invention provides a smaller chip area of ​​the present invention, which corresponds to a chip area reduction of more than 90%. The lower memory cell programming voltage according to some embodiments results in lower memory cell stress, thereby improving reliability compared to memory cells using metal fuses. In addition, according to some embodiments, memory cells using metal fuses have data security issues, which are eliminated in the memory cells. In addition, the memory cells according to some embodiments are suitable for advanced process nodes. In contrast, memory cells using gate oxide antifuses or metal fuses may encounter scalability and / or manufacturability issues at advanced process nodes.

[0042] Figure 3 is a schematic circuit diagram of a memory device 300 according to some embodiments.

[0043] The memory device 300 includes a plurality of memory cells Bit_0, Bit_1, ..., Bit_7. Each memory cell Bit_0, Bit_1, ..., Bit_7 has a 1T1C configuration of the memory cell 200 with a source line SL grounded, and includes a transistor and a capacitor coupled in series between the corresponding bit line and the ground. For example, the memory cells Bit_0, Bit_1, ..., Bit_7 include capacitors C0, C1, ..., C7 and transistors T0, T1, ..., T7, respectively. The capacitors C0, C1, C2, C3 of the memory cells Bit_0, Bit_1, Bit_2, Bit_3 are usually coupled to the bit line BL0. The gate terminals of the transistors T0, T1, T2, T3 are correspondingly coupled to the word lines WL0, WL1, WL2, WL3. The capacitors C4, C5, C6, C7 of the memory cells Bit_4, Bit_5, Bit_6, Bit_7 are usually coupled to the bit line BL1. The gate terminals of transistors T4, T5, T6, and T7 are coupled to word lines WL0, WL1, WL2, and WL3, respectively. Memory cells Bit_0, Bit_1, Bit_2, and Bit_3 commonly coupled to bit line BL0 correspond to a first memory cell string, and memory cells Bit_4, Bit_5, Bit_6, and Bit_7 commonly coupled to bit line BL1 correspond to a second memory cell string. In at least one embodiment, each memory cell Bit_0, Bit_1, ..., Bit_7 corresponds to a memory cell MC, each of bit lines BL0 and BL1 corresponds to bit line BL, and each of word lines WL0, WL1, WL2, and WL3 corresponds to a word line WL in the memory device 100. In at least one embodiment, one or more advantages described herein can be realized in the memory device 300.

[0044] 4A to 4D 4 is a schematic diagram of various layers in an IC layout diagram 400 of a memory device according to some embodiments. In at least one embodiment, the IC layout diagram 400 includes memory cells Bit_0, Bit_1, Bit_2, and Bit_3 of the memory device 300. The memory cells Bit_0, Bit_1, Bit_2, and Bit_3 are arranged adjacent to each other. 4A to 4D The boundary of the memory cell Bit_2 is shown in FIG. 1 , and for simplicity, 4A to 4D In at least one embodiment, the IC layout 400 and / or the layout of one or more memory cells Bit_0, Bit_1, Bit_2, Bit_3 are stored in a standard cell library on a non-transitory computer readable medium.

[0045] Figure 4AA schematic diagram 400A at the device level of an IC layout diagram 400 is included. The IC layout diagram 400 includes a first active area OD1, a second active area OD2, gate areas PO1, PO2, ..., PO6, and conductive areas MD0, MD1, ..., MD6. The first active area OD1 and the second active area OD2 extend in a first direction (i.e., the X direction). The active area is sometimes referred to as an oxide definition (OD) area and is schematically illustrated in the accompanying drawings with the label "OD". The X direction is sometimes referred to as the OD direction. The first active area OD1 and the second active area OD2 include P-type dopants and / or N-type dopants to form one or more circuit elements or devices. Examples of circuit elements include, but are not limited to, transistors and diodes. An active area configured to form one or more PMOS devices therein is referred to as a "PMOS active area", and an active area configured to form one or more NMOS devices therein is referred to as an "NMOS active area". For example, the first active region OD1 and the second active region OD2 are both NMOS active regions configured to form NMOS transistors in the memory cells Bit_0 , Bit_1 , Bit_2 , and Bit_3 .

[0046] The gate regions PO1, PO2, ..., PO6 extend in a second direction (i.e., Y direction) transverse to the X direction from the first active region OD1 across the second active region OD2. Each gate region PO1, PO2, ..., PO6 includes a conductive material, such as polysilicon, and is schematically illustrated in the accompanying drawings with the label "PO". The Y direction is sometimes referred to as the Poly direction. Other conductive materials for the gate regions, such as metals, are within the scope of various embodiments. Figure 4A In the instance configuration of Figure 3 Each transistor in the memory cell Bit_0 includes two devices. Figure 4A The transistor T1 (not shown) of the memory cell Bit_1 is composed of the gate regions PO2 and PO3 coupled in parallel and the corresponding source / drain regions in the second active region OD2. Figure 4A The transistor T2 (not shown) of the memory cell Bit_2 is composed of the gate regions PO2 and PO3 coupled in parallel and the corresponding source / drain regions in the first active region OD1. Figure 4A The transistor T3 (not shown) of the memory cell Bit_3 is composed of the gate regions PO4 and PO5 coupled in parallel and the corresponding source / drain regions in the first active region OD1. Figure 4A The gate regions PO4 and PO5 are connected in parallel and the corresponding source / drain regions in the second active region OD2 are formed. The gate regions PO1 and PO6 are dummy gate regions.

[0047] IC layout diagram 400 also includes cut Poly regions CPO1, CPO2, CPO3, CPO4 extending across gate regions PO1, PO2, ..., PO6 in the X direction and corresponding to regions where gate regions PO1, PO2, ..., PO6 will not be formed. Cut Poly regions CPO1, CPO2, CPO3, CPO4 are schematically illustrated in the figure with the label "CPO".

[0048] Conductive regions MD0, MD1, ..., MD6 extend in the Y direction and are arranged alternately with gate regions PO1, PO2, ..., PO6 in the X direction. Conductive regions MD0, MD1, ..., MD6 overlap and are configured to form an electrical connection with the first active region OD1 and the second active region OD2. Conductive regions MD0, MD1, ..., MD6 are referred to herein as "MD regions", i.e., metal zero peroxide regions, and are schematically illustrated in the accompanying drawings with the label "MD". The MD region includes a conductive material formed above the corresponding active region to define an electrical connection from one or more devices formed in the active region to other internal circuits or external circuits of the memory device. In some embodiments, the spacing in the X direction between adjacent MD regions, i.e., the distance in the X direction between the center lines of adjacent MD regions, is equal to the spacing in the X direction between adjacent gate regions PO1, PO2, ..., PO6.

[0049] The regions MD2 , MD4 overlap and are configured to form electrical connections to the drain regions of the transistors T0 , T1 , T2 , T3 of the memory cells Bit_0 , Bit_1 , Bit_2 , Bit_3 in the first and second active regions OD1 , OD2 .

[0050] The regions MD1 , MD3 , MD5 overlap and are configured to form electrical connections with source regions of transistors T0 , T1 , T2 , T3 of memory cells Bit_0 , Bit_1 , Bit_2 , Bit_3 in the first and second active regions OD1 , OD2 .

[0051] Regions MD0, MD3, MD6 are arranged along the boundaries of memory cells Bit_0, Bit_1, Bit_2, Bit_3 and overlap. In the placement and routing operation described herein (also referred to as "automatic placement and routing (APR)"), cells are placed in an IC layout to abut each other at their respective boundaries, e.g. Figure 4A Shown schematically.

[0052] The IC layout diagram 400 also includes cut MD regions CMD1, CMD2, CMD3, CMD4 extending across regions MD0, MD2, MD4, MD6 in the X direction and corresponding to regions where regions MD0, MD2, MD4, MD6 will not be formed. The cut MD regions CMD1, CMD2, CMD3, CMD4 are schematically illustrated in the figures with the label "CMD".

[0053] IC layout 400 also includes conductive vias over and in electrical contact with corresponding gate regions or MD regions. Vias over and in electrical contact with MD regions are sometimes referred to as "vias to devices" and are schematically illustrated in the accompanying drawings with the label "VD". Vias over and in electrical contact with gate regions are sometimes referred to as vias to gates and are schematically illustrated in the accompanying drawings with the label "VG". Figure 4A In the example configuration of , IC layout diagram 400 includes vias VD1 , VD2 , . . . , VD7 and vias VG1 , VG2 , . . . , VG8 .

[0054] The through holes VD6, VD1, VD2, VD7 are electrically contacted with the regions MD2, MD4 above the first active region OD1 and the second active region OD2, and are configured to electrically couple the drain regions of the transistors T0, T1, T2, T3 of the memory cells Bit_0, Bit_1, Bit_2, Bit_3 to one or more upper layers to couple with the corresponding capacitors C0, C1, C2, C3 of the memory cells Bit_0, Bit_1, Bit_2, Bit_3.

[0055] Vias VD3, VD4, VD5 are in electrical contact with regions MD1, MD3, MD5 and are configured to electrically couple source regions of transistors T0, T1, T2, T3 of memory cells Bit_0, Bit_1, Bit_2, Bit_3 to one or more upper layers, for example, to a layer including a conductive pattern having a ground voltage VSS.

[0056] Vias VG5, VG6 are electrically in contact with gate regions PO2, PO3 in memory cell Bit_0 and are configured to electrically couple the gate of transistor T0 of memory cell Bit_0 to one or more upper layers to couple with corresponding word line WL0 as described herein. Transistor T0 has a gate consisting of gate regions PO2, PO3 coupled in parallel, a drain coupled to region MD2, and a source coupled to regions MD1, MD3.

[0057] The vias VG1, VG2 are in electrical contact with the gate regions PO2, PO3 in the memory cell Bit_1 and are configured to electrically couple the gate of the transistor T1 of the memory cell Bit_1 to one or more upper layers to couple with the corresponding word line WL1 as described herein. The transistor T1 has a gate consisting of the gate regions PO2, PO3 coupled in parallel, a drain coupled to the region MD2, and a source coupled to the regions MD1, MD3.

[0058] The vias VG3, VG4 are in electrical contact with the gate regions PO4, PO5 in the memory cell Bit_2 and are configured to electrically couple the gate of the transistor T2 of the memory cell Bit_2 to one or more upper layers to couple with the corresponding word line WL2 as described herein. The transistor T2 has a gate consisting of the gate regions PO4, PO5 coupled in parallel, a drain coupled to the region MD4, and a source coupled to the regions MD3, MD5.

[0059] Vias VG7, VG8 are electrically in contact with gate regions PO4, PO5 in memory cell Bit_3 and are configured to electrically couple the gate of transistor T3 of memory cell Bit_3 to one or more upper layers to couple with corresponding word line WL3 as described herein. Transistor T3 has a gate consisting of gate regions PO4, PO5 coupled in parallel, a drain coupled to region MD4, and a source coupled to regions MD3, MD5.

[0060] Figure 4B 4 is a schematic diagram 400B at the M0 and M1 layers of the IC layout diagram 400. The M0 layer, i.e., the zero metal (M0) layer, is the lowest metal layer directly located above the VD and VG vias and electrically contacted therewith, and is schematically shown in the figure with the label "M0". The M1 layer is a metal layer directly located above the M0 layer, and is schematically shown in the figure with the label "M1". The IC layout diagram 400 also includes other metal layers stacked in sequence above the M1 layer, and are schematically shown in the figure with corresponding labels, such as "M2", "M5", "M6" and "M7". The layout diagram 400 also includes a via layer of continuous metal layers arranged between and electrically coupled to continuous metal layers. The via layer Vn is arranged between and electrically couples the Mn layer and the Mn+1 layer, where n is an integer from zero to zero. For example, the via zero (V0) layer is the lowest via layer arranged between and electrically couples the M0 layer and the M1 layer, and is schematically shown in the figure with the label "V0". Other via layers are schematically shown in the drawings with corresponding labels such as "V1", "V5" and "V6". For simplicity, gate regions PO1, PO2, ..., PO6 are shown in FIG. Figure 4B Schematically illustrated by the corresponding center line, also called the "gate rail".

[0061] The M0 layer includes conductive patterns M0_1, M0_2, ..., M0_8 and SL. The IC layout diagram 400 also includes cut M0 regions CM0_1, M0_2 ​​corresponding to regions where the M0 layer will not be formed. The cut M0 regions CM0_1, CM0_2 are schematically shown in the drawing with a label "CM0".

[0062] Patterns M0_7, M0_1, M0_2, M0_8 are located above corresponding through holes VD6, VD1, VD2, VD7 and are electrically contacted with the devices, and are configured to electrically couple the drain regions of transistors T0, T1, T2, T3 of memory cells Bit_0, Bit_1, Bit_2, Bit_3 to one or more upper layers to couple with corresponding capacitors C0, C1, C2, C3 of memory cells Bit_0, Bit_1, Bit_2, Bit_3.

[0063] Patterns M0_3 and M0_4 are electrically isolated from each other by cutting M0 region CM0_1, and patterns M0_5 and M0_6 are electrically isolated from each other by cutting M0 region CM0_2. Pattern M0_3 is located above and electrically in contact with vias VG1 and VG2 to couple in parallel gate regions PO2 and PO3 of transistor T1 of memory cell Bit_1. Pattern M0_4 is located above and electrically in contact with vias VG3 and VG4 to couple in parallel gate regions PO4 and PO5 of transistor T2 of memory cell Bit_2. Pattern M0_5 is located above and electrically in contact with vias VG5 and VG6 to couple in parallel gate regions PO2 and PO3 of transistor T0 of memory cell Bit_0. Pattern M0_6 is located above and electrically in contact with vias VG7 and VG8 to couple in parallel gate regions PO4 and PO5 of transistor T3 of memory cell Bit_3. The patterns M0_5 , M0_3 , M0_4 , M0_6 are configured to couple gate regions of transistors T0 , T1 , T2 , T3 of memory cells Bit_0 , Bit_1 , Bit_2 , Bit_3 to corresponding word lines WL0 , WL1 , WL2 , WL3 , as described herein.

[0064] The pattern SL is located above and electrically contacts the vias VD3, VD4, and VD5, and is configured to electrically couple the source regions of the transistors T0, T1, T2, and T3 of the memory cells Bit_0, Bit_1, Bit_2, and Bit_3 to the ground voltage VSS. In at least one embodiment, the pattern SL corresponds to Figure 1 and FIG. 2A to FIG. 2C The source line SL is described.

[0065] The M1 layer includes conductive patterns M1_1, M1_2, ..., M1_7 and word line patterns WL0, WL1, WL2, WL3. The V0 layer includes vias V0_1, V0_2, ..., V0_11 arranged between and electrically coupling corresponding patterns of the M0 and M1 layers.

[0066] Patterns M0_7, M0_1, M0_2, M0_8 are correspondingly coupled to patterns M1_6, M1_2, M1_3, M1_7 through corresponding through holes V0_10, V0_1, V0_2, V0_11 to electrically couple drain regions of transistors T0, T1, T2, T3 of memory cells Bit_0, Bit_1, Bit_2, Bit_3 with corresponding capacitors C0, C1, C2, C3 of corresponding memory cells Bit_0, Bit_1, Bit_2, Bit_3, as described herein.

[0067] The patterns M0_5, M0_3, M0_4, and M0_6 are respectively coupled to the word line patterns WL1, WL2, WL0, and WL3 through the corresponding through holes V0_8, V0_3, V0_4, and V0_9 to electrically couple the gate regions of the transistors T0, T1, T2, and T3 of the memory cells Bit_0, Bit_1, Bit_2, and Bit_3 with the corresponding word line patterns WL0, WL1, WL2, and WL3. In at least one embodiment, the word line patterns WL0, WL1, WL2, and WL3 correspond to the Figure 3 The word lines WL0, WL1, WL2, WL3 described; and / or coupled to the related Figure 1 and 2A to Figure 2C Describe the word line.

[0068] The pattern SL is coupled to the patterns M1_4, M1_1, M1_5 through corresponding vias V0_5, V0_6, V0_7. The patterns M1_4, M1_1, M1_5 are used to further route (or elevate) the pattern SL to the M2 layer.

[0069] Figure 4C 400C is a schematic diagram at the M1 and M2 layers of the IC layout diagram 400. The schematic diagram 400C also shows a via layer between the M1 layer and the M2 layer, namely the V1 layer. The M2 layer includes conductive patterns M2_1, M2_2, ..., M2_15, and the V1 layer includes vias V1_1, V1_2, ..., V1_17.

[0070] The patterns M2_2 , M2_3 , M2_6 , and M2_7 are correspondingly coupled to the word line patterns WL0 , WL3 , WL1 , and WL2 on the M1 layer through corresponding vias V1_1 , V1_2 , V1_5 , and V1_6 .

[0071] The patterns M2_9 , M2_10 , M2_13 , and M2_14 are correspondingly coupled to the word line patterns WL0 , WL3 , WL1 , and WL2 on the M1 layer through corresponding vias V1_10 , V1_11 , V1_14 , and V1_15 .

[0072] The patterns M2_11, M2_4, M2_5, M2_12 are correspondingly coupled to the patterns M1_6, M1_2, M1_3, M1_7 on the M1 layer through the corresponding through holes V1_12, V1_3, V1_4, V1_13 to electrically couple the drain regions of the transistors T0, T1, T2, T3 of the memory cells Bit_0, Bit_1, Bit_2, Bit_3 with the corresponding capacitors C0, C1, C2, C3 of the corresponding memory cells Bit_0, Bit_1, Bit_2, Bit_3, as described herein.

[0073] The pattern M2_8 is coupled to the patterns M1_4, M1_1, M1_5 on the M1 layer through corresponding vias V1_7, V1_8, V1_9.

[0074] The patterns M2_1 and M2_15 are located on the boundaries of the memory cells Bit_0 , Bit_1 , Bit_2 , and Bit_3 , and are coupled to the pattern M1_1 on the M1 layer through corresponding vias V1_16 and V1_17 .

[0075] In at least one embodiment, a conductive pattern similar to the M1 layer is repeated in the M3 layer and the M5 layer, and a conductive pattern similar to the M2 layer is repeated in the M4 layer. The via layers, namely the V2 layer, the V3 layer, and the V4 layer, are configured in a manner similar to that described with respect to Figure 4C As a result, the M5 layer includes a conductive pattern that corresponds to and is electrically coupled to the conductive pattern of the M1 layer, as described herein.

[0076] Figure 4D 4 is a schematic diagram 400D of the M5, M6 and M7 layers of the IC layout diagram 400. The schematic diagram 400D also shows a via layer between the M6 ​​layer and the M7 layer, namely, the V6 layer. For simplicity, the V5 layer between the M5 layer and the M6 ​​layer is omitted.

[0077] The IC layout diagram 400 also includes a MIM layer schematically shown in the figure with the label "MIM". The MIM layer includes a multilayer structure MIM_0, which has at least a lower electrode, an upper electrode, and an insulating material sandwiched between the lower electrode and the upper electrode. The boundary between the upper electrode and the insulating material of the structure MIM_0 in the memory cell Bit_2 is Figure 4D The boundary of transistor T2 in memory cell Bit_2 is schematically indicated by rectangle C2 and corresponds to capacitor C2 of memory cell Bit_2. Figure 4D In the figure, it is schematically indicated by rectangle T2. Figure 4D As shown, capacitor C2 at least partially overlaps with transistor T2. The boundaries of the upper electrodes in capacitors C0, C1, C3 with the insulating material of structure MIM_0 and the boundaries of corresponding transistors T0, T1, T3 in other memory cells Bit_0, Bit_1, Bit_3 are configured in a similar manner. Therefore, in memory cells Bit_0, Bit_1, Bit_2, Bit_3, the upper electrode and insulating material of each capacitor are isolated from the upper electrodes and insulating materials of other capacitors. The lower electrode extends continuously in and between memory cells Bit_0, Bit_1, Bit_2, Bit_3, is configured as a common electrode of capacitors C0, C1, C2, C3 of memory cells Bit_0, Bit_1, Bit_2, Bit_3, and is electrically coupled to bit line BL0, as described herein. This article about FIG. 6A to FIG. 6B Describe the structure MIM_0 in detail.

[0078] The M5 layer includes conductive patterns M5_1, M5_2, ..., M5_7; and word line patterns WL0, WL1, WL2, WL3 corresponding to and electrically coupled with the patterns M1_1, M1_2, ..., M1_7 and the word line patterns WL0, WL1, WL2, WL3 in the M1 layer.

[0079] The M6 ​​layer includes conductive patterns M6_1, M6_2, M6_3, M6_4 that are correspondingly coupled to patterns M5_2, M5_3, M5_6, M5_7 through corresponding vias (not shown) in the V5 layer. As a result, the patterns M6_3, M6_1, M6_2, M6_4 are correspondingly coupled to the drain regions of transistors T0, T1, T2, T3 of memory cells Bit_1, Bit_2, Bit_0, Bit_3.

[0080] The M7 layer includes conductive patterns M7_1, M7_2, M7_3, M7_4 and a bit line pattern BL0. The V6 layer includes vias V6_1, V6_2, . . . , V6_11.

[0081] The patterns M7_1, M7_2, M7_3, M7_4 are respectively coupled to the patterns M6_1, M6_2, M6_3, M6_4 through the corresponding vias V6_1, V6_2, V6_7, V6_8. As a result, the patterns M7_3, M7_1, M7_2, M7_4 are respectively coupled to the drain regions of the transistors T0, T1, T2, T3 of the memory cells Bit_1, Bit_2, Bit_0, Bit_3.

[0082] Patterns M7_1, M7_2, M7_3, and M7_4 are also coupled to the upper electrode in structure MIM_0 through corresponding through holes V6_3, V6_4, V6_5, and V6_6. For example, pattern M7_2 is coupled to the upper electrode of capacitor C2 in memory cell Bit_2 through corresponding through hole V6_4. As a result, the drain region of transistor T2 is sequentially coupled to the upper electrode or first end of capacitor C2 in memory cell Bit_2 through MD region MD4, through hole VD2, pattern M0_2, through hole V0_2, pattern M1_3, through hole V1_4, pattern M2_5, corresponding through holes and patterns in V2, M3, V3, M4, and V4 layers, pattern M5_3, corresponding through holes in V5 layer, pattern M6_2, through hole V6_2, pattern M7_2, and through hole V6_4. The drain regions of the transistors T0 , T1 , T3 of the other memory cells Bit_0 , Bit_1 , Bit_3 are coupled to the upper electrodes or first terminals of the corresponding capacitors C0 , C1 , C3 in a similar manner.

[0083] The bit line pattern BL0 is coupled to the common lower electrode or second end of the capacitors C0, C1, C2, C3 of the memory cells Bit_0, Bit_1, Bit_2, Bit_3 through vias V6_9, V6_10, V6_11. In at least one embodiment, the bit line pattern BL0 corresponds to the common lower electrode or second end of the capacitors C0, C1, C2, C3 of the memory cells Bit_0, Bit_1, Bit_2, Bit_3. Figure 3 and / or coupled to the bit line BL0 described above through another via and / or metal layer. Figure 1 and FIG. 2A to FIG. 2C Describes the bit lines.

[0084] In at least one embodiment, memory cells Bit_0, Bit_1, Bit_2, and Bit_3 have a symmetrical configuration relative to each other. For example, the patterns and / or regions in the various layers in memory cell Bit_2 are symmetrical across the X direction relative to the corresponding patterns and / or regions in the corresponding layers in memory cell Bit_3. In other words, memory cell Bit_3 can be obtained by flipping memory cell Bit_2 across the X direction. Similarly, memory cell Bit_1 can be obtained by flipping memory cell Bit_0 across the X direction. Memory cell Bit_1 can be obtained by flipping memory cell Bit_2 across the Y direction. Memory cell Bit_0 can be obtained by flipping memory cell Bit_3 across the Y direction.

[0085] exist 4A to 4DIn an example configuration, the source line SL is arranged in one or more even metal layers, the word lines WL0, WL1, WL2, WL3 are arranged in one or more odd metal layers, and the bit line BL0 is arranged in one or more metal layers starting from the M7 layer. For example, the source line SL is arranged in one or more of the M0 layer, the M2 layer, or the M4 layer, and the word lines WL0, WL1, WL2, WL3 are arranged in one or more of the M1 layer, the M3 layer, or the M5 layer. The described arrangement is an example. Other configurations are within the scope of various embodiments. In addition, in 4A to 4D In the example configuration of , the MIM layer is arranged between the M6 ​​layer and the M7 layer. However, in at least one embodiment, the MIM layer is arranged between any two metal layers. In at least one embodiment, one or more advantages described herein can be achieved in a memory device corresponding to the IC layout diagram 400.

[0086] Figure 5A is a schematic diagram 500A of an IC layout diagram 500 of a memory device according to some embodiments.

[0087] In at least one embodiment, IC layout 500 corresponds to memory device 300. IC layout 500 includes IC layout 400 and IC layout 400' which is the same as IC layout 400 and is arranged adjacent to IC layout 400 in the Y direction. IC layout 400' includes memory cells Bit_4, Bit_5, Bit_6, Bit_7 of memory device 300. The capacitors of memory cells Bit_4, Bit_5, Bit_6, Bit_7 are configured by structure MIM_1 in the MIM layer and are coupled to bit line pattern BL1. In at least one embodiment, bit line pattern BL1 corresponds to memory device 300. Figure 3 and / or coupled to the bit line BL1 described above through another via and / or metal layer. Figure 1 and FIG. 2A to FIG. 2C Describes the bit lines.

[0088] Figure 5B is a schematic diagram 500B of an IC layout diagram 500 , including a circuit diagram, according to some embodiments.

[0089] Schematic diagram 500B shows capacitors C0, C1, ..., C7 and transistors T0, T1, ..., T7 in corresponding memory cells Bit_0, Bit_1, ..., Bit_7. Figure 3 The electrical connections between capacitors C0, C1, ..., C7, transistors T0, T1, ..., T7, word lines WL0, WL1, WL2, WL3, and bit lines BL0, BL1 are described. Figure 5AThe physical arrangement (except size and shape) of capacitors C0, C1, ..., C7, transistors T0, T1, ..., T7, word lines WL0, WL1, WL2, WL3, and bit lines BL0, BL1 is described.

[0090] Transistors T0, T1, ..., T7 are arranged in an array having rows 541, 542, 543, 544 and columns 547, 548. Capacitors C0, C1, ..., C7 are arranged in the same array. Two word lines are arranged in each column. For example, word lines WL0, WL1 are arranged in column 547, and word lines WL2, WL3 are arranged in column 548.

[0091] The gates of the transistors in each column are electrically coupled to either of the two word lines arranged in the column. For example, in column 547, the gates of transistors T0 and T4 are coupled to word line WL0, while the gates of transistors T1 and T5 are coupled to word line WL1. In column 548, the gates of transistors T2 and T6 are coupled to word line WL2, while the gates of transistors T3 and T7 are coupled to word line WL3.

[0092] Each bit line is coupled to capacitors in two rows. For example, bit line BL0 is coupled to capacitors C1, C2 in row 541, and is also coupled to capacitors C0, C3 in row 542. Bit line BL1 is coupled to capacitors C5, C6 in row 543, and is also coupled to capacitors C4, C7 in row 544. In at least one embodiment, one or more advantages described herein can be achieved in a memory device corresponding to IC layout diagram 500.

[0093] Fig. 6A is a schematic cross-sectional view of an IC device 600A according to some embodiments. In at least one embodiment, the IC device 600A corresponds to Figure 1 , Figure 3 , 4A to 4D , FIG. 5A to FIG. 5B One or more memory devices and / or IC layouts are described.

[0094] IC device 600A includes a substrate 640, at least one transistor 650 over substrate 640, an interconnect structure 660 over transistor 650 and substrate 640, and a MIM structure 670 over transistor 650 and substrate 640. MIM structure 670 includes a capacitor coupled to transistor 650 to form a memory cell.

[0095] In some embodiments, substrate 640 is a semiconductor substrate. N-type and P-type dopants are added to the substrate to form N-wells 651, 652 and a P-well (not shown) respectively. In some embodiments, an isolation structure is formed between adjacent P-wells and N-wells. Fig. 6A Several components such as the P-well and isolation structures are omitted.

[0096] Transistor 650 includes a gate region and a source / drain region. N wells 651, 652 define the source / drain region of transistor 650. For example, N well 651 defines the drain region of transistor 650 and is referred to as drain region 651 in this article, and N well 652 defines the source region of transistor 650 and is referred to as source region 652 in this article. The gate region of transistor 650 includes a stack of gate dielectric layers 653, 654 and gate electrode 655. In at least one embodiment, transistor 650 includes a gate dielectric layer instead of multiple gate dielectrics. Example materials of one or more gate dielectric layers include HfO2, ZrO2, etc. Example materials of gate electrode 655 include polysilicon, metal, etc.

[0097] IC device 600A also includes contact structures, which are configured to electrically couple transistor 650 to other circuits in IC device 600A. The contact structure includes MD regions 656, 657, which are correspondingly located above drain region 651 and source region 652 and electrically contacted therewith. The contact structure also includes various through holes. For example, a VG through hole (not shown) is located above gate electrode 655 and electrically contacted with the device, and is configured to couple gate electrode 655 to word line WL in interconnect structure 660, as described herein. VD through holes 658, 659 are correspondingly located above MD regions 656, 657 and electrically contacted therewith. As described herein, VD through hole 658 is configured to couple drain region 651 to a capacitor in MIM structure 670. As described herein, VD through hole 659 is configured to couple source region 652 to source line SL in interconnect structure 660.

[0098] The interconnect structure 660 includes a plurality of metal layers M0, M1, ..., and a plurality of via layers V0, V1, ..., which are alternately arranged in the thickness direction (i.e., the Z direction) of the substrate 640. The interconnect structure 660 also includes metal layers and via layers in which various interlayer dielectric (ILD) layers (not shown) are embedded. The metal layers and via layers of the interconnect structure 660 are configured to electrically couple various components or circuits of the IC device 600A to each other and to external circuits. Although the M7 layer is Fig. 6A 6 is shown as being at the top level of the interconnect structure 660, but in at least one embodiment, the interconnect structure 660 includes other metal layers and / or via layers higher than the M7 layer.

[0099] exist Fig. 6AIn the example configuration of , the interconnect structure 660 includes the following structures stacked up in sequence in the Z direction and electrically coupled to the VD via 658: an M0 pattern 661, various patterns and vias (not shown) in layers V0, M1, ..., V4, an M5 pattern 662, a V5 via 663, an M6 pattern 664, and a V6 via 665 in the V6 layer. The V6 layer also includes V6 vias 666, 667. The overlying M7 layer includes M7 patterns 668, 669 that are electrically isolated from each other. The M7 pattern 668 electrically couples the V6 via 665 with the V6 via 666. The M7 pattern 669 is coupled to the V6 via 667 and is configured to define or couple to the bit line BL, as described herein.

[0100] The MIM structure 670 is arranged above the M6 ​​layer and includes a multi-layer structure. Fig. 6A In an example configuration, the MIM structure 670 includes the following layers stacked in sequence above the M6 ​​layer in the Z direction: one or more passivation layers 671, 672, a lower conductive layer (or electrode layer) 673, an insulating layer 674, an upper conductive layer 675, and one or more passivation layers 676, 677. For example, the passivation layers 671, 677 include TEOS (tetraethyl orthosilicate), the passivation layers 672, 676 include SBL (silicide barrier layer), the conductive layers 673, 675 include TiN and / or TaN, and the insulating layer 674 includes a high-k dielectric as described herein. In at least one embodiment, the plurality of passivation layers 671, 672 are replaced with a single passivation layer; and / or the plurality of passivation layers 676, 677 are replaced with a single passivation layer. The lower conductive layer 673 is coupled to the M7 pattern 669 through the V6 via 667 for connection to the bit line BL. Insulating layer 674, upper conductive layer 675, and one or more passivation layers 676, 677 are patterned to exist below V6 via 666 but not below V6 via 667. V6 via 666 extends through one or more passivation layers 676, 677 to electrically couple upper conductive layer 675 to M7 pattern 668, and thus to drain region 651 of transistor 650 through various patterns and vias in various metal layers and via layers, as described herein.

[0101] The lower conductive layer 673, the insulating layer 674, and the upper conductive layer 675 below the V6 via 666 together define a capacitor 680 in the MIM structure 670. The upper conductive layer 675 corresponds to a first end of the capacitor 680 coupled to the drain region 651 of the transistor 650. The lower conductive layer 673 corresponds to a second end of the capacitor 680 coupled to the bit line BL. The insulating layer 674 corresponds to an insulating material of the capacitor 680 configured to break down at a predetermined breakdown voltage. As a result, the capacitor 680 is coupled in series with the transistor 650 between the bit line BL and the source line SL (or ground) to define a memory cell. The capacitor 680 and the transistor 650 at least partially overlap each other in the Z direction, as shown in FIG. Fig. 6A It is schematically shown in FIG.

[0102] In at least one embodiment, the structure including transistor 650 coupled to capacitor 680 corresponds to Figure 3 , 4A to 4D For example, capacitor 680 corresponds to capacitor C2, transistor 650 corresponds to transistor T2, MD region 657 corresponds to region MD5, VD via 659 corresponds to via VD5, gate electrode 655 corresponds to gate region PO5, MD region 656 corresponds to region MD4, VD via 658 corresponds to via VD2, M0 pattern 661 corresponds to pattern M0_2, M5 pattern 662 corresponds to pattern M5_3, M6 pattern 664 corresponds to pattern M6_2, V6 via 665 corresponds to via V6_2, M7 pattern 668 corresponds to pattern M7_2, V6 via 666 corresponds to via V6_4, MIM structure 670 corresponds to structure MIM_0, V6 via 667 corresponds to one or more of vias V6_9, V6_10, V6_11, and M7 pattern 669 corresponds to bit line pattern BL0.

[0103] exist Fig. 6A In the example configuration of , the MIM structure 670 is arranged between the M6 ​​layer and the M7 layer. However, other arrangements in which the MIM structure 670 is arranged between any two metal layers of the interconnect structure 660 are within the scope of various embodiments. In some embodiments, the pattern 668 coupled to the transistor 650 and the pattern 669 coupled to the bit line are arranged in different metal layers. In at least one embodiment, one or more advantages described herein can be achieved in the IC device 600A.

[0104] Figure 6B is a schematic cross-sectional view of an IC device 600B according to some embodiments. In at least one embodiment, the IC device 600B corresponds to Figure 1 , Figure 3 , 4A to 4D , FIG. 5A to FIG. 5B One or more memory devices and / or IC layouts are described.

[0105] Compared to IC device 600A, IC device 600B also includes a transistor 682 and a capacitor 684 in MIM structure 670 above substrate 640. Transistor 682 and capacitor 684 are coupled in series between source line SL and bit line BL to define a memory cell in a manner similar to transistor 650 and capacitor 680. For example, the drain of transistor 682 is coupled to M7 pattern 686 through various metal layers and via layers, then coupled to V6 via 688, and then coupled to upper conductive layer 675 defining an upper electrode of capacitor 684. Lower conductive layer 673 defines a common lower electrode for both capacitor 680 and capacitor 684.

[0106] In at least one embodiment, the structure including transistor 682 coupled to capacitor 684 corresponds to Figure 3 , 4A to 4D For example, capacitor 684 corresponds to capacitor C1, transistor 682 corresponds to transistor T1, M7 pattern 686 corresponds to pattern M7_7, and V6 via 688 corresponds to via V6_3. In at least one embodiment, one or more advantages described herein can be achieved in IC device 600B.

[0107] Figure 6C is a schematic cross-sectional view of an IC device 600C according to some embodiments. In at least one embodiment, the IC device 600C corresponds to Figure 1 , Figure 3 , 4A to 4D , FIG. 5A to FIG. 5B One or more memory devices and / or IC layouts are described.

[0108] Compared to IC device 600A in which pattern 669 for bit lines is arranged in M7 layer, IC device 600B includes corresponding pattern 695 for bit lines in M1 layer. IC device 600C includes V0 vias 691, 692, 693 and M1 patterns 694, 695 corresponding to V6 vias 665, 666, 667 and M7 patterns 668, 669 in IC device 600A.

[0109] exist Figure 6C In the example configuration of , one or more layers of the MIM structure 670 are at the same or lower level than the M0 layer in the Z direction. In at least one embodiment (not shown), the MIM structure 670 is located above the M0 layer in a manner similar to the IC device 600A, in which the MIM structure 670 is located above the M6 ​​layer.

[0110] exist Figure 6CIn the example configuration of , capacitor 680 does not overlap transistor 650 in the Z direction. Even when capacitor 680 is coupled to bit line BL in the M1 layer, it is within the scope of various embodiments to form capacitor 680 to at least partially overlap transistor 650 in the Z direction.

[0111] The described configuration is an example where the MIM capacitor in the memory cell is formed directly below the M1 layer or the M7 layer and electrically coupled to the M1 layer or the M7 layer. In at least one embodiment, the MIM capacitor in the memory cell is formed directly below any metal layer higher than the M0 layer and electrically coupled to the M0 layer. In at least one embodiment, one or more advantages described herein can be achieved in the IC device 600C.

[0112] 7A to 7D is a schematic cross-sectional view of an IC device 700 fabricated at various stages of a fabrication process according to some embodiments. In at least one embodiment, the IC device 700 corresponds to Figure 1 , Figure 3 , 4A to 4D , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6C One or more memory devices and / or IC layouts and / or IC devices are described. 7A to 7D In FIG. 6A to FIG. 6C The corresponding element in the element is increased by 100 FIG. 6A to FIG. 6C Reference numerals indicate.

[0113] exist Fig. 7A In the present invention, the manufacturing process starts with a substrate 740. In at least one embodiment, the substrate 740 includes a silicon substrate. In at least one embodiment, the substrate 740 includes silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor materials.

[0114] In front end of line (FEOL) processing, at least one transistor 750 is formed over substrate 740. For example, one or more masks corresponding to one or more active regions in layout 400 are used to form active regions (not shown) in or over substrate 740. A gate dielectric layer (not shown) is deposited over substrate 740. In at least one embodiment, the gate dielectric layer corresponds to the active regions of the substrate 750. Fig. 6A 653, 654 are described. Example materials for the gate dielectric layer include, but are not limited to, a high-k dielectric layer, an interfacial layer, and / or a combination thereof. In some embodiments, the gate dielectric layer is deposited over the substrate 740 by atomic layer deposition (ALD) or other suitable techniques. A gate electrode layer (not shown) is deposited over the gate dielectric layer. In at least one embodiment, the gate electrode layer corresponds to Fig. 6AThe gate electrode 655 is described. Example materials for the gate electrode layer include, but are not limited to, polysilicon, metal, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and / or other suitable conductive materials. In some embodiments, the gate electrode layer is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD or sputtering), plating, atomic layer deposition (ALD), and / or other suitable processes.

[0115] After the FEOL process, a back-end process (BEOL) process is performed to form an interconnect structure 760 above at least one transistor 750 to electrically couple the various components or circuits of the IC device 700 to each other and to external circuits. In at least one embodiment, the interconnect structure 760 includes a contact structure and two structures covering the metal and via layers in sequence. The contact structure includes an MD region, a VD via, and a VG via. The metal layers and via layers above correspondingly include metal layers M0, M1, etc.; and via layers V0, V1, etc. In at least one embodiment, the interconnect structure 760 is manufactured layer by layer in sequence from the substrate 740 upward using one or more masks corresponding to the contact structure, metal layer, and via layer in the layout diagram 400.

[0116] Fig. 7A The interconnect structure 760 is shown at the following stage: a metal layer Mn (n is a non-negative integer) has been formed, an ILD layer 721 has been deposited over the metal layer Mn, and a planarization process has been performed to expose an Mn pattern 764 of the metal layer Mn and planarize an upper surface 722 of the ILD layer 721. The Mn pattern 764 is coupled to a source / drain region (not shown) of at least one transistor 750 through one or more metal layers, via layers, and / or contact structures (not shown). At this stage, the formation of the MIM structure of one or more capacitors begins.

[0117] Specifically, forming the MIM structure includes sequentially depositing one or more passivation layers 771, 772 on the upper surface 722 of the ILD layer 721, and then depositing a lower conductive layer 773 on the one or more passivation layers 771, 772. The one or more passivation layers 771, 772 and the lower conductive layer 773 are deposited or patterned to expose the Mn pattern 764. Fig. 7A As shown, a resulting structure 700A is obtained.

[0118] exist Figure 7B In, through Fig. 7AThe formation of the MIM structure is continued by sequentially depositing an insulating layer 774, an upper conductive layer 775, and then one or more passivation layers 776, 777 over the resulting structure as shown. In at least one embodiment, the insulating layer 774, the upper conductive layer 775, and the one or more passivation layers 776, 777 are deposited over the entire upper surface of the structure 700A and then patterned, for example by etching, to expose a portion 723 of the lower conductive layer 773. Figure 7B As shown, a resulting structure 700B is obtained. The structure 700B includes a capacitor 780 composed of a multi-layer structure in which an insulating layer 774 is sandwiched between a lower conductive layer 773 and an upper conductive layer 775. The capacitor 780 partially overlaps the transistor 750 in the Z direction.

[0119] exist Figure 7C In the embodiment, an ILD layer 724 is deposited over the structure 700B, and then vias 765, 766, 767 of the via layer Vn are formed in the ILD layer 724 to electrically contact the Mn pattern 764, the upper conductive layer 775, and the portion 723 of the lower conductive layer 773, respectively. The Vn via 776 not only extends through a portion of the thickness of the ILD 724, but also extends through one or more passivation layers 776, 777. A planarization process is performed, and the resulting structure 700C is obtained, as shown in FIG. Figure 7C shown.

[0120] exist Fig.7D In the embodiment, a metal layer Mn+1 is deposited over the structure 700C and patterned to obtain Mn+1 patterns 768, 769. The Mn+1 pattern 768 is electrically coupled to the Vn vias 765, 766. The Mn+1 pattern 769 is electrically coupled to the Vn via 767 and is configured as or coupled to the bit line BL. Fig.7D As shown, the resulting structure 700D is obtained. In some embodiments, one or more additional metal layers and / or via layers are formed above the structure 700D to complete the IC device 700. The manufacturing process is described in the example. Other manufacturing processes are within the scope of various embodiments. In at least one embodiment, in the IC device and / or memory device manufactured according to the described manufacturing process, one or more advantages described herein can be achieved.

[0121] Figure 8 is a flow chart of a method 800 according to some embodiments. In at least one embodiment, the method 800 is used for one or more of the following operations: generating a layout diagram for a memory cell, or building a standard cell library including one or more memory cells.

[0122] In some embodiments, one or more operations of method 800 are performed as part of a method of forming one or more memory devices and / or IC devices described herein. In some embodiments, one or more operations of method 800 are performed as part of an automatic placement and routing (APR) method. In some embodiments, one or more operations of method 800 are performed by an APR system (e.g., Fig.11 In some embodiments, one or more operations of method 800 are performed as follows: Fig. 9 In some embodiments, one or more operations of method 800 are performed as described in relation to Fig.12 In some embodiments, one or more operations of method 800 are performed by a processor (such as a processor related to Fig.11 In some embodiments, one or more operations of method 800 are performed by a processor (such as a processor of the EDA system described herein). Fig.11 In some embodiments, one or more operations in the method 800 described herein are omitted.

[0123] At operation 805, an active region and at least one gate region are arranged within the boundaries of the memory cell to define a transistor. Figure 4A As depicted, the active region OD1 and the at least one gate region PO5 are arranged within the boundary of the memory cell Bit_2 to define the transistor T2.

[0124] At operation 815, at least one metal layer and / or at least one via layer is disposed over the transistor to electrically couple the gate region of the transistor to the word line and provide electrical connections to the source / drain region of the transistor. FIG. 4B to FIG. 4D Description: various metal layers M0, M1, ..., and / or via layers V0, V1, ... are arranged above transistor T2 to electrically couple the gate region PO5 of the transistor to the word line WL2 and provide electrical connection to the source / drain region (below region MD4) of the transistor.

[0125] At operation 825, a MIM layer is disposed over the transistor to define a capacitor within the boundaries of the memory cell. Figure 4D 1 , a MIM layer including a multilayer structure MIM_0 is arranged above the transistor T2. The multilayer structure MIM_0 has a portion defining a capacitor C2 within the boundaries of the memory cell Bit_2.

[0126] At operation 835, at least one additional metal layer and / or at least one additional via layer is disposed over the MIM layer to electrically couple the capacitor between the bit line and the source / drain region of the transistor. Figure 4D As depicted, the M7 layer and the V6 layer are disposed over the MIM layer to electrically couple the capacitor C2 between the bit line BL0 and the source / drain regions of the transistor T2.

[0127] At operation 845, the generated layout diagram of the memory cell having a transistor and a capacitor within the boundary of the memory cell is stored in a standard cell library on a non-transitory computer readable medium. In some embodiments, various memory cells with symmetrical configurations are generated and stored in a standard cell library. For example, as described herein, a layout diagram of one or more memory cells Bit_0, Bit_1, Bit_3 is generated and stored in a standard cell library. Memory cell Bit_1 has a layout diagram that is symmetrical with the layout diagram of memory cell Bit_2 across the Y direction. Memory cell Bit_0 has a layout diagram that is symmetrical with the layout diagram of memory cell Bit_1 across the X direction. Memory cell Bit_3 has a layout diagram that is symmetrical with the layout diagram of memory cell Bit_2 across the X direction.

[0128] At operation 855, based on the generated layout map, at least one of the elements in the layer of the semiconductor mask or IC device is manufactured, for example, as described with respect to Fig.12 In at least one embodiment, operation 855 is omitted.

[0129] In at least one embodiment, all operations of method 800 are performed automatically without user input or intervention.

[0130] Fig. 9 is a flow chart of a method 900 according to some embodiments. In at least one embodiment, the method 900 is used to generate an IC layout diagram of an IC device based on cells received from a standard cell library.

[0131] In some embodiments, one or more operations of method 900 are performed to form part of one or more memory devices and / or IC devices described herein. In some embodiments, one or more operations of method 900 are performed as part of an APR method. In some embodiments, one or more operations of method 900 are performed by an APR system (e.g., Fig.11 In some embodiments, one or more operations of method 900 are performed as follows: Fig.12 In some embodiments, one or more operations of method 900 are performed by a processor (such as a processor) Fig.11 The described EDA system is executed by a processor).

[0132] At operation 955, two or more memory cells having a symmetrical layout diagram are placed adjacent to each other, each memory cell having a transistor and a capacitor coupled in series between a bit line and a source line, and the capacitor is arranged above the transistor. For example, one or more memory cells Bit_0, Bit_1, Bit_2, Bit_3 are read from a standard cell library. The memory cells Bit_0, Bit_1, Bit_2, Bit_3 have a layout diagram that is symmetrical to each other as described herein. Each memory cell Bit_0, Bit_1, Bit_2, Bit_3 has a transistor T0, T1, T2, T3 and a capacitor C0, C1, C2, C3 coupled in series between a bit line BL and a source line SL, as described with respect to FIG. 2A to FIG. 2C , Figure 3 Description. Figure 4D As described, capacitors C0, C1, C2, and C3 are arranged above transistors T0, T1, T2, and T3. Memory cells Bit_0, Bit_1, Bit_2, and Bit_3 having mutually symmetrical layout diagrams are placed adjacent to each other to obtain an IC layout diagram 400, as described with respect to Figure 4D In some embodiments, multiple instances of the IC layout diagram 400 are repeatedly placed adjacent to each other in at least one of the X direction or the Y direction to obtain a larger IC layout diagram for a memory device. Figure 5A An example is described in which two instances of the IC layout diagram 400 are placed adjacent to each other in the Y direction.

[0133] At operation 965, the generated IC layout diagram is stored on a non-transitory computer readable medium. For example, the IC layout diagrams 400, 500 are stored on a non-transitory computer readable medium.

[0134] At operation 975, based on the generated IC layout diagram, at least one of the elements in the layers of the semiconductor mask or IC device is manufactured, for example, as described with respect to Fig.12 In at least one embodiment, operation 975 is omitted. In at least one embodiment, all operations of method 900 are performed automatically without user input or intervention.

[0135] In some embodiments, one or more of the units, IC devices, and methods described are applicable to various types of transistor or device technologies, including but not limited to planar transistor technology, FINFET technology, nanosheet FET technology, nanowire FET technology, etc.

[0136] Fig.10is a flow chart of a method 1000 for manufacturing an IC device according to some embodiments. In at least one embodiment, the IC device is manufactured according to the manufacturing method 1000 based on the IC layout generated by the method 900 .

[0137] At operation 1005, a plurality of transistors are formed over a substrate. The plurality of transistors are arranged in an array, the array comprising rows and columns transverse to the rows. For example, as described with respect to FIG. 6A to FIG. 6C , Fig. 7A As described above, a plurality of transistors are formed over the substrate 640, 740. The plurality of transistors, for example, transistors T0, T1, ..., T7 are arranged in an array including rows and columns transverse to the rows, as described with reference to Figure 5B describe.

[0138] At operation 1015, a plurality of word lines are formed over the plurality of transistors. The gates of the transistors in each of the columns are electrically coupled to at least one corresponding word line in the plurality of word lines. Figure 4B , FIG. 6A to FIG. 6C , Fig. 7A As described above, a plurality of word lines WL0, WL1, WL2, and WL3 are formed above the transistor. Figure 5B As shown, the gates of transistors in each column, such as transistors T0 and T4 in column 547, are electrically coupled to at least one corresponding word line, such as word line WL0. The gates of other transistors in the same column (e.g., transistors T1 and T5 in column 547) are electrically coupled to another corresponding word line, such as word line WL1.

[0139] At operation 1025, a plurality of MIM capacitors are formed above a plurality of transistors. The plurality of capacitors are arranged in the same array as the plurality of transistors. Each of the plurality of capacitors overlaps a corresponding transistor of the plurality of transistors in a thickness direction of the substrate. Each of the plurality of capacitors includes a first end and a second end, the second end being electrically coupled to a source / drain region of the corresponding transistor. For example, as described with respect to FIG. 6A to FIG. 6C , Figure 7B As described above, a plurality of capacitors are formed above the transistors. Capacitors, such as capacitors C0, C1, ..., C7, are arranged in the same array as transistors T0, T1, ..., T7, as described above. Figure 5B Description. Figure 4D , FIG. 6A to FIG. 6B , Figure 7B As shown, each capacitor (e.g., capacitor 680) overlaps a corresponding transistor (e.g., transistor 650) in the Z direction. Each capacitor, such as capacitor 680, includes an end, such as an upper conductive layer 675 electrically coupled to a source / drain region (e.g., drain region 651) of a corresponding transistor (e.g., transistor 650), as shown in FIG. FIG. 2A to FIG. 2B , Figure 3 , Figure 5B , FIG. 6A to FIG. 6C describe.

[0140] At operation 1035, a plurality of bit lines are formed over the plurality of capacitors. A first end of each of the capacitors in the row is electrically coupled to a corresponding bit line in the plurality of bit lines. For example, a plurality of bit lines BL0, BL1 are formed over capacitors C0, C1, C7, as described with respect to Figure 5A , FIG. 6A to FIG. 6C , Fig.7D The other end of the capacitors in each row (eg, capacitors C1, C2 in row 541) is electrically coupled to a corresponding bit line, such as bit line BL0, as described with respect to Figure 5B , FIG. 6A to FIG. 6C , Fig.7D describe.

[0141] The described methods include example operations, but they do not necessarily require execution in the order shown. According to the spirit and scope of the embodiments of the present invention, operations can be appropriately added, replaced, changed in order and / or eliminated. Embodiments combining different features and / or different embodiments are within the scope of the present invention and will be apparent to those of ordinary skill in the art after reviewing the present invention.

[0142] In some embodiments, at least one of the methods discussed above is performed in whole or in part by at least one EDA system. In some embodiments, the EAD system may be used as part of a design room of an IC manufacturing system discussed below.

[0143] Fig.11 is a block diagram of an electronic design automation (EDA) system 1100 according to some embodiments.

[0144] In some embodiments, the EDA system 1100 includes an APR system. According to one or more embodiments, the methods of designing a layout diagram described herein represent a wire routing arrangement, which may be implemented using the EDA system 1100, for example, according to some embodiments.

[0145] In some embodiments, EDA system 1100 is a general purpose computing device that includes a hardware processor 1102 and a non-volatile computer readable storage medium 1104. Storage medium 1104 is encoded with, i.e. stores, computer program code 1106 (i.e., a set of executable instructions), among other things. Execution of instructions 1106 by hardware processor 1102 (at least in part) represents an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter, referred to as processes and / or methods).

[0146] The processor 1102 is electrically coupled to the computer-readable storage medium 1104 via a bus 1108. The processor 1102 is also electrically coupled to an input / output (I / O) interface 1110 via the bus 1108. A network interface 1112 is also electrically coupled to the processor 1102 via the bus 1108. The network interface 1112 is connected to a network 1114 so that the processor 1102 and the computer-readable storage medium 1104 can be connected to external elements via the network 1114. The processor 1102 is configured to execute a computer program code 1106 encoded in the computer-readable storage medium 1104 so that the system 1100 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0147] In one or more embodiments, the computer readable storage medium 1104 is an electronic, magnetic, optical fiber, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the computer readable storage medium 1104 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer readable storage medium 1104 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0148] In one or more embodiments, the storage medium 1104 stores computer program code 1106 configured to enable the system 1100 (where such execution (at least in part) represents an EDA tool) to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1104 also stores information that facilitates the execution of part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1104 stores a standard cell library 1107, including standard cells such as those disclosed herein.

[0149] The EDA system 1100 includes an I / O interface 1110. The input / output interface 1110 is coupled to external circuits. In one or more embodiments, the I / O interface 1110 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for transmitting information and commands to the processor 1102.

[0150] The EDA system 1100 also includes a network interface 1112 coupled to the processor 1102. The network interface 1112 allows the system 1100 to communicate with a network 1114 connected to one or more other computer systems. The network interface 1112 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS or WCDMA, or a wired network interface, such as ETHERNET, USB or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more systems 1100.

[0151] The system 1100 is configured to receive information through the I / O interface 1110. The information received through the I / O interface 1110 includes one or more instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 1102. The information is transmitted to the processor 1102 via the bus 1108. The EDA system 1100 is configured to receive information related to a user interface (UI) through the I / O interface 1110. The information is stored in the computer readable medium 1104 as the user interface (UI) 1142.

[0152] In some embodiments, part or all of the processes and / or methods mentioned are implemented as independent software applications for execution by a processor. In some embodiments, part or all of the processes and / or methods mentioned are implemented as software applications that are part of additional software applications. In some embodiments, part or all of the processes and / or methods mentioned are implemented as plug-ins for software applications. In some embodiments, part or all of the processes and / or methods mentioned are executed as software applications that are part of EDA tools. In some embodiments, part or all of the processes and / or methods mentioned are implemented as software applications used by EDA system 1100. In some embodiments, a layout diagram including standard cells is generated using tools such as VIRTUOSO available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0153] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, for example, one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, a RAM, a memory card, etc.

[0154] Fig.121 is a block diagram of an integrated circuit (IC) manufacturing system 1200 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1200 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one element in a layer of a semiconductor integrated circuit.

[0155] exist Fig.12 In the present invention, the IC manufacturing system 1200 includes entities that interact with each other in the design, development and manufacturing cycle, such as a design room 1220, a mask room 1230, and an IC manufacturer / producer ("fab") 1250 and / or services related to manufacturing IC devices 1260. The entities in the system 1200 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1220, the mask room 1230, and the ICfab 1250 are owned by a single larger company. In some embodiments, two or more of the design room 1220, the mask room 1230, and the IC fab 1250 coexist in a common facility and use common resources.

[0156] The design office (or design team) 1220 generates an IC design layout 1222. The IC design layout 1222 includes various geometric patterns designed for the IC device 1260. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various elements constituting the IC device 1260 to be manufactured. The various layers are combined to form various IC components. For example, a portion of the IC design layout 1222 includes various IC components, such as active areas, gate electrodes, source and drain, metal lines or vias of interlayer interconnects, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers arranged on a semiconductor substrate. The design office 1220 implements an appropriate design program to form the IC design layout 1222. The design process includes one or more of a logical design, a physical design or a layout and routing operation. The IC design layout 1222 is presented in one or more data files with information of the geometric patterns. For example, the IC design layout 1222 can be represented in a GDSII file format or a DFII file format.

[0157] The mask chamber 1230 includes data preparation 1232 and mask manufacturing 1244. The mask chamber 1230 uses the IC design layout drawing 1222 to manufacture one or more masks 1245 to manufacture various layers of the IC device 1260 according to the IC design layout drawing 1222. The mask chamber 1230 performs mask data preparation 1232, wherein the IC design layout drawing 1222 is translated into a representative data file ("RDF"). The mask data preparation 1232 provides the RDF to the mask manufacturing 1244. The mask manufacturing 1244 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate template) 1245 or a semiconductor wafer 1253. The design layout drawing 1222 is manipulated by the mask data preparation 1232 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1250. In Fig.12 , mask data preparation 1232 and mask manufacturing 1244 are shown as separate elements. In some embodiments, mask data preparation 1232 and mask manufacturing 1244 can be collectively referred to as mask data preparation.

[0158] In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts the IC design layout 1222. In some embodiments, mask data preparation 1232 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0159] In some embodiments, mask data preparation 1232 includes a mask rule checker (MRC) that checks an IC design layout 1222 that has been processed in OPC with a set of mask creation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins to account for issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for constraints during mask fabrication 1244, which may undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0160] In some embodiments, mask data preparation 1232 includes a lithography process check (LPC), which simulates a process to be performed by ICfab 1250 to manufacture IC device 1260. LPC simulates this process based on IC design layout 1222 to create a simulated manufactured device, such as IC device 1260. Process parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as, aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), and other suitable factors, etc. or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1222.

[0161] It should be understood that the above description of mask data preparation 1232 has been simplified for clarity. In some embodiments, data preparation 1232 includes additional features such as logic operations (LOPs) to modify IC design layout 1222 according to manufacturing rules. In addition, the processes applied to IC design layout 1222 during data preparation 1232 can be performed in a variety of different orders.

[0162] After mask data preparation 1232 and during mask manufacturing 1244, a mask 1245 or a set of masks 1245 are manufactured based on the modified IC design layout 1222. In some embodiments, mask manufacturing 1244 includes performing one or more photolithography exposures based on the IC design layout 1222. In some embodiments, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (photomask or reticle) 1245 according to the modified IC design layout 1222. Mask 1245 can be formed by various techniques. In some embodiments, mask 1245 is formed using binary techniques. In some embodiments, the mask pattern includes an opaque area and a transparent area. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) already coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1245 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1245, various components in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. One or more masks generated by mask manufacturing 1244 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1253, in etching processes to form various etched regions in semiconductor wafer 1253, and / or in other suitable processes.

[0163] IC fab 1250 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 1250 is a semiconductor foundry. For example, there may be a manufacturing plant for front-end manufacturing (front-end of line (FEOL) manufacturing) of multiple IC products, while a second manufacturing plant may provide back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing plant may provide other services for the foundry business.

[0164] IC fab 1250 includes fabrication tools 1252 configured to perform various fabrication operations on semiconductor wafer 1253 such that IC devices 1260 are fabricated according to one or more masks (e.g., mask 1245). In various embodiments, fabrication tools 1252 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication devices capable of performing one or more suitable fabrication processes as discussed herein.

[0165] IC fab 1250 uses mask 1245 manufactured by mask chamber 1230 to manufacture IC device 1260. Therefore, ICfab 1250 at least indirectly uses IC design layout 1222 to prepare IC device 1260. In some embodiments, semiconductor wafer 1253 is manufactured by IC fab 1250 using mask 1245 to form IC device 1260. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 1222 at least indirectly. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate having a plurality of material layers formed thereon. Semiconductor wafer 1253 also includes one or more of various doped regions, dielectric components, and multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0166] With respect to integrated circuit (IC) manufacturing systems (e.g., Fig.12 Details of the system 1200 and the IC manufacturing process associated therewith are found, for example, in U.S. Patent No. 9,256,709 issued on February 9, 2016, U.S. Patent No. 20150278429 published on October 1, 2015, U.S. Patent No. 20140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0167] For example, in U.S. Pat. No. 9,256,709, an IC design layout is generated in a design house (or design team). The IC design layout includes various geometric patterns designed for IC devices. The geometric patterns correspond to the patterns of metal, oxide or semiconductor layers that constitute the various components of the IC device to be manufactured. The various layers are combined to form various IC functions. For example, parts of the IC design layout include various IC components, such as active areas, gate electrodes, source and drain, metal lines or vias for interlayer interconnection, and openings for pads formed in semiconductors, which will be formed in semiconductor substrates (e.g., silicon wafers) and various material layers disposed on the semiconductor substrate. The design house performs appropriate design processes to form the IC design layout. The design process may include logic design, physical design and / or layout and wiring. The IC design layout is presented in one or more data files with geometric pattern information. The mask house uses the IC design layout to manufacture one or more masks, which are used to manufacture the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer, wherein the design layout prepared by the mask data preparation is modified to comply with a specific mask manufacturer and / or mask vendor, and then manufactured. In the present embodiment, mask data preparation and mask manufacturing are illustrated as separate elements, however, mask data preparation and mask manufacturing can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has been processed in OPC, which mask creation rules may contain some geometric and connectivity restrictions to ensure sufficient margin.

[0168] For example, in U.S. pre-grant publication No. 20150278429, in one embodiment, an IC manufacturing system can employ maskless lithography, such as electron beam lithography or optical maskless lithography. In such a system, mask manufacturing is bypassed, and the IC design layout is modified by data preparation suitable for wafer processing using a specific maskless lithography technology. Data preparation modifies the design layout suitable for subsequent operations in the IC manufacturing system. The result of data preparation is represented by one or more data files, such as files in a GDSII file format or a DFII file format. One or more data files include information of geometric patterns, such as polygons representing main design patterns and / or auxiliary components. In the present embodiment, one or more data files also include auxiliary data generated by data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask manufacturing performed by a mask room and wafer exposure performed by an IC manufacturer.

[0169] For example, in pre-grant announcement No. 20140040838, the IC design layout is presented in one or more data files with geometric pattern information. In one example, the IC design layout is represented in a "GDS" format known in the art. In an alternative embodiment, the IC design layout can be transmitted between components in an IC manufacturing system in an alternative file format such as DFII, CIF, OASIS or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include major IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines, interlayer interconnection vias, and openings for pads formed in semiconductors, which will be formed in semiconductor substrates (e.g., silicon wafers) and various material layers disposed on semiconductor substrates. The IC design layout may also include some auxiliary components, such as those used for imaging effects, processing enhancements and / or mask identification information.

[0170] For example, in U.S. Pat. No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model according to the equipment data, material data and inspection results of the mask. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher or a photoresist stripper. The metrology tool performs a post-etch inspection or a post-strip inspection and obtains a post-etch inspection result or a post-strip inspection result, respectively. The controller is used for run-to-run control of the processing tool, including feedforward control and feedback control. The controller receives the post-etch or post-strip inspection results from the metrology tool and retrieves the device and material data from the database. The controller connected to the manufacturing execution system generates a manufacturing model of the processing tool and calibrates the manufacturing model according to the equipment data, material data and inspection results of the mask. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0171] In some embodiments, a memory device includes at least one bit line, at least one word line, and at least one memory cell including a capacitor and a transistor. The transistor has: a gate terminal coupled to the word line; a first terminal; and a second terminal. The capacitor has: a first end coupled to the first terminal of the transistor; a second end coupled to the bit line; and an insulating material located between the first end and the second end. The insulating material is configured to break down at a predetermined breakdown voltage or a higher breakdown voltage applied between the first end and the second end.

[0172] In the above memory device, at least one memory cell is configured to store data having any of: a first value corresponding to an insulating material broken down under previous application of a predetermined breakdown voltage or higher; and a second value corresponding to an insulating material not yet broken down.

[0173] In the above-mentioned memory device, the second terminal of the transistor is grounded.

[0174] In the above-mentioned memory device, it also includes: a controller, which is coupled to at least one memory cell through at least one bit line and at least one word line, wherein the controller is configured to apply a turn-on voltage to the gate terminal of the transistor via at least one word line to turn on the transistor in a programming operation, and apply a programming voltage to the second end of the capacitor via at least one bit line to apply a predetermined breakdown voltage or a higher breakdown voltage between the first end and the second end of the capacitor when the transistor is turned on, so as to break down the insulating material of the capacitor.

[0175] In the above-mentioned memory device, the controller is configured to apply a turn-on voltage to the gate terminal of the transistor via at least one word line to turn on the transistor in a read operation, and apply a read voltage to the second end of the capacitor via at least one bit line to detect data stored in at least one memory cell when the transistor is turned on.

[0176] In the above-mentioned memory device, at least one word line is a plurality of word lines, at least one memory cell is a plurality of memory cells, second ends of capacitors of the plurality of memory cells are commonly coupled to at least one bit line, gate terminals of transistors of the plurality of memory cells are correspondingly coupled to the plurality of word lines, and second terminals of transistors of the plurality of memory cells are grounded.

[0177] In the above-mentioned memory device, at least one bit line is a plurality of bit lines, at least one word line is a plurality of word lines, at least one memory cell is a plurality of memory cell strings, second ends of capacitors of memory cells in each of the plurality of memory cell strings are commonly coupled to corresponding bit lines of the plurality of bit lines, gate terminals of transistors of memory cells in each of the plurality of memory cell strings are correspondingly coupled to the plurality of word lines, and second terminals of transistors of memory cells in the plurality of memory cell strings are grounded.

[0178] In the above-mentioned memory device, it also includes: a substrate having a transistor on it; at least one metal layer located above the substrate, the at least one metal layer including at least one bit line; and a conductive pattern electrically isolated from the at least one bit line; a first conductive layer located between the at least one metal layer and the substrate in the thickness direction of the substrate, the first conductive layer including a first end of the capacitor; a second conductive layer located between the at least one metal layer and the substrate in the thickness direction, the second conductive layer including a second end of the capacitor; and an insulating layer located between the first conductive layer and the second conductive layer in the thickness direction, the insulating layer including an insulating material of the capacitor.

[0179] In the above-mentioned memory device, it also includes: a first through hole extending between the first end of the capacitor in the first conductive layer and the first part of the conductive pattern and electrically coupling the two, a second through hole extending between the second end of the capacitor in the second conductive layer and at least one bit line and electrically coupling the two; and a third through hole electrically coupling the second part of the conductive pattern and the first terminal of the transistor.

[0180] In the above memory device, at least one metal layer is higher than the zero metal layer above the substrate.

[0181] In some embodiments, an integrated circuit (IC) device includes: a substrate having a plurality of transistors thereon; a metal layer located above the substrate, the metal layer including at least one bit line; and a plurality of capacitors located between the metal layer and the substrate in a thickness direction of the substrate. Each of the plurality of capacitors is coupled between at least one bit line and a first source / drain region of a corresponding transistor in the plurality of transistors. Each of the plurality of capacitors includes an insulating material configured to break down at a predetermined breakdown voltage or a higher breakdown voltage applied across the insulating material.

[0182] In the above-mentioned IC device, it also includes: a first conductive layer, which is located between at least one metal layer and the substrate in the thickness direction, and the first conductive layer includes the first ends of multiple capacitors; a second conductive layer, which is located between at least one metal layer and the substrate in the thickness direction, and the second conductive layer includes the second ends of multiple capacitors; and an insulating layer, which is located between the first conductive layer and the second conductive layer in the thickness direction, and the insulating layer includes insulating materials of multiple capacitors.

[0183] In the above-mentioned IC device, it also includes: multiple conductive patterns, which are electrically isolated from at least one bit line; multiple first through holes, each extending downward from at least one bit line to the first end of a corresponding capacitor among a plurality of capacitors in the thickness direction; multiple second through holes, each extending downward from a corresponding conductive pattern among the multiple conductive patterns to the second end of a corresponding capacitor among the multiple capacitors in the thickness direction; and multiple third through holes, each extending downward from a corresponding conductive pattern among the multiple conductive patterns in the thickness direction to electrically couple the corresponding capacitor to the first source / drain region of the corresponding transistor.

[0184] In the above IC device, the metal layer includes both at least one bit line and a plurality of conductive patterns.

[0185] The IC device further comprises: first and second passivation layers, between which the first conductive layer, the second conductive layer and the insulating layer are sandwiched in the thickness direction.

[0186] In the above IC device, each of the plurality of transistors further includes a second source / drain region connected to ground.

[0187] In the above IC device, it also includes: a plurality of word lines, each of which is electrically coupled to a gate region of a corresponding transistor among the plurality of transistors.

[0188] In the above-mentioned IC device, it also includes: an interconnection structure located above the substrate and electrically coupled to multiple transistors, wherein the interconnection structure includes multiple metal layers stacked on each other in the thickness direction, and the multiple metal layers include: a metal layer including at least one bit line, and a lower metal layer located directly below the metal layer, and multiple capacitors are located between the metal layer and the lower metal layer in the thickness direction.

[0189] In some embodiments, a method includes: forming a plurality of transistors above a substrate. The plurality of transistors are arranged in an array, the array including rows and columns transverse to the rows. The method also includes: forming a plurality of word lines above the plurality of transistors. The gate of the transistor in each of the columns is electrically coupled to at least one corresponding word line in the plurality of word lines. The method also includes: forming a plurality of metal-insulator-metal (MIM) capacitors above the plurality of transistors. The plurality of capacitors are arranged in the same array as the plurality of transistors. Each of the plurality of capacitors overlaps with a corresponding transistor in the thickness direction of the substrate. Each of the plurality of capacitors includes a first end and a second end, the second end being electrically coupled to a source / drain region of the corresponding transistor. The method also includes: forming a plurality of bit lines above the plurality of capacitors. The first end of the capacitor in each of the rows is electrically coupled to a corresponding bit line in the plurality of bit lines.

[0190] In the above method, the transistors in each of the columns include a first transistor having a gate electrically coupled to a first corresponding word line in a plurality of word lines; and a second transistor having a gate electrically coupled to a second corresponding word line in a plurality of word lines; and each of the plurality of bit lines is electrically coupled to a first end of a capacitor in two of the rows.

[0191] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present invention.

Claims

1. A storage device, comprising: at least one bit line; at least one word line; at least one memory cell including a capacitor and a transistor; as well as a controller coupled to the at least one memory cell via the at least one bit line and the at least one word line, Wherein, the transistor has a gate terminal coupled to the word line; The first terminal, and The second terminal, The capacitor has a first terminal coupled to the first terminal of the transistor, a second terminal coupled to the bit line; and an insulating material located between the first end and the second end and configured to break down at a predetermined breakdown voltage or higher breakdown voltage applied between the first end and the second end, wherein the controller is configured to, in a programming operation, applying a turn-on voltage to the gate terminal of the transistor via the at least one word line to turn on the transistor, and A programming voltage is applied to the second end of the capacitor via the at least one bit line to apply the predetermined breakdown voltage or higher between the first and second ends of the capacitor to break down the insulating material of the capacitor when the transistor is turned on.

2. The memory device according to claim 1, wherein The at least one memory unit is configured to store data having any of the following: a first value corresponding to the insulating material breaking down under a previous application of the predetermined breakdown voltage or higher; and The second value corresponds to the insulating material not yet broken down.

3. The memory device according to claim 1, wherein The second terminal of the transistor is grounded.

4. The memory device according to claim 1, wherein: The memory device is a one-time programmable non-volatile memory, and The at least one memory cell comprises at least one one-time programmable memory cell.

5. The memory device according to claim 1, wherein The controller is configured to, in a read operation, applying the turn-on voltage to the gate terminal of the transistor via the at least one word line to turn on the transistor, and A read voltage is applied to the second end of the capacitor via the at least one bit line to detect data stored in the at least one memory cell when the transistor is turned on.

6. The memory device according to claim 1, wherein The at least one word line is a plurality of word lines, the at least one memory cell is a plurality of memory cells, The second ends of the capacitors of the plurality of memory cells are commonly coupled to the at least one bit line, The gate terminals of the transistors of the plurality of memory cells are correspondingly coupled to the plurality of word lines, and The second terminals of the transistors of the plurality of memory cells are grounded.

7. The memory device according to claim 1, wherein The at least one bit line is a plurality of bit lines, The at least one word line is a plurality of word lines, at least one memory cell is a plurality of memory cell strings, the second ends of the capacitors of the memory cells in each of the plurality of memory cell strings being commonly coupled to a corresponding bit line of the plurality of bit lines, The gate terminals of the transistors of the memory cells in each of the plurality of memory cell strings are correspondingly coupled to a plurality of word lines, and The second terminals of the transistors of the memory cells in the plurality of memory cell strings are grounded.

8. The memory device according to claim 1, further comprising: a substrate having the transistor thereon; At least one metal layer is located above the substrate, and the at least one metal layer includes the at least one bit line; and a conductive pattern electrically isolated from the at least one bit line; a first conductive layer, located between the at least one metal layer and the substrate in a thickness direction of the substrate, the first conductive layer including the first end of the capacitor; a second conductive layer located between the at least one metal layer and the substrate in the thickness direction, the second conductive layer including the second end of the capacitor; as well as An insulating layer is located between the first conductive layer and the second conductive layer in the thickness direction, and the insulating layer includes the insulating material of the capacitor.

9. The memory device according to claim 8, further comprising: a first via extending between the first end of the capacitor and a first portion of the conductive pattern in the first conductive layer and electrically coupling the two, a second via extending between and electrically coupling the second end of the capacitor and the at least one bit line in the second conductive layer; as well as A third via electrically couples the second portion of the conductive pattern with the first terminal of the transistor.

10. The memory device according to claim 9, wherein The at least one metal layer is higher than a metal zero layer above the substrate.

11. An integrated circuit device comprising: a substrate having a plurality of transistors thereon; A metal layer, located above the substrate, comprising: at least one bit line; and a plurality of conductive patterns electrically isolated from the at least one bit line; a plurality of capacitors located between the metal layer and the substrate in a thickness direction of the substrate, in, Each capacitor of the plurality of capacitors comprises: a first terminal electrically coupled to the at least one bit line; a second end electrically coupled to a corresponding conductive pattern among the plurality of conductive patterns, the corresponding conductive pattern electrically coupled to a first source / drain region of a corresponding transistor among the plurality of transistors; and An insulating material configured to break down at a predetermined breakdown voltage or higher applied across the insulating material.

12. The integrated circuit device according to claim 11, further comprising: a first conductive layer located between the at least one metal layer and the substrate in the thickness direction, the first conductive layer including the first end of each capacitor of the plurality of capacitors; a second conductive layer located between the at least one metal layer and the substrate in the thickness direction, the second conductive layer including the second end of each capacitor of the plurality of capacitors; and An insulating layer is located between the first conductive layer and the second conductive layer in the thickness direction, and the insulating layer includes the insulating material of each capacitor of the plurality of capacitors.

13. The integrated circuit device according to claim 12, further comprising: a plurality of first through holes, first through holes of the plurality of first through holes extending downwardly from the at least one bit line to first ends of corresponding capacitors of the plurality of capacitors in the thickness direction; a plurality of second through holes, second through holes of the plurality of second through holes extending downwardly from the first portion of the corresponding conductive pattern to the second end of the corresponding capacitor of the plurality of capacitors in the thickness direction; as well as A plurality of third vias, third vias of the plurality of third vias extending downward from the second portion of the corresponding conductive pattern in the thickness direction to electrically couple the corresponding capacitor to the first source / drain region of the corresponding transistor.

14. The integrated circuit device of claim 13, wherein Each of the plurality of capacitors does not overlap the corresponding transistor in the thickness direction of the substrate.

15. The integrated circuit device of claim 12, further comprising: The first and second passivation layers sandwich the first conductive layer, the second conductive layer, and the insulating layer therebetween in the thickness direction.

16. The integrated circuit device of claim 11, wherein Each transistor of the plurality of transistors further includes a second source / drain region connected to ground.

17. The integrated circuit device of claim 11, further comprising: A plurality of word lines are each electrically coupled to a gate region of a corresponding transistor of the plurality of transistors.

18. The integrated circuit device of claim 11, further comprising: an interconnect structure located above the substrate and electrically coupled to the plurality of transistors, in, The interconnect structure includes a plurality of metal layers stacked on top of each other in the thickness direction, The plurality of metal layers include a metal layer including the at least one bit line, and the underlying metal layer, located directly beneath the metal layer, and Each capacitor of the plurality of capacitors is completely located between the metal layer and the underlying metal layer in the thickness direction.

19. A method of forming a memory device, comprising: A plurality of transistors are formed over the substrate, wherein The plurality of transistors are arranged in an array, the array comprising rows and columns transverse to the rows; A plurality of word lines are formed above the plurality of transistors, wherein The gates of the transistors in each of the columns are electrically coupled to at least one corresponding word line of the plurality of word lines; A plurality of capacitors are formed over the plurality of transistors, the plurality of capacitors being metal-insulator-metal (MIM) capacitors, wherein The plurality of capacitors are arranged in the same array as the plurality of transistors; Each capacitor of the plurality of capacitors overlaps with a corresponding transistor of the plurality of transistors in a thickness direction of the substrate; Each capacitor of the plurality of capacitors comprises a first terminal and a second terminal, A plurality of first through holes, a plurality of second through holes, and a plurality of third through holes are formed, wherein for each capacitor of the plurality of capacitors, The first end is below the lower end of the corresponding first through hole among the plurality of first through holes, and the first end is electrically connected to the lower end of the corresponding first through hole. The second end is below a lower end of a corresponding second through hole among the plurality of second through holes, the second end being electrically connected to the lower end of the corresponding second through hole, and The source / drain region of the corresponding transistor is electrically connected to the corresponding third through hole of the plurality of third through holes; forming a plurality of conductive patterns over the plurality of capacitors, wherein each of the plurality of conductive patterns is located above an upper end of a second through hole among the plurality of second through holes and above an upper end of a third through hole among the plurality of third through holes, and connects the upper end of the second through hole among the plurality of second through holes and the upper end of the third through hole among the plurality of third through holes to electrically connect the second end of each of the plurality of capacitors and the source / drain region of the corresponding transistor; and A plurality of bit lines are formed above the plurality of capacitors, wherein Each of the plurality of bit lines is located above and electrically connected to an upper end of the first through-hole electrically connecting the first ends of the capacitors in each of the rows.

20. The method according to claim 19, wherein The transistors in each of the columns include a first transistor having the gate electrically coupled to a first corresponding word line among the plurality of word lines; as well as a second transistor having the gate electrically coupled to a second corresponding word line of the plurality of word lines; and Each bit line of the plurality of bit lines is electrically coupled to the first end of the capacitor in two of the rows.

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